drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5,
  65         MCC_STATUS_NOT_SUPPORTED = 66
  66 };
  67
  68 #define CQE_STATUS_COMPL_MASK           0xFFFF
  69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70 #define CQE_STATUS_EXTD_MASK            0xFFFF
  71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73 struct be_mcc_compl {
  74         u32 status;             /* dword 0 */
  75         u32 tag0;               /* dword 1 */
  76         u32 tag1;               /* dword 2 */
  77         u32 flags;              /* dword 3 */
  78 };
  79
  80 /* When the async bit of mcc_compl is set, the last 4 bytes of
  81  * mcc_compl is interpreted as follows:
  82  */
  83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT  16
  86 #define ASYNC_TRAILER_EVENT_TYPE_MASK   0xFF
  87 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  88 #define ASYNC_EVENT_CODE_GRP_5          0x5
  89 #define ASYNC_EVENT_QOS_SPEED           0x1
  90 #define ASYNC_EVENT_COS_PRIORITY        0x2
  91 #define ASYNC_EVENT_PVID_STATE          0x3
  92 struct be_async_event_trailer {
  93         u32 code;
  94 };
  95
  96 enum {
  97         ASYNC_EVENT_LINK_DOWN   = 0x0,
  98         ASYNC_EVENT_LINK_UP     = 0x1
  99 };
 100
 101 /* When the event code of an async trailer is link-state, the mcc_compl
 102  * must be interpreted as follows
 103  */
 104 struct be_async_event_link_state {
 105         u8 physical_port;
 106         u8 port_link_status;
 107         u8 port_duplex;
 108         u8 port_speed;
 109         u8 port_fault;
 110         u8 rsvd0[7];
 111         struct be_async_event_trailer trailer;
 112 } __packed;
 113
 114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
 115  * the mcc_compl must be interpreted as follows
 116  */
 117 struct be_async_event_grp5_qos_link_speed {
 118         u8 physical_port;
 119         u8 rsvd[5];
 120         u16 qos_link_speed;
 121         u32 event_tag;
 122         struct be_async_event_trailer trailer;
 123 } __packed;
 124
 125 /* When the event code of an async trailer is GRP5 and event type is
 126  * CoS-Priority, the mcc_compl must be interpreted as follows
 127  */
 128 struct be_async_event_grp5_cos_priority {
 129         u8 physical_port;
 130         u8 available_priority_bmap;
 131         u8 reco_default_priority;
 132         u8 valid;
 133         u8 rsvd0;
 134         u8 event_tag;
 135         struct be_async_event_trailer trailer;
 136 } __packed;
 137
 138 /* When the event code of an async trailer is GRP5 and event type is
 139  * PVID state, the mcc_compl must be interpreted as follows
 140  */
 141 struct be_async_event_grp5_pvid_state {
 142         u8 enabled;
 143         u8 rsvd0;
 144         u16 tag;
 145         u32 event_tag;
 146         u32 rsvd1;
 147         struct be_async_event_trailer trailer;
 148 } __packed;
 149
 150 struct be_mcc_mailbox {
 151         struct be_mcc_wrb wrb;
 152         struct be_mcc_compl compl;
 153 };
 154
 155 #define CMD_SUBSYSTEM_COMMON    0x1
 156 #define CMD_SUBSYSTEM_ETH       0x3
 157 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 158
 159 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 160 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 161 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 162 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 163 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 164 #define OPCODE_COMMON_READ_FLASHROM                     6
 165 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 166 #define OPCODE_COMMON_CQ_CREATE                         12
 167 #define OPCODE_COMMON_EQ_CREATE                         13
 168 #define OPCODE_COMMON_MCC_CREATE                        21
 169 #define OPCODE_COMMON_SET_QOS                           28
 170 #define OPCODE_COMMON_MCC_CREATE_EXT                    90
 171 #define OPCODE_COMMON_SEEPROM_READ                      30
 172 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES               32
 173 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 174 #define OPCODE_COMMON_GET_FW_VERSION                    35
 175 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 176 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 177 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 178 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 179 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 180 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 181 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 182 #define OPCODE_COMMON_MCC_DESTROY                       53
 183 #define OPCODE_COMMON_CQ_DESTROY                        54
 184 #define OPCODE_COMMON_EQ_DESTROY                        55
 185 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 186 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 187 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 188 #define OPCODE_COMMON_FUNCTION_RESET                    61
 189 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 190 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 191 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 192 #define OPCODE_COMMON_GET_PHY_DETAILS                   102
 193 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP           103
 194 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES    121
 195
 196 #define OPCODE_ETH_RSS_CONFIG                           1
 197 #define OPCODE_ETH_ACPI_CONFIG                          2
 198 #define OPCODE_ETH_PROMISCUOUS                          3
 199 #define OPCODE_ETH_GET_STATISTICS                       4
 200 #define OPCODE_ETH_TX_CREATE                            7
 201 #define OPCODE_ETH_RX_CREATE                            8
 202 #define OPCODE_ETH_TX_DESTROY                           9
 203 #define OPCODE_ETH_RX_DESTROY                           10
 204 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 205
 206 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 207 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 208 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
 209
 210 struct be_cmd_req_hdr {
 211         u8 opcode;              /* dword 0 */
 212         u8 subsystem;           /* dword 0 */
 213         u8 port_number;         /* dword 0 */
 214         u8 domain;              /* dword 0 */
 215         u32 timeout;            /* dword 1 */
 216         u32 request_length;     /* dword 2 */
 217         u8 version;             /* dword 3 */
 218         u8 rsvd[3];             /* dword 3 */
 219 };
 220
 221 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 222 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 223 struct be_cmd_resp_hdr {
 224         u32 info;               /* dword 0 */
 225         u32 status;             /* dword 1 */
 226         u32 response_length;    /* dword 2 */
 227         u32 actual_resp_len;    /* dword 3 */
 228 };
 229
 230 struct phys_addr {
 231         u32 lo;
 232         u32 hi;
 233 };
 234
 235 /**************************
 236  * BE Command definitions *
 237  **************************/
 238
 239 /* Pseudo amap definition in which each bit of the actual structure is defined
 240  * as a byte: used to calculate offset/shift/mask of each field */
 241 struct amap_eq_context {
 242         u8 cidx[13];            /* dword 0*/
 243         u8 rsvd0[3];            /* dword 0*/
 244         u8 epidx[13];           /* dword 0*/
 245         u8 valid;               /* dword 0*/
 246         u8 rsvd1;               /* dword 0*/
 247         u8 size;                /* dword 0*/
 248         u8 pidx[13];            /* dword 1*/
 249         u8 rsvd2[3];            /* dword 1*/
 250         u8 pd[10];              /* dword 1*/
 251         u8 count[3];            /* dword 1*/
 252         u8 solevent;            /* dword 1*/
 253         u8 stalled;             /* dword 1*/
 254         u8 armed;               /* dword 1*/
 255         u8 rsvd3[4];            /* dword 2*/
 256         u8 func[8];             /* dword 2*/
 257         u8 rsvd4;               /* dword 2*/
 258         u8 delaymult[10];       /* dword 2*/
 259         u8 rsvd5[2];            /* dword 2*/
 260         u8 phase[2];            /* dword 2*/
 261         u8 nodelay;             /* dword 2*/
 262         u8 rsvd6[4];            /* dword 2*/
 263         u8 rsvd7[32];           /* dword 3*/
 264 } __packed;
 265
 266 struct be_cmd_req_eq_create {
 267         struct be_cmd_req_hdr hdr;
 268         u16 num_pages;          /* sword */
 269         u16 rsvd0;              /* sword */
 270         u8 context[sizeof(struct amap_eq_context) / 8];
 271         struct phys_addr pages[8];
 272 } __packed;
 273
 274 struct be_cmd_resp_eq_create {
 275         struct be_cmd_resp_hdr resp_hdr;
 276         u16 eq_id;              /* sword */
 277         u16 rsvd0;              /* sword */
 278 } __packed;
 279
 280 /******************** Mac query ***************************/
 281 enum {
 282         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 283         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 284         MAC_ADDRESS_TYPE_PD = 0x2,
 285         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 286 };
 287
 288 struct mac_addr {
 289         u16 size_of_struct;
 290         u8 addr[ETH_ALEN];
 291 } __packed;
 292
 293 struct be_cmd_req_mac_query {
 294         struct be_cmd_req_hdr hdr;
 295         u8 type;
 296         u8 permanent;
 297         u16 if_id;
 298 } __packed;
 299
 300 struct be_cmd_resp_mac_query {
 301         struct be_cmd_resp_hdr hdr;
 302         struct mac_addr mac;
 303 };
 304
 305 /******************** PMac Add ***************************/
 306 struct be_cmd_req_pmac_add {
 307         struct be_cmd_req_hdr hdr;
 308         u32 if_id;
 309         u8 mac_address[ETH_ALEN];
 310         u8 rsvd0[2];
 311 } __packed;
 312
 313 struct be_cmd_resp_pmac_add {
 314         struct be_cmd_resp_hdr hdr;
 315         u32 pmac_id;
 316 };
 317
 318 /******************** PMac Del ***************************/
 319 struct be_cmd_req_pmac_del {
 320         struct be_cmd_req_hdr hdr;
 321         u32 if_id;
 322         u32 pmac_id;
 323 };
 324
 325 /******************** Create CQ ***************************/
 326 /* Pseudo amap definition in which each bit of the actual structure is defined
 327  * as a byte: used to calculate offset/shift/mask of each field */
 328 struct amap_cq_context_be {
 329         u8 cidx[11];            /* dword 0*/
 330         u8 rsvd0;               /* dword 0*/
 331         u8 coalescwm[2];        /* dword 0*/
 332         u8 nodelay;             /* dword 0*/
 333         u8 epidx[11];           /* dword 0*/
 334         u8 rsvd1;               /* dword 0*/
 335         u8 count[2];            /* dword 0*/
 336         u8 valid;               /* dword 0*/
 337         u8 solevent;            /* dword 0*/
 338         u8 eventable;           /* dword 0*/
 339         u8 pidx[11];            /* dword 1*/
 340         u8 rsvd2;               /* dword 1*/
 341         u8 pd[10];              /* dword 1*/
 342         u8 eqid[8];             /* dword 1*/
 343         u8 stalled;             /* dword 1*/
 344         u8 armed;               /* dword 1*/
 345         u8 rsvd3[4];            /* dword 2*/
 346         u8 func[8];             /* dword 2*/
 347         u8 rsvd4[20];           /* dword 2*/
 348         u8 rsvd5[32];           /* dword 3*/
 349 } __packed;
 350
 351 struct amap_cq_context_lancer {
 352         u8 rsvd0[12];           /* dword 0*/
 353         u8 coalescwm[2];        /* dword 0*/
 354         u8 nodelay;             /* dword 0*/
 355         u8 rsvd1[12];           /* dword 0*/
 356         u8 count[2];            /* dword 0*/
 357         u8 valid;               /* dword 0*/
 358         u8 rsvd2;               /* dword 0*/
 359         u8 eventable;           /* dword 0*/
 360         u8 eqid[16];            /* dword 1*/
 361         u8 rsvd3[15];           /* dword 1*/
 362         u8 armed;               /* dword 1*/
 363         u8 rsvd4[32];           /* dword 2*/
 364         u8 rsvd5[32];           /* dword 3*/
 365 } __packed;
 366
 367 struct be_cmd_req_cq_create {
 368         struct be_cmd_req_hdr hdr;
 369         u16 num_pages;
 370         u8 page_size;
 371         u8 rsvd0;
 372         u8 context[sizeof(struct amap_cq_context_be) / 8];
 373         struct phys_addr pages[8];
 374 } __packed;
 375
 376
 377 struct be_cmd_resp_cq_create {
 378         struct be_cmd_resp_hdr hdr;
 379         u16 cq_id;
 380         u16 rsvd0;
 381 } __packed;
 382
 383 /******************** Create MCCQ ***************************/
 384 /* Pseudo amap definition in which each bit of the actual structure is defined
 385  * as a byte: used to calculate offset/shift/mask of each field */
 386 struct amap_mcc_context_be {
 387         u8 con_index[14];
 388         u8 rsvd0[2];
 389         u8 ring_size[4];
 390         u8 fetch_wrb;
 391         u8 fetch_r2t;
 392         u8 cq_id[10];
 393         u8 prod_index[14];
 394         u8 fid[8];
 395         u8 pdid[9];
 396         u8 valid;
 397         u8 rsvd1[32];
 398         u8 rsvd2[32];
 399 } __packed;
 400
 401 struct amap_mcc_context_lancer {
 402         u8 async_cq_id[16];
 403         u8 ring_size[4];
 404         u8 rsvd0[12];
 405         u8 rsvd1[31];
 406         u8 valid;
 407         u8 async_cq_valid[1];
 408         u8 rsvd2[31];
 409         u8 rsvd3[32];
 410 } __packed;
 411
 412 struct be_cmd_req_mcc_create {
 413         struct be_cmd_req_hdr hdr;
 414         u16 num_pages;
 415         u16 cq_id;
 416         u32 async_event_bitmap[1];
 417         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 418         struct phys_addr pages[8];
 419 } __packed;
 420
 421 struct be_cmd_resp_mcc_create {
 422         struct be_cmd_resp_hdr hdr;
 423         u16 id;
 424         u16 rsvd0;
 425 } __packed;
 426
 427 /******************** Create TxQ ***************************/
 428 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 429 #define BE_ULP1_NUM                             1
 430
 431 /* Pseudo amap definition in which each bit of the actual structure is defined
 432  * as a byte: used to calculate offset/shift/mask of each field */
 433 struct amap_tx_context {
 434         u8 if_id[16];           /* dword 0 */
 435         u8 tx_ring_size[4];     /* dword 0 */
 436         u8 rsvd1[26];           /* dword 0 */
 437         u8 pci_func_id[8];      /* dword 1 */
 438         u8 rsvd2[9];            /* dword 1 */
 439         u8 ctx_valid;           /* dword 1 */
 440         u8 cq_id_send[16];      /* dword 2 */
 441         u8 rsvd3[16];           /* dword 2 */
 442         u8 rsvd4[32];           /* dword 3 */
 443         u8 rsvd5[32];           /* dword 4 */
 444         u8 rsvd6[32];           /* dword 5 */
 445         u8 rsvd7[32];           /* dword 6 */
 446         u8 rsvd8[32];           /* dword 7 */
 447         u8 rsvd9[32];           /* dword 8 */
 448         u8 rsvd10[32];          /* dword 9 */
 449         u8 rsvd11[32];          /* dword 10 */
 450         u8 rsvd12[32];          /* dword 11 */
 451         u8 rsvd13[32];          /* dword 12 */
 452         u8 rsvd14[32];          /* dword 13 */
 453         u8 rsvd15[32];          /* dword 14 */
 454         u8 rsvd16[32];          /* dword 15 */
 455 } __packed;
 456
 457 struct be_cmd_req_eth_tx_create {
 458         struct be_cmd_req_hdr hdr;
 459         u8 num_pages;
 460         u8 ulp_num;
 461         u8 type;
 462         u8 bound_port;
 463         u8 context[sizeof(struct amap_tx_context) / 8];
 464         struct phys_addr pages[8];
 465 } __packed;
 466
 467 struct be_cmd_resp_eth_tx_create {
 468         struct be_cmd_resp_hdr hdr;
 469         u16 cid;
 470         u16 rsvd0;
 471 } __packed;
 472
 473 /******************** Create RxQ ***************************/
 474 struct be_cmd_req_eth_rx_create {
 475         struct be_cmd_req_hdr hdr;
 476         u16 cq_id;
 477         u8 frag_size;
 478         u8 num_pages;
 479         struct phys_addr pages[2];
 480         u32 interface_id;
 481         u16 max_frame_size;
 482         u16 rsvd0;
 483         u32 rss_queue;
 484 } __packed;
 485
 486 struct be_cmd_resp_eth_rx_create {
 487         struct be_cmd_resp_hdr hdr;
 488         u16 id;
 489         u8 rss_id;
 490         u8 rsvd0;
 491 } __packed;
 492
 493 /******************** Q Destroy  ***************************/
 494 /* Type of Queue to be destroyed */
 495 enum {
 496         QTYPE_EQ = 1,
 497         QTYPE_CQ,
 498         QTYPE_TXQ,
 499         QTYPE_RXQ,
 500         QTYPE_MCCQ
 501 };
 502
 503 struct be_cmd_req_q_destroy {
 504         struct be_cmd_req_hdr hdr;
 505         u16 id;
 506         u16 bypass_flush;       /* valid only for rx q destroy */
 507 } __packed;
 508
 509 /************ I/f Create (it's actually I/f Config Create)**********/
 510
 511 /* Capability flags for the i/f */
 512 enum be_if_flags {
 513         BE_IF_FLAGS_RSS = 0x4,
 514         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 515         BE_IF_FLAGS_BROADCAST = 0x10,
 516         BE_IF_FLAGS_UNTAGGED = 0x20,
 517         BE_IF_FLAGS_ULP = 0x40,
 518         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 519         BE_IF_FLAGS_VLAN = 0x100,
 520         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 521         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 522         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
 523         BE_IF_FLAGS_MULTICAST = 0x1000
 524 };
 525
 526 /* An RX interface is an object with one or more MAC addresses and
 527  * filtering capabilities. */
 528 struct be_cmd_req_if_create {
 529         struct be_cmd_req_hdr hdr;
 530         u32 version;            /* ignore currently */
 531         u32 capability_flags;
 532         u32 enable_flags;
 533         u8 mac_addr[ETH_ALEN];
 534         u8 rsvd0;
 535         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 536         u32 vlan_tag;    /* not used currently */
 537 } __packed;
 538
 539 struct be_cmd_resp_if_create {
 540         struct be_cmd_resp_hdr hdr;
 541         u32 interface_id;
 542         u32 pmac_id;
 543 };
 544
 545 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 546 struct be_cmd_req_if_destroy {
 547         struct be_cmd_req_hdr hdr;
 548         u32 interface_id;
 549 };
 550
 551 /*************** HW Stats Get **********************************/
 552 struct be_port_rxf_stats {
 553         u32 rx_bytes_lsd;       /* dword 0*/
 554         u32 rx_bytes_msd;       /* dword 1*/
 555         u32 rx_total_frames;    /* dword 2*/
 556         u32 rx_unicast_frames;  /* dword 3*/
 557         u32 rx_multicast_frames;        /* dword 4*/
 558         u32 rx_broadcast_frames;        /* dword 5*/
 559         u32 rx_crc_errors;      /* dword 6*/
 560         u32 rx_alignment_symbol_errors; /* dword 7*/
 561         u32 rx_pause_frames;    /* dword 8*/
 562         u32 rx_control_frames;  /* dword 9*/
 563         u32 rx_in_range_errors; /* dword 10*/
 564         u32 rx_out_range_errors;        /* dword 11*/
 565         u32 rx_frame_too_long;  /* dword 12*/
 566         u32 rx_address_match_errors;    /* dword 13*/
 567         u32 rx_vlan_mismatch;   /* dword 14*/
 568         u32 rx_dropped_too_small;       /* dword 15*/
 569         u32 rx_dropped_too_short;       /* dword 16*/
 570         u32 rx_dropped_header_too_small;        /* dword 17*/
 571         u32 rx_dropped_tcp_length;      /* dword 18*/
 572         u32 rx_dropped_runt;    /* dword 19*/
 573         u32 rx_64_byte_packets; /* dword 20*/
 574         u32 rx_65_127_byte_packets;     /* dword 21*/
 575         u32 rx_128_256_byte_packets;    /* dword 22*/
 576         u32 rx_256_511_byte_packets;    /* dword 23*/
 577         u32 rx_512_1023_byte_packets;   /* dword 24*/
 578         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 579         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 580         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 581         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 582         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 583         u32 rx_ip_checksum_errs;        /* dword 30*/
 584         u32 rx_tcp_checksum_errs;       /* dword 31*/
 585         u32 rx_udp_checksum_errs;       /* dword 32*/
 586         u32 rx_non_rss_packets; /* dword 33*/
 587         u32 rx_ipv4_packets;    /* dword 34*/
 588         u32 rx_ipv6_packets;    /* dword 35*/
 589         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 590         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 591         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 592         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 593         u32 rx_chute1_packets;  /* dword 40*/
 594         u32 rx_chute2_packets;  /* dword 41*/
 595         u32 rx_chute3_packets;  /* dword 42*/
 596         u32 rx_management_packets;      /* dword 43*/
 597         u32 rx_switched_unicast_packets;        /* dword 44*/
 598         u32 rx_switched_multicast_packets;      /* dword 45*/
 599         u32 rx_switched_broadcast_packets;      /* dword 46*/
 600         u32 tx_bytes_lsd;       /* dword 47*/
 601         u32 tx_bytes_msd;       /* dword 48*/
 602         u32 tx_unicastframes;   /* dword 49*/
 603         u32 tx_multicastframes; /* dword 50*/
 604         u32 tx_broadcastframes; /* dword 51*/
 605         u32 tx_pauseframes;     /* dword 52*/
 606         u32 tx_controlframes;   /* dword 53*/
 607         u32 tx_64_byte_packets; /* dword 54*/
 608         u32 tx_65_127_byte_packets;     /* dword 55*/
 609         u32 tx_128_256_byte_packets;    /* dword 56*/
 610         u32 tx_256_511_byte_packets;    /* dword 57*/
 611         u32 tx_512_1023_byte_packets;   /* dword 58*/
 612         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 613         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 614         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 615         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 616         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 617         u32 rx_fifo_overflow;   /* dword 64*/
 618         u32 rx_input_fifo_overflow;     /* dword 65*/
 619 };
 620
 621 struct be_rxf_stats {
 622         struct be_port_rxf_stats port[2];
 623         u32 rx_drops_no_pbuf;   /* dword 132*/
 624         u32 rx_drops_no_txpb;   /* dword 133*/
 625         u32 rx_drops_no_erx_descr;      /* dword 134*/
 626         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 627         u32 management_rx_port_packets; /* dword 136*/
 628         u32 management_rx_port_bytes;   /* dword 137*/
 629         u32 management_rx_port_pause_frames;    /* dword 138*/
 630         u32 management_rx_port_errors;  /* dword 139*/
 631         u32 management_tx_port_packets; /* dword 140*/
 632         u32 management_tx_port_bytes;   /* dword 141*/
 633         u32 management_tx_port_pause;   /* dword 142*/
 634         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 635         u32 rx_drops_too_many_frags;    /* dword 144*/
 636         u32 rx_drops_invalid_ring;      /* dword 145*/
 637         u32 forwarded_packets;  /* dword 146*/
 638         u32 rx_drops_mtu;       /* dword 147*/
 639         u32 rsvd0[7];
 640         u32 port0_jabber_events;
 641         u32 port1_jabber_events;
 642         u32 rsvd1[6];
 643 };
 644
 645 struct be_erx_stats {
 646         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 647         u32 debug_wdma_sent_hold;          /* dword 44*/
 648         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 649         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 650         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 651 };
 652
 653 struct be_pmem_stats {
 654         u32 eth_red_drops;
 655         u32 rsvd[4];
 656 };
 657
 658 struct be_hw_stats {
 659         struct be_rxf_stats rxf;
 660         u32 rsvd[48];
 661         struct be_erx_stats erx;
 662         struct be_pmem_stats pmem;
 663 };
 664
 665 struct be_cmd_req_get_stats {
 666         struct be_cmd_req_hdr hdr;
 667         u8 rsvd[sizeof(struct be_hw_stats)];
 668 };
 669
 670 struct be_cmd_resp_get_stats {
 671         struct be_cmd_resp_hdr hdr;
 672         struct be_hw_stats hw_stats;
 673 };
 674
 675 struct be_cmd_req_get_cntl_addnl_attribs {
 676         struct be_cmd_req_hdr hdr;
 677         u8 rsvd[8];
 678 };
 679
 680 struct be_cmd_resp_get_cntl_addnl_attribs {
 681         struct be_cmd_resp_hdr hdr;
 682         u16 ipl_file_number;
 683         u8 ipl_file_version;
 684         u8 rsvd0;
 685         u8 on_die_temperature; /* in degrees centigrade*/
 686         u8 rsvd1[3];
 687 };
 688
 689 struct be_cmd_req_vlan_config {
 690         struct be_cmd_req_hdr hdr;
 691         u8 interface_id;
 692         u8 promiscuous;
 693         u8 untagged;
 694         u8 num_vlan;
 695         u16 normal_vlan[64];
 696 } __packed;
 697
 698 struct be_cmd_req_promiscuous_config {
 699         struct be_cmd_req_hdr hdr;
 700         u8 port0_promiscuous;
 701         u8 port1_promiscuous;
 702         u16 rsvd0;
 703 } __packed;
 704
 705 /******************** Multicast MAC Config *******************/
 706 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 707 struct macaddr {
 708         u8 byte[ETH_ALEN];
 709 };
 710
 711 struct be_cmd_req_mcast_mac_config {
 712         struct be_cmd_req_hdr hdr;
 713         u16 num_mac;
 714         u8 promiscuous;
 715         u8 interface_id;
 716         struct macaddr mac[BE_MAX_MC];
 717 } __packed;
 718
 719 static inline struct be_hw_stats *
 720 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 721 {
 722         return &cmd->hw_stats;
 723 }
 724
 725 /******************** Link Status Query *******************/
 726 struct be_cmd_req_link_status {
 727         struct be_cmd_req_hdr hdr;
 728         u32 rsvd;
 729 };
 730
 731 enum {
 732         PHY_LINK_DUPLEX_NONE = 0x0,
 733         PHY_LINK_DUPLEX_HALF = 0x1,
 734         PHY_LINK_DUPLEX_FULL = 0x2
 735 };
 736
 737 enum {
 738         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 739         PHY_LINK_SPEED_10MBPS = 0x1,
 740         PHY_LINK_SPEED_100MBPS = 0x2,
 741         PHY_LINK_SPEED_1GBPS = 0x3,
 742         PHY_LINK_SPEED_10GBPS = 0x4
 743 };
 744
 745 struct be_cmd_resp_link_status {
 746         struct be_cmd_resp_hdr hdr;
 747         u8 physical_port;
 748         u8 mac_duplex;
 749         u8 mac_speed;
 750         u8 mac_fault;
 751         u8 mgmt_mac_duplex;
 752         u8 mgmt_mac_speed;
 753         u16 link_speed;
 754         u32 rsvd0;
 755 } __packed;
 756
 757 /******************** Port Identification ***************************/
 758 /*    Identifies the type of port attached to NIC     */
 759 struct be_cmd_req_port_type {
 760         struct be_cmd_req_hdr hdr;
 761         u32 page_num;
 762         u32 port;
 763 };
 764
 765 enum {
 766         TR_PAGE_A0 = 0xa0,
 767         TR_PAGE_A2 = 0xa2
 768 };
 769
 770 struct be_cmd_resp_port_type {
 771         struct be_cmd_resp_hdr hdr;
 772         u32 page_num;
 773         u32 port;
 774         struct data {
 775                 u8 identifier;
 776                 u8 identifier_ext;
 777                 u8 connector;
 778                 u8 transceiver[8];
 779                 u8 rsvd0[3];
 780                 u8 length_km;
 781                 u8 length_hm;
 782                 u8 length_om1;
 783                 u8 length_om2;
 784                 u8 length_cu;
 785                 u8 length_cu_m;
 786                 u8 vendor_name[16];
 787                 u8 rsvd;
 788                 u8 vendor_oui[3];
 789                 u8 vendor_pn[16];
 790                 u8 vendor_rev[4];
 791         } data;
 792 };
 793
 794 /******************** Get FW Version *******************/
 795 struct be_cmd_req_get_fw_version {
 796         struct be_cmd_req_hdr hdr;
 797         u8 rsvd0[FW_VER_LEN];
 798         u8 rsvd1[FW_VER_LEN];
 799 } __packed;
 800
 801 struct be_cmd_resp_get_fw_version {
 802         struct be_cmd_resp_hdr hdr;
 803         u8 firmware_version_string[FW_VER_LEN];
 804         u8 fw_on_flash_version_string[FW_VER_LEN];
 805 } __packed;
 806
 807 /******************** Set Flow Contrl *******************/
 808 struct be_cmd_req_set_flow_control {
 809         struct be_cmd_req_hdr hdr;
 810         u16 tx_flow_control;
 811         u16 rx_flow_control;
 812 } __packed;
 813
 814 /******************** Get Flow Contrl *******************/
 815 struct be_cmd_req_get_flow_control {
 816         struct be_cmd_req_hdr hdr;
 817         u32 rsvd;
 818 };
 819
 820 struct be_cmd_resp_get_flow_control {
 821         struct be_cmd_resp_hdr hdr;
 822         u16 tx_flow_control;
 823         u16 rx_flow_control;
 824 } __packed;
 825
 826 /******************** Modify EQ Delay *******************/
 827 struct be_cmd_req_modify_eq_delay {
 828         struct be_cmd_req_hdr hdr;
 829         u32 num_eq;
 830         struct {
 831                 u32 eq_id;
 832                 u32 phase;
 833                 u32 delay_multiplier;
 834         } delay[8];
 835 } __packed;
 836
 837 struct be_cmd_resp_modify_eq_delay {
 838         struct be_cmd_resp_hdr hdr;
 839         u32 rsvd0;
 840 } __packed;
 841
 842 /******************** Get FW Config *******************/
 843 #define BE_FUNCTION_CAPS_RSS                    0x2
 844 struct be_cmd_req_query_fw_cfg {
 845         struct be_cmd_req_hdr hdr;
 846         u32 rsvd[31];
 847 };
 848
 849 struct be_cmd_resp_query_fw_cfg {
 850         struct be_cmd_resp_hdr hdr;
 851         u32 be_config_number;
 852         u32 asic_revision;
 853         u32 phys_port;
 854         u32 function_mode;
 855         u32 rsvd[26];
 856         u32 function_caps;
 857 };
 858
 859 /******************** RSS Config *******************/
 860 /* RSS types */
 861 #define RSS_ENABLE_NONE                         0x0
 862 #define RSS_ENABLE_IPV4                         0x1
 863 #define RSS_ENABLE_TCP_IPV4                     0x2
 864 #define RSS_ENABLE_IPV6                         0x4
 865 #define RSS_ENABLE_TCP_IPV6                     0x8
 866
 867 struct be_cmd_req_rss_config {
 868         struct be_cmd_req_hdr hdr;
 869         u32 if_id;
 870         u16 enable_rss;
 871         u16 cpu_table_size_log2;
 872         u32 hash[10];
 873         u8 cpu_table[128];
 874         u8 flush;
 875         u8 rsvd0[3];
 876 };
 877
 878 /******************** Port Beacon ***************************/
 879
 880 #define BEACON_STATE_ENABLED            0x1
 881 #define BEACON_STATE_DISABLED           0x0
 882
 883 struct be_cmd_req_enable_disable_beacon {
 884         struct be_cmd_req_hdr hdr;
 885         u8  port_num;
 886         u8  beacon_state;
 887         u8  beacon_duration;
 888         u8  status_duration;
 889 } __packed;
 890
 891 struct be_cmd_resp_enable_disable_beacon {
 892         struct be_cmd_resp_hdr resp_hdr;
 893         u32 rsvd0;
 894 } __packed;
 895
 896 struct be_cmd_req_get_beacon_state {
 897         struct be_cmd_req_hdr hdr;
 898         u8  port_num;
 899         u8  rsvd0;
 900         u16 rsvd1;
 901 } __packed;
 902
 903 struct be_cmd_resp_get_beacon_state {
 904         struct be_cmd_resp_hdr resp_hdr;
 905         u8 beacon_state;
 906         u8 rsvd0[3];
 907 } __packed;
 908
 909 /****************** Firmware Flash ******************/
 910 struct flashrom_params {
 911         u32 op_code;
 912         u32 op_type;
 913         u32 data_buf_size;
 914         u32 offset;
 915         u8 data_buf[4];
 916 };
 917
 918 struct be_cmd_write_flashrom {
 919         struct be_cmd_req_hdr hdr;
 920         struct flashrom_params params;
 921 };
 922
 923 /************************ WOL *******************************/
 924 struct be_cmd_req_acpi_wol_magic_config{
 925         struct be_cmd_req_hdr hdr;
 926         u32 rsvd0[145];
 927         u8 magic_mac[6];
 928         u8 rsvd2[2];
 929 } __packed;
 930
 931 /********************** LoopBack test *********************/
 932 struct be_cmd_req_loopback_test {
 933         struct be_cmd_req_hdr hdr;
 934         u32 loopback_type;
 935         u32 num_pkts;
 936         u64 pattern;
 937         u32 src_port;
 938         u32 dest_port;
 939         u32 pkt_size;
 940 };
 941
 942 struct be_cmd_resp_loopback_test {
 943         struct be_cmd_resp_hdr resp_hdr;
 944         u32    status;
 945         u32    num_txfer;
 946         u32    num_rx;
 947         u32    miscomp_off;
 948         u32    ticks_compl;
 949 };
 950
 951 struct be_cmd_req_set_lmode {
 952         struct be_cmd_req_hdr hdr;
 953         u8 src_port;
 954         u8 dest_port;
 955         u8 loopback_type;
 956         u8 loopback_state;
 957 };
 958
 959 struct be_cmd_resp_set_lmode {
 960         struct be_cmd_resp_hdr resp_hdr;
 961         u8 rsvd0[4];
 962 };
 963
 964 /********************** DDR DMA test *********************/
 965 struct be_cmd_req_ddrdma_test {
 966         struct be_cmd_req_hdr hdr;
 967         u64 pattern;
 968         u32 byte_count;
 969         u32 rsvd0;
 970         u8  snd_buff[4096];
 971         u8  rsvd1[4096];
 972 };
 973
 974 struct be_cmd_resp_ddrdma_test {
 975         struct be_cmd_resp_hdr hdr;
 976         u64 pattern;
 977         u32 byte_cnt;
 978         u32 snd_err;
 979         u8  rsvd0[4096];
 980         u8  rcv_buff[4096];
 981 };
 982
 983 /*********************** SEEPROM Read ***********************/
 984
 985 #define BE_READ_SEEPROM_LEN 1024
 986 struct be_cmd_req_seeprom_read {
 987         struct be_cmd_req_hdr hdr;
 988         u8 rsvd0[BE_READ_SEEPROM_LEN];
 989 };
 990
 991 struct be_cmd_resp_seeprom_read {
 992         struct be_cmd_req_hdr hdr;
 993         u8 seeprom_data[BE_READ_SEEPROM_LEN];
 994 };
 995
 996 enum {
 997         PHY_TYPE_CX4_10GB = 0,
 998         PHY_TYPE_XFP_10GB,
 999         PHY_TYPE_SFP_1GB,
1000         PHY_TYPE_SFP_PLUS_10GB,
1001         PHY_TYPE_KR_10GB,
1002         PHY_TYPE_KX4_10GB,
1003         PHY_TYPE_BASET_10GB,
1004         PHY_TYPE_BASET_1GB,
1005         PHY_TYPE_DISABLED = 255
1006 };
1007
1008 struct be_cmd_req_get_phy_info {
1009         struct be_cmd_req_hdr hdr;
1010         u8 rsvd0[24];
1011 };
1012 struct be_cmd_resp_get_phy_info {
1013         struct be_cmd_req_hdr hdr;
1014         u16 phy_type;
1015         u16 interface_type;
1016         u32 misc_params;
1017         u32 future_use[4];
1018 };
1019
1020 /*********************** Set QOS ***********************/
1021
1022 #define BE_QOS_BITS_NIC                         1
1023
1024 struct be_cmd_req_set_qos {
1025         struct be_cmd_req_hdr hdr;
1026         u32 valid_bits;
1027         u32 max_bps_nic;
1028         u32 rsvd[7];
1029 };
1030
1031 struct be_cmd_resp_set_qos {
1032         struct be_cmd_resp_hdr hdr;
1033         u32 rsvd;
1034 };
1035
1036 /*********************** Controller Attributes ***********************/
1037 struct be_cmd_req_cntl_attribs {
1038         struct be_cmd_req_hdr hdr;
1039 };
1040
1041 struct be_cmd_resp_cntl_attribs {
1042         struct be_cmd_resp_hdr hdr;
1043         struct mgmt_controller_attrib attribs;
1044 };
1045
1046 /*********************** Set driver function ***********************/
1047 #define CAPABILITY_SW_TIMESTAMPS        2
1048 #define CAPABILITY_BE3_NATIVE_ERX_API   4
1049
1050 struct be_cmd_req_set_func_cap {
1051         struct be_cmd_req_hdr hdr;
1052         u32 valid_cap_flags;
1053         u32 cap_flags;
1054         u8 rsvd[212];
1055 };
1056
1057 struct be_cmd_resp_set_func_cap {
1058         struct be_cmd_resp_hdr hdr;
1059         u32 valid_cap_flags;
1060         u32 cap_flags;
1061         u8 rsvd[212];
1062 };
1063
1064 extern int be_pci_fnum_get(struct be_adapter *adapter);
1065 extern int be_cmd_POST(struct be_adapter *adapter);
1066 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1067                         u8 type, bool permanent, u32 if_handle);
1068 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1069                         u32 if_id, u32 *pmac_id, u32 domain);
1070 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1071                         u32 pmac_id, u32 domain);
1072 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1073                         u32 en_flags, u8 *mac, bool pmac_invalid,
1074                         u32 *if_handle, u32 *pmac_id, u32 domain);
1075 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1076                         u32 domain);
1077 extern int be_cmd_eq_create(struct be_adapter *adapter,
1078                         struct be_queue_info *eq, int eq_delay);
1079 extern int be_cmd_cq_create(struct be_adapter *adapter,
1080                         struct be_queue_info *cq, struct be_queue_info *eq,
1081                         bool sol_evts, bool no_delay,
1082                         int num_cqe_dma_coalesce);
1083 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1084                         struct be_queue_info *mccq,
1085                         struct be_queue_info *cq);
1086 extern int be_cmd_txq_create(struct be_adapter *adapter,
1087                         struct be_queue_info *txq,
1088                         struct be_queue_info *cq);
1089 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1090                         struct be_queue_info *rxq, u16 cq_id,
1091                         u16 frag_size, u16 max_frame_size, u32 if_id,
1092                         u32 rss, u8 *rss_id);
1093 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1094                         int type);
1095 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1096                         bool *link_up, u8 *mac_speed, u16 *link_speed);
1097 extern int be_cmd_reset(struct be_adapter *adapter);
1098 extern int be_cmd_get_stats(struct be_adapter *adapter,
1099                         struct be_dma_mem *nonemb_cmd);
1100 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1101
1102 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1103 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1104                         u16 *vtag_array, u32 num, bool untagged,
1105                         bool promiscuous);
1106 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
1107                         u8 port_num, bool en);
1108 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1109                         struct net_device *netdev, struct be_dma_mem *mem);
1110 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1111                         u32 tx_fc, u32 rx_fc);
1112 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1113                         u32 *tx_fc, u32 *rx_fc);
1114 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1115                         u32 *port_num, u32 *function_mode, u32 *function_caps);
1116 extern int be_cmd_reset_function(struct be_adapter *adapter);
1117 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1118                         u16 table_size);
1119 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1120 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1121                         u8 port_num, u8 beacon, u8 status, u8 state);
1122 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1123                         u8 port_num, u32 *state);
1124 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1125                         struct be_dma_mem *cmd, u32 flash_oper,
1126                         u32 flash_opcode, u32 buf_size);
1127 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1128                                 int offset);
1129 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1130                                 struct be_dma_mem *nonemb_cmd);
1131 extern int be_cmd_fw_init(struct be_adapter *adapter);
1132 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1133 extern void be_async_mcc_enable(struct be_adapter *adapter);
1134 extern void be_async_mcc_disable(struct be_adapter *adapter);
1135 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1136                                 u32 loopback_type, u32 pkt_size,
1137                                 u32 num_pkts, u64 pattern);
1138 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1139                         u32 byte_cnt, struct be_dma_mem *cmd);
1140 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1141                                 struct be_dma_mem *nonemb_cmd);
1142 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1143                                 u8 loopback_type, u8 enable);
1144 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1145                 struct be_dma_mem *cmd);
1146 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1147 extern void be_detect_dump_ue(struct be_adapter *adapter);
1148 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1149 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1150 extern int be_cmd_check_native_mode(struct be_adapter *adapter);
1151