drivers/net/benet/be_hw.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /********* Mailbox door bell *************/
  19 /* Used for driver communication with the FW.
  20  * The software must write this register twice to post any command. First,
  21  * it writes the register with hi=1 and the upper bits of the physical address
  22  * for the MAILBOX structure. Software must poll the ready bit until this
  23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
  24  * bits in the address. It must poll the ready bit until the command is
  25  * complete. Upon completion, the MAILBOX will contain a valid completion
  26  * queue entry.
  27  */
  28 #define MPU_MAILBOX_DB_OFFSET   0x160
  29 #define MPU_MAILBOX_DB_RDY_MASK 0x1     /* bit 0 */
  30 #define MPU_MAILBOX_DB_HI_MASK  0x2     /* bit 1 */
  31
  32 #define MPU_EP_CONTROL          0
  33
  34 /********** MPU semphore ******************/
  35 #define MPU_EP_SEMAPHORE_OFFSET         0xac
  36 #define EP_SEMAPHORE_POST_STAGE_MASK    0x0000FFFF
  37 #define EP_SEMAPHORE_POST_ERR_MASK      0x1
  38 #define EP_SEMAPHORE_POST_ERR_SHIFT     31
  39 /* MPU semphore POST stage values */
  40 #define POST_STAGE_AWAITING_HOST_RDY    0x1 /* FW awaiting goahead from host */
  41 #define POST_STAGE_HOST_RDY             0x2 /* Host has given go-ahed to FW */
  42 #define POST_STAGE_BE_RESET             0x3 /* Host wants to reset chip */
  43 #define POST_STAGE_ARMFW_RDY            0xc000  /* FW is done with POST */
  44
  45 /********* Memory BAR register ************/
  46 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
  47 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  48  * Disable" may still globally block interrupts in addition to individual
  49  * interrupt masks; a mechanism for the device driver to block all interrupts
  50  * atomically without having to arbitrate for the PCI Interrupt Disable bit
  51  * with the OS.
  52  */
  53 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29) /* bit 29 */
  54 /* PCI physical function number */
  55 #define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK         0x7     /* bits 26 - 28 */
  56 #define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT        26
  57
  58 /********* ISR0 Register offset **********/
  59 #define CEV_ISR0_OFFSET                         0xC18
  60 #define CEV_ISR_SIZE                            4
  61
  62 /********* Event Q door bell *************/
  63 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
  64 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
  65 /* Clear the interrupt for this eq */
  66 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
  67 /* Must be 1 */
  68 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
  69 /* Number of event entries processed */
  70 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
  71 /* Rearm bit */
  72 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
  73
  74 /********* Compl Q door bell *************/
  75 #define DB_CQ_OFFSET                    0x120
  76 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
  77 /* Number of event entries processed */
  78 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
  79 /* Rearm bit */
  80 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
  81
  82 /********** TX ULP door bell *************/
  83 #define DB_TXULP1_OFFSET                0x60
  84 #define DB_TXULP_RING_ID_MASK           0x7FF   /* bits 0 - 10 */
  85 /* Number of tx entries posted */
  86 #define DB_TXULP_NUM_POSTED_SHIFT       (16)    /* bits 16 - 29 */
  87 #define DB_TXULP_NUM_POSTED_MASK        0x3FFF  /* bits 16 - 29 */
  88
  89 /********** RQ(erx) door bell ************/
  90 #define DB_RQ_OFFSET                    0x100
  91 #define DB_RQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
  92 /* Number of rx frags posted */
  93 #define DB_RQ_NUM_POSTED_SHIFT          (24)    /* bits 24 - 31 */
  94
  95 /********** MCC door bell ************/
  96 #define DB_MCCQ_OFFSET                  0x140
  97 #define DB_MCCQ_RING_ID_MASK            0x7FF   /* bits 0 - 10 */
  98 /* Number of entries posted */
  99 #define DB_MCCQ_NUM_POSTED_SHIFT        (16)    /* bits 16 - 29 */
 100
 101 /*
 102  * BE descriptors: host memory data structures whose formats
 103  * are hardwired in BE silicon.
 104  */
 105 /* Event Queue Descriptor */
 106 #define EQ_ENTRY_VALID_MASK             0x1     /* bit 0 */
 107 #define EQ_ENTRY_RES_ID_MASK            0xFFFF  /* bits 16 - 31 */
 108 #define EQ_ENTRY_RES_ID_SHIFT           16
 109 struct be_eq_entry {
 110         u32 evt;
 111 };
 112
 113 /* TX Queue Descriptor */
 114 #define ETH_WRB_FRAG_LEN_MASK           0xFFFF
 115 struct be_eth_wrb {
 116         u32 frag_pa_hi;         /* dword 0 */
 117         u32 frag_pa_lo;         /* dword 1 */
 118         u32 rsvd0;              /* dword 2 */
 119         u32 frag_len;           /* dword 3: bits 0 - 15 */
 120 } __packed;
 121
 122 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 123  * actual structure is defined as a byte : used to calculate
 124  * offset/shift/mask of each field */
 125 struct amap_eth_hdr_wrb {
 126         u8 rsvd0[32];           /* dword 0 */
 127         u8 rsvd1[32];           /* dword 1 */
 128         u8 complete;            /* dword 2 */
 129         u8 event;
 130         u8 crc;
 131         u8 forward;
 132         u8 ipsec;
 133         u8 mgmt;
 134         u8 ipcs;
 135         u8 udpcs;
 136         u8 tcpcs;
 137         u8 lso;
 138         u8 vlan;
 139         u8 gso[2];
 140         u8 num_wrb[5];
 141         u8 lso_mss[14];
 142         u8 len[16];             /* dword 3 */
 143         u8 vlan_tag[16];
 144 } __packed;
 145
 146 struct be_eth_hdr_wrb {
 147         u32 dw[4];
 148 };
 149
 150 /* TX Compl Queue Descriptor */
 151
 152 /* Pseudo amap definition for eth_tx_compl in which each bit of the
 153  * actual structure is defined as a byte: used to calculate
 154  * offset/shift/mask of each field */
 155 struct amap_eth_tx_compl {
 156         u8 wrb_index[16];       /* dword 0 */
 157         u8 ct[2];               /* dword 0 */
 158         u8 port[2];             /* dword 0 */
 159         u8 rsvd0[8];            /* dword 0 */
 160         u8 status[4];           /* dword 0 */
 161         u8 user_bytes[16];      /* dword 1 */
 162         u8 nwh_bytes[8];        /* dword 1 */
 163         u8 lso;                 /* dword 1 */
 164         u8 cast_enc[2];         /* dword 1 */
 165         u8 rsvd1[5];            /* dword 1 */
 166         u8 rsvd2[32];           /* dword 2 */
 167         u8 pkts[16];            /* dword 3 */
 168         u8 ringid[11];          /* dword 3 */
 169         u8 hash_val[4];         /* dword 3 */
 170         u8 valid;               /* dword 3 */
 171 } __packed;
 172
 173 struct be_eth_tx_compl {
 174         u32 dw[4];
 175 };
 176
 177 /* RX Queue Descriptor */
 178 struct be_eth_rx_d {
 179         u32 fragpa_hi;
 180         u32 fragpa_lo;
 181 };
 182
 183 /* RX Compl Queue Descriptor */
 184
 185 /* Pseudo amap definition for eth_rx_compl in which each bit of the
 186  * actual structure is defined as a byte: used to calculate
 187  * offset/shift/mask of each field */
 188 struct amap_eth_rx_compl {
 189         u8 vlan_tag[16];        /* dword 0 */
 190         u8 pktsize[14];         /* dword 0 */
 191         u8 port;                /* dword 0 */
 192         u8 ip_opt;              /* dword 0 */
 193         u8 err;                 /* dword 1 */
 194         u8 rsshp;               /* dword 1 */
 195         u8 ipf;                 /* dword 1 */
 196         u8 tcpf;                /* dword 1 */
 197         u8 udpf;                /* dword 1 */
 198         u8 ipcksm;              /* dword 1 */
 199         u8 l4_cksm;             /* dword 1 */
 200         u8 ip_version;          /* dword 1 */
 201         u8 macdst[6];           /* dword 1 */
 202         u8 vtp;                 /* dword 1 */
 203         u8 rsvd0;               /* dword 1 */
 204         u8 fragndx[10];         /* dword 1 */
 205         u8 ct[2];               /* dword 1 */
 206         u8 sw;                  /* dword 1 */
 207         u8 numfrags[3];         /* dword 1 */
 208         u8 rss_flush;           /* dword 2 */
 209         u8 cast_enc[2];         /* dword 2 */
 210         u8 qnq;                 /* dword 2 */
 211         u8 rss_bank;            /* dword 2 */
 212         u8 rsvd1[23];           /* dword 2 */
 213         u8 lro_pkt;             /* dword 2 */
 214         u8 rsvd2[2];            /* dword 2 */
 215         u8 valid;               /* dword 2 */
 216         u8 rsshash[32];         /* dword 3 */
 217 } __packed;
 218
 219 struct be_eth_rx_compl {
 220         u32 dw[4];
 221 };