drivers/net/benet/be_hw.h

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /********* Mailbox door bell *************/
  19 /* Used for driver communication with the FW.
  20  * The software must write this register twice to post any command. First,
  21  * it writes the register with hi=1 and the upper bits of the physical address
  22  * for the MAILBOX structure. Software must poll the ready bit until this
  23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
  24  * bits in the address. It must poll the ready bit until the command is
  25  * complete. Upon completion, the MAILBOX will contain a valid completion
  26  * queue entry.
  27  */
  28 #define MPU_MAILBOX_DB_OFFSET   0x160
  29 #define MPU_MAILBOX_DB_RDY_MASK 0x1     /* bit 0 */
  30 #define MPU_MAILBOX_DB_HI_MASK  0x2     /* bit 1 */
  31
  32 #define MPU_EP_CONTROL          0
  33
  34 /********** MPU semphore ******************/
  35 #define MPU_EP_SEMAPHORE_OFFSET         0xac
  36 #define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET        0x400
  37 #define EP_SEMAPHORE_POST_STAGE_MASK            0x0000FFFF
  38 #define EP_SEMAPHORE_POST_ERR_MASK              0x1
  39 #define EP_SEMAPHORE_POST_ERR_SHIFT             31
  40
  41 /* MPU semphore POST stage values */
  42 #define POST_STAGE_AWAITING_HOST_RDY    0x1 /* FW awaiting goahead from host */
  43 #define POST_STAGE_HOST_RDY             0x2 /* Host has given go-ahed to FW */
  44 #define POST_STAGE_BE_RESET             0x3 /* Host wants to reset chip */
  45 #define POST_STAGE_ARMFW_RDY            0xc000  /* FW is done with POST */
  46
  47
  48 /* Lancer SLIPORT_CONTROL SLIPORT_STATUS registers */
  49 #define SLIPORT_STATUS_OFFSET           0x404
  50 #define SLIPORT_CONTROL_OFFSET          0x408
  51
  52 #define SLIPORT_STATUS_ERR_MASK         0x80000000
  53 #define SLIPORT_STATUS_RN_MASK          0x01000000
  54 #define SLIPORT_STATUS_RDY_MASK         0x00800000
  55
  56
  57 #define SLI_PORT_CONTROL_IP_MASK        0x08000000
  58
  59 /********* Memory BAR register ************/
  60 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
  61 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  62  * Disable" may still globally block interrupts in addition to individual
  63  * interrupt masks; a mechanism for the device driver to block all interrupts
  64  * atomically without having to arbitrate for the PCI Interrupt Disable bit
  65  * with the OS.
  66  */
  67 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29) /* bit 29 */
  68
  69 /********* Power management (WOL) **********/
  70 #define PCICFG_PM_CONTROL_OFFSET                0x44
  71 #define PCICFG_PM_CONTROL_MASK                  0x108   /* bits 3 & 8 */
  72
  73 /********* Online Control Registers *******/
  74 #define PCICFG_ONLINE0                          0xB0
  75 #define PCICFG_ONLINE1                          0xB4
  76
  77 /********* UE Status and Mask Registers ***/
  78 #define PCICFG_UE_STATUS_LOW                    0xA0
  79 #define PCICFG_UE_STATUS_HIGH                   0xA4
  80 #define PCICFG_UE_STATUS_LOW_MASK               0xA8
  81 #define PCICFG_UE_STATUS_HI_MASK                0xAC
  82
  83 /******** SLI_INTF ***********************/
  84 #define SLI_INTF_REG_OFFSET                     0x58
  85 #define SLI_INTF_VALID_MASK                     0xE0000000
  86 #define SLI_INTF_VALID                          0xC0000000
  87 #define SLI_INTF_HINT2_MASK                     0x1F000000
  88 #define SLI_INTF_HINT2_SHIFT                    24
  89 #define SLI_INTF_HINT1_MASK                     0x00FF0000
  90 #define SLI_INTF_HINT1_SHIFT                    16
  91 #define SLI_INTF_FAMILY_MASK                    0x00000F00
  92 #define SLI_INTF_FAMILY_SHIFT                   8
  93 #define SLI_INTF_IF_TYPE_MASK                   0x0000F000
  94 #define SLI_INTF_IF_TYPE_SHIFT                  12
  95 #define SLI_INTF_REV_MASK                       0x000000F0
  96 #define SLI_INTF_REV_SHIFT                      4
  97 #define SLI_INTF_FT_MASK                        0x00000001
  98
  99
 100 /* SLI family */
 101 #define BE_SLI_FAMILY           0x0
 102 #define LANCER_A0_SLI_FAMILY    0xA
 103
 104
 105 /********* ISR0 Register offset **********/
 106 #define CEV_ISR0_OFFSET                         0xC18
 107 #define CEV_ISR_SIZE                            4
 108
 109 /********* Event Q door bell *************/
 110 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 111 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
 112 #define DB_EQ_RING_ID_EXT_MASK          0x3e00  /* bits 9-13 */
 113 #define DB_EQ_RING_ID_EXT_MASK_SHIFT    (2) /* qid bits 9-13 placing at 11-15 */
 114
 115 /* Clear the interrupt for this eq */
 116 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 117 /* Must be 1 */
 118 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 119 /* Number of event entries processed */
 120 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 121 /* Rearm bit */
 122 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 123
 124 /********* Compl Q door bell *************/
 125 #define DB_CQ_OFFSET                    0x120
 126 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 127 #define DB_CQ_RING_ID_EXT_MASK          0x7C00  /* bits 10-14 */
 128 #define DB_CQ_RING_ID_EXT_MASK_SHIFT    (1)     /* qid bits 10-14
 129                                                  placing at 11-15 */
 130
 131 /* Number of event entries processed */
 132 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 133 /* Rearm bit */
 134 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 135
 136 /********** TX ULP door bell *************/
 137 #define DB_TXULP1_OFFSET                0x60
 138 #define DB_TXULP_RING_ID_MASK           0x7FF   /* bits 0 - 10 */
 139 /* Number of tx entries posted */
 140 #define DB_TXULP_NUM_POSTED_SHIFT       (16)    /* bits 16 - 29 */
 141 #define DB_TXULP_NUM_POSTED_MASK        0x3FFF  /* bits 16 - 29 */
 142
 143 /********** RQ(erx) door bell ************/
 144 #define DB_RQ_OFFSET                    0x100
 145 #define DB_RQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 146 /* Number of rx frags posted */
 147 #define DB_RQ_NUM_POSTED_SHIFT          (24)    /* bits 24 - 31 */
 148
 149 /********** MCC door bell ************/
 150 #define DB_MCCQ_OFFSET                  0x140
 151 #define DB_MCCQ_RING_ID_MASK            0x7FF   /* bits 0 - 10 */
 152 /* Number of entries posted */
 153 #define DB_MCCQ_NUM_POSTED_SHIFT        (16)    /* bits 16 - 29 */
 154
 155 /********** SRIOV VF PCICFG OFFSET ********/
 156 #define SRIOV_VF_PCICFG_OFFSET          (4096)
 157
 158 /* Flashrom related descriptors */
 159 #define IMAGE_TYPE_FIRMWARE             160
 160 #define IMAGE_TYPE_BOOTCODE             224
 161 #define IMAGE_TYPE_OPTIONROM            32
 162
 163 #define NUM_FLASHDIR_ENTRIES            32
 164
 165 #define IMG_TYPE_ISCSI_ACTIVE           0
 166 #define IMG_TYPE_REDBOOT                1
 167 #define IMG_TYPE_BIOS                   2
 168 #define IMG_TYPE_PXE_BIOS               3
 169 #define IMG_TYPE_FCOE_BIOS              8
 170 #define IMG_TYPE_ISCSI_BACKUP           9
 171 #define IMG_TYPE_FCOE_FW_ACTIVE         10
 172 #define IMG_TYPE_FCOE_FW_BACKUP         11
 173 #define IMG_TYPE_NCSI_FW                13
 174
 175 #define FLASHROM_OPER_FLASH             1
 176 #define FLASHROM_OPER_SAVE              2
 177 #define FLASHROM_OPER_REPORT            4
 178
 179 #define FLASH_IMAGE_MAX_SIZE_g2            (1310720) /* Max firmware image sz */
 180 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2       (262144)  /* Max OPTION ROM img sz */
 181 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2   (262144)  /* Max Redboot image sz */
 182 #define FLASH_IMAGE_MAX_SIZE_g3            (2097152) /* Max fw image size */
 183 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3       (524288)  /* Max OPTION ROM img sz */
 184 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3   (1048576)  /* Max Redboot image sz */
 185 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3       (262144)  /* Max NSCI image sz */
 186
 187 #define FLASH_NCSI_MAGIC                (0x16032009)
 188 #define FLASH_NCSI_DISABLED             (0)
 189 #define FLASH_NCSI_ENABLED              (1)
 190
 191 #define FLASH_NCSI_BITFILE_HDR_OFFSET   (0x600000)
 192
 193 /* Offsets for components on Flash. */
 194 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
 195 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2  (2359296)
 196 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2  (3670016)
 197 #define FLASH_FCoE_BACKUP_IMAGE_START_g2   (4980736)
 198 #define FLASH_iSCSI_BIOS_START_g2          (7340032)
 199 #define FLASH_PXE_BIOS_START_g2            (7864320)
 200 #define FLASH_FCoE_BIOS_START_g2           (524288)
 201 #define FLASH_REDBOOT_START_g2            (0)
 202
 203 #define FLASH_NCSI_START_g3                (15990784)
 204 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
 205 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3  (4194304)
 206 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3  (6291456)
 207 #define FLASH_FCoE_BACKUP_IMAGE_START_g3   (8388608)
 208 #define FLASH_iSCSI_BIOS_START_g3          (12582912)
 209 #define FLASH_PXE_BIOS_START_g3            (13107200)
 210 #define FLASH_FCoE_BIOS_START_g3           (13631488)
 211 #define FLASH_REDBOOT_START_g3             (262144)
 212
 213 /************* Rx Packet Type Encoding **************/
 214 #define BE_UNICAST_PACKET               0
 215 #define BE_MULTICAST_PACKET             1
 216 #define BE_BROADCAST_PACKET             2
 217 #define BE_RSVD_PACKET                  3
 218
 219 /*
 220  * BE descriptors: host memory data structures whose formats
 221  * are hardwired in BE silicon.
 222  */
 223 /* Event Queue Descriptor */
 224 #define EQ_ENTRY_VALID_MASK             0x1     /* bit 0 */
 225 #define EQ_ENTRY_RES_ID_MASK            0xFFFF  /* bits 16 - 31 */
 226 #define EQ_ENTRY_RES_ID_SHIFT           16
 227
 228 struct be_eq_entry {
 229         u32 evt;
 230 };
 231
 232 /* TX Queue Descriptor */
 233 #define ETH_WRB_FRAG_LEN_MASK           0xFFFF
 234 struct be_eth_wrb {
 235         u32 frag_pa_hi;         /* dword 0 */
 236         u32 frag_pa_lo;         /* dword 1 */
 237         u32 rsvd0;              /* dword 2 */
 238         u32 frag_len;           /* dword 3: bits 0 - 15 */
 239 } __packed;
 240
 241 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 242  * actual structure is defined as a byte : used to calculate
 243  * offset/shift/mask of each field */
 244 struct amap_eth_hdr_wrb {
 245         u8 rsvd0[32];           /* dword 0 */
 246         u8 rsvd1[32];           /* dword 1 */
 247         u8 complete;            /* dword 2 */
 248         u8 event;
 249         u8 crc;
 250         u8 forward;
 251         u8 lso6;
 252         u8 mgmt;
 253         u8 ipcs;
 254         u8 udpcs;
 255         u8 tcpcs;
 256         u8 lso;
 257         u8 vlan;
 258         u8 gso[2];
 259         u8 num_wrb[5];
 260         u8 lso_mss[14];
 261         u8 len[16];             /* dword 3 */
 262         u8 vlan_tag[16];
 263 } __packed;
 264
 265 struct be_eth_hdr_wrb {
 266         u32 dw[4];
 267 };
 268
 269 /* TX Compl Queue Descriptor */
 270
 271 /* Pseudo amap definition for eth_tx_compl in which each bit of the
 272  * actual structure is defined as a byte: used to calculate
 273  * offset/shift/mask of each field */
 274 struct amap_eth_tx_compl {
 275         u8 wrb_index[16];       /* dword 0 */
 276         u8 ct[2];               /* dword 0 */
 277         u8 port[2];             /* dword 0 */
 278         u8 rsvd0[8];            /* dword 0 */
 279         u8 status[4];           /* dword 0 */
 280         u8 user_bytes[16];      /* dword 1 */
 281         u8 nwh_bytes[8];        /* dword 1 */
 282         u8 lso;                 /* dword 1 */
 283         u8 cast_enc[2];         /* dword 1 */
 284         u8 rsvd1[5];            /* dword 1 */
 285         u8 rsvd2[32];           /* dword 2 */
 286         u8 pkts[16];            /* dword 3 */
 287         u8 ringid[11];          /* dword 3 */
 288         u8 hash_val[4];         /* dword 3 */
 289         u8 valid;               /* dword 3 */
 290 } __packed;
 291
 292 struct be_eth_tx_compl {
 293         u32 dw[4];
 294 };
 295
 296 /* RX Queue Descriptor */
 297 struct be_eth_rx_d {
 298         u32 fragpa_hi;
 299         u32 fragpa_lo;
 300 };
 301
 302 /* RX Compl Queue Descriptor */
 303
 304 /* Pseudo amap definition for eth_rx_compl in which each bit of the
 305  * actual structure is defined as a byte: used to calculate
 306  * offset/shift/mask of each field */
 307 struct amap_eth_rx_compl {
 308         u8 vlan_tag[16];        /* dword 0 */
 309         u8 pktsize[14];         /* dword 0 */
 310         u8 port;                /* dword 0 */
 311         u8 ip_opt;              /* dword 0 */
 312         u8 err;                 /* dword 1 */
 313         u8 rsshp;               /* dword 1 */
 314         u8 ipf;                 /* dword 1 */
 315         u8 tcpf;                /* dword 1 */
 316         u8 udpf;                /* dword 1 */
 317         u8 ipcksm;              /* dword 1 */
 318         u8 l4_cksm;             /* dword 1 */
 319         u8 ip_version;          /* dword 1 */
 320         u8 macdst[6];           /* dword 1 */
 321         u8 vtp;                 /* dword 1 */
 322         u8 rsvd0;               /* dword 1 */
 323         u8 fragndx[10];         /* dword 1 */
 324         u8 ct[2];               /* dword 1 */
 325         u8 sw;                  /* dword 1 */
 326         u8 numfrags[3];         /* dword 1 */
 327         u8 rss_flush;           /* dword 2 */
 328         u8 cast_enc[2];         /* dword 2 */
 329         u8 vtm;                 /* dword 2 */
 330         u8 rss_bank;            /* dword 2 */
 331         u8 rsvd1[23];           /* dword 2 */
 332         u8 lro_pkt;             /* dword 2 */
 333         u8 rsvd2[2];            /* dword 2 */
 334         u8 valid;               /* dword 2 */
 335         u8 rsshash[32];         /* dword 3 */
 336 } __packed;
 337
 338 struct be_eth_rx_compl {
 339         u32 dw[4];
 340 };
 341
 342 struct mgmt_hba_attribs {
 343         u8 flashrom_version_string[32];
 344         u8 manufacturer_name[32];
 345         u32 supported_modes;
 346         u32 rsvd0[3];
 347         u8 ncsi_ver_string[12];
 348         u32 default_extended_timeout;
 349         u8 controller_model_number[32];
 350         u8 controller_description[64];
 351         u8 controller_serial_number[32];
 352         u8 ip_version_string[32];
 353         u8 firmware_version_string[32];
 354         u8 bios_version_string[32];
 355         u8 redboot_version_string[32];
 356         u8 driver_version_string[32];
 357         u8 fw_on_flash_version_string[32];
 358         u32 functionalities_supported;
 359         u16 max_cdblength;
 360         u8 asic_revision;
 361         u8 generational_guid[16];
 362         u8 hba_port_count;
 363         u16 default_link_down_timeout;
 364         u8 iscsi_ver_min_max;
 365         u8 multifunction_device;
 366         u8 cache_valid;
 367         u8 hba_status;
 368         u8 max_domains_supported;
 369         u8 phy_port;
 370         u32 firmware_post_status;
 371         u32 hba_mtu[8];
 372         u32 rsvd1[4];
 373 };
 374
 375 struct mgmt_controller_attrib {
 376         struct mgmt_hba_attribs hba_attribs;
 377         u16 pci_vendor_id;
 378         u16 pci_device_id;
 379         u16 pci_sub_vendor_id;
 380         u16 pci_sub_system_id;
 381         u8 pci_bus_number;
 382         u8 pci_device_number;
 383         u8 pci_function_number;
 384         u8 interface_type;
 385         u64 unique_identifier;
 386         u32 rsvd0[5];
 387 };
 388
 389 struct controller_id {
 390         u32 vendor;
 391         u32 device;
 392         u32 subvendor;
 393         u32 subdevice;
 394 };
 395
 396 struct flash_comp {
 397         unsigned long offset;
 398         int optype;
 399         int size;
 400 };
 401
 402 struct image_hdr {
 403         u32 imageid;
 404         u32 imageoffset;
 405         u32 imagelength;
 406         u32 image_checksum;
 407         u8 image_version[32];
 408 };
 409 struct flash_file_hdr_g2 {
 410         u8 sign[32];
 411         u32 cksum;
 412         u32 antidote;
 413         struct controller_id cont_id;
 414         u32 file_len;
 415         u32 chunk_num;
 416         u32 total_chunks;
 417         u32 num_imgs;
 418         u8 build[24];
 419 };
 420
 421 struct flash_file_hdr_g3 {
 422         u8 sign[52];
 423         u8 ufi_version[4];
 424         u32 file_len;
 425         u32 cksum;
 426         u32 antidote;
 427         u32 num_imgs;
 428         u8 build[24];
 429         u8 rsvd[32];
 430 };
 431
 432 struct flash_section_hdr {
 433         u32 format_rev;
 434         u32 cksum;
 435         u32 antidote;
 436         u32 build_no;
 437         u8 id_string[64];
 438         u32 active_entry_mask;
 439         u32 valid_entry_mask;
 440         u32 org_content_mask;
 441         u32 rsvd0;
 442         u32 rsvd1;
 443         u32 rsvd2;
 444         u32 rsvd3;
 445         u32 rsvd4;
 446 };
 447
 448 struct flash_section_entry {
 449         u32 type;
 450         u32 offset;
 451         u32 pad_size;
 452         u32 image_size;
 453         u32 cksum;
 454         u32 entry_point;
 455         u32 rsvd0;
 456         u32 rsvd1;
 457         u8 ver_data[32];
 458 };
 459
 460 struct flash_section_info {
 461         u8 cookie[32];
 462         struct flash_section_hdr fsec_hdr;
 463         struct flash_section_entry fsec_entry[32];
 464 };