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netdev: bfin_mac: invalid data cache only once for each new rx skb buffer
[deliverable/linux.git] / drivers / net / bfin_mac.c
1 /*
2 * Blackfin On-Chip MAC Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/irq.h>
20 #include <linux/io.h>
21 #include <linux/ioport.h>
22 #include <linux/crc32.h>
23 #include <linux/device.h>
24 #include <linux/spinlock.h>
25 #include <linux/mii.h>
26 #include <linux/phy.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/skbuff.h>
31 #include <linux/platform_device.h>
32
33 #include <asm/dma.h>
34 #include <linux/dma-mapping.h>
35
36 #include <asm/div64.h>
37 #include <asm/dpmc.h>
38 #include <asm/blackfin.h>
39 #include <asm/cacheflush.h>
40 #include <asm/portmux.h>
41
42 #include "bfin_mac.h"
43
44 #define DRV_NAME "bfin_mac"
45 #define DRV_VERSION "1.1"
46 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
47 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
48
49 MODULE_AUTHOR(DRV_AUTHOR);
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
53
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
56 # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
57 #else
58 # define bfin_mac_alloc(dma_handle, size) \
59 dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr) \
61 dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
62 #endif
63
64 #define PKT_BUF_SZ 1580
65
66 #define MAX_TIMEOUT_CNT 500
67
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
77
78 #if defined(CONFIG_BFIN_MAC_RMII)
79 static u16 pin_req[] = P_RMII0;
80 #else
81 static u16 pin_req[] = P_MII0;
82 #endif
83
84 static void bfin_mac_disable(void);
85 static void bfin_mac_enable(void);
86
87 static void desc_list_free(void)
88 {
89 struct net_dma_desc_rx *r;
90 struct net_dma_desc_tx *t;
91 int i;
92 #if !defined(CONFIG_BFIN_MAC_USE_L1)
93 dma_addr_t dma_handle = 0;
94 #endif
95
96 if (tx_desc) {
97 t = tx_list_head;
98 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
99 if (t) {
100 if (t->skb) {
101 dev_kfree_skb(t->skb);
102 t->skb = NULL;
103 }
104 t = t->next;
105 }
106 }
107 bfin_mac_free(dma_handle, tx_desc);
108 }
109
110 if (rx_desc) {
111 r = rx_list_head;
112 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
113 if (r) {
114 if (r->skb) {
115 dev_kfree_skb(r->skb);
116 r->skb = NULL;
117 }
118 r = r->next;
119 }
120 }
121 bfin_mac_free(dma_handle, rx_desc);
122 }
123 }
124
125 static int desc_list_init(void)
126 {
127 int i;
128 struct sk_buff *new_skb;
129 #if !defined(CONFIG_BFIN_MAC_USE_L1)
130 /*
131 * This dma_handle is useless in Blackfin dma_alloc_coherent().
132 * The real dma handler is the return value of dma_alloc_coherent().
133 */
134 dma_addr_t dma_handle;
135 #endif
136
137 tx_desc = bfin_mac_alloc(&dma_handle,
138 sizeof(struct net_dma_desc_tx) *
139 CONFIG_BFIN_TX_DESC_NUM);
140 if (tx_desc == NULL)
141 goto init_error;
142
143 rx_desc = bfin_mac_alloc(&dma_handle,
144 sizeof(struct net_dma_desc_rx) *
145 CONFIG_BFIN_RX_DESC_NUM);
146 if (rx_desc == NULL)
147 goto init_error;
148
149 /* init tx_list */
150 tx_list_head = tx_list_tail = tx_desc;
151
152 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
153 struct net_dma_desc_tx *t = tx_desc + i;
154 struct dma_descriptor *a = &(t->desc_a);
155 struct dma_descriptor *b = &(t->desc_b);
156
157 /*
158 * disable DMA
159 * read from memory WNR = 0
160 * wordsize is 32 bits
161 * 6 half words is desc size
162 * large desc flow
163 */
164 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
165 a->start_addr = (unsigned long)t->packet;
166 a->x_count = 0;
167 a->next_dma_desc = b;
168
169 /*
170 * enabled DMA
171 * write to memory WNR = 1
172 * wordsize is 32 bits
173 * disable interrupt
174 * 6 half words is desc size
175 * large desc flow
176 */
177 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
178 b->start_addr = (unsigned long)(&(t->status));
179 b->x_count = 0;
180
181 t->skb = NULL;
182 tx_list_tail->desc_b.next_dma_desc = a;
183 tx_list_tail->next = t;
184 tx_list_tail = t;
185 }
186 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
187 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
188 current_tx_ptr = tx_list_head;
189
190 /* init rx_list */
191 rx_list_head = rx_list_tail = rx_desc;
192
193 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
194 struct net_dma_desc_rx *r = rx_desc + i;
195 struct dma_descriptor *a = &(r->desc_a);
196 struct dma_descriptor *b = &(r->desc_b);
197
198 /* allocate a new skb for next time receive */
199 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
200 if (!new_skb) {
201 printk(KERN_NOTICE DRV_NAME
202 ": init: low on mem - packet dropped\n");
203 goto init_error;
204 }
205 skb_reserve(new_skb, NET_IP_ALIGN);
206 /* Invidate the data cache of skb->data range when it is write back
207 * cache. It will prevent overwritting the new data from DMA
208 */
209 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
210 (unsigned long)new_skb->end);
211 r->skb = new_skb;
212
213 /*
214 * enabled DMA
215 * write to memory WNR = 1
216 * wordsize is 32 bits
217 * disable interrupt
218 * 6 half words is desc size
219 * large desc flow
220 */
221 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
222 /* since RXDWA is enabled */
223 a->start_addr = (unsigned long)new_skb->data - 2;
224 a->x_count = 0;
225 a->next_dma_desc = b;
226
227 /*
228 * enabled DMA
229 * write to memory WNR = 1
230 * wordsize is 32 bits
231 * enable interrupt
232 * 6 half words is desc size
233 * large desc flow
234 */
235 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
236 NDSIZE_6 | DMAFLOW_LARGE;
237 b->start_addr = (unsigned long)(&(r->status));
238 b->x_count = 0;
239
240 rx_list_tail->desc_b.next_dma_desc = a;
241 rx_list_tail->next = r;
242 rx_list_tail = r;
243 }
244 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
245 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
246 current_rx_ptr = rx_list_head;
247
248 return 0;
249
250 init_error:
251 desc_list_free();
252 printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
253 return -ENOMEM;
254 }
255
256
257 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
258
259 /*
260 * MII operations
261 */
262 /* Wait until the previous MDC/MDIO transaction has completed */
263 static void bfin_mdio_poll(void)
264 {
265 int timeout_cnt = MAX_TIMEOUT_CNT;
266
267 /* poll the STABUSY bit */
268 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
269 udelay(1);
270 if (timeout_cnt-- < 0) {
271 printk(KERN_ERR DRV_NAME
272 ": wait MDC/MDIO transaction to complete timeout\n");
273 break;
274 }
275 }
276 }
277
278 /* Read an off-chip register in a PHY through the MDC/MDIO port */
279 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
280 {
281 bfin_mdio_poll();
282
283 /* read mode */
284 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
285 SET_REGAD((u16) regnum) |
286 STABUSY);
287
288 bfin_mdio_poll();
289
290 return (int) bfin_read_EMAC_STADAT();
291 }
292
293 /* Write an off-chip register in a PHY through the MDC/MDIO port */
294 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
295 u16 value)
296 {
297 bfin_mdio_poll();
298
299 bfin_write_EMAC_STADAT((u32) value);
300
301 /* write mode */
302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
304 STAOP |
305 STABUSY);
306
307 bfin_mdio_poll();
308
309 return 0;
310 }
311
312 static int bfin_mdiobus_reset(struct mii_bus *bus)
313 {
314 return 0;
315 }
316
317 static void bfin_mac_adjust_link(struct net_device *dev)
318 {
319 struct bfin_mac_local *lp = netdev_priv(dev);
320 struct phy_device *phydev = lp->phydev;
321 unsigned long flags;
322 int new_state = 0;
323
324 spin_lock_irqsave(&lp->lock, flags);
325 if (phydev->link) {
326 /* Now we make sure that we can be in full duplex mode.
327 * If not, we operate in half-duplex mode. */
328 if (phydev->duplex != lp->old_duplex) {
329 u32 opmode = bfin_read_EMAC_OPMODE();
330 new_state = 1;
331
332 if (phydev->duplex)
333 opmode |= FDMODE;
334 else
335 opmode &= ~(FDMODE);
336
337 bfin_write_EMAC_OPMODE(opmode);
338 lp->old_duplex = phydev->duplex;
339 }
340
341 if (phydev->speed != lp->old_speed) {
342 #if defined(CONFIG_BFIN_MAC_RMII)
343 u32 opmode = bfin_read_EMAC_OPMODE();
344 switch (phydev->speed) {
345 case 10:
346 opmode |= RMII_10;
347 break;
348 case 100:
349 opmode &= ~(RMII_10);
350 break;
351 default:
352 printk(KERN_WARNING
353 "%s: Ack! Speed (%d) is not 10/100!\n",
354 DRV_NAME, phydev->speed);
355 break;
356 }
357 bfin_write_EMAC_OPMODE(opmode);
358 #endif
359
360 new_state = 1;
361 lp->old_speed = phydev->speed;
362 }
363
364 if (!lp->old_link) {
365 new_state = 1;
366 lp->old_link = 1;
367 }
368 } else if (lp->old_link) {
369 new_state = 1;
370 lp->old_link = 0;
371 lp->old_speed = 0;
372 lp->old_duplex = -1;
373 }
374
375 if (new_state) {
376 u32 opmode = bfin_read_EMAC_OPMODE();
377 phy_print_status(phydev);
378 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
379 }
380
381 spin_unlock_irqrestore(&lp->lock, flags);
382 }
383
384 /* MDC = 2.5 MHz */
385 #define MDC_CLK 2500000
386
387 static int mii_probe(struct net_device *dev)
388 {
389 struct bfin_mac_local *lp = netdev_priv(dev);
390 struct phy_device *phydev = NULL;
391 unsigned short sysctl;
392 int i;
393 u32 sclk, mdc_div;
394
395 /* Enable PHY output early */
396 if (!(bfin_read_VR_CTL() & CLKBUFOE))
397 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
398
399 sclk = get_sclk();
400 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
401
402 sysctl = bfin_read_EMAC_SYSCTL();
403 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
404 bfin_write_EMAC_SYSCTL(sysctl);
405
406 /* search for connect PHY device */
407 for (i = 0; i < PHY_MAX_ADDR; i++) {
408 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
409
410 if (!tmp_phydev)
411 continue; /* no PHY here... */
412
413 phydev = tmp_phydev;
414 break; /* found it */
415 }
416
417 /* now we are supposed to have a proper phydev, to attach to... */
418 if (!phydev) {
419 printk(KERN_INFO "%s: Don't found any phy device at all\n",
420 dev->name);
421 return -ENODEV;
422 }
423
424 #if defined(CONFIG_BFIN_MAC_RMII)
425 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
426 0, PHY_INTERFACE_MODE_RMII);
427 #else
428 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
429 0, PHY_INTERFACE_MODE_MII);
430 #endif
431
432 if (IS_ERR(phydev)) {
433 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
434 return PTR_ERR(phydev);
435 }
436
437 /* mask with MAC supported features */
438 phydev->supported &= (SUPPORTED_10baseT_Half
439 | SUPPORTED_10baseT_Full
440 | SUPPORTED_100baseT_Half
441 | SUPPORTED_100baseT_Full
442 | SUPPORTED_Autoneg
443 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
444 | SUPPORTED_MII
445 | SUPPORTED_TP);
446
447 phydev->advertising = phydev->supported;
448
449 lp->old_link = 0;
450 lp->old_speed = 0;
451 lp->old_duplex = -1;
452 lp->phydev = phydev;
453
454 printk(KERN_INFO "%s: attached PHY driver [%s] "
455 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
456 "@sclk=%dMHz)\n",
457 DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
458 MDC_CLK, mdc_div, sclk/1000000);
459
460 return 0;
461 }
462
463 /*
464 * Ethtool support
465 */
466
467 static int
468 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
469 {
470 struct bfin_mac_local *lp = netdev_priv(dev);
471
472 if (lp->phydev)
473 return phy_ethtool_gset(lp->phydev, cmd);
474
475 return -EINVAL;
476 }
477
478 static int
479 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
480 {
481 struct bfin_mac_local *lp = netdev_priv(dev);
482
483 if (!capable(CAP_NET_ADMIN))
484 return -EPERM;
485
486 if (lp->phydev)
487 return phy_ethtool_sset(lp->phydev, cmd);
488
489 return -EINVAL;
490 }
491
492 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
493 struct ethtool_drvinfo *info)
494 {
495 strcpy(info->driver, DRV_NAME);
496 strcpy(info->version, DRV_VERSION);
497 strcpy(info->fw_version, "N/A");
498 strcpy(info->bus_info, dev_name(&dev->dev));
499 }
500
501 static const struct ethtool_ops bfin_mac_ethtool_ops = {
502 .get_settings = bfin_mac_ethtool_getsettings,
503 .set_settings = bfin_mac_ethtool_setsettings,
504 .get_link = ethtool_op_get_link,
505 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
506 };
507
508 /**************************************************************************/
509 void setup_system_regs(struct net_device *dev)
510 {
511 unsigned short sysctl;
512
513 /*
514 * Odd word alignment for Receive Frame DMA word
515 * Configure checksum support and rcve frame word alignment
516 */
517 sysctl = bfin_read_EMAC_SYSCTL();
518 #if defined(BFIN_MAC_CSUM_OFFLOAD)
519 sysctl |= RXDWA | RXCKS;
520 #else
521 sysctl |= RXDWA;
522 #endif
523 bfin_write_EMAC_SYSCTL(sysctl);
524
525 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
526
527 /* Initialize the TX DMA channel registers */
528 bfin_write_DMA2_X_COUNT(0);
529 bfin_write_DMA2_X_MODIFY(4);
530 bfin_write_DMA2_Y_COUNT(0);
531 bfin_write_DMA2_Y_MODIFY(0);
532
533 /* Initialize the RX DMA channel registers */
534 bfin_write_DMA1_X_COUNT(0);
535 bfin_write_DMA1_X_MODIFY(4);
536 bfin_write_DMA1_Y_COUNT(0);
537 bfin_write_DMA1_Y_MODIFY(0);
538 }
539
540 static void setup_mac_addr(u8 *mac_addr)
541 {
542 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
543 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
544
545 /* this depends on a little-endian machine */
546 bfin_write_EMAC_ADDRLO(addr_low);
547 bfin_write_EMAC_ADDRHI(addr_hi);
548 }
549
550 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
551 {
552 struct sockaddr *addr = p;
553 if (netif_running(dev))
554 return -EBUSY;
555 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
556 setup_mac_addr(dev->dev_addr);
557 return 0;
558 }
559
560 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
561 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
562
563 static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
564 struct ifreq *ifr, int cmd)
565 {
566 struct hwtstamp_config config;
567 struct bfin_mac_local *lp = netdev_priv(netdev);
568 u16 ptpctl;
569 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
570
571 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
572 return -EFAULT;
573
574 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
575 __func__, config.flags, config.tx_type, config.rx_filter);
576
577 /* reserved for future extensions */
578 if (config.flags)
579 return -EINVAL;
580
581 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
582 (config.tx_type != HWTSTAMP_TX_ON))
583 return -ERANGE;
584
585 ptpctl = bfin_read_EMAC_PTP_CTL();
586
587 switch (config.rx_filter) {
588 case HWTSTAMP_FILTER_NONE:
589 /*
590 * Dont allow any timestamping
591 */
592 ptpfv3 = 0xFFFFFFFF;
593 bfin_write_EMAC_PTP_FV3(ptpfv3);
594 break;
595 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
596 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
597 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
598 /*
599 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
600 * to enable all the field matches.
601 */
602 ptpctl &= ~0x1F00;
603 bfin_write_EMAC_PTP_CTL(ptpctl);
604 /*
605 * Keep the default values of the EMAC_PTP_FOFF register.
606 */
607 ptpfoff = 0x4A24170C;
608 bfin_write_EMAC_PTP_FOFF(ptpfoff);
609 /*
610 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
611 * registers.
612 */
613 ptpfv1 = 0x11040800;
614 bfin_write_EMAC_PTP_FV1(ptpfv1);
615 ptpfv2 = 0x0140013F;
616 bfin_write_EMAC_PTP_FV2(ptpfv2);
617 /*
618 * The default value (0xFFFC) allows the timestamping of both
619 * received Sync messages and Delay_Req messages.
620 */
621 ptpfv3 = 0xFFFFFFFC;
622 bfin_write_EMAC_PTP_FV3(ptpfv3);
623
624 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
625 break;
626 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
627 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
628 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
629 /* Clear all five comparison mask bits (bits[12:8]) in the
630 * EMAC_PTP_CTL register to enable all the field matches.
631 */
632 ptpctl &= ~0x1F00;
633 bfin_write_EMAC_PTP_CTL(ptpctl);
634 /*
635 * Keep the default values of the EMAC_PTP_FOFF register, except set
636 * the PTPCOF field to 0x2A.
637 */
638 ptpfoff = 0x2A24170C;
639 bfin_write_EMAC_PTP_FOFF(ptpfoff);
640 /*
641 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
642 * registers.
643 */
644 ptpfv1 = 0x11040800;
645 bfin_write_EMAC_PTP_FV1(ptpfv1);
646 ptpfv2 = 0x0140013F;
647 bfin_write_EMAC_PTP_FV2(ptpfv2);
648 /*
649 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
650 * the value to 0xFFF0.
651 */
652 ptpfv3 = 0xFFFFFFF0;
653 bfin_write_EMAC_PTP_FV3(ptpfv3);
654
655 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
656 break;
657 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
658 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
659 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
660 /*
661 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
662 * EFTM and PTPCM field comparison.
663 */
664 ptpctl &= ~0x1100;
665 bfin_write_EMAC_PTP_CTL(ptpctl);
666 /*
667 * Keep the default values of all the fields of the EMAC_PTP_FOFF
668 * register, except set the PTPCOF field to 0x0E.
669 */
670 ptpfoff = 0x0E24170C;
671 bfin_write_EMAC_PTP_FOFF(ptpfoff);
672 /*
673 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
674 * corresponds to PTP messages on the MAC layer.
675 */
676 ptpfv1 = 0x110488F7;
677 bfin_write_EMAC_PTP_FV1(ptpfv1);
678 ptpfv2 = 0x0140013F;
679 bfin_write_EMAC_PTP_FV2(ptpfv2);
680 /*
681 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
682 * messages, set the value to 0xFFF0.
683 */
684 ptpfv3 = 0xFFFFFFF0;
685 bfin_write_EMAC_PTP_FV3(ptpfv3);
686
687 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
688 break;
689 default:
690 return -ERANGE;
691 }
692
693 if (config.tx_type == HWTSTAMP_TX_OFF &&
694 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
695 ptpctl &= ~PTP_EN;
696 bfin_write_EMAC_PTP_CTL(ptpctl);
697
698 SSYNC();
699 } else {
700 ptpctl |= PTP_EN;
701 bfin_write_EMAC_PTP_CTL(ptpctl);
702
703 /*
704 * clear any existing timestamp
705 */
706 bfin_read_EMAC_PTP_RXSNAPLO();
707 bfin_read_EMAC_PTP_RXSNAPHI();
708
709 bfin_read_EMAC_PTP_TXSNAPLO();
710 bfin_read_EMAC_PTP_TXSNAPHI();
711
712 /*
713 * Set registers so that rollover occurs soon to test this.
714 */
715 bfin_write_EMAC_PTP_TIMELO(0x00000000);
716 bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
717
718 SSYNC();
719
720 lp->compare.last_update = 0;
721 timecounter_init(&lp->clock,
722 &lp->cycles,
723 ktime_to_ns(ktime_get_real()));
724 timecompare_update(&lp->compare, 0);
725 }
726
727 lp->stamp_cfg = config;
728 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
729 -EFAULT : 0;
730 }
731
732 static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
733 {
734 ktime_t sys = ktime_get_real();
735
736 pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
737 __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
738 sys.tv.nsec, cmp->offset, cmp->skew);
739 }
740
741 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
742 {
743 struct bfin_mac_local *lp = netdev_priv(netdev);
744 union skb_shared_tx *shtx = skb_tx(skb);
745
746 if (shtx->hardware) {
747 int timeout_cnt = MAX_TIMEOUT_CNT;
748
749 /* When doing time stamping, keep the connection to the socket
750 * a while longer
751 */
752 shtx->in_progress = 1;
753
754 /*
755 * The timestamping is done at the EMAC module's MII/RMII interface
756 * when the module sees the Start of Frame of an event message packet. This
757 * interface is the closest possible place to the physical Ethernet transmission
758 * medium, providing the best timing accuracy.
759 */
760 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
761 udelay(1);
762 if (timeout_cnt == 0)
763 printk(KERN_ERR DRV_NAME
764 ": fails to timestamp the TX packet\n");
765 else {
766 struct skb_shared_hwtstamps shhwtstamps;
767 u64 ns;
768 u64 regval;
769
770 regval = bfin_read_EMAC_PTP_TXSNAPLO();
771 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
772 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
773 ns = timecounter_cyc2time(&lp->clock,
774 regval);
775 timecompare_update(&lp->compare, ns);
776 shhwtstamps.hwtstamp = ns_to_ktime(ns);
777 shhwtstamps.syststamp =
778 timecompare_transform(&lp->compare, ns);
779 skb_tstamp_tx(skb, &shhwtstamps);
780
781 bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
782 }
783 }
784 }
785
786 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
787 {
788 struct bfin_mac_local *lp = netdev_priv(netdev);
789 u32 valid;
790 u64 regval, ns;
791 struct skb_shared_hwtstamps *shhwtstamps;
792
793 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
794 return;
795
796 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
797 if (!valid)
798 return;
799
800 shhwtstamps = skb_hwtstamps(skb);
801
802 regval = bfin_read_EMAC_PTP_RXSNAPLO();
803 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
804 ns = timecounter_cyc2time(&lp->clock, regval);
805 timecompare_update(&lp->compare, ns);
806 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
807 shhwtstamps->hwtstamp = ns_to_ktime(ns);
808 shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
809
810 bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
811 }
812
813 /*
814 * bfin_read_clock - read raw cycle counter (to be used by time counter)
815 */
816 static cycle_t bfin_read_clock(const struct cyclecounter *tc)
817 {
818 u64 stamp;
819
820 stamp = bfin_read_EMAC_PTP_TIMELO();
821 stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
822
823 return stamp;
824 }
825
826 #define PTP_CLK 25000000
827
828 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
829 {
830 struct bfin_mac_local *lp = netdev_priv(netdev);
831 u64 append;
832
833 /* Initialize hardware timer */
834 append = PTP_CLK * (1ULL << 32);
835 do_div(append, get_sclk());
836 bfin_write_EMAC_PTP_ADDEND((u32)append);
837
838 memset(&lp->cycles, 0, sizeof(lp->cycles));
839 lp->cycles.read = bfin_read_clock;
840 lp->cycles.mask = CLOCKSOURCE_MASK(64);
841 lp->cycles.mult = 1000000000 / PTP_CLK;
842 lp->cycles.shift = 0;
843
844 /* Synchronize our NIC clock against system wall clock */
845 memset(&lp->compare, 0, sizeof(lp->compare));
846 lp->compare.source = &lp->clock;
847 lp->compare.target = ktime_get_real;
848 lp->compare.num_samples = 10;
849
850 /* Initialize hwstamp config */
851 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
852 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
853 }
854
855 #else
856 # define bfin_mac_hwtstamp_is_none(cfg) 0
857 # define bfin_mac_hwtstamp_init(dev)
858 # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
859 # define bfin_rx_hwtstamp(dev, skb)
860 # define bfin_tx_hwtstamp(dev, skb)
861 #endif
862
863 static void adjust_tx_list(void)
864 {
865 int timeout_cnt = MAX_TIMEOUT_CNT;
866
867 if (tx_list_head->status.status_word != 0 &&
868 current_tx_ptr != tx_list_head) {
869 goto adjust_head; /* released something, just return; */
870 }
871
872 /*
873 * if nothing released, check wait condition
874 * current's next can not be the head,
875 * otherwise the dma will not stop as we want
876 */
877 if (current_tx_ptr->next->next == tx_list_head) {
878 while (tx_list_head->status.status_word == 0) {
879 udelay(10);
880 if (tx_list_head->status.status_word != 0 ||
881 !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) {
882 goto adjust_head;
883 }
884 if (timeout_cnt-- < 0) {
885 printk(KERN_ERR DRV_NAME
886 ": wait for adjust tx list head timeout\n");
887 break;
888 }
889 }
890 if (tx_list_head->status.status_word != 0) {
891 goto adjust_head;
892 }
893 }
894
895 return;
896
897 adjust_head:
898 do {
899 tx_list_head->desc_a.config &= ~DMAEN;
900 tx_list_head->status.status_word = 0;
901 if (tx_list_head->skb) {
902 dev_kfree_skb(tx_list_head->skb);
903 tx_list_head->skb = NULL;
904 } else {
905 printk(KERN_ERR DRV_NAME
906 ": no sk_buff in a transmitted frame!\n");
907 }
908 tx_list_head = tx_list_head->next;
909 } while (tx_list_head->status.status_word != 0 &&
910 current_tx_ptr != tx_list_head);
911 return;
912
913 }
914
915 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
916 struct net_device *dev)
917 {
918 u16 *data;
919 u32 data_align = (unsigned long)(skb->data) & 0x3;
920 union skb_shared_tx *shtx = skb_tx(skb);
921
922 current_tx_ptr->skb = skb;
923
924 if (data_align == 0x2) {
925 /* move skb->data to current_tx_ptr payload */
926 data = (u16 *)(skb->data) - 1;
927 *data = (u16)(skb->len);
928 /*
929 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
930 * a DMA_Length_Word field associated with the packet. The lower 12 bits
931 * of this field are the length of the packet payload in bytes and the higher
932 * 4 bits are the timestamping enable field.
933 */
934 if (shtx->hardware)
935 *data |= 0x1000;
936
937 current_tx_ptr->desc_a.start_addr = (u32)data;
938 /* this is important! */
939 blackfin_dcache_flush_range((u32)data,
940 (u32)((u8 *)data + skb->len + 4));
941 } else {
942 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
943 /* enable timestamping for the sent packet */
944 if (shtx->hardware)
945 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
946 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
947 skb->len);
948 current_tx_ptr->desc_a.start_addr =
949 (u32)current_tx_ptr->packet;
950 if (current_tx_ptr->status.status_word != 0)
951 current_tx_ptr->status.status_word = 0;
952 blackfin_dcache_flush_range(
953 (u32)current_tx_ptr->packet,
954 (u32)(current_tx_ptr->packet + skb->len + 2));
955 }
956
957 /* make sure the internal data buffers in the core are drained
958 * so that the DMA descriptors are completely written when the
959 * DMA engine goes to fetch them below
960 */
961 SSYNC();
962
963 /* enable this packet's dma */
964 current_tx_ptr->desc_a.config |= DMAEN;
965
966 /* tx dma is running, just return */
967 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
968 goto out;
969
970 /* tx dma is not running */
971 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
972 /* dma enabled, read from memory, size is 6 */
973 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
974 /* Turn on the EMAC tx */
975 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
976
977 out:
978 adjust_tx_list();
979
980 bfin_tx_hwtstamp(dev, skb);
981
982 current_tx_ptr = current_tx_ptr->next;
983 dev->stats.tx_packets++;
984 dev->stats.tx_bytes += (skb->len);
985 return NETDEV_TX_OK;
986 }
987
988 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
989 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
990
991 static void bfin_mac_rx(struct net_device *dev)
992 {
993 struct sk_buff *skb, *new_skb;
994 unsigned short len;
995 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
996
997 /* check if frame status word reports an error condition
998 * we which case we simply drop the packet
999 */
1000 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1001 printk(KERN_NOTICE DRV_NAME
1002 ": rx: receive error - packet dropped\n");
1003 dev->stats.rx_dropped++;
1004 goto out;
1005 }
1006
1007 /* allocate a new skb for next time receive */
1008 skb = current_rx_ptr->skb;
1009
1010 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
1011 if (!new_skb) {
1012 printk(KERN_NOTICE DRV_NAME
1013 ": rx: low on mem - packet dropped\n");
1014 dev->stats.rx_dropped++;
1015 goto out;
1016 }
1017 /* reserve 2 bytes for RXDWA padding */
1018 skb_reserve(new_skb, NET_IP_ALIGN);
1019 /* Invidate the data cache of skb->data range when it is write back
1020 * cache. It will prevent overwritting the new data from DMA
1021 */
1022 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1023 (unsigned long)new_skb->end);
1024
1025 current_rx_ptr->skb = new_skb;
1026 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1027
1028 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
1029 skb_put(skb, len);
1030
1031 skb->protocol = eth_type_trans(skb, dev);
1032
1033 bfin_rx_hwtstamp(dev, skb);
1034
1035 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1036 skb->csum = current_rx_ptr->status.ip_payload_csum;
1037 skb->ip_summed = CHECKSUM_COMPLETE;
1038 #endif
1039
1040 netif_rx(skb);
1041 dev->stats.rx_packets++;
1042 dev->stats.rx_bytes += len;
1043 out:
1044 current_rx_ptr->status.status_word = 0x00000000;
1045 current_rx_ptr = current_rx_ptr->next;
1046 }
1047
1048 /* interrupt routine to handle rx and error signal */
1049 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1050 {
1051 struct net_device *dev = dev_id;
1052 int number = 0;
1053
1054 get_one_packet:
1055 if (current_rx_ptr->status.status_word == 0) {
1056 /* no more new packet received */
1057 if (number == 0) {
1058 if (current_rx_ptr->next->status.status_word != 0) {
1059 current_rx_ptr = current_rx_ptr->next;
1060 goto real_rx;
1061 }
1062 }
1063 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1064 DMA_DONE | DMA_ERR);
1065 return IRQ_HANDLED;
1066 }
1067
1068 real_rx:
1069 bfin_mac_rx(dev);
1070 number++;
1071 goto get_one_packet;
1072 }
1073
1074 #ifdef CONFIG_NET_POLL_CONTROLLER
1075 static void bfin_mac_poll(struct net_device *dev)
1076 {
1077 disable_irq(IRQ_MAC_RX);
1078 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1079 enable_irq(IRQ_MAC_RX);
1080 }
1081 #endif /* CONFIG_NET_POLL_CONTROLLER */
1082
1083 static void bfin_mac_disable(void)
1084 {
1085 unsigned int opmode;
1086
1087 opmode = bfin_read_EMAC_OPMODE();
1088 opmode &= (~RE);
1089 opmode &= (~TE);
1090 /* Turn off the EMAC */
1091 bfin_write_EMAC_OPMODE(opmode);
1092 }
1093
1094 /*
1095 * Enable Interrupts, Receive, and Transmit
1096 */
1097 static void bfin_mac_enable(void)
1098 {
1099 u32 opmode;
1100
1101 pr_debug("%s: %s\n", DRV_NAME, __func__);
1102
1103 /* Set RX DMA */
1104 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1105 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1106
1107 /* Wait MII done */
1108 bfin_mdio_poll();
1109
1110 /* We enable only RX here */
1111 /* ASTP : Enable Automatic Pad Stripping
1112 PR : Promiscuous Mode for test
1113 PSF : Receive frames with total length less than 64 bytes.
1114 FDMODE : Full Duplex Mode
1115 LB : Internal Loopback for test
1116 RE : Receiver Enable */
1117 opmode = bfin_read_EMAC_OPMODE();
1118 if (opmode & FDMODE)
1119 opmode |= PSF;
1120 else
1121 opmode |= DRO | DC | PSF;
1122 opmode |= RE;
1123
1124 #if defined(CONFIG_BFIN_MAC_RMII)
1125 opmode |= RMII; /* For Now only 100MBit are supported */
1126 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
1127 opmode |= TE;
1128 #endif
1129 #endif
1130 /* Turn on the EMAC rx */
1131 bfin_write_EMAC_OPMODE(opmode);
1132 }
1133
1134 /* Our watchdog timed out. Called by the networking layer */
1135 static void bfin_mac_timeout(struct net_device *dev)
1136 {
1137 pr_debug("%s: %s\n", dev->name, __func__);
1138
1139 bfin_mac_disable();
1140
1141 /* reset tx queue */
1142 tx_list_tail = tx_list_head->next;
1143
1144 bfin_mac_enable();
1145
1146 /* We can accept TX packets again */
1147 dev->trans_start = jiffies; /* prevent tx timeout */
1148 netif_wake_queue(dev);
1149 }
1150
1151 static void bfin_mac_multicast_hash(struct net_device *dev)
1152 {
1153 u32 emac_hashhi, emac_hashlo;
1154 struct netdev_hw_addr *ha;
1155 char *addrs;
1156 u32 crc;
1157
1158 emac_hashhi = emac_hashlo = 0;
1159
1160 netdev_for_each_mc_addr(ha, dev) {
1161 addrs = ha->addr;
1162
1163 /* skip non-multicast addresses */
1164 if (!(*addrs & 1))
1165 continue;
1166
1167 crc = ether_crc(ETH_ALEN, addrs);
1168 crc >>= 26;
1169
1170 if (crc & 0x20)
1171 emac_hashhi |= 1 << (crc & 0x1f);
1172 else
1173 emac_hashlo |= 1 << (crc & 0x1f);
1174 }
1175
1176 bfin_write_EMAC_HASHHI(emac_hashhi);
1177 bfin_write_EMAC_HASHLO(emac_hashlo);
1178 }
1179
1180 /*
1181 * This routine will, depending on the values passed to it,
1182 * either make it accept multicast packets, go into
1183 * promiscuous mode (for TCPDUMP and cousins) or accept
1184 * a select set of multicast packets
1185 */
1186 static void bfin_mac_set_multicast_list(struct net_device *dev)
1187 {
1188 u32 sysctl;
1189
1190 if (dev->flags & IFF_PROMISC) {
1191 printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
1192 sysctl = bfin_read_EMAC_OPMODE();
1193 sysctl |= RAF;
1194 bfin_write_EMAC_OPMODE(sysctl);
1195 } else if (dev->flags & IFF_ALLMULTI) {
1196 /* accept all multicast */
1197 sysctl = bfin_read_EMAC_OPMODE();
1198 sysctl |= PAM;
1199 bfin_write_EMAC_OPMODE(sysctl);
1200 } else if (!netdev_mc_empty(dev)) {
1201 /* set up multicast hash table */
1202 sysctl = bfin_read_EMAC_OPMODE();
1203 sysctl |= HM;
1204 bfin_write_EMAC_OPMODE(sysctl);
1205 bfin_mac_multicast_hash(dev);
1206 } else {
1207 /* clear promisc or multicast mode */
1208 sysctl = bfin_read_EMAC_OPMODE();
1209 sysctl &= ~(RAF | PAM);
1210 bfin_write_EMAC_OPMODE(sysctl);
1211 }
1212 }
1213
1214 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1215 {
1216 switch (cmd) {
1217 case SIOCSHWTSTAMP:
1218 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1219 default:
1220 return -EOPNOTSUPP;
1221 }
1222 }
1223
1224 /*
1225 * this puts the device in an inactive state
1226 */
1227 static void bfin_mac_shutdown(struct net_device *dev)
1228 {
1229 /* Turn off the EMAC */
1230 bfin_write_EMAC_OPMODE(0x00000000);
1231 /* Turn off the EMAC RX DMA */
1232 bfin_write_DMA1_CONFIG(0x0000);
1233 bfin_write_DMA2_CONFIG(0x0000);
1234 }
1235
1236 /*
1237 * Open and Initialize the interface
1238 *
1239 * Set up everything, reset the card, etc..
1240 */
1241 static int bfin_mac_open(struct net_device *dev)
1242 {
1243 struct bfin_mac_local *lp = netdev_priv(dev);
1244 int retval;
1245 pr_debug("%s: %s\n", dev->name, __func__);
1246
1247 /*
1248 * Check that the address is valid. If its not, refuse
1249 * to bring the device up. The user must specify an
1250 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1251 */
1252 if (!is_valid_ether_addr(dev->dev_addr)) {
1253 printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
1254 return -EINVAL;
1255 }
1256
1257 /* initial rx and tx list */
1258 retval = desc_list_init();
1259
1260 if (retval)
1261 return retval;
1262
1263 phy_start(lp->phydev);
1264 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
1265 setup_system_regs(dev);
1266 setup_mac_addr(dev->dev_addr);
1267 bfin_mac_disable();
1268 bfin_mac_enable();
1269 pr_debug("hardware init finished\n");
1270 netif_start_queue(dev);
1271 netif_carrier_on(dev);
1272
1273 return 0;
1274 }
1275
1276 /*
1277 * this makes the board clean up everything that it can
1278 * and not talk to the outside world. Caused by
1279 * an 'ifconfig ethX down'
1280 */
1281 static int bfin_mac_close(struct net_device *dev)
1282 {
1283 struct bfin_mac_local *lp = netdev_priv(dev);
1284 pr_debug("%s: %s\n", dev->name, __func__);
1285
1286 netif_stop_queue(dev);
1287 netif_carrier_off(dev);
1288
1289 phy_stop(lp->phydev);
1290 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1291
1292 /* clear everything */
1293 bfin_mac_shutdown(dev);
1294
1295 /* free the rx/tx buffers */
1296 desc_list_free();
1297
1298 return 0;
1299 }
1300
1301 static const struct net_device_ops bfin_mac_netdev_ops = {
1302 .ndo_open = bfin_mac_open,
1303 .ndo_stop = bfin_mac_close,
1304 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1305 .ndo_set_mac_address = bfin_mac_set_mac_address,
1306 .ndo_tx_timeout = bfin_mac_timeout,
1307 .ndo_set_multicast_list = bfin_mac_set_multicast_list,
1308 .ndo_do_ioctl = bfin_mac_ioctl,
1309 .ndo_validate_addr = eth_validate_addr,
1310 .ndo_change_mtu = eth_change_mtu,
1311 #ifdef CONFIG_NET_POLL_CONTROLLER
1312 .ndo_poll_controller = bfin_mac_poll,
1313 #endif
1314 };
1315
1316 static int __devinit bfin_mac_probe(struct platform_device *pdev)
1317 {
1318 struct net_device *ndev;
1319 struct bfin_mac_local *lp;
1320 struct platform_device *pd;
1321 int rc;
1322
1323 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1324 if (!ndev) {
1325 dev_err(&pdev->dev, "Cannot allocate net device!\n");
1326 return -ENOMEM;
1327 }
1328
1329 SET_NETDEV_DEV(ndev, &pdev->dev);
1330 platform_set_drvdata(pdev, ndev);
1331 lp = netdev_priv(ndev);
1332
1333 /* Grab the MAC address in the MAC */
1334 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1335 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1336
1337 /* probe mac */
1338 /*todo: how to proble? which is revision_register */
1339 bfin_write_EMAC_ADDRLO(0x12345678);
1340 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1341 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1342 rc = -ENODEV;
1343 goto out_err_probe_mac;
1344 }
1345
1346
1347 /*
1348 * Is it valid? (Did bootloader initialize it?)
1349 * Grab the MAC from the board somehow
1350 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1351 */
1352 if (!is_valid_ether_addr(ndev->dev_addr))
1353 bfin_get_ether_addr(ndev->dev_addr);
1354
1355 /* If still not valid, get a random one */
1356 if (!is_valid_ether_addr(ndev->dev_addr))
1357 random_ether_addr(ndev->dev_addr);
1358
1359 setup_mac_addr(ndev->dev_addr);
1360
1361 if (!pdev->dev.platform_data) {
1362 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1363 rc = -ENODEV;
1364 goto out_err_probe_mac;
1365 }
1366 pd = pdev->dev.platform_data;
1367 lp->mii_bus = platform_get_drvdata(pd);
1368 lp->mii_bus->priv = ndev;
1369
1370 rc = mii_probe(ndev);
1371 if (rc) {
1372 dev_err(&pdev->dev, "MII Probe failed!\n");
1373 goto out_err_mii_probe;
1374 }
1375
1376 /* Fill in the fields of the device structure with ethernet values. */
1377 ether_setup(ndev);
1378
1379 ndev->netdev_ops = &bfin_mac_netdev_ops;
1380 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1381
1382 spin_lock_init(&lp->lock);
1383
1384 /* now, enable interrupts */
1385 /* register irq handler */
1386 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1387 IRQF_DISABLED, "EMAC_RX", ndev);
1388 if (rc) {
1389 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1390 rc = -EBUSY;
1391 goto out_err_request_irq;
1392 }
1393
1394 rc = register_netdev(ndev);
1395 if (rc) {
1396 dev_err(&pdev->dev, "Cannot register net device!\n");
1397 goto out_err_reg_ndev;
1398 }
1399
1400 bfin_mac_hwtstamp_init(ndev);
1401
1402 /* now, print out the card info, in a short format.. */
1403 dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1404
1405 return 0;
1406
1407 out_err_reg_ndev:
1408 free_irq(IRQ_MAC_RX, ndev);
1409 out_err_request_irq:
1410 out_err_mii_probe:
1411 mdiobus_unregister(lp->mii_bus);
1412 mdiobus_free(lp->mii_bus);
1413 peripheral_free_list(pin_req);
1414 out_err_probe_mac:
1415 platform_set_drvdata(pdev, NULL);
1416 free_netdev(ndev);
1417
1418 return rc;
1419 }
1420
1421 static int __devexit bfin_mac_remove(struct platform_device *pdev)
1422 {
1423 struct net_device *ndev = platform_get_drvdata(pdev);
1424 struct bfin_mac_local *lp = netdev_priv(ndev);
1425
1426 platform_set_drvdata(pdev, NULL);
1427
1428 lp->mii_bus->priv = NULL;
1429
1430 unregister_netdev(ndev);
1431
1432 free_irq(IRQ_MAC_RX, ndev);
1433
1434 free_netdev(ndev);
1435
1436 peripheral_free_list(pin_req);
1437
1438 return 0;
1439 }
1440
1441 #ifdef CONFIG_PM
1442 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1443 {
1444 struct net_device *net_dev = platform_get_drvdata(pdev);
1445
1446 if (netif_running(net_dev))
1447 bfin_mac_close(net_dev);
1448
1449 return 0;
1450 }
1451
1452 static int bfin_mac_resume(struct platform_device *pdev)
1453 {
1454 struct net_device *net_dev = platform_get_drvdata(pdev);
1455
1456 if (netif_running(net_dev))
1457 bfin_mac_open(net_dev);
1458
1459 return 0;
1460 }
1461 #else
1462 #define bfin_mac_suspend NULL
1463 #define bfin_mac_resume NULL
1464 #endif /* CONFIG_PM */
1465
1466 static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1467 {
1468 struct mii_bus *miibus;
1469 int rc, i;
1470
1471 /*
1472 * We are setting up a network card,
1473 * so set the GPIO pins to Ethernet mode
1474 */
1475 rc = peripheral_request_list(pin_req, DRV_NAME);
1476 if (rc) {
1477 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1478 return rc;
1479 }
1480
1481 rc = -ENOMEM;
1482 miibus = mdiobus_alloc();
1483 if (miibus == NULL)
1484 goto out_err_alloc;
1485 miibus->read = bfin_mdiobus_read;
1486 miibus->write = bfin_mdiobus_write;
1487 miibus->reset = bfin_mdiobus_reset;
1488
1489 miibus->parent = &pdev->dev;
1490 miibus->name = "bfin_mii_bus";
1491 snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
1492 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1493 if (miibus->irq == NULL)
1494 goto out_err_alloc;
1495 for (i = 0; i < PHY_MAX_ADDR; ++i)
1496 miibus->irq[i] = PHY_POLL;
1497
1498 rc = mdiobus_register(miibus);
1499 if (rc) {
1500 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1501 goto out_err_mdiobus_register;
1502 }
1503
1504 platform_set_drvdata(pdev, miibus);
1505 return 0;
1506
1507 out_err_mdiobus_register:
1508 mdiobus_free(miibus);
1509 out_err_alloc:
1510 peripheral_free_list(pin_req);
1511
1512 return rc;
1513 }
1514
1515 static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1516 {
1517 struct mii_bus *miibus = platform_get_drvdata(pdev);
1518 platform_set_drvdata(pdev, NULL);
1519 mdiobus_unregister(miibus);
1520 mdiobus_free(miibus);
1521 peripheral_free_list(pin_req);
1522 return 0;
1523 }
1524
1525 static struct platform_driver bfin_mii_bus_driver = {
1526 .probe = bfin_mii_bus_probe,
1527 .remove = __devexit_p(bfin_mii_bus_remove),
1528 .driver = {
1529 .name = "bfin_mii_bus",
1530 .owner = THIS_MODULE,
1531 },
1532 };
1533
1534 static struct platform_driver bfin_mac_driver = {
1535 .probe = bfin_mac_probe,
1536 .remove = __devexit_p(bfin_mac_remove),
1537 .resume = bfin_mac_resume,
1538 .suspend = bfin_mac_suspend,
1539 .driver = {
1540 .name = DRV_NAME,
1541 .owner = THIS_MODULE,
1542 },
1543 };
1544
1545 static int __init bfin_mac_init(void)
1546 {
1547 int ret;
1548 ret = platform_driver_register(&bfin_mii_bus_driver);
1549 if (!ret)
1550 return platform_driver_register(&bfin_mac_driver);
1551 return -ENODEV;
1552 }
1553
1554 module_init(bfin_mac_init);
1555
1556 static void __exit bfin_mac_cleanup(void)
1557 {
1558 platform_driver_unregister(&bfin_mac_driver);
1559 platform_driver_unregister(&bfin_mii_bus_driver);
1560 }
1561
1562 module_exit(bfin_mac_cleanup);
1563
Linux kernel - Deliverables
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