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[NET]: Nuke SET_MODULE_OWNER macro.
[deliverable/linux.git] / drivers / net / bmac.c
1 /*
2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1998 Randy Gobbel.
6 *
7 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
8 * dynamic procfs inode.
9 */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/timer.h>
17 #include <linux/proc_fs.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/crc32.h>
21 #include <linux/bitrev.h>
22 #include <linux/ethtool.h>
23 #include <asm/prom.h>
24 #include <asm/dbdma.h>
25 #include <asm/io.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/machdep.h>
29 #include <asm/pmac_feature.h>
30 #include <asm/macio.h>
31 #include <asm/irq.h>
32
33 #include "bmac.h"
34
35 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
36 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
37
38 /*
39 * CRC polynomial - used in working out multicast filter bits.
40 */
41 #define ENET_CRCPOLY 0x04c11db7
42
43 /* switch to use multicast code lifted from sunhme driver */
44 #define SUNHME_MULTICAST
45
46 #define N_RX_RING 64
47 #define N_TX_RING 32
48 #define MAX_TX_ACTIVE 1
49 #define ETHERCRC 4
50 #define ETHERMINPACKET 64
51 #define ETHERMTU 1500
52 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
53 #define TX_TIMEOUT HZ /* 1 second */
54
55 /* Bits in transmit DMA status */
56 #define TX_DMA_ERR 0x80
57
58 #define XXDEBUG(args)
59
60 struct bmac_data {
61 /* volatile struct bmac *bmac; */
62 struct sk_buff_head *queue;
63 volatile struct dbdma_regs __iomem *tx_dma;
64 int tx_dma_intr;
65 volatile struct dbdma_regs __iomem *rx_dma;
66 int rx_dma_intr;
67 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
68 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
69 struct macio_dev *mdev;
70 int is_bmac_plus;
71 struct sk_buff *rx_bufs[N_RX_RING];
72 int rx_fill;
73 int rx_empty;
74 struct sk_buff *tx_bufs[N_TX_RING];
75 int tx_fill;
76 int tx_empty;
77 unsigned char tx_fullup;
78 struct net_device_stats stats;
79 struct timer_list tx_timeout;
80 int timeout_active;
81 int sleeping;
82 int opened;
83 unsigned short hash_use_count[64];
84 unsigned short hash_table_mask[4];
85 spinlock_t lock;
86 };
87
88 #if 0 /* Move that to ethtool */
89
90 typedef struct bmac_reg_entry {
91 char *name;
92 unsigned short reg_offset;
93 } bmac_reg_entry_t;
94
95 #define N_REG_ENTRIES 31
96
97 static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
98 {"MEMADD", MEMADD},
99 {"MEMDATAHI", MEMDATAHI},
100 {"MEMDATALO", MEMDATALO},
101 {"TXPNTR", TXPNTR},
102 {"RXPNTR", RXPNTR},
103 {"IPG1", IPG1},
104 {"IPG2", IPG2},
105 {"ALIMIT", ALIMIT},
106 {"SLOT", SLOT},
107 {"PALEN", PALEN},
108 {"PAPAT", PAPAT},
109 {"TXSFD", TXSFD},
110 {"JAM", JAM},
111 {"TXCFG", TXCFG},
112 {"TXMAX", TXMAX},
113 {"TXMIN", TXMIN},
114 {"PAREG", PAREG},
115 {"DCNT", DCNT},
116 {"NCCNT", NCCNT},
117 {"NTCNT", NTCNT},
118 {"EXCNT", EXCNT},
119 {"LTCNT", LTCNT},
120 {"TXSM", TXSM},
121 {"RXCFG", RXCFG},
122 {"RXMAX", RXMAX},
123 {"RXMIN", RXMIN},
124 {"FRCNT", FRCNT},
125 {"AECNT", AECNT},
126 {"FECNT", FECNT},
127 {"RXSM", RXSM},
128 {"RXCV", RXCV}
129 };
130
131 #endif
132
133 static unsigned char *bmac_emergency_rxbuf;
134
135 /*
136 * Number of bytes of private data per BMAC: allow enough for
137 * the rx and tx dma commands plus a branch dma command each,
138 * and another 16 bytes to allow us to align the dma command
139 * buffers on a 16 byte boundary.
140 */
141 #define PRIV_BYTES (sizeof(struct bmac_data) \
142 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
143 + sizeof(struct sk_buff_head))
144
145 static int bmac_open(struct net_device *dev);
146 static int bmac_close(struct net_device *dev);
147 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
148 static struct net_device_stats *bmac_stats(struct net_device *dev);
149 static void bmac_set_multicast(struct net_device *dev);
150 static void bmac_reset_and_enable(struct net_device *dev);
151 static void bmac_start_chip(struct net_device *dev);
152 static void bmac_init_chip(struct net_device *dev);
153 static void bmac_init_registers(struct net_device *dev);
154 static void bmac_enable_and_reset_chip(struct net_device *dev);
155 static int bmac_set_address(struct net_device *dev, void *addr);
156 static irqreturn_t bmac_misc_intr(int irq, void *dev_id);
157 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id);
158 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id);
159 static void bmac_set_timeout(struct net_device *dev);
160 static void bmac_tx_timeout(unsigned long data);
161 static int bmac_output(struct sk_buff *skb, struct net_device *dev);
162 static void bmac_start(struct net_device *dev);
163
164 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
165 #define DBDMA_CLEAR(x) ( (x) << 16)
166
167 static inline void
168 dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
169 {
170 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
171 return;
172 }
173
174 static inline unsigned long
175 dbdma_ld32(volatile __u32 __iomem *a)
176 {
177 __u32 swap;
178 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
179 return swap;
180 }
181
182 static void
183 dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
184 {
185 dbdma_st32(&dmap->control,
186 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
187 eieio();
188 }
189
190 static void
191 dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
192 {
193 dbdma_st32(&dmap->control,
194 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
195 eieio();
196 while (dbdma_ld32(&dmap->status) & RUN)
197 eieio();
198 }
199
200 static void
201 dbdma_setcmd(volatile struct dbdma_cmd *cp,
202 unsigned short cmd, unsigned count, unsigned long addr,
203 unsigned long cmd_dep)
204 {
205 out_le16(&cp->command, cmd);
206 out_le16(&cp->req_count, count);
207 out_le32(&cp->phy_addr, addr);
208 out_le32(&cp->cmd_dep, cmd_dep);
209 out_le16(&cp->xfer_status, 0);
210 out_le16(&cp->res_count, 0);
211 }
212
213 static inline
214 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
215 {
216 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
217 }
218
219
220 static inline
221 unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
222 {
223 return in_le16((void __iomem *)dev->base_addr + reg_offset);
224 }
225
226 static void
227 bmac_enable_and_reset_chip(struct net_device *dev)
228 {
229 struct bmac_data *bp = netdev_priv(dev);
230 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
231 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
232
233 if (rd)
234 dbdma_reset(rd);
235 if (td)
236 dbdma_reset(td);
237
238 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
239 }
240
241 #define MIFDELAY udelay(10)
242
243 static unsigned int
244 bmac_mif_readbits(struct net_device *dev, int nb)
245 {
246 unsigned int val = 0;
247
248 while (--nb >= 0) {
249 bmwrite(dev, MIFCSR, 0);
250 MIFDELAY;
251 if (bmread(dev, MIFCSR) & 8)
252 val |= 1 << nb;
253 bmwrite(dev, MIFCSR, 1);
254 MIFDELAY;
255 }
256 bmwrite(dev, MIFCSR, 0);
257 MIFDELAY;
258 bmwrite(dev, MIFCSR, 1);
259 MIFDELAY;
260 return val;
261 }
262
263 static void
264 bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
265 {
266 int b;
267
268 while (--nb >= 0) {
269 b = (val & (1 << nb))? 6: 4;
270 bmwrite(dev, MIFCSR, b);
271 MIFDELAY;
272 bmwrite(dev, MIFCSR, b|1);
273 MIFDELAY;
274 }
275 }
276
277 static unsigned int
278 bmac_mif_read(struct net_device *dev, unsigned int addr)
279 {
280 unsigned int val;
281
282 bmwrite(dev, MIFCSR, 4);
283 MIFDELAY;
284 bmac_mif_writebits(dev, ~0U, 32);
285 bmac_mif_writebits(dev, 6, 4);
286 bmac_mif_writebits(dev, addr, 10);
287 bmwrite(dev, MIFCSR, 2);
288 MIFDELAY;
289 bmwrite(dev, MIFCSR, 1);
290 MIFDELAY;
291 val = bmac_mif_readbits(dev, 17);
292 bmwrite(dev, MIFCSR, 4);
293 MIFDELAY;
294 return val;
295 }
296
297 static void
298 bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
299 {
300 bmwrite(dev, MIFCSR, 4);
301 MIFDELAY;
302 bmac_mif_writebits(dev, ~0U, 32);
303 bmac_mif_writebits(dev, 5, 4);
304 bmac_mif_writebits(dev, addr, 10);
305 bmac_mif_writebits(dev, 2, 2);
306 bmac_mif_writebits(dev, val, 16);
307 bmac_mif_writebits(dev, 3, 2);
308 }
309
310 static void
311 bmac_init_registers(struct net_device *dev)
312 {
313 struct bmac_data *bp = netdev_priv(dev);
314 volatile unsigned short regValue;
315 unsigned short *pWord16;
316 int i;
317
318 /* XXDEBUG(("bmac: enter init_registers\n")); */
319
320 bmwrite(dev, RXRST, RxResetValue);
321 bmwrite(dev, TXRST, TxResetBit);
322
323 i = 100;
324 do {
325 --i;
326 udelay(10000);
327 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
328 } while ((regValue & TxResetBit) && i > 0);
329
330 if (!bp->is_bmac_plus) {
331 regValue = bmread(dev, XCVRIF);
332 regValue |= ClkBit | SerialMode | COLActiveLow;
333 bmwrite(dev, XCVRIF, regValue);
334 udelay(10000);
335 }
336
337 bmwrite(dev, RSEED, (unsigned short)0x1968);
338
339 regValue = bmread(dev, XIFC);
340 regValue |= TxOutputEnable;
341 bmwrite(dev, XIFC, regValue);
342
343 bmread(dev, PAREG);
344
345 /* set collision counters to 0 */
346 bmwrite(dev, NCCNT, 0);
347 bmwrite(dev, NTCNT, 0);
348 bmwrite(dev, EXCNT, 0);
349 bmwrite(dev, LTCNT, 0);
350
351 /* set rx counters to 0 */
352 bmwrite(dev, FRCNT, 0);
353 bmwrite(dev, LECNT, 0);
354 bmwrite(dev, AECNT, 0);
355 bmwrite(dev, FECNT, 0);
356 bmwrite(dev, RXCV, 0);
357
358 /* set tx fifo information */
359 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
360
361 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
362 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
363
364 /* set rx fifo information */
365 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
366 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
367
368 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
369 bmread(dev, STATUS); /* read it just to clear it */
370
371 /* zero out the chip Hash Filter registers */
372 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
373 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
374 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
375 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
376 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
377
378 pWord16 = (unsigned short *)dev->dev_addr;
379 bmwrite(dev, MADD0, *pWord16++);
380 bmwrite(dev, MADD1, *pWord16++);
381 bmwrite(dev, MADD2, *pWord16);
382
383 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
384
385 bmwrite(dev, INTDISABLE, EnableNormal);
386
387 return;
388 }
389
390 #if 0
391 static void
392 bmac_disable_interrupts(struct net_device *dev)
393 {
394 bmwrite(dev, INTDISABLE, DisableAll);
395 }
396
397 static void
398 bmac_enable_interrupts(struct net_device *dev)
399 {
400 bmwrite(dev, INTDISABLE, EnableNormal);
401 }
402 #endif
403
404
405 static void
406 bmac_start_chip(struct net_device *dev)
407 {
408 struct bmac_data *bp = netdev_priv(dev);
409 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
410 unsigned short oldConfig;
411
412 /* enable rx dma channel */
413 dbdma_continue(rd);
414
415 oldConfig = bmread(dev, TXCFG);
416 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
417
418 /* turn on rx plus any other bits already on (promiscuous possibly) */
419 oldConfig = bmread(dev, RXCFG);
420 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
421 udelay(20000);
422 }
423
424 static void
425 bmac_init_phy(struct net_device *dev)
426 {
427 unsigned int addr;
428 struct bmac_data *bp = netdev_priv(dev);
429
430 printk(KERN_DEBUG "phy registers:");
431 for (addr = 0; addr < 32; ++addr) {
432 if ((addr & 7) == 0)
433 printk("\n" KERN_DEBUG);
434 printk(" %.4x", bmac_mif_read(dev, addr));
435 }
436 printk("\n");
437 if (bp->is_bmac_plus) {
438 unsigned int capable, ctrl;
439
440 ctrl = bmac_mif_read(dev, 0);
441 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
442 if (bmac_mif_read(dev, 4) != capable
443 || (ctrl & 0x1000) == 0) {
444 bmac_mif_write(dev, 4, capable);
445 bmac_mif_write(dev, 0, 0x1200);
446 } else
447 bmac_mif_write(dev, 0, 0x1000);
448 }
449 }
450
451 static void bmac_init_chip(struct net_device *dev)
452 {
453 bmac_init_phy(dev);
454 bmac_init_registers(dev);
455 }
456
457 #ifdef CONFIG_PM
458 static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
459 {
460 struct net_device* dev = macio_get_drvdata(mdev);
461 struct bmac_data *bp = netdev_priv(dev);
462 unsigned long flags;
463 unsigned short config;
464 int i;
465
466 netif_device_detach(dev);
467 /* prolly should wait for dma to finish & turn off the chip */
468 spin_lock_irqsave(&bp->lock, flags);
469 if (bp->timeout_active) {
470 del_timer(&bp->tx_timeout);
471 bp->timeout_active = 0;
472 }
473 disable_irq(dev->irq);
474 disable_irq(bp->tx_dma_intr);
475 disable_irq(bp->rx_dma_intr);
476 bp->sleeping = 1;
477 spin_unlock_irqrestore(&bp->lock, flags);
478 if (bp->opened) {
479 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
480 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
481
482 config = bmread(dev, RXCFG);
483 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
484 config = bmread(dev, TXCFG);
485 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
486 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
487 /* disable rx and tx dma */
488 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
489 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
490 /* free some skb's */
491 for (i=0; i<N_RX_RING; i++) {
492 if (bp->rx_bufs[i] != NULL) {
493 dev_kfree_skb(bp->rx_bufs[i]);
494 bp->rx_bufs[i] = NULL;
495 }
496 }
497 for (i = 0; i<N_TX_RING; i++) {
498 if (bp->tx_bufs[i] != NULL) {
499 dev_kfree_skb(bp->tx_bufs[i]);
500 bp->tx_bufs[i] = NULL;
501 }
502 }
503 }
504 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
505 return 0;
506 }
507
508 static int bmac_resume(struct macio_dev *mdev)
509 {
510 struct net_device* dev = macio_get_drvdata(mdev);
511 struct bmac_data *bp = netdev_priv(dev);
512
513 /* see if this is enough */
514 if (bp->opened)
515 bmac_reset_and_enable(dev);
516
517 enable_irq(dev->irq);
518 enable_irq(bp->tx_dma_intr);
519 enable_irq(bp->rx_dma_intr);
520 netif_device_attach(dev);
521
522 return 0;
523 }
524 #endif /* CONFIG_PM */
525
526 static int bmac_set_address(struct net_device *dev, void *addr)
527 {
528 struct bmac_data *bp = netdev_priv(dev);
529 unsigned char *p = addr;
530 unsigned short *pWord16;
531 unsigned long flags;
532 int i;
533
534 XXDEBUG(("bmac: enter set_address\n"));
535 spin_lock_irqsave(&bp->lock, flags);
536
537 for (i = 0; i < 6; ++i) {
538 dev->dev_addr[i] = p[i];
539 }
540 /* load up the hardware address */
541 pWord16 = (unsigned short *)dev->dev_addr;
542 bmwrite(dev, MADD0, *pWord16++);
543 bmwrite(dev, MADD1, *pWord16++);
544 bmwrite(dev, MADD2, *pWord16);
545
546 spin_unlock_irqrestore(&bp->lock, flags);
547 XXDEBUG(("bmac: exit set_address\n"));
548 return 0;
549 }
550
551 static inline void bmac_set_timeout(struct net_device *dev)
552 {
553 struct bmac_data *bp = netdev_priv(dev);
554 unsigned long flags;
555
556 spin_lock_irqsave(&bp->lock, flags);
557 if (bp->timeout_active)
558 del_timer(&bp->tx_timeout);
559 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
560 bp->tx_timeout.function = bmac_tx_timeout;
561 bp->tx_timeout.data = (unsigned long) dev;
562 add_timer(&bp->tx_timeout);
563 bp->timeout_active = 1;
564 spin_unlock_irqrestore(&bp->lock, flags);
565 }
566
567 static void
568 bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
569 {
570 void *vaddr;
571 unsigned long baddr;
572 unsigned long len;
573
574 len = skb->len;
575 vaddr = skb->data;
576 baddr = virt_to_bus(vaddr);
577
578 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
579 }
580
581 static void
582 bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
583 {
584 unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
585
586 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
587 virt_to_bus(addr), 0);
588 }
589
590 static void
591 bmac_init_tx_ring(struct bmac_data *bp)
592 {
593 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
594
595 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
596
597 bp->tx_empty = 0;
598 bp->tx_fill = 0;
599 bp->tx_fullup = 0;
600
601 /* put a branch at the end of the tx command list */
602 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
603 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
604
605 /* reset tx dma */
606 dbdma_reset(td);
607 out_le32(&td->wait_sel, 0x00200020);
608 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
609 }
610
611 static int
612 bmac_init_rx_ring(struct bmac_data *bp)
613 {
614 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
615 int i;
616 struct sk_buff *skb;
617
618 /* initialize list of sk_buffs for receiving and set up recv dma */
619 memset((char *)bp->rx_cmds, 0,
620 (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
621 for (i = 0; i < N_RX_RING; i++) {
622 if ((skb = bp->rx_bufs[i]) == NULL) {
623 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
624 if (skb != NULL)
625 skb_reserve(skb, 2);
626 }
627 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
628 }
629
630 bp->rx_empty = 0;
631 bp->rx_fill = i;
632
633 /* Put a branch back to the beginning of the receive command list */
634 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
635 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
636
637 /* start rx dma */
638 dbdma_reset(rd);
639 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
640
641 return 1;
642 }
643
644
645 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
646 {
647 struct bmac_data *bp = netdev_priv(dev);
648 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
649 int i;
650
651 /* see if there's a free slot in the tx ring */
652 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
653 /* bp->tx_empty, bp->tx_fill)); */
654 i = bp->tx_fill + 1;
655 if (i >= N_TX_RING)
656 i = 0;
657 if (i == bp->tx_empty) {
658 netif_stop_queue(dev);
659 bp->tx_fullup = 1;
660 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
661 return -1; /* can't take it at the moment */
662 }
663
664 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
665
666 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
667
668 bp->tx_bufs[bp->tx_fill] = skb;
669 bp->tx_fill = i;
670
671 bp->stats.tx_bytes += skb->len;
672
673 dbdma_continue(td);
674
675 return 0;
676 }
677
678 static int rxintcount;
679
680 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id)
681 {
682 struct net_device *dev = (struct net_device *) dev_id;
683 struct bmac_data *bp = netdev_priv(dev);
684 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
685 volatile struct dbdma_cmd *cp;
686 int i, nb, stat;
687 struct sk_buff *skb;
688 unsigned int residual;
689 int last;
690 unsigned long flags;
691
692 spin_lock_irqsave(&bp->lock, flags);
693
694 if (++rxintcount < 10) {
695 XXDEBUG(("bmac_rxdma_intr\n"));
696 }
697
698 last = -1;
699 i = bp->rx_empty;
700
701 while (1) {
702 cp = &bp->rx_cmds[i];
703 stat = ld_le16(&cp->xfer_status);
704 residual = ld_le16(&cp->res_count);
705 if ((stat & ACTIVE) == 0)
706 break;
707 nb = RX_BUFLEN - residual - 2;
708 if (nb < (ETHERMINPACKET - ETHERCRC)) {
709 skb = NULL;
710 bp->stats.rx_length_errors++;
711 bp->stats.rx_errors++;
712 } else {
713 skb = bp->rx_bufs[i];
714 bp->rx_bufs[i] = NULL;
715 }
716 if (skb != NULL) {
717 nb -= ETHERCRC;
718 skb_put(skb, nb);
719 skb->protocol = eth_type_trans(skb, dev);
720 netif_rx(skb);
721 dev->last_rx = jiffies;
722 ++bp->stats.rx_packets;
723 bp->stats.rx_bytes += nb;
724 } else {
725 ++bp->stats.rx_dropped;
726 }
727 dev->last_rx = jiffies;
728 if ((skb = bp->rx_bufs[i]) == NULL) {
729 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
730 if (skb != NULL)
731 skb_reserve(bp->rx_bufs[i], 2);
732 }
733 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
734 st_le16(&cp->res_count, 0);
735 st_le16(&cp->xfer_status, 0);
736 last = i;
737 if (++i >= N_RX_RING) i = 0;
738 }
739
740 if (last != -1) {
741 bp->rx_fill = last;
742 bp->rx_empty = i;
743 }
744
745 dbdma_continue(rd);
746 spin_unlock_irqrestore(&bp->lock, flags);
747
748 if (rxintcount < 10) {
749 XXDEBUG(("bmac_rxdma_intr done\n"));
750 }
751 return IRQ_HANDLED;
752 }
753
754 static int txintcount;
755
756 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id)
757 {
758 struct net_device *dev = (struct net_device *) dev_id;
759 struct bmac_data *bp = netdev_priv(dev);
760 volatile struct dbdma_cmd *cp;
761 int stat;
762 unsigned long flags;
763
764 spin_lock_irqsave(&bp->lock, flags);
765
766 if (txintcount++ < 10) {
767 XXDEBUG(("bmac_txdma_intr\n"));
768 }
769
770 /* del_timer(&bp->tx_timeout); */
771 /* bp->timeout_active = 0; */
772
773 while (1) {
774 cp = &bp->tx_cmds[bp->tx_empty];
775 stat = ld_le16(&cp->xfer_status);
776 if (txintcount < 10) {
777 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
778 }
779 if (!(stat & ACTIVE)) {
780 /*
781 * status field might not have been filled by DBDMA
782 */
783 if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
784 break;
785 }
786
787 if (bp->tx_bufs[bp->tx_empty]) {
788 ++bp->stats.tx_packets;
789 dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]);
790 }
791 bp->tx_bufs[bp->tx_empty] = NULL;
792 bp->tx_fullup = 0;
793 netif_wake_queue(dev);
794 if (++bp->tx_empty >= N_TX_RING)
795 bp->tx_empty = 0;
796 if (bp->tx_empty == bp->tx_fill)
797 break;
798 }
799
800 spin_unlock_irqrestore(&bp->lock, flags);
801
802 if (txintcount < 10) {
803 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
804 }
805
806 bmac_start(dev);
807 return IRQ_HANDLED;
808 }
809
810 static struct net_device_stats *bmac_stats(struct net_device *dev)
811 {
812 struct bmac_data *p = netdev_priv(dev);
813
814 return &p->stats;
815 }
816
817 #ifndef SUNHME_MULTICAST
818 /* Real fast bit-reversal algorithm, 6-bit values */
819 static int reverse6[64] = {
820 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
821 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
822 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
823 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
824 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
825 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
826 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
827 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
828 };
829
830 static unsigned int
831 crc416(unsigned int curval, unsigned short nxtval)
832 {
833 register unsigned int counter, cur = curval, next = nxtval;
834 register int high_crc_set, low_data_set;
835
836 /* Swap bytes */
837 next = ((next & 0x00FF) << 8) | (next >> 8);
838
839 /* Compute bit-by-bit */
840 for (counter = 0; counter < 16; ++counter) {
841 /* is high CRC bit set? */
842 if ((cur & 0x80000000) == 0) high_crc_set = 0;
843 else high_crc_set = 1;
844
845 cur = cur << 1;
846
847 if ((next & 0x0001) == 0) low_data_set = 0;
848 else low_data_set = 1;
849
850 next = next >> 1;
851
852 /* do the XOR */
853 if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
854 }
855 return cur;
856 }
857
858 static unsigned int
859 bmac_crc(unsigned short *address)
860 {
861 unsigned int newcrc;
862
863 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
864 newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
865 newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
866 newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
867
868 return(newcrc);
869 }
870
871 /*
872 * Add requested mcast addr to BMac's hash table filter.
873 *
874 */
875
876 static void
877 bmac_addhash(struct bmac_data *bp, unsigned char *addr)
878 {
879 unsigned int crc;
880 unsigned short mask;
881
882 if (!(*addr)) return;
883 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
884 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
885 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
886 mask = crc % 16;
887 mask = (unsigned char)1 << mask;
888 bp->hash_use_count[crc/16] |= mask;
889 }
890
891 static void
892 bmac_removehash(struct bmac_data *bp, unsigned char *addr)
893 {
894 unsigned int crc;
895 unsigned char mask;
896
897 /* Now, delete the address from the filter copy, as indicated */
898 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
899 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
900 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
901 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
902 mask = crc % 16;
903 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
904 bp->hash_table_mask[crc/16] &= mask;
905 }
906
907 /*
908 * Sync the adapter with the software copy of the multicast mask
909 * (logical address filter).
910 */
911
912 static void
913 bmac_rx_off(struct net_device *dev)
914 {
915 unsigned short rx_cfg;
916
917 rx_cfg = bmread(dev, RXCFG);
918 rx_cfg &= ~RxMACEnable;
919 bmwrite(dev, RXCFG, rx_cfg);
920 do {
921 rx_cfg = bmread(dev, RXCFG);
922 } while (rx_cfg & RxMACEnable);
923 }
924
925 unsigned short
926 bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
927 {
928 unsigned short rx_cfg;
929
930 rx_cfg = bmread(dev, RXCFG);
931 rx_cfg |= RxMACEnable;
932 if (hash_enable) rx_cfg |= RxHashFilterEnable;
933 else rx_cfg &= ~RxHashFilterEnable;
934 if (promisc_enable) rx_cfg |= RxPromiscEnable;
935 else rx_cfg &= ~RxPromiscEnable;
936 bmwrite(dev, RXRST, RxResetValue);
937 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
938 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
939 bmwrite(dev, RXCFG, rx_cfg );
940 return rx_cfg;
941 }
942
943 static void
944 bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
945 {
946 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
947 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
948 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
949 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
950 }
951
952 #if 0
953 static void
954 bmac_add_multi(struct net_device *dev,
955 struct bmac_data *bp, unsigned char *addr)
956 {
957 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
958 bmac_addhash(bp, addr);
959 bmac_rx_off(dev);
960 bmac_update_hash_table_mask(dev, bp);
961 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
962 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
963 }
964
965 static void
966 bmac_remove_multi(struct net_device *dev,
967 struct bmac_data *bp, unsigned char *addr)
968 {
969 bmac_removehash(bp, addr);
970 bmac_rx_off(dev);
971 bmac_update_hash_table_mask(dev, bp);
972 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
973 }
974 #endif
975
976 /* Set or clear the multicast filter for this adaptor.
977 num_addrs == -1 Promiscuous mode, receive all packets
978 num_addrs == 0 Normal mode, clear multicast list
979 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
980 best-effort filtering.
981 */
982 static void bmac_set_multicast(struct net_device *dev)
983 {
984 struct dev_mc_list *dmi;
985 struct bmac_data *bp = netdev_priv(dev);
986 int num_addrs = dev->mc_count;
987 unsigned short rx_cfg;
988 int i;
989
990 if (bp->sleeping)
991 return;
992
993 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
994
995 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
996 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
997 bmac_update_hash_table_mask(dev, bp);
998 rx_cfg = bmac_rx_on(dev, 1, 0);
999 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
1000 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
1001 rx_cfg = bmread(dev, RXCFG);
1002 rx_cfg |= RxPromiscEnable;
1003 bmwrite(dev, RXCFG, rx_cfg);
1004 rx_cfg = bmac_rx_on(dev, 0, 1);
1005 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
1006 } else {
1007 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
1008 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
1009 if (num_addrs == 0) {
1010 rx_cfg = bmac_rx_on(dev, 0, 0);
1011 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
1012 } else {
1013 for (dmi=dev->mc_list; dmi!=NULL; dmi=dmi->next)
1014 bmac_addhash(bp, dmi->dmi_addr);
1015 bmac_update_hash_table_mask(dev, bp);
1016 rx_cfg = bmac_rx_on(dev, 1, 0);
1017 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
1018 }
1019 }
1020 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
1021 }
1022 #else /* ifdef SUNHME_MULTICAST */
1023
1024 /* The version of set_multicast below was lifted from sunhme.c */
1025
1026 static void bmac_set_multicast(struct net_device *dev)
1027 {
1028 struct dev_mc_list *dmi = dev->mc_list;
1029 char *addrs;
1030 int i;
1031 unsigned short rx_cfg;
1032 u32 crc;
1033
1034 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1035 bmwrite(dev, BHASH0, 0xffff);
1036 bmwrite(dev, BHASH1, 0xffff);
1037 bmwrite(dev, BHASH2, 0xffff);
1038 bmwrite(dev, BHASH3, 0xffff);
1039 } else if(dev->flags & IFF_PROMISC) {
1040 rx_cfg = bmread(dev, RXCFG);
1041 rx_cfg |= RxPromiscEnable;
1042 bmwrite(dev, RXCFG, rx_cfg);
1043 } else {
1044 u16 hash_table[4];
1045
1046 rx_cfg = bmread(dev, RXCFG);
1047 rx_cfg &= ~RxPromiscEnable;
1048 bmwrite(dev, RXCFG, rx_cfg);
1049
1050 for(i = 0; i < 4; i++) hash_table[i] = 0;
1051
1052 for(i = 0; i < dev->mc_count; i++) {
1053 addrs = dmi->dmi_addr;
1054 dmi = dmi->next;
1055
1056 if(!(*addrs & 1))
1057 continue;
1058
1059 crc = ether_crc_le(6, addrs);
1060 crc >>= 26;
1061 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1062 }
1063 bmwrite(dev, BHASH0, hash_table[0]);
1064 bmwrite(dev, BHASH1, hash_table[1]);
1065 bmwrite(dev, BHASH2, hash_table[2]);
1066 bmwrite(dev, BHASH3, hash_table[3]);
1067 }
1068 }
1069 #endif /* SUNHME_MULTICAST */
1070
1071 static int miscintcount;
1072
1073 static irqreturn_t bmac_misc_intr(int irq, void *dev_id)
1074 {
1075 struct net_device *dev = (struct net_device *) dev_id;
1076 struct bmac_data *bp = netdev_priv(dev);
1077 unsigned int status = bmread(dev, STATUS);
1078 if (miscintcount++ < 10) {
1079 XXDEBUG(("bmac_misc_intr\n"));
1080 }
1081 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
1082 /* bmac_txdma_intr_inner(irq, dev_id); */
1083 /* if (status & FrameReceived) bp->stats.rx_dropped++; */
1084 if (status & RxErrorMask) bp->stats.rx_errors++;
1085 if (status & RxCRCCntExp) bp->stats.rx_crc_errors++;
1086 if (status & RxLenCntExp) bp->stats.rx_length_errors++;
1087 if (status & RxOverFlow) bp->stats.rx_over_errors++;
1088 if (status & RxAlignCntExp) bp->stats.rx_frame_errors++;
1089
1090 /* if (status & FrameSent) bp->stats.tx_dropped++; */
1091 if (status & TxErrorMask) bp->stats.tx_errors++;
1092 if (status & TxUnderrun) bp->stats.tx_fifo_errors++;
1093 if (status & TxNormalCollExp) bp->stats.collisions++;
1094 return IRQ_HANDLED;
1095 }
1096
1097 /*
1098 * Procedure for reading EEPROM
1099 */
1100 #define SROMAddressLength 5
1101 #define DataInOn 0x0008
1102 #define DataInOff 0x0000
1103 #define Clk 0x0002
1104 #define ChipSelect 0x0001
1105 #define SDIShiftCount 3
1106 #define SD0ShiftCount 2
1107 #define DelayValue 1000 /* number of microseconds */
1108 #define SROMStartOffset 10 /* this is in words */
1109 #define SROMReadCount 3 /* number of words to read from SROM */
1110 #define SROMAddressBits 6
1111 #define EnetAddressOffset 20
1112
1113 static unsigned char
1114 bmac_clock_out_bit(struct net_device *dev)
1115 {
1116 unsigned short data;
1117 unsigned short val;
1118
1119 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1120 udelay(DelayValue);
1121
1122 data = bmread(dev, SROMCSR);
1123 udelay(DelayValue);
1124 val = (data >> SD0ShiftCount) & 1;
1125
1126 bmwrite(dev, SROMCSR, ChipSelect);
1127 udelay(DelayValue);
1128
1129 return val;
1130 }
1131
1132 static void
1133 bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1134 {
1135 unsigned short data;
1136
1137 if (val != 0 && val != 1) return;
1138
1139 data = (val << SDIShiftCount);
1140 bmwrite(dev, SROMCSR, data | ChipSelect );
1141 udelay(DelayValue);
1142
1143 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1144 udelay(DelayValue);
1145
1146 bmwrite(dev, SROMCSR, data | ChipSelect);
1147 udelay(DelayValue);
1148 }
1149
1150 static void
1151 reset_and_select_srom(struct net_device *dev)
1152 {
1153 /* first reset */
1154 bmwrite(dev, SROMCSR, 0);
1155 udelay(DelayValue);
1156
1157 /* send it the read command (110) */
1158 bmac_clock_in_bit(dev, 1);
1159 bmac_clock_in_bit(dev, 1);
1160 bmac_clock_in_bit(dev, 0);
1161 }
1162
1163 static unsigned short
1164 read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1165 {
1166 unsigned short data, val;
1167 int i;
1168
1169 /* send out the address we want to read from */
1170 for (i = 0; i < addr_len; i++) {
1171 val = addr >> (addr_len-i-1);
1172 bmac_clock_in_bit(dev, val & 1);
1173 }
1174
1175 /* Now read in the 16-bit data */
1176 data = 0;
1177 for (i = 0; i < 16; i++) {
1178 val = bmac_clock_out_bit(dev);
1179 data <<= 1;
1180 data |= val;
1181 }
1182 bmwrite(dev, SROMCSR, 0);
1183
1184 return data;
1185 }
1186
1187 /*
1188 * It looks like Cogent and SMC use different methods for calculating
1189 * checksums. What a pain..
1190 */
1191
1192 static int
1193 bmac_verify_checksum(struct net_device *dev)
1194 {
1195 unsigned short data, storedCS;
1196
1197 reset_and_select_srom(dev);
1198 data = read_srom(dev, 3, SROMAddressBits);
1199 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1200
1201 return 0;
1202 }
1203
1204
1205 static void
1206 bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1207 {
1208 int i;
1209 unsigned short data;
1210
1211 for (i = 0; i < 6; i++)
1212 {
1213 reset_and_select_srom(dev);
1214 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1215 ea[2*i] = bitrev8(data & 0x0ff);
1216 ea[2*i+1] = bitrev8((data >> 8) & 0x0ff);
1217 }
1218 }
1219
1220 static void bmac_reset_and_enable(struct net_device *dev)
1221 {
1222 struct bmac_data *bp = netdev_priv(dev);
1223 unsigned long flags;
1224 struct sk_buff *skb;
1225 unsigned char *data;
1226
1227 spin_lock_irqsave(&bp->lock, flags);
1228 bmac_enable_and_reset_chip(dev);
1229 bmac_init_tx_ring(bp);
1230 bmac_init_rx_ring(bp);
1231 bmac_init_chip(dev);
1232 bmac_start_chip(dev);
1233 bmwrite(dev, INTDISABLE, EnableNormal);
1234 bp->sleeping = 0;
1235
1236 /*
1237 * It seems that the bmac can't receive until it's transmitted
1238 * a packet. So we give it a dummy packet to transmit.
1239 */
1240 skb = dev_alloc_skb(ETHERMINPACKET);
1241 if (skb != NULL) {
1242 data = skb_put(skb, ETHERMINPACKET);
1243 memset(data, 0, ETHERMINPACKET);
1244 memcpy(data, dev->dev_addr, 6);
1245 memcpy(data+6, dev->dev_addr, 6);
1246 bmac_transmit_packet(skb, dev);
1247 }
1248 spin_unlock_irqrestore(&bp->lock, flags);
1249 }
1250 static void bmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1251 {
1252 struct bmac_data *bp = netdev_priv(dev);
1253 strcpy(info->driver, "bmac");
1254 strcpy(info->bus_info, bp->mdev->ofdev.dev.bus_id);
1255 }
1256
1257 static const struct ethtool_ops bmac_ethtool_ops = {
1258 .get_drvinfo = bmac_get_drvinfo,
1259 .get_link = ethtool_op_get_link,
1260 };
1261
1262 static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
1263 {
1264 int j, rev, ret;
1265 struct bmac_data *bp;
1266 const unsigned char *prop_addr;
1267 unsigned char addr[6];
1268 struct net_device *dev;
1269 int is_bmac_plus = ((int)match->data) != 0;
1270
1271 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
1272 printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
1273 return -ENODEV;
1274 }
1275 prop_addr = of_get_property(macio_get_of_node(mdev),
1276 "mac-address", NULL);
1277 if (prop_addr == NULL) {
1278 prop_addr = of_get_property(macio_get_of_node(mdev),
1279 "local-mac-address", NULL);
1280 if (prop_addr == NULL) {
1281 printk(KERN_ERR "BMAC: Can't get mac-address\n");
1282 return -ENODEV;
1283 }
1284 }
1285 memcpy(addr, prop_addr, sizeof(addr));
1286
1287 dev = alloc_etherdev(PRIV_BYTES);
1288 if (!dev) {
1289 printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n");
1290 return -ENOMEM;
1291 }
1292
1293 bp = netdev_priv(dev);
1294 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
1295 macio_set_drvdata(mdev, dev);
1296
1297 bp->mdev = mdev;
1298 spin_lock_init(&bp->lock);
1299
1300 if (macio_request_resources(mdev, "bmac")) {
1301 printk(KERN_ERR "BMAC: can't request IO resource !\n");
1302 goto out_free;
1303 }
1304
1305 dev->base_addr = (unsigned long)
1306 ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
1307 if (dev->base_addr == 0)
1308 goto out_release;
1309
1310 dev->irq = macio_irq(mdev, 0);
1311
1312 bmac_enable_and_reset_chip(dev);
1313 bmwrite(dev, INTDISABLE, DisableAll);
1314
1315 rev = addr[0] == 0 && addr[1] == 0xA0;
1316 for (j = 0; j < 6; ++j)
1317 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
1318
1319 /* Enable chip without interrupts for now */
1320 bmac_enable_and_reset_chip(dev);
1321 bmwrite(dev, INTDISABLE, DisableAll);
1322
1323 dev->open = bmac_open;
1324 dev->stop = bmac_close;
1325 dev->ethtool_ops = &bmac_ethtool_ops;
1326 dev->hard_start_xmit = bmac_output;
1327 dev->get_stats = bmac_stats;
1328 dev->set_multicast_list = bmac_set_multicast;
1329 dev->set_mac_address = bmac_set_address;
1330
1331 bmac_get_station_address(dev, addr);
1332 if (bmac_verify_checksum(dev) != 0)
1333 goto err_out_iounmap;
1334
1335 bp->is_bmac_plus = is_bmac_plus;
1336 bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
1337 if (!bp->tx_dma)
1338 goto err_out_iounmap;
1339 bp->tx_dma_intr = macio_irq(mdev, 1);
1340 bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
1341 if (!bp->rx_dma)
1342 goto err_out_iounmap_tx;
1343 bp->rx_dma_intr = macio_irq(mdev, 2);
1344
1345 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1346 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1347
1348 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1349 skb_queue_head_init(bp->queue);
1350
1351 init_timer(&bp->tx_timeout);
1352
1353 ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
1354 if (ret) {
1355 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1356 goto err_out_iounmap_rx;
1357 }
1358 ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
1359 if (ret) {
1360 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
1361 goto err_out_irq0;
1362 }
1363 ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
1364 if (ret) {
1365 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
1366 goto err_out_irq1;
1367 }
1368
1369 /* Mask chip interrupts and disable chip, will be
1370 * re-enabled on open()
1371 */
1372 disable_irq(dev->irq);
1373 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1374
1375 if (register_netdev(dev) != 0) {
1376 printk(KERN_ERR "BMAC: Ethernet registration failed\n");
1377 goto err_out_irq2;
1378 }
1379
1380 printk(KERN_INFO "%s: BMAC%s at", dev->name, (is_bmac_plus? "+": ""));
1381 for (j = 0; j < 6; ++j)
1382 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
1383 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1384 printk("\n");
1385
1386 return 0;
1387
1388 err_out_irq2:
1389 free_irq(bp->rx_dma_intr, dev);
1390 err_out_irq1:
1391 free_irq(bp->tx_dma_intr, dev);
1392 err_out_irq0:
1393 free_irq(dev->irq, dev);
1394 err_out_iounmap_rx:
1395 iounmap(bp->rx_dma);
1396 err_out_iounmap_tx:
1397 iounmap(bp->tx_dma);
1398 err_out_iounmap:
1399 iounmap((void __iomem *)dev->base_addr);
1400 out_release:
1401 macio_release_resources(mdev);
1402 out_free:
1403 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1404 free_netdev(dev);
1405
1406 return -ENODEV;
1407 }
1408
1409 static int bmac_open(struct net_device *dev)
1410 {
1411 struct bmac_data *bp = netdev_priv(dev);
1412 /* XXDEBUG(("bmac: enter open\n")); */
1413 /* reset the chip */
1414 bp->opened = 1;
1415 bmac_reset_and_enable(dev);
1416 enable_irq(dev->irq);
1417 return 0;
1418 }
1419
1420 static int bmac_close(struct net_device *dev)
1421 {
1422 struct bmac_data *bp = netdev_priv(dev);
1423 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1424 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1425 unsigned short config;
1426 int i;
1427
1428 bp->sleeping = 1;
1429
1430 /* disable rx and tx */
1431 config = bmread(dev, RXCFG);
1432 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1433
1434 config = bmread(dev, TXCFG);
1435 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1436
1437 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1438
1439 /* disable rx and tx dma */
1440 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1441 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1442
1443 /* free some skb's */
1444 XXDEBUG(("bmac: free rx bufs\n"));
1445 for (i=0; i<N_RX_RING; i++) {
1446 if (bp->rx_bufs[i] != NULL) {
1447 dev_kfree_skb(bp->rx_bufs[i]);
1448 bp->rx_bufs[i] = NULL;
1449 }
1450 }
1451 XXDEBUG(("bmac: free tx bufs\n"));
1452 for (i = 0; i<N_TX_RING; i++) {
1453 if (bp->tx_bufs[i] != NULL) {
1454 dev_kfree_skb(bp->tx_bufs[i]);
1455 bp->tx_bufs[i] = NULL;
1456 }
1457 }
1458 XXDEBUG(("bmac: all bufs freed\n"));
1459
1460 bp->opened = 0;
1461 disable_irq(dev->irq);
1462 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1463
1464 return 0;
1465 }
1466
1467 static void
1468 bmac_start(struct net_device *dev)
1469 {
1470 struct bmac_data *bp = netdev_priv(dev);
1471 int i;
1472 struct sk_buff *skb;
1473 unsigned long flags;
1474
1475 if (bp->sleeping)
1476 return;
1477
1478 spin_lock_irqsave(&bp->lock, flags);
1479 while (1) {
1480 i = bp->tx_fill + 1;
1481 if (i >= N_TX_RING)
1482 i = 0;
1483 if (i == bp->tx_empty)
1484 break;
1485 skb = skb_dequeue(bp->queue);
1486 if (skb == NULL)
1487 break;
1488 bmac_transmit_packet(skb, dev);
1489 }
1490 spin_unlock_irqrestore(&bp->lock, flags);
1491 }
1492
1493 static int
1494 bmac_output(struct sk_buff *skb, struct net_device *dev)
1495 {
1496 struct bmac_data *bp = netdev_priv(dev);
1497 skb_queue_tail(bp->queue, skb);
1498 bmac_start(dev);
1499 return 0;
1500 }
1501
1502 static void bmac_tx_timeout(unsigned long data)
1503 {
1504 struct net_device *dev = (struct net_device *) data;
1505 struct bmac_data *bp = netdev_priv(dev);
1506 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1507 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1508 volatile struct dbdma_cmd *cp;
1509 unsigned long flags;
1510 unsigned short config, oldConfig;
1511 int i;
1512
1513 XXDEBUG(("bmac: tx_timeout called\n"));
1514 spin_lock_irqsave(&bp->lock, flags);
1515 bp->timeout_active = 0;
1516
1517 /* update various counters */
1518 /* bmac_handle_misc_intrs(bp, 0); */
1519
1520 cp = &bp->tx_cmds[bp->tx_empty];
1521 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1522 /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1523 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1524
1525 /* turn off both tx and rx and reset the chip */
1526 config = bmread(dev, RXCFG);
1527 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1528 config = bmread(dev, TXCFG);
1529 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1530 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1531 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1532 bmac_enable_and_reset_chip(dev);
1533
1534 /* restart rx dma */
1535 cp = bus_to_virt(ld_le32(&rd->cmdptr));
1536 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1537 out_le16(&cp->xfer_status, 0);
1538 out_le32(&rd->cmdptr, virt_to_bus(cp));
1539 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1540
1541 /* fix up the transmit side */
1542 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1543 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1544 i = bp->tx_empty;
1545 ++bp->stats.tx_errors;
1546 if (i != bp->tx_fill) {
1547 dev_kfree_skb(bp->tx_bufs[i]);
1548 bp->tx_bufs[i] = NULL;
1549 if (++i >= N_TX_RING) i = 0;
1550 bp->tx_empty = i;
1551 }
1552 bp->tx_fullup = 0;
1553 netif_wake_queue(dev);
1554 if (i != bp->tx_fill) {
1555 cp = &bp->tx_cmds[i];
1556 out_le16(&cp->xfer_status, 0);
1557 out_le16(&cp->command, OUTPUT_LAST);
1558 out_le32(&td->cmdptr, virt_to_bus(cp));
1559 out_le32(&td->control, DBDMA_SET(RUN));
1560 /* bmac_set_timeout(dev); */
1561 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1562 }
1563
1564 /* turn it back on */
1565 oldConfig = bmread(dev, RXCFG);
1566 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1567 oldConfig = bmread(dev, TXCFG);
1568 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1569
1570 spin_unlock_irqrestore(&bp->lock, flags);
1571 }
1572
1573 #if 0
1574 static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1575 {
1576 int i,*ip;
1577
1578 for (i=0;i< count;i++) {
1579 ip = (int*)(cp+i);
1580
1581 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1582 ld_le32(ip+0),
1583 ld_le32(ip+1),
1584 ld_le32(ip+2),
1585 ld_le32(ip+3));
1586 }
1587
1588 }
1589 #endif
1590
1591 #if 0
1592 static int
1593 bmac_proc_info(char *buffer, char **start, off_t offset, int length)
1594 {
1595 int len = 0;
1596 off_t pos = 0;
1597 off_t begin = 0;
1598 int i;
1599
1600 if (bmac_devs == NULL)
1601 return (-ENOSYS);
1602
1603 len += sprintf(buffer, "BMAC counters & registers\n");
1604
1605 for (i = 0; i<N_REG_ENTRIES; i++) {
1606 len += sprintf(buffer + len, "%s: %#08x\n",
1607 reg_entries[i].name,
1608 bmread(bmac_devs, reg_entries[i].reg_offset));
1609 pos = begin + len;
1610
1611 if (pos < offset) {
1612 len = 0;
1613 begin = pos;
1614 }
1615
1616 if (pos > offset+length) break;
1617 }
1618
1619 *start = buffer + (offset - begin);
1620 len -= (offset - begin);
1621
1622 if (len > length) len = length;
1623
1624 return len;
1625 }
1626 #endif
1627
1628 static int __devexit bmac_remove(struct macio_dev *mdev)
1629 {
1630 struct net_device *dev = macio_get_drvdata(mdev);
1631 struct bmac_data *bp = netdev_priv(dev);
1632
1633 unregister_netdev(dev);
1634
1635 free_irq(dev->irq, dev);
1636 free_irq(bp->tx_dma_intr, dev);
1637 free_irq(bp->rx_dma_intr, dev);
1638
1639 iounmap((void __iomem *)dev->base_addr);
1640 iounmap(bp->tx_dma);
1641 iounmap(bp->rx_dma);
1642
1643 macio_release_resources(mdev);
1644
1645 free_netdev(dev);
1646
1647 return 0;
1648 }
1649
1650 static struct of_device_id bmac_match[] =
1651 {
1652 {
1653 .name = "bmac",
1654 .data = (void *)0,
1655 },
1656 {
1657 .type = "network",
1658 .compatible = "bmac+",
1659 .data = (void *)1,
1660 },
1661 {},
1662 };
1663 MODULE_DEVICE_TABLE (of, bmac_match);
1664
1665 static struct macio_driver bmac_driver =
1666 {
1667 .name = "bmac",
1668 .match_table = bmac_match,
1669 .probe = bmac_probe,
1670 .remove = bmac_remove,
1671 #ifdef CONFIG_PM
1672 .suspend = bmac_suspend,
1673 .resume = bmac_resume,
1674 #endif
1675 };
1676
1677
1678 static int __init bmac_init(void)
1679 {
1680 if (bmac_emergency_rxbuf == NULL) {
1681 bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
1682 if (bmac_emergency_rxbuf == NULL) {
1683 printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n");
1684 return -ENOMEM;
1685 }
1686 }
1687
1688 return macio_register_driver(&bmac_driver);
1689 }
1690
1691 static void __exit bmac_exit(void)
1692 {
1693 macio_unregister_driver(&bmac_driver);
1694
1695 kfree(bmac_emergency_rxbuf);
1696 bmac_emergency_rxbuf = NULL;
1697 }
1698
1699 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1700 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1701 MODULE_LICENSE("GPL");
1702
1703 module_init(bmac_init);
1704 module_exit(bmac_exit);
Linux kernel - Deliverables
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