2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 * Copyright (C) 1998 Randy Gobbel.
7 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
8 * dynamic procfs inode.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/timer.h>
17 #include <linux/proc_fs.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/crc32.h>
21 #include <linux/bitrev.h>
22 #include <linux/ethtool.h>
24 #include <asm/dbdma.h>
27 #include <asm/pgtable.h>
28 #include <asm/machdep.h>
29 #include <asm/pmac_feature.h>
30 #include <asm/macio.h>
35 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
36 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
39 * CRC polynomial - used in working out multicast filter bits.
41 #define ENET_CRCPOLY 0x04c11db7
43 /* switch to use multicast code lifted from sunhme driver */
44 #define SUNHME_MULTICAST
48 #define MAX_TX_ACTIVE 1
50 #define ETHERMINPACKET 64
52 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
53 #define TX_TIMEOUT HZ /* 1 second */
55 /* Bits in transmit DMA status */
56 #define TX_DMA_ERR 0x80
61 /* volatile struct bmac *bmac; */
62 struct sk_buff_head
*queue
;
63 volatile struct dbdma_regs __iomem
*tx_dma
;
65 volatile struct dbdma_regs __iomem
*rx_dma
;
67 volatile struct dbdma_cmd
*tx_cmds
; /* xmit dma command list */
68 volatile struct dbdma_cmd
*rx_cmds
; /* recv dma command list */
69 struct macio_dev
*mdev
;
71 struct sk_buff
*rx_bufs
[N_RX_RING
];
74 struct sk_buff
*tx_bufs
[N_TX_RING
];
77 unsigned char tx_fullup
;
78 struct net_device_stats stats
;
79 struct timer_list tx_timeout
;
83 unsigned short hash_use_count
[64];
84 unsigned short hash_table_mask
[4];
88 #if 0 /* Move that to ethtool */
90 typedef struct bmac_reg_entry
{
92 unsigned short reg_offset
;
95 #define N_REG_ENTRIES 31
97 static bmac_reg_entry_t reg_entries
[N_REG_ENTRIES
] = {
99 {"MEMDATAHI", MEMDATAHI
},
100 {"MEMDATALO", MEMDATALO
},
133 static unsigned char *bmac_emergency_rxbuf
;
136 * Number of bytes of private data per BMAC: allow enough for
137 * the rx and tx dma commands plus a branch dma command each,
138 * and another 16 bytes to allow us to align the dma command
139 * buffers on a 16 byte boundary.
141 #define PRIV_BYTES (sizeof(struct bmac_data) \
142 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
143 + sizeof(struct sk_buff_head))
145 static int bmac_open(struct net_device
*dev
);
146 static int bmac_close(struct net_device
*dev
);
147 static int bmac_transmit_packet(struct sk_buff
*skb
, struct net_device
*dev
);
148 static struct net_device_stats
*bmac_stats(struct net_device
*dev
);
149 static void bmac_set_multicast(struct net_device
*dev
);
150 static void bmac_reset_and_enable(struct net_device
*dev
);
151 static void bmac_start_chip(struct net_device
*dev
);
152 static void bmac_init_chip(struct net_device
*dev
);
153 static void bmac_init_registers(struct net_device
*dev
);
154 static void bmac_enable_and_reset_chip(struct net_device
*dev
);
155 static int bmac_set_address(struct net_device
*dev
, void *addr
);
156 static irqreturn_t
bmac_misc_intr(int irq
, void *dev_id
);
157 static irqreturn_t
bmac_txdma_intr(int irq
, void *dev_id
);
158 static irqreturn_t
bmac_rxdma_intr(int irq
, void *dev_id
);
159 static void bmac_set_timeout(struct net_device
*dev
);
160 static void bmac_tx_timeout(unsigned long data
);
161 static int bmac_output(struct sk_buff
*skb
, struct net_device
*dev
);
162 static void bmac_start(struct net_device
*dev
);
164 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
165 #define DBDMA_CLEAR(x) ( (x) << 16)
168 dbdma_st32(volatile __u32 __iomem
*a
, unsigned long x
)
170 __asm__
volatile( "stwbrx %0,0,%1" : : "r" (x
), "r" (a
) : "memory");
174 static inline unsigned long
175 dbdma_ld32(volatile __u32 __iomem
*a
)
178 __asm__
volatile ("lwbrx %0,0,%1" : "=r" (swap
) : "r" (a
));
183 dbdma_continue(volatile struct dbdma_regs __iomem
*dmap
)
185 dbdma_st32(&dmap
->control
,
186 DBDMA_SET(RUN
|WAKE
) | DBDMA_CLEAR(PAUSE
|DEAD
));
191 dbdma_reset(volatile struct dbdma_regs __iomem
*dmap
)
193 dbdma_st32(&dmap
->control
,
194 DBDMA_CLEAR(ACTIVE
|DEAD
|WAKE
|FLUSH
|PAUSE
|RUN
));
196 while (dbdma_ld32(&dmap
->status
) & RUN
)
201 dbdma_setcmd(volatile struct dbdma_cmd
*cp
,
202 unsigned short cmd
, unsigned count
, unsigned long addr
,
203 unsigned long cmd_dep
)
205 out_le16(&cp
->command
, cmd
);
206 out_le16(&cp
->req_count
, count
);
207 out_le32(&cp
->phy_addr
, addr
);
208 out_le32(&cp
->cmd_dep
, cmd_dep
);
209 out_le16(&cp
->xfer_status
, 0);
210 out_le16(&cp
->res_count
, 0);
214 void bmwrite(struct net_device
*dev
, unsigned long reg_offset
, unsigned data
)
216 out_le16((void __iomem
*)dev
->base_addr
+ reg_offset
, data
);
221 unsigned short bmread(struct net_device
*dev
, unsigned long reg_offset
)
223 return in_le16((void __iomem
*)dev
->base_addr
+ reg_offset
);
227 bmac_enable_and_reset_chip(struct net_device
*dev
)
229 struct bmac_data
*bp
= netdev_priv(dev
);
230 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
231 volatile struct dbdma_regs __iomem
*td
= bp
->tx_dma
;
238 pmac_call_feature(PMAC_FTR_BMAC_ENABLE
, macio_get_of_node(bp
->mdev
), 0, 1);
241 #define MIFDELAY udelay(10)
244 bmac_mif_readbits(struct net_device
*dev
, int nb
)
246 unsigned int val
= 0;
249 bmwrite(dev
, MIFCSR
, 0);
251 if (bmread(dev
, MIFCSR
) & 8)
253 bmwrite(dev
, MIFCSR
, 1);
256 bmwrite(dev
, MIFCSR
, 0);
258 bmwrite(dev
, MIFCSR
, 1);
264 bmac_mif_writebits(struct net_device
*dev
, unsigned int val
, int nb
)
269 b
= (val
& (1 << nb
))? 6: 4;
270 bmwrite(dev
, MIFCSR
, b
);
272 bmwrite(dev
, MIFCSR
, b
|1);
278 bmac_mif_read(struct net_device
*dev
, unsigned int addr
)
282 bmwrite(dev
, MIFCSR
, 4);
284 bmac_mif_writebits(dev
, ~0U, 32);
285 bmac_mif_writebits(dev
, 6, 4);
286 bmac_mif_writebits(dev
, addr
, 10);
287 bmwrite(dev
, MIFCSR
, 2);
289 bmwrite(dev
, MIFCSR
, 1);
291 val
= bmac_mif_readbits(dev
, 17);
292 bmwrite(dev
, MIFCSR
, 4);
298 bmac_mif_write(struct net_device
*dev
, unsigned int addr
, unsigned int val
)
300 bmwrite(dev
, MIFCSR
, 4);
302 bmac_mif_writebits(dev
, ~0U, 32);
303 bmac_mif_writebits(dev
, 5, 4);
304 bmac_mif_writebits(dev
, addr
, 10);
305 bmac_mif_writebits(dev
, 2, 2);
306 bmac_mif_writebits(dev
, val
, 16);
307 bmac_mif_writebits(dev
, 3, 2);
311 bmac_init_registers(struct net_device
*dev
)
313 struct bmac_data
*bp
= netdev_priv(dev
);
314 volatile unsigned short regValue
;
315 unsigned short *pWord16
;
318 /* XXDEBUG(("bmac: enter init_registers\n")); */
320 bmwrite(dev
, RXRST
, RxResetValue
);
321 bmwrite(dev
, TXRST
, TxResetBit
);
327 regValue
= bmread(dev
, TXRST
); /* wait for reset to clear..acknowledge */
328 } while ((regValue
& TxResetBit
) && i
> 0);
330 if (!bp
->is_bmac_plus
) {
331 regValue
= bmread(dev
, XCVRIF
);
332 regValue
|= ClkBit
| SerialMode
| COLActiveLow
;
333 bmwrite(dev
, XCVRIF
, regValue
);
337 bmwrite(dev
, RSEED
, (unsigned short)0x1968);
339 regValue
= bmread(dev
, XIFC
);
340 regValue
|= TxOutputEnable
;
341 bmwrite(dev
, XIFC
, regValue
);
345 /* set collision counters to 0 */
346 bmwrite(dev
, NCCNT
, 0);
347 bmwrite(dev
, NTCNT
, 0);
348 bmwrite(dev
, EXCNT
, 0);
349 bmwrite(dev
, LTCNT
, 0);
351 /* set rx counters to 0 */
352 bmwrite(dev
, FRCNT
, 0);
353 bmwrite(dev
, LECNT
, 0);
354 bmwrite(dev
, AECNT
, 0);
355 bmwrite(dev
, FECNT
, 0);
356 bmwrite(dev
, RXCV
, 0);
358 /* set tx fifo information */
359 bmwrite(dev
, TXTH
, 4); /* 4 octets before tx starts */
361 bmwrite(dev
, TXFIFOCSR
, 0); /* first disable txFIFO */
362 bmwrite(dev
, TXFIFOCSR
, TxFIFOEnable
);
364 /* set rx fifo information */
365 bmwrite(dev
, RXFIFOCSR
, 0); /* first disable rxFIFO */
366 bmwrite(dev
, RXFIFOCSR
, RxFIFOEnable
);
368 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
369 bmread(dev
, STATUS
); /* read it just to clear it */
371 /* zero out the chip Hash Filter registers */
372 for (i
=0; i
<4; i
++) bp
->hash_table_mask
[i
] = 0;
373 bmwrite(dev
, BHASH3
, bp
->hash_table_mask
[0]); /* bits 15 - 0 */
374 bmwrite(dev
, BHASH2
, bp
->hash_table_mask
[1]); /* bits 31 - 16 */
375 bmwrite(dev
, BHASH1
, bp
->hash_table_mask
[2]); /* bits 47 - 32 */
376 bmwrite(dev
, BHASH0
, bp
->hash_table_mask
[3]); /* bits 63 - 48 */
378 pWord16
= (unsigned short *)dev
->dev_addr
;
379 bmwrite(dev
, MADD0
, *pWord16
++);
380 bmwrite(dev
, MADD1
, *pWord16
++);
381 bmwrite(dev
, MADD2
, *pWord16
);
383 bmwrite(dev
, RXCFG
, RxCRCNoStrip
| RxHashFilterEnable
| RxRejectOwnPackets
);
385 bmwrite(dev
, INTDISABLE
, EnableNormal
);
392 bmac_disable_interrupts(struct net_device
*dev
)
394 bmwrite(dev
, INTDISABLE
, DisableAll
);
398 bmac_enable_interrupts(struct net_device
*dev
)
400 bmwrite(dev
, INTDISABLE
, EnableNormal
);
406 bmac_start_chip(struct net_device
*dev
)
408 struct bmac_data
*bp
= netdev_priv(dev
);
409 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
410 unsigned short oldConfig
;
412 /* enable rx dma channel */
415 oldConfig
= bmread(dev
, TXCFG
);
416 bmwrite(dev
, TXCFG
, oldConfig
| TxMACEnable
);
418 /* turn on rx plus any other bits already on (promiscuous possibly) */
419 oldConfig
= bmread(dev
, RXCFG
);
420 bmwrite(dev
, RXCFG
, oldConfig
| RxMACEnable
);
425 bmac_init_phy(struct net_device
*dev
)
428 struct bmac_data
*bp
= netdev_priv(dev
);
430 printk(KERN_DEBUG
"phy registers:");
431 for (addr
= 0; addr
< 32; ++addr
) {
433 printk("\n" KERN_DEBUG
);
434 printk(" %.4x", bmac_mif_read(dev
, addr
));
437 if (bp
->is_bmac_plus
) {
438 unsigned int capable
, ctrl
;
440 ctrl
= bmac_mif_read(dev
, 0);
441 capable
= ((bmac_mif_read(dev
, 1) & 0xf800) >> 6) | 1;
442 if (bmac_mif_read(dev
, 4) != capable
443 || (ctrl
& 0x1000) == 0) {
444 bmac_mif_write(dev
, 4, capable
);
445 bmac_mif_write(dev
, 0, 0x1200);
447 bmac_mif_write(dev
, 0, 0x1000);
451 static void bmac_init_chip(struct net_device
*dev
)
454 bmac_init_registers(dev
);
458 static int bmac_suspend(struct macio_dev
*mdev
, pm_message_t state
)
460 struct net_device
* dev
= macio_get_drvdata(mdev
);
461 struct bmac_data
*bp
= netdev_priv(dev
);
463 unsigned short config
;
466 netif_device_detach(dev
);
467 /* prolly should wait for dma to finish & turn off the chip */
468 spin_lock_irqsave(&bp
->lock
, flags
);
469 if (bp
->timeout_active
) {
470 del_timer(&bp
->tx_timeout
);
471 bp
->timeout_active
= 0;
473 disable_irq(dev
->irq
);
474 disable_irq(bp
->tx_dma_intr
);
475 disable_irq(bp
->rx_dma_intr
);
477 spin_unlock_irqrestore(&bp
->lock
, flags
);
479 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
480 volatile struct dbdma_regs __iomem
*td
= bp
->tx_dma
;
482 config
= bmread(dev
, RXCFG
);
483 bmwrite(dev
, RXCFG
, (config
& ~RxMACEnable
));
484 config
= bmread(dev
, TXCFG
);
485 bmwrite(dev
, TXCFG
, (config
& ~TxMACEnable
));
486 bmwrite(dev
, INTDISABLE
, DisableAll
); /* disable all intrs */
487 /* disable rx and tx dma */
488 st_le32(&rd
->control
, DBDMA_CLEAR(RUN
|PAUSE
|FLUSH
|WAKE
)); /* clear run bit */
489 st_le32(&td
->control
, DBDMA_CLEAR(RUN
|PAUSE
|FLUSH
|WAKE
)); /* clear run bit */
490 /* free some skb's */
491 for (i
=0; i
<N_RX_RING
; i
++) {
492 if (bp
->rx_bufs
[i
] != NULL
) {
493 dev_kfree_skb(bp
->rx_bufs
[i
]);
494 bp
->rx_bufs
[i
] = NULL
;
497 for (i
= 0; i
<N_TX_RING
; i
++) {
498 if (bp
->tx_bufs
[i
] != NULL
) {
499 dev_kfree_skb(bp
->tx_bufs
[i
]);
500 bp
->tx_bufs
[i
] = NULL
;
504 pmac_call_feature(PMAC_FTR_BMAC_ENABLE
, macio_get_of_node(bp
->mdev
), 0, 0);
508 static int bmac_resume(struct macio_dev
*mdev
)
510 struct net_device
* dev
= macio_get_drvdata(mdev
);
511 struct bmac_data
*bp
= netdev_priv(dev
);
513 /* see if this is enough */
515 bmac_reset_and_enable(dev
);
517 enable_irq(dev
->irq
);
518 enable_irq(bp
->tx_dma_intr
);
519 enable_irq(bp
->rx_dma_intr
);
520 netif_device_attach(dev
);
524 #endif /* CONFIG_PM */
526 static int bmac_set_address(struct net_device
*dev
, void *addr
)
528 struct bmac_data
*bp
= netdev_priv(dev
);
529 unsigned char *p
= addr
;
530 unsigned short *pWord16
;
534 XXDEBUG(("bmac: enter set_address\n"));
535 spin_lock_irqsave(&bp
->lock
, flags
);
537 for (i
= 0; i
< 6; ++i
) {
538 dev
->dev_addr
[i
] = p
[i
];
540 /* load up the hardware address */
541 pWord16
= (unsigned short *)dev
->dev_addr
;
542 bmwrite(dev
, MADD0
, *pWord16
++);
543 bmwrite(dev
, MADD1
, *pWord16
++);
544 bmwrite(dev
, MADD2
, *pWord16
);
546 spin_unlock_irqrestore(&bp
->lock
, flags
);
547 XXDEBUG(("bmac: exit set_address\n"));
551 static inline void bmac_set_timeout(struct net_device
*dev
)
553 struct bmac_data
*bp
= netdev_priv(dev
);
556 spin_lock_irqsave(&bp
->lock
, flags
);
557 if (bp
->timeout_active
)
558 del_timer(&bp
->tx_timeout
);
559 bp
->tx_timeout
.expires
= jiffies
+ TX_TIMEOUT
;
560 bp
->tx_timeout
.function
= bmac_tx_timeout
;
561 bp
->tx_timeout
.data
= (unsigned long) dev
;
562 add_timer(&bp
->tx_timeout
);
563 bp
->timeout_active
= 1;
564 spin_unlock_irqrestore(&bp
->lock
, flags
);
568 bmac_construct_xmt(struct sk_buff
*skb
, volatile struct dbdma_cmd
*cp
)
576 baddr
= virt_to_bus(vaddr
);
578 dbdma_setcmd(cp
, (OUTPUT_LAST
| INTR_ALWAYS
| WAIT_IFCLR
), len
, baddr
, 0);
582 bmac_construct_rxbuff(struct sk_buff
*skb
, volatile struct dbdma_cmd
*cp
)
584 unsigned char *addr
= skb
? skb
->data
: bmac_emergency_rxbuf
;
586 dbdma_setcmd(cp
, (INPUT_LAST
| INTR_ALWAYS
), RX_BUFLEN
,
587 virt_to_bus(addr
), 0);
591 bmac_init_tx_ring(struct bmac_data
*bp
)
593 volatile struct dbdma_regs __iomem
*td
= bp
->tx_dma
;
595 memset((char *)bp
->tx_cmds
, 0, (N_TX_RING
+1) * sizeof(struct dbdma_cmd
));
601 /* put a branch at the end of the tx command list */
602 dbdma_setcmd(&bp
->tx_cmds
[N_TX_RING
],
603 (DBDMA_NOP
| BR_ALWAYS
), 0, 0, virt_to_bus(bp
->tx_cmds
));
607 out_le32(&td
->wait_sel
, 0x00200020);
608 out_le32(&td
->cmdptr
, virt_to_bus(bp
->tx_cmds
));
612 bmac_init_rx_ring(struct bmac_data
*bp
)
614 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
618 /* initialize list of sk_buffs for receiving and set up recv dma */
619 memset((char *)bp
->rx_cmds
, 0,
620 (N_RX_RING
+ 1) * sizeof(struct dbdma_cmd
));
621 for (i
= 0; i
< N_RX_RING
; i
++) {
622 if ((skb
= bp
->rx_bufs
[i
]) == NULL
) {
623 bp
->rx_bufs
[i
] = skb
= dev_alloc_skb(RX_BUFLEN
+2);
627 bmac_construct_rxbuff(skb
, &bp
->rx_cmds
[i
]);
633 /* Put a branch back to the beginning of the receive command list */
634 dbdma_setcmd(&bp
->rx_cmds
[N_RX_RING
],
635 (DBDMA_NOP
| BR_ALWAYS
), 0, 0, virt_to_bus(bp
->rx_cmds
));
639 out_le32(&rd
->cmdptr
, virt_to_bus(bp
->rx_cmds
));
645 static int bmac_transmit_packet(struct sk_buff
*skb
, struct net_device
*dev
)
647 struct bmac_data
*bp
= netdev_priv(dev
);
648 volatile struct dbdma_regs __iomem
*td
= bp
->tx_dma
;
651 /* see if there's a free slot in the tx ring */
652 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
653 /* bp->tx_empty, bp->tx_fill)); */
657 if (i
== bp
->tx_empty
) {
658 netif_stop_queue(dev
);
660 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
661 return -1; /* can't take it at the moment */
664 dbdma_setcmd(&bp
->tx_cmds
[i
], DBDMA_STOP
, 0, 0, 0);
666 bmac_construct_xmt(skb
, &bp
->tx_cmds
[bp
->tx_fill
]);
668 bp
->tx_bufs
[bp
->tx_fill
] = skb
;
671 bp
->stats
.tx_bytes
+= skb
->len
;
678 static int rxintcount
;
680 static irqreturn_t
bmac_rxdma_intr(int irq
, void *dev_id
)
682 struct net_device
*dev
= (struct net_device
*) dev_id
;
683 struct bmac_data
*bp
= netdev_priv(dev
);
684 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
685 volatile struct dbdma_cmd
*cp
;
688 unsigned int residual
;
692 spin_lock_irqsave(&bp
->lock
, flags
);
694 if (++rxintcount
< 10) {
695 XXDEBUG(("bmac_rxdma_intr\n"));
702 cp
= &bp
->rx_cmds
[i
];
703 stat
= ld_le16(&cp
->xfer_status
);
704 residual
= ld_le16(&cp
->res_count
);
705 if ((stat
& ACTIVE
) == 0)
707 nb
= RX_BUFLEN
- residual
- 2;
708 if (nb
< (ETHERMINPACKET
- ETHERCRC
)) {
710 bp
->stats
.rx_length_errors
++;
711 bp
->stats
.rx_errors
++;
713 skb
= bp
->rx_bufs
[i
];
714 bp
->rx_bufs
[i
] = NULL
;
719 skb
->protocol
= eth_type_trans(skb
, dev
);
721 dev
->last_rx
= jiffies
;
722 ++bp
->stats
.rx_packets
;
723 bp
->stats
.rx_bytes
+= nb
;
725 ++bp
->stats
.rx_dropped
;
727 dev
->last_rx
= jiffies
;
728 if ((skb
= bp
->rx_bufs
[i
]) == NULL
) {
729 bp
->rx_bufs
[i
] = skb
= dev_alloc_skb(RX_BUFLEN
+2);
731 skb_reserve(bp
->rx_bufs
[i
], 2);
733 bmac_construct_rxbuff(skb
, &bp
->rx_cmds
[i
]);
734 st_le16(&cp
->res_count
, 0);
735 st_le16(&cp
->xfer_status
, 0);
737 if (++i
>= N_RX_RING
) i
= 0;
746 spin_unlock_irqrestore(&bp
->lock
, flags
);
748 if (rxintcount
< 10) {
749 XXDEBUG(("bmac_rxdma_intr done\n"));
754 static int txintcount
;
756 static irqreturn_t
bmac_txdma_intr(int irq
, void *dev_id
)
758 struct net_device
*dev
= (struct net_device
*) dev_id
;
759 struct bmac_data
*bp
= netdev_priv(dev
);
760 volatile struct dbdma_cmd
*cp
;
764 spin_lock_irqsave(&bp
->lock
, flags
);
766 if (txintcount
++ < 10) {
767 XXDEBUG(("bmac_txdma_intr\n"));
770 /* del_timer(&bp->tx_timeout); */
771 /* bp->timeout_active = 0; */
774 cp
= &bp
->tx_cmds
[bp
->tx_empty
];
775 stat
= ld_le16(&cp
->xfer_status
);
776 if (txintcount
< 10) {
777 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat
));
779 if (!(stat
& ACTIVE
)) {
781 * status field might not have been filled by DBDMA
783 if (cp
== bus_to_virt(in_le32(&bp
->tx_dma
->cmdptr
)))
787 if (bp
->tx_bufs
[bp
->tx_empty
]) {
788 ++bp
->stats
.tx_packets
;
789 dev_kfree_skb_irq(bp
->tx_bufs
[bp
->tx_empty
]);
791 bp
->tx_bufs
[bp
->tx_empty
] = NULL
;
793 netif_wake_queue(dev
);
794 if (++bp
->tx_empty
>= N_TX_RING
)
796 if (bp
->tx_empty
== bp
->tx_fill
)
800 spin_unlock_irqrestore(&bp
->lock
, flags
);
802 if (txintcount
< 10) {
803 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
810 static struct net_device_stats
*bmac_stats(struct net_device
*dev
)
812 struct bmac_data
*p
= netdev_priv(dev
);
817 #ifndef SUNHME_MULTICAST
818 /* Real fast bit-reversal algorithm, 6-bit values */
819 static int reverse6
[64] = {
820 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
821 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
822 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
823 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
824 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
825 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
826 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
827 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
831 crc416(unsigned int curval
, unsigned short nxtval
)
833 register unsigned int counter
, cur
= curval
, next
= nxtval
;
834 register int high_crc_set
, low_data_set
;
837 next
= ((next
& 0x00FF) << 8) | (next
>> 8);
839 /* Compute bit-by-bit */
840 for (counter
= 0; counter
< 16; ++counter
) {
841 /* is high CRC bit set? */
842 if ((cur
& 0x80000000) == 0) high_crc_set
= 0;
843 else high_crc_set
= 1;
847 if ((next
& 0x0001) == 0) low_data_set
= 0;
848 else low_data_set
= 1;
853 if (high_crc_set
^ low_data_set
) cur
= cur
^ ENET_CRCPOLY
;
859 bmac_crc(unsigned short *address
)
863 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address
, address
[1], address
[2]));
864 newcrc
= crc416(0xffffffff, *address
); /* address bits 47 - 32 */
865 newcrc
= crc416(newcrc
, address
[1]); /* address bits 31 - 16 */
866 newcrc
= crc416(newcrc
, address
[2]); /* address bits 15 - 0 */
872 * Add requested mcast addr to BMac's hash table filter.
877 bmac_addhash(struct bmac_data
*bp
, unsigned char *addr
)
882 if (!(*addr
)) return;
883 crc
= bmac_crc((unsigned short *)addr
) & 0x3f; /* Big-endian alert! */
884 crc
= reverse6
[crc
]; /* Hyperfast bit-reversing algorithm */
885 if (bp
->hash_use_count
[crc
]++) return; /* This bit is already set */
887 mask
= (unsigned char)1 << mask
;
888 bp
->hash_use_count
[crc
/16] |= mask
;
892 bmac_removehash(struct bmac_data
*bp
, unsigned char *addr
)
897 /* Now, delete the address from the filter copy, as indicated */
898 crc
= bmac_crc((unsigned short *)addr
) & 0x3f; /* Big-endian alert! */
899 crc
= reverse6
[crc
]; /* Hyperfast bit-reversing algorithm */
900 if (bp
->hash_use_count
[crc
] == 0) return; /* That bit wasn't in use! */
901 if (--bp
->hash_use_count
[crc
]) return; /* That bit is still in use */
903 mask
= ((unsigned char)1 << mask
) ^ 0xffff; /* To turn off bit */
904 bp
->hash_table_mask
[crc
/16] &= mask
;
908 * Sync the adapter with the software copy of the multicast mask
909 * (logical address filter).
913 bmac_rx_off(struct net_device
*dev
)
915 unsigned short rx_cfg
;
917 rx_cfg
= bmread(dev
, RXCFG
);
918 rx_cfg
&= ~RxMACEnable
;
919 bmwrite(dev
, RXCFG
, rx_cfg
);
921 rx_cfg
= bmread(dev
, RXCFG
);
922 } while (rx_cfg
& RxMACEnable
);
926 bmac_rx_on(struct net_device
*dev
, int hash_enable
, int promisc_enable
)
928 unsigned short rx_cfg
;
930 rx_cfg
= bmread(dev
, RXCFG
);
931 rx_cfg
|= RxMACEnable
;
932 if (hash_enable
) rx_cfg
|= RxHashFilterEnable
;
933 else rx_cfg
&= ~RxHashFilterEnable
;
934 if (promisc_enable
) rx_cfg
|= RxPromiscEnable
;
935 else rx_cfg
&= ~RxPromiscEnable
;
936 bmwrite(dev
, RXRST
, RxResetValue
);
937 bmwrite(dev
, RXFIFOCSR
, 0); /* first disable rxFIFO */
938 bmwrite(dev
, RXFIFOCSR
, RxFIFOEnable
);
939 bmwrite(dev
, RXCFG
, rx_cfg
);
944 bmac_update_hash_table_mask(struct net_device
*dev
, struct bmac_data
*bp
)
946 bmwrite(dev
, BHASH3
, bp
->hash_table_mask
[0]); /* bits 15 - 0 */
947 bmwrite(dev
, BHASH2
, bp
->hash_table_mask
[1]); /* bits 31 - 16 */
948 bmwrite(dev
, BHASH1
, bp
->hash_table_mask
[2]); /* bits 47 - 32 */
949 bmwrite(dev
, BHASH0
, bp
->hash_table_mask
[3]); /* bits 63 - 48 */
954 bmac_add_multi(struct net_device
*dev
,
955 struct bmac_data
*bp
, unsigned char *addr
)
957 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
958 bmac_addhash(bp
, addr
);
960 bmac_update_hash_table_mask(dev
, bp
);
961 bmac_rx_on(dev
, 1, (dev
->flags
& IFF_PROMISC
)? 1 : 0);
962 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
966 bmac_remove_multi(struct net_device
*dev
,
967 struct bmac_data
*bp
, unsigned char *addr
)
969 bmac_removehash(bp
, addr
);
971 bmac_update_hash_table_mask(dev
, bp
);
972 bmac_rx_on(dev
, 1, (dev
->flags
& IFF_PROMISC
)? 1 : 0);
976 /* Set or clear the multicast filter for this adaptor.
977 num_addrs == -1 Promiscuous mode, receive all packets
978 num_addrs == 0 Normal mode, clear multicast list
979 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
980 best-effort filtering.
982 static void bmac_set_multicast(struct net_device
*dev
)
984 struct dev_mc_list
*dmi
;
985 struct bmac_data
*bp
= netdev_priv(dev
);
986 int num_addrs
= dev
->mc_count
;
987 unsigned short rx_cfg
;
993 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs
));
995 if((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 64)) {
996 for (i
=0; i
<4; i
++) bp
->hash_table_mask
[i
] = 0xffff;
997 bmac_update_hash_table_mask(dev
, bp
);
998 rx_cfg
= bmac_rx_on(dev
, 1, 0);
999 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
1000 } else if ((dev
->flags
& IFF_PROMISC
) || (num_addrs
< 0)) {
1001 rx_cfg
= bmread(dev
, RXCFG
);
1002 rx_cfg
|= RxPromiscEnable
;
1003 bmwrite(dev
, RXCFG
, rx_cfg
);
1004 rx_cfg
= bmac_rx_on(dev
, 0, 1);
1005 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg
));
1007 for (i
=0; i
<4; i
++) bp
->hash_table_mask
[i
] = 0;
1008 for (i
=0; i
<64; i
++) bp
->hash_use_count
[i
] = 0;
1009 if (num_addrs
== 0) {
1010 rx_cfg
= bmac_rx_on(dev
, 0, 0);
1011 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg
));
1013 for (dmi
=dev
->mc_list
; dmi
!=NULL
; dmi
=dmi
->next
)
1014 bmac_addhash(bp
, dmi
->dmi_addr
);
1015 bmac_update_hash_table_mask(dev
, bp
);
1016 rx_cfg
= bmac_rx_on(dev
, 1, 0);
1017 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg
));
1020 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
1022 #else /* ifdef SUNHME_MULTICAST */
1024 /* The version of set_multicast below was lifted from sunhme.c */
1026 static void bmac_set_multicast(struct net_device
*dev
)
1028 struct dev_mc_list
*dmi
= dev
->mc_list
;
1031 unsigned short rx_cfg
;
1034 if((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 64)) {
1035 bmwrite(dev
, BHASH0
, 0xffff);
1036 bmwrite(dev
, BHASH1
, 0xffff);
1037 bmwrite(dev
, BHASH2
, 0xffff);
1038 bmwrite(dev
, BHASH3
, 0xffff);
1039 } else if(dev
->flags
& IFF_PROMISC
) {
1040 rx_cfg
= bmread(dev
, RXCFG
);
1041 rx_cfg
|= RxPromiscEnable
;
1042 bmwrite(dev
, RXCFG
, rx_cfg
);
1046 rx_cfg
= bmread(dev
, RXCFG
);
1047 rx_cfg
&= ~RxPromiscEnable
;
1048 bmwrite(dev
, RXCFG
, rx_cfg
);
1050 for(i
= 0; i
< 4; i
++) hash_table
[i
] = 0;
1052 for(i
= 0; i
< dev
->mc_count
; i
++) {
1053 addrs
= dmi
->dmi_addr
;
1059 crc
= ether_crc_le(6, addrs
);
1061 hash_table
[crc
>> 4] |= 1 << (crc
& 0xf);
1063 bmwrite(dev
, BHASH0
, hash_table
[0]);
1064 bmwrite(dev
, BHASH1
, hash_table
[1]);
1065 bmwrite(dev
, BHASH2
, hash_table
[2]);
1066 bmwrite(dev
, BHASH3
, hash_table
[3]);
1069 #endif /* SUNHME_MULTICAST */
1071 static int miscintcount
;
1073 static irqreturn_t
bmac_misc_intr(int irq
, void *dev_id
)
1075 struct net_device
*dev
= (struct net_device
*) dev_id
;
1076 struct bmac_data
*bp
= netdev_priv(dev
);
1077 unsigned int status
= bmread(dev
, STATUS
);
1078 if (miscintcount
++ < 10) {
1079 XXDEBUG(("bmac_misc_intr\n"));
1081 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
1082 /* bmac_txdma_intr_inner(irq, dev_id); */
1083 /* if (status & FrameReceived) bp->stats.rx_dropped++; */
1084 if (status
& RxErrorMask
) bp
->stats
.rx_errors
++;
1085 if (status
& RxCRCCntExp
) bp
->stats
.rx_crc_errors
++;
1086 if (status
& RxLenCntExp
) bp
->stats
.rx_length_errors
++;
1087 if (status
& RxOverFlow
) bp
->stats
.rx_over_errors
++;
1088 if (status
& RxAlignCntExp
) bp
->stats
.rx_frame_errors
++;
1090 /* if (status & FrameSent) bp->stats.tx_dropped++; */
1091 if (status
& TxErrorMask
) bp
->stats
.tx_errors
++;
1092 if (status
& TxUnderrun
) bp
->stats
.tx_fifo_errors
++;
1093 if (status
& TxNormalCollExp
) bp
->stats
.collisions
++;
1098 * Procedure for reading EEPROM
1100 #define SROMAddressLength 5
1101 #define DataInOn 0x0008
1102 #define DataInOff 0x0000
1104 #define ChipSelect 0x0001
1105 #define SDIShiftCount 3
1106 #define SD0ShiftCount 2
1107 #define DelayValue 1000 /* number of microseconds */
1108 #define SROMStartOffset 10 /* this is in words */
1109 #define SROMReadCount 3 /* number of words to read from SROM */
1110 #define SROMAddressBits 6
1111 #define EnetAddressOffset 20
1113 static unsigned char
1114 bmac_clock_out_bit(struct net_device
*dev
)
1116 unsigned short data
;
1119 bmwrite(dev
, SROMCSR
, ChipSelect
| Clk
);
1122 data
= bmread(dev
, SROMCSR
);
1124 val
= (data
>> SD0ShiftCount
) & 1;
1126 bmwrite(dev
, SROMCSR
, ChipSelect
);
1133 bmac_clock_in_bit(struct net_device
*dev
, unsigned int val
)
1135 unsigned short data
;
1137 if (val
!= 0 && val
!= 1) return;
1139 data
= (val
<< SDIShiftCount
);
1140 bmwrite(dev
, SROMCSR
, data
| ChipSelect
);
1143 bmwrite(dev
, SROMCSR
, data
| ChipSelect
| Clk
);
1146 bmwrite(dev
, SROMCSR
, data
| ChipSelect
);
1151 reset_and_select_srom(struct net_device
*dev
)
1154 bmwrite(dev
, SROMCSR
, 0);
1157 /* send it the read command (110) */
1158 bmac_clock_in_bit(dev
, 1);
1159 bmac_clock_in_bit(dev
, 1);
1160 bmac_clock_in_bit(dev
, 0);
1163 static unsigned short
1164 read_srom(struct net_device
*dev
, unsigned int addr
, unsigned int addr_len
)
1166 unsigned short data
, val
;
1169 /* send out the address we want to read from */
1170 for (i
= 0; i
< addr_len
; i
++) {
1171 val
= addr
>> (addr_len
-i
-1);
1172 bmac_clock_in_bit(dev
, val
& 1);
1175 /* Now read in the 16-bit data */
1177 for (i
= 0; i
< 16; i
++) {
1178 val
= bmac_clock_out_bit(dev
);
1182 bmwrite(dev
, SROMCSR
, 0);
1188 * It looks like Cogent and SMC use different methods for calculating
1189 * checksums. What a pain..
1193 bmac_verify_checksum(struct net_device
*dev
)
1195 unsigned short data
, storedCS
;
1197 reset_and_select_srom(dev
);
1198 data
= read_srom(dev
, 3, SROMAddressBits
);
1199 storedCS
= ((data
>> 8) & 0x0ff) | ((data
<< 8) & 0xff00);
1206 bmac_get_station_address(struct net_device
*dev
, unsigned char *ea
)
1209 unsigned short data
;
1211 for (i
= 0; i
< 6; i
++)
1213 reset_and_select_srom(dev
);
1214 data
= read_srom(dev
, i
+ EnetAddressOffset
/2, SROMAddressBits
);
1215 ea
[2*i
] = bitrev8(data
& 0x0ff);
1216 ea
[2*i
+1] = bitrev8((data
>> 8) & 0x0ff);
1220 static void bmac_reset_and_enable(struct net_device
*dev
)
1222 struct bmac_data
*bp
= netdev_priv(dev
);
1223 unsigned long flags
;
1224 struct sk_buff
*skb
;
1225 unsigned char *data
;
1227 spin_lock_irqsave(&bp
->lock
, flags
);
1228 bmac_enable_and_reset_chip(dev
);
1229 bmac_init_tx_ring(bp
);
1230 bmac_init_rx_ring(bp
);
1231 bmac_init_chip(dev
);
1232 bmac_start_chip(dev
);
1233 bmwrite(dev
, INTDISABLE
, EnableNormal
);
1237 * It seems that the bmac can't receive until it's transmitted
1238 * a packet. So we give it a dummy packet to transmit.
1240 skb
= dev_alloc_skb(ETHERMINPACKET
);
1242 data
= skb_put(skb
, ETHERMINPACKET
);
1243 memset(data
, 0, ETHERMINPACKET
);
1244 memcpy(data
, dev
->dev_addr
, 6);
1245 memcpy(data
+6, dev
->dev_addr
, 6);
1246 bmac_transmit_packet(skb
, dev
);
1248 spin_unlock_irqrestore(&bp
->lock
, flags
);
1250 static void bmac_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1252 struct bmac_data
*bp
= netdev_priv(dev
);
1253 strcpy(info
->driver
, "bmac");
1254 strcpy(info
->bus_info
, bp
->mdev
->ofdev
.dev
.bus_id
);
1257 static const struct ethtool_ops bmac_ethtool_ops
= {
1258 .get_drvinfo
= bmac_get_drvinfo
,
1259 .get_link
= ethtool_op_get_link
,
1262 static int __devinit
bmac_probe(struct macio_dev
*mdev
, const struct of_device_id
*match
)
1265 struct bmac_data
*bp
;
1266 const unsigned char *prop_addr
;
1267 unsigned char addr
[6];
1268 struct net_device
*dev
;
1269 int is_bmac_plus
= ((int)match
->data
) != 0;
1271 if (macio_resource_count(mdev
) != 3 || macio_irq_count(mdev
) != 3) {
1272 printk(KERN_ERR
"BMAC: can't use, need 3 addrs and 3 intrs\n");
1275 prop_addr
= of_get_property(macio_get_of_node(mdev
),
1276 "mac-address", NULL
);
1277 if (prop_addr
== NULL
) {
1278 prop_addr
= of_get_property(macio_get_of_node(mdev
),
1279 "local-mac-address", NULL
);
1280 if (prop_addr
== NULL
) {
1281 printk(KERN_ERR
"BMAC: Can't get mac-address\n");
1285 memcpy(addr
, prop_addr
, sizeof(addr
));
1287 dev
= alloc_etherdev(PRIV_BYTES
);
1289 printk(KERN_ERR
"BMAC: alloc_etherdev failed, out of memory\n");
1293 bp
= netdev_priv(dev
);
1294 SET_MODULE_OWNER(dev
);
1295 SET_NETDEV_DEV(dev
, &mdev
->ofdev
.dev
);
1296 macio_set_drvdata(mdev
, dev
);
1299 spin_lock_init(&bp
->lock
);
1301 if (macio_request_resources(mdev
, "bmac")) {
1302 printk(KERN_ERR
"BMAC: can't request IO resource !\n");
1306 dev
->base_addr
= (unsigned long)
1307 ioremap(macio_resource_start(mdev
, 0), macio_resource_len(mdev
, 0));
1308 if (dev
->base_addr
== 0)
1311 dev
->irq
= macio_irq(mdev
, 0);
1313 bmac_enable_and_reset_chip(dev
);
1314 bmwrite(dev
, INTDISABLE
, DisableAll
);
1316 rev
= addr
[0] == 0 && addr
[1] == 0xA0;
1317 for (j
= 0; j
< 6; ++j
)
1318 dev
->dev_addr
[j
] = rev
? bitrev8(addr
[j
]): addr
[j
];
1320 /* Enable chip without interrupts for now */
1321 bmac_enable_and_reset_chip(dev
);
1322 bmwrite(dev
, INTDISABLE
, DisableAll
);
1324 dev
->open
= bmac_open
;
1325 dev
->stop
= bmac_close
;
1326 dev
->ethtool_ops
= &bmac_ethtool_ops
;
1327 dev
->hard_start_xmit
= bmac_output
;
1328 dev
->get_stats
= bmac_stats
;
1329 dev
->set_multicast_list
= bmac_set_multicast
;
1330 dev
->set_mac_address
= bmac_set_address
;
1332 bmac_get_station_address(dev
, addr
);
1333 if (bmac_verify_checksum(dev
) != 0)
1334 goto err_out_iounmap
;
1336 bp
->is_bmac_plus
= is_bmac_plus
;
1337 bp
->tx_dma
= ioremap(macio_resource_start(mdev
, 1), macio_resource_len(mdev
, 1));
1339 goto err_out_iounmap
;
1340 bp
->tx_dma_intr
= macio_irq(mdev
, 1);
1341 bp
->rx_dma
= ioremap(macio_resource_start(mdev
, 2), macio_resource_len(mdev
, 2));
1343 goto err_out_iounmap_tx
;
1344 bp
->rx_dma_intr
= macio_irq(mdev
, 2);
1346 bp
->tx_cmds
= (volatile struct dbdma_cmd
*) DBDMA_ALIGN(bp
+ 1);
1347 bp
->rx_cmds
= bp
->tx_cmds
+ N_TX_RING
+ 1;
1349 bp
->queue
= (struct sk_buff_head
*)(bp
->rx_cmds
+ N_RX_RING
+ 1);
1350 skb_queue_head_init(bp
->queue
);
1352 init_timer(&bp
->tx_timeout
);
1354 ret
= request_irq(dev
->irq
, bmac_misc_intr
, 0, "BMAC-misc", dev
);
1356 printk(KERN_ERR
"BMAC: can't get irq %d\n", dev
->irq
);
1357 goto err_out_iounmap_rx
;
1359 ret
= request_irq(bp
->tx_dma_intr
, bmac_txdma_intr
, 0, "BMAC-txdma", dev
);
1361 printk(KERN_ERR
"BMAC: can't get irq %d\n", bp
->tx_dma_intr
);
1364 ret
= request_irq(bp
->rx_dma_intr
, bmac_rxdma_intr
, 0, "BMAC-rxdma", dev
);
1366 printk(KERN_ERR
"BMAC: can't get irq %d\n", bp
->rx_dma_intr
);
1370 /* Mask chip interrupts and disable chip, will be
1371 * re-enabled on open()
1373 disable_irq(dev
->irq
);
1374 pmac_call_feature(PMAC_FTR_BMAC_ENABLE
, macio_get_of_node(bp
->mdev
), 0, 0);
1376 if (register_netdev(dev
) != 0) {
1377 printk(KERN_ERR
"BMAC: Ethernet registration failed\n");
1381 printk(KERN_INFO
"%s: BMAC%s at", dev
->name
, (is_bmac_plus
? "+": ""));
1382 for (j
= 0; j
< 6; ++j
)
1383 printk("%c%.2x", (j
? ':': ' '), dev
->dev_addr
[j
]);
1384 XXDEBUG((", base_addr=%#0lx", dev
->base_addr
));
1390 free_irq(bp
->rx_dma_intr
, dev
);
1392 free_irq(bp
->tx_dma_intr
, dev
);
1394 free_irq(dev
->irq
, dev
);
1396 iounmap(bp
->rx_dma
);
1398 iounmap(bp
->tx_dma
);
1400 iounmap((void __iomem
*)dev
->base_addr
);
1402 macio_release_resources(mdev
);
1404 pmac_call_feature(PMAC_FTR_BMAC_ENABLE
, macio_get_of_node(bp
->mdev
), 0, 0);
1410 static int bmac_open(struct net_device
*dev
)
1412 struct bmac_data
*bp
= netdev_priv(dev
);
1413 /* XXDEBUG(("bmac: enter open\n")); */
1414 /* reset the chip */
1416 bmac_reset_and_enable(dev
);
1417 enable_irq(dev
->irq
);
1421 static int bmac_close(struct net_device
*dev
)
1423 struct bmac_data
*bp
= netdev_priv(dev
);
1424 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
1425 volatile struct dbdma_regs __iomem
*td
= bp
->tx_dma
;
1426 unsigned short config
;
1431 /* disable rx and tx */
1432 config
= bmread(dev
, RXCFG
);
1433 bmwrite(dev
, RXCFG
, (config
& ~RxMACEnable
));
1435 config
= bmread(dev
, TXCFG
);
1436 bmwrite(dev
, TXCFG
, (config
& ~TxMACEnable
));
1438 bmwrite(dev
, INTDISABLE
, DisableAll
); /* disable all intrs */
1440 /* disable rx and tx dma */
1441 st_le32(&rd
->control
, DBDMA_CLEAR(RUN
|PAUSE
|FLUSH
|WAKE
)); /* clear run bit */
1442 st_le32(&td
->control
, DBDMA_CLEAR(RUN
|PAUSE
|FLUSH
|WAKE
)); /* clear run bit */
1444 /* free some skb's */
1445 XXDEBUG(("bmac: free rx bufs\n"));
1446 for (i
=0; i
<N_RX_RING
; i
++) {
1447 if (bp
->rx_bufs
[i
] != NULL
) {
1448 dev_kfree_skb(bp
->rx_bufs
[i
]);
1449 bp
->rx_bufs
[i
] = NULL
;
1452 XXDEBUG(("bmac: free tx bufs\n"));
1453 for (i
= 0; i
<N_TX_RING
; i
++) {
1454 if (bp
->tx_bufs
[i
] != NULL
) {
1455 dev_kfree_skb(bp
->tx_bufs
[i
]);
1456 bp
->tx_bufs
[i
] = NULL
;
1459 XXDEBUG(("bmac: all bufs freed\n"));
1462 disable_irq(dev
->irq
);
1463 pmac_call_feature(PMAC_FTR_BMAC_ENABLE
, macio_get_of_node(bp
->mdev
), 0, 0);
1469 bmac_start(struct net_device
*dev
)
1471 struct bmac_data
*bp
= netdev_priv(dev
);
1473 struct sk_buff
*skb
;
1474 unsigned long flags
;
1479 spin_lock_irqsave(&bp
->lock
, flags
);
1481 i
= bp
->tx_fill
+ 1;
1484 if (i
== bp
->tx_empty
)
1486 skb
= skb_dequeue(bp
->queue
);
1489 bmac_transmit_packet(skb
, dev
);
1491 spin_unlock_irqrestore(&bp
->lock
, flags
);
1495 bmac_output(struct sk_buff
*skb
, struct net_device
*dev
)
1497 struct bmac_data
*bp
= netdev_priv(dev
);
1498 skb_queue_tail(bp
->queue
, skb
);
1503 static void bmac_tx_timeout(unsigned long data
)
1505 struct net_device
*dev
= (struct net_device
*) data
;
1506 struct bmac_data
*bp
= netdev_priv(dev
);
1507 volatile struct dbdma_regs __iomem
*td
= bp
->tx_dma
;
1508 volatile struct dbdma_regs __iomem
*rd
= bp
->rx_dma
;
1509 volatile struct dbdma_cmd
*cp
;
1510 unsigned long flags
;
1511 unsigned short config
, oldConfig
;
1514 XXDEBUG(("bmac: tx_timeout called\n"));
1515 spin_lock_irqsave(&bp
->lock
, flags
);
1516 bp
->timeout_active
= 0;
1518 /* update various counters */
1519 /* bmac_handle_misc_intrs(bp, 0); */
1521 cp
= &bp
->tx_cmds
[bp
->tx_empty
];
1522 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1523 /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1524 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1526 /* turn off both tx and rx and reset the chip */
1527 config
= bmread(dev
, RXCFG
);
1528 bmwrite(dev
, RXCFG
, (config
& ~RxMACEnable
));
1529 config
= bmread(dev
, TXCFG
);
1530 bmwrite(dev
, TXCFG
, (config
& ~TxMACEnable
));
1531 out_le32(&td
->control
, DBDMA_CLEAR(RUN
|PAUSE
|FLUSH
|WAKE
|ACTIVE
|DEAD
));
1532 printk(KERN_ERR
"bmac: transmit timeout - resetting\n");
1533 bmac_enable_and_reset_chip(dev
);
1535 /* restart rx dma */
1536 cp
= bus_to_virt(ld_le32(&rd
->cmdptr
));
1537 out_le32(&rd
->control
, DBDMA_CLEAR(RUN
|PAUSE
|FLUSH
|WAKE
|ACTIVE
|DEAD
));
1538 out_le16(&cp
->xfer_status
, 0);
1539 out_le32(&rd
->cmdptr
, virt_to_bus(cp
));
1540 out_le32(&rd
->control
, DBDMA_SET(RUN
|WAKE
));
1542 /* fix up the transmit side */
1543 XXDEBUG((KERN_DEBUG
"bmac: tx empty=%d fill=%d fullup=%d\n",
1544 bp
->tx_empty
, bp
->tx_fill
, bp
->tx_fullup
));
1546 ++bp
->stats
.tx_errors
;
1547 if (i
!= bp
->tx_fill
) {
1548 dev_kfree_skb(bp
->tx_bufs
[i
]);
1549 bp
->tx_bufs
[i
] = NULL
;
1550 if (++i
>= N_TX_RING
) i
= 0;
1554 netif_wake_queue(dev
);
1555 if (i
!= bp
->tx_fill
) {
1556 cp
= &bp
->tx_cmds
[i
];
1557 out_le16(&cp
->xfer_status
, 0);
1558 out_le16(&cp
->command
, OUTPUT_LAST
);
1559 out_le32(&td
->cmdptr
, virt_to_bus(cp
));
1560 out_le32(&td
->control
, DBDMA_SET(RUN
));
1561 /* bmac_set_timeout(dev); */
1562 XXDEBUG((KERN_DEBUG
"bmac: starting %d\n", i
));
1565 /* turn it back on */
1566 oldConfig
= bmread(dev
, RXCFG
);
1567 bmwrite(dev
, RXCFG
, oldConfig
| RxMACEnable
);
1568 oldConfig
= bmread(dev
, TXCFG
);
1569 bmwrite(dev
, TXCFG
, oldConfig
| TxMACEnable
);
1571 spin_unlock_irqrestore(&bp
->lock
, flags
);
1575 static void dump_dbdma(volatile struct dbdma_cmd
*cp
,int count
)
1579 for (i
=0;i
< count
;i
++) {
1582 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1594 bmac_proc_info(char *buffer
, char **start
, off_t offset
, int length
)
1601 if (bmac_devs
== NULL
)
1604 len
+= sprintf(buffer
, "BMAC counters & registers\n");
1606 for (i
= 0; i
<N_REG_ENTRIES
; i
++) {
1607 len
+= sprintf(buffer
+ len
, "%s: %#08x\n",
1608 reg_entries
[i
].name
,
1609 bmread(bmac_devs
, reg_entries
[i
].reg_offset
));
1617 if (pos
> offset
+length
) break;
1620 *start
= buffer
+ (offset
- begin
);
1621 len
-= (offset
- begin
);
1623 if (len
> length
) len
= length
;
1629 static int __devexit
bmac_remove(struct macio_dev
*mdev
)
1631 struct net_device
*dev
= macio_get_drvdata(mdev
);
1632 struct bmac_data
*bp
= netdev_priv(dev
);
1634 unregister_netdev(dev
);
1636 free_irq(dev
->irq
, dev
);
1637 free_irq(bp
->tx_dma_intr
, dev
);
1638 free_irq(bp
->rx_dma_intr
, dev
);
1640 iounmap((void __iomem
*)dev
->base_addr
);
1641 iounmap(bp
->tx_dma
);
1642 iounmap(bp
->rx_dma
);
1644 macio_release_resources(mdev
);
1651 static struct of_device_id bmac_match
[] =
1659 .compatible
= "bmac+",
1664 MODULE_DEVICE_TABLE (of
, bmac_match
);
1666 static struct macio_driver bmac_driver
=
1669 .match_table
= bmac_match
,
1670 .probe
= bmac_probe
,
1671 .remove
= bmac_remove
,
1673 .suspend
= bmac_suspend
,
1674 .resume
= bmac_resume
,
1679 static int __init
bmac_init(void)
1681 if (bmac_emergency_rxbuf
== NULL
) {
1682 bmac_emergency_rxbuf
= kmalloc(RX_BUFLEN
, GFP_KERNEL
);
1683 if (bmac_emergency_rxbuf
== NULL
) {
1684 printk(KERN_ERR
"BMAC: can't allocate emergency RX buffer\n");
1689 return macio_register_driver(&bmac_driver
);
1692 static void __exit
bmac_exit(void)
1694 macio_unregister_driver(&bmac_driver
);
1696 kfree(bmac_emergency_rxbuf
);
1697 bmac_emergency_rxbuf
= NULL
;
1700 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1701 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1702 MODULE_LICENSE("GPL");
1704 module_init(bmac_init
);
1705 module_exit(bmac_exit
);