1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004, 2005 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
15 #define DRV_MODULE_NAME "bnx2"
16 #define PFX DRV_MODULE_NAME ": "
17 #define DRV_MODULE_VERSION "1.2.19"
18 #define DRV_MODULE_RELDATE "May 23, 2005"
20 #define RUN_AT(x) (jiffies + (x))
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT (5*HZ)
25 static char version
[] __devinitdata
=
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION
);
33 static int disable_msi
= 0;
35 module_param(disable_msi
, int, 0);
36 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
46 /* indexed by board_t, above */
49 } board_info
[] __devinitdata
= {
50 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51 { "HP NC370T Multifunction Gigabit Server Adapter" },
52 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" },
57 static struct pci_device_id bnx2_pci_tbl
[] = {
58 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706
,
59 PCI_VENDOR_ID_HP
, 0x3101, 0, 0, NC370T
},
60 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706
,
61 PCI_VENDOR_ID_HP
, 0x3106, 0, 0, NC370I
},
62 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706
,
63 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5706
},
64 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706S
,
65 PCI_VENDOR_ID_HP
, 0x3102, 0, 0, NC370F
},
66 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706S
,
67 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5706S
},
71 static struct flash_spec flash_table
[] =
74 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
75 1, SEEPROM_PAGE_BITS
, SEEPROM_PAGE_SIZE
,
76 SEEPROM_BYTE_ADDR_MASK
, SEEPROM_TOTAL_SIZE
,
79 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
80 1, SEEPROM_PAGE_BITS
, SEEPROM_PAGE_SIZE
,
81 SEEPROM_BYTE_ADDR_MASK
, SEEPROM_TOTAL_SIZE
,
83 /* ATMEL AT45DB011B (buffered flash) */
84 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
85 1, BUFFERED_FLASH_PAGE_BITS
, BUFFERED_FLASH_PAGE_SIZE
,
86 BUFFERED_FLASH_BYTE_ADDR_MASK
, BUFFERED_FLASH_TOTAL_SIZE
,
88 /* Saifun SA25F005 (non-buffered flash) */
89 /* strap, cfg1, & write1 need updates */
90 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
91 0, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
92 SAIFUN_FLASH_BYTE_ADDR_MASK
, SAIFUN_FLASH_BASE_TOTAL_SIZE
,
93 "Non-buffered flash (64kB)"},
94 /* Saifun SA25F010 (non-buffered flash) */
95 /* strap, cfg1, & write1 need updates */
96 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
97 0, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
98 SAIFUN_FLASH_BYTE_ADDR_MASK
, SAIFUN_FLASH_BASE_TOTAL_SIZE
*2,
99 "Non-buffered flash (128kB)"},
100 /* Saifun SA25F020 (non-buffered flash) */
101 /* strap, cfg1, & write1 need updates */
102 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
103 0, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
104 SAIFUN_FLASH_BYTE_ADDR_MASK
, SAIFUN_FLASH_BASE_TOTAL_SIZE
*4,
105 "Non-buffered flash (256kB)"},
108 MODULE_DEVICE_TABLE(pci
, bnx2_pci_tbl
);
111 bnx2_reg_rd_ind(struct bnx2
*bp
, u32 offset
)
113 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW_ADDRESS
, offset
);
114 return (REG_RD(bp
, BNX2_PCICFG_REG_WINDOW
));
118 bnx2_reg_wr_ind(struct bnx2
*bp
, u32 offset
, u32 val
)
120 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW_ADDRESS
, offset
);
121 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW
, val
);
125 bnx2_ctx_wr(struct bnx2
*bp
, u32 cid_addr
, u32 offset
, u32 val
)
128 REG_WR(bp
, BNX2_CTX_DATA_ADR
, offset
);
129 REG_WR(bp
, BNX2_CTX_DATA
, val
);
133 bnx2_read_phy(struct bnx2
*bp
, u32 reg
, u32
*val
)
138 if (bp
->phy_flags
& PHY_INT_MODE_AUTO_POLLING_FLAG
) {
139 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
140 val1
&= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
142 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
143 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
148 val1
= (bp
->phy_addr
<< 21) | (reg
<< 16) |
149 BNX2_EMAC_MDIO_COMM_COMMAND_READ
| BNX2_EMAC_MDIO_COMM_DISEXT
|
150 BNX2_EMAC_MDIO_COMM_START_BUSY
;
151 REG_WR(bp
, BNX2_EMAC_MDIO_COMM
, val1
);
153 for (i
= 0; i
< 50; i
++) {
156 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_COMM
);
157 if (!(val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
)) {
160 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_COMM
);
161 val1
&= BNX2_EMAC_MDIO_COMM_DATA
;
167 if (val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
) {
176 if (bp
->phy_flags
& PHY_INT_MODE_AUTO_POLLING_FLAG
) {
177 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
178 val1
|= BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
180 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
181 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
190 bnx2_write_phy(struct bnx2
*bp
, u32 reg
, u32 val
)
195 if (bp
->phy_flags
& PHY_INT_MODE_AUTO_POLLING_FLAG
) {
196 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
197 val1
&= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
199 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
200 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
205 val1
= (bp
->phy_addr
<< 21) | (reg
<< 16) | val
|
206 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE
|
207 BNX2_EMAC_MDIO_COMM_START_BUSY
| BNX2_EMAC_MDIO_COMM_DISEXT
;
208 REG_WR(bp
, BNX2_EMAC_MDIO_COMM
, val1
);
210 for (i
= 0; i
< 50; i
++) {
213 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_COMM
);
214 if (!(val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
)) {
220 if (val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
)
225 if (bp
->phy_flags
& PHY_INT_MODE_AUTO_POLLING_FLAG
) {
226 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
227 val1
|= BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
229 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
230 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
239 bnx2_disable_int(struct bnx2
*bp
)
241 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
242 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
243 REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
);
247 bnx2_enable_int(struct bnx2
*bp
)
251 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
252 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
| bp
->last_status_idx
);
254 val
= REG_RD(bp
, BNX2_HC_COMMAND
);
255 REG_WR(bp
, BNX2_HC_COMMAND
, val
| BNX2_HC_COMMAND_COAL_NOW
);
259 bnx2_disable_int_sync(struct bnx2
*bp
)
261 atomic_inc(&bp
->intr_sem
);
262 bnx2_disable_int(bp
);
263 synchronize_irq(bp
->pdev
->irq
);
267 bnx2_netif_stop(struct bnx2
*bp
)
269 bnx2_disable_int_sync(bp
);
270 if (netif_running(bp
->dev
)) {
271 netif_poll_disable(bp
->dev
);
272 netif_tx_disable(bp
->dev
);
273 bp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
278 bnx2_netif_start(struct bnx2
*bp
)
280 if (atomic_dec_and_test(&bp
->intr_sem
)) {
281 if (netif_running(bp
->dev
)) {
282 netif_wake_queue(bp
->dev
);
283 netif_poll_enable(bp
->dev
);
290 bnx2_free_mem(struct bnx2
*bp
)
293 pci_free_consistent(bp
->pdev
, sizeof(struct statistics_block
),
294 bp
->stats_blk
, bp
->stats_blk_mapping
);
295 bp
->stats_blk
= NULL
;
297 if (bp
->status_blk
) {
298 pci_free_consistent(bp
->pdev
, sizeof(struct status_block
),
299 bp
->status_blk
, bp
->status_blk_mapping
);
300 bp
->status_blk
= NULL
;
302 if (bp
->tx_desc_ring
) {
303 pci_free_consistent(bp
->pdev
,
304 sizeof(struct tx_bd
) * TX_DESC_CNT
,
305 bp
->tx_desc_ring
, bp
->tx_desc_mapping
);
306 bp
->tx_desc_ring
= NULL
;
308 if (bp
->tx_buf_ring
) {
309 kfree(bp
->tx_buf_ring
);
310 bp
->tx_buf_ring
= NULL
;
312 if (bp
->rx_desc_ring
) {
313 pci_free_consistent(bp
->pdev
,
314 sizeof(struct rx_bd
) * RX_DESC_CNT
,
315 bp
->rx_desc_ring
, bp
->rx_desc_mapping
);
316 bp
->rx_desc_ring
= NULL
;
318 if (bp
->rx_buf_ring
) {
319 kfree(bp
->rx_buf_ring
);
320 bp
->rx_buf_ring
= NULL
;
325 bnx2_alloc_mem(struct bnx2
*bp
)
327 bp
->tx_buf_ring
= kmalloc(sizeof(struct sw_bd
) * TX_DESC_CNT
,
329 if (bp
->tx_buf_ring
== NULL
)
332 memset(bp
->tx_buf_ring
, 0, sizeof(struct sw_bd
) * TX_DESC_CNT
);
333 bp
->tx_desc_ring
= pci_alloc_consistent(bp
->pdev
,
334 sizeof(struct tx_bd
) *
336 &bp
->tx_desc_mapping
);
337 if (bp
->tx_desc_ring
== NULL
)
340 bp
->rx_buf_ring
= kmalloc(sizeof(struct sw_bd
) * RX_DESC_CNT
,
342 if (bp
->rx_buf_ring
== NULL
)
345 memset(bp
->rx_buf_ring
, 0, sizeof(struct sw_bd
) * RX_DESC_CNT
);
346 bp
->rx_desc_ring
= pci_alloc_consistent(bp
->pdev
,
347 sizeof(struct rx_bd
) *
349 &bp
->rx_desc_mapping
);
350 if (bp
->rx_desc_ring
== NULL
)
353 bp
->status_blk
= pci_alloc_consistent(bp
->pdev
,
354 sizeof(struct status_block
),
355 &bp
->status_blk_mapping
);
356 if (bp
->status_blk
== NULL
)
359 memset(bp
->status_blk
, 0, sizeof(struct status_block
));
361 bp
->stats_blk
= pci_alloc_consistent(bp
->pdev
,
362 sizeof(struct statistics_block
),
363 &bp
->stats_blk_mapping
);
364 if (bp
->stats_blk
== NULL
)
367 memset(bp
->stats_blk
, 0, sizeof(struct statistics_block
));
377 bnx2_report_link(struct bnx2
*bp
)
380 netif_carrier_on(bp
->dev
);
381 printk(KERN_INFO PFX
"%s NIC Link is Up, ", bp
->dev
->name
);
383 printk("%d Mbps ", bp
->line_speed
);
385 if (bp
->duplex
== DUPLEX_FULL
)
386 printk("full duplex");
388 printk("half duplex");
391 if (bp
->flow_ctrl
& FLOW_CTRL_RX
) {
392 printk(", receive ");
393 if (bp
->flow_ctrl
& FLOW_CTRL_TX
)
394 printk("& transmit ");
397 printk(", transmit ");
399 printk("flow control ON");
404 netif_carrier_off(bp
->dev
);
405 printk(KERN_ERR PFX
"%s NIC Link is Down\n", bp
->dev
->name
);
410 bnx2_resolve_flow_ctrl(struct bnx2
*bp
)
412 u32 local_adv
, remote_adv
;
415 if ((bp
->autoneg
& (AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
)) !=
416 (AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
)) {
418 if (bp
->duplex
== DUPLEX_FULL
) {
419 bp
->flow_ctrl
= bp
->req_flow_ctrl
;
424 if (bp
->duplex
!= DUPLEX_FULL
) {
428 bnx2_read_phy(bp
, MII_ADVERTISE
, &local_adv
);
429 bnx2_read_phy(bp
, MII_LPA
, &remote_adv
);
431 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
432 u32 new_local_adv
= 0;
433 u32 new_remote_adv
= 0;
435 if (local_adv
& ADVERTISE_1000XPAUSE
)
436 new_local_adv
|= ADVERTISE_PAUSE_CAP
;
437 if (local_adv
& ADVERTISE_1000XPSE_ASYM
)
438 new_local_adv
|= ADVERTISE_PAUSE_ASYM
;
439 if (remote_adv
& ADVERTISE_1000XPAUSE
)
440 new_remote_adv
|= ADVERTISE_PAUSE_CAP
;
441 if (remote_adv
& ADVERTISE_1000XPSE_ASYM
)
442 new_remote_adv
|= ADVERTISE_PAUSE_ASYM
;
444 local_adv
= new_local_adv
;
445 remote_adv
= new_remote_adv
;
448 /* See Table 28B-3 of 802.3ab-1999 spec. */
449 if (local_adv
& ADVERTISE_PAUSE_CAP
) {
450 if(local_adv
& ADVERTISE_PAUSE_ASYM
) {
451 if (remote_adv
& ADVERTISE_PAUSE_CAP
) {
452 bp
->flow_ctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
454 else if (remote_adv
& ADVERTISE_PAUSE_ASYM
) {
455 bp
->flow_ctrl
= FLOW_CTRL_RX
;
459 if (remote_adv
& ADVERTISE_PAUSE_CAP
) {
460 bp
->flow_ctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
464 else if (local_adv
& ADVERTISE_PAUSE_ASYM
) {
465 if ((remote_adv
& ADVERTISE_PAUSE_CAP
) &&
466 (remote_adv
& ADVERTISE_PAUSE_ASYM
)) {
468 bp
->flow_ctrl
= FLOW_CTRL_TX
;
474 bnx2_serdes_linkup(struct bnx2
*bp
)
476 u32 bmcr
, local_adv
, remote_adv
, common
;
479 bp
->line_speed
= SPEED_1000
;
481 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
482 if (bmcr
& BMCR_FULLDPLX
) {
483 bp
->duplex
= DUPLEX_FULL
;
486 bp
->duplex
= DUPLEX_HALF
;
489 if (!(bmcr
& BMCR_ANENABLE
)) {
493 bnx2_read_phy(bp
, MII_ADVERTISE
, &local_adv
);
494 bnx2_read_phy(bp
, MII_LPA
, &remote_adv
);
496 common
= local_adv
& remote_adv
;
497 if (common
& (ADVERTISE_1000XHALF
| ADVERTISE_1000XFULL
)) {
499 if (common
& ADVERTISE_1000XFULL
) {
500 bp
->duplex
= DUPLEX_FULL
;
503 bp
->duplex
= DUPLEX_HALF
;
511 bnx2_copper_linkup(struct bnx2
*bp
)
515 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
516 if (bmcr
& BMCR_ANENABLE
) {
517 u32 local_adv
, remote_adv
, common
;
519 bnx2_read_phy(bp
, MII_CTRL1000
, &local_adv
);
520 bnx2_read_phy(bp
, MII_STAT1000
, &remote_adv
);
522 common
= local_adv
& (remote_adv
>> 2);
523 if (common
& ADVERTISE_1000FULL
) {
524 bp
->line_speed
= SPEED_1000
;
525 bp
->duplex
= DUPLEX_FULL
;
527 else if (common
& ADVERTISE_1000HALF
) {
528 bp
->line_speed
= SPEED_1000
;
529 bp
->duplex
= DUPLEX_HALF
;
532 bnx2_read_phy(bp
, MII_ADVERTISE
, &local_adv
);
533 bnx2_read_phy(bp
, MII_LPA
, &remote_adv
);
535 common
= local_adv
& remote_adv
;
536 if (common
& ADVERTISE_100FULL
) {
537 bp
->line_speed
= SPEED_100
;
538 bp
->duplex
= DUPLEX_FULL
;
540 else if (common
& ADVERTISE_100HALF
) {
541 bp
->line_speed
= SPEED_100
;
542 bp
->duplex
= DUPLEX_HALF
;
544 else if (common
& ADVERTISE_10FULL
) {
545 bp
->line_speed
= SPEED_10
;
546 bp
->duplex
= DUPLEX_FULL
;
548 else if (common
& ADVERTISE_10HALF
) {
549 bp
->line_speed
= SPEED_10
;
550 bp
->duplex
= DUPLEX_HALF
;
559 if (bmcr
& BMCR_SPEED100
) {
560 bp
->line_speed
= SPEED_100
;
563 bp
->line_speed
= SPEED_10
;
565 if (bmcr
& BMCR_FULLDPLX
) {
566 bp
->duplex
= DUPLEX_FULL
;
569 bp
->duplex
= DUPLEX_HALF
;
577 bnx2_set_mac_link(struct bnx2
*bp
)
581 REG_WR(bp
, BNX2_EMAC_TX_LENGTHS
, 0x2620);
582 if (bp
->link_up
&& (bp
->line_speed
== SPEED_1000
) &&
583 (bp
->duplex
== DUPLEX_HALF
)) {
584 REG_WR(bp
, BNX2_EMAC_TX_LENGTHS
, 0x26ff);
587 /* Configure the EMAC mode register. */
588 val
= REG_RD(bp
, BNX2_EMAC_MODE
);
590 val
&= ~(BNX2_EMAC_MODE_PORT
| BNX2_EMAC_MODE_HALF_DUPLEX
|
591 BNX2_EMAC_MODE_MAC_LOOP
| BNX2_EMAC_MODE_FORCE_LINK
);
594 if (bp
->line_speed
!= SPEED_1000
)
595 val
|= BNX2_EMAC_MODE_PORT_MII
;
597 val
|= BNX2_EMAC_MODE_PORT_GMII
;
600 val
|= BNX2_EMAC_MODE_PORT_GMII
;
603 /* Set the MAC to operate in the appropriate duplex mode. */
604 if (bp
->duplex
== DUPLEX_HALF
)
605 val
|= BNX2_EMAC_MODE_HALF_DUPLEX
;
606 REG_WR(bp
, BNX2_EMAC_MODE
, val
);
608 /* Enable/disable rx PAUSE. */
609 bp
->rx_mode
&= ~BNX2_EMAC_RX_MODE_FLOW_EN
;
611 if (bp
->flow_ctrl
& FLOW_CTRL_RX
)
612 bp
->rx_mode
|= BNX2_EMAC_RX_MODE_FLOW_EN
;
613 REG_WR(bp
, BNX2_EMAC_RX_MODE
, bp
->rx_mode
);
615 /* Enable/disable tx PAUSE. */
616 val
= REG_RD(bp
, BNX2_EMAC_TX_MODE
);
617 val
&= ~BNX2_EMAC_TX_MODE_FLOW_EN
;
619 if (bp
->flow_ctrl
& FLOW_CTRL_TX
)
620 val
|= BNX2_EMAC_TX_MODE_FLOW_EN
;
621 REG_WR(bp
, BNX2_EMAC_TX_MODE
, val
);
623 /* Acknowledge the interrupt. */
624 REG_WR(bp
, BNX2_EMAC_STATUS
, BNX2_EMAC_STATUS_LINK_CHANGE
);
630 bnx2_set_link(struct bnx2
*bp
)
635 if (bp
->loopback
== MAC_LOOPBACK
) {
640 link_up
= bp
->link_up
;
642 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
643 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
645 if ((bp
->phy_flags
& PHY_SERDES_FLAG
) &&
646 (CHIP_NUM(bp
) == CHIP_NUM_5706
)) {
649 val
= REG_RD(bp
, BNX2_EMAC_STATUS
);
650 if (val
& BNX2_EMAC_STATUS_LINK
)
651 bmsr
|= BMSR_LSTATUS
;
653 bmsr
&= ~BMSR_LSTATUS
;
656 if (bmsr
& BMSR_LSTATUS
) {
659 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
660 bnx2_serdes_linkup(bp
);
663 bnx2_copper_linkup(bp
);
665 bnx2_resolve_flow_ctrl(bp
);
668 if ((bp
->phy_flags
& PHY_SERDES_FLAG
) &&
669 (bp
->autoneg
& AUTONEG_SPEED
)) {
673 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
674 if (!(bmcr
& BMCR_ANENABLE
)) {
675 bnx2_write_phy(bp
, MII_BMCR
, bmcr
|
679 bp
->phy_flags
&= ~PHY_PARALLEL_DETECT_FLAG
;
683 if (bp
->link_up
!= link_up
) {
684 bnx2_report_link(bp
);
687 bnx2_set_mac_link(bp
);
693 bnx2_reset_phy(struct bnx2
*bp
)
698 bnx2_write_phy(bp
, MII_BMCR
, BMCR_RESET
);
700 #define PHY_RESET_MAX_WAIT 100
701 for (i
= 0; i
< PHY_RESET_MAX_WAIT
; i
++) {
704 bnx2_read_phy(bp
, MII_BMCR
, ®
);
705 if (!(reg
& BMCR_RESET
)) {
710 if (i
== PHY_RESET_MAX_WAIT
) {
717 bnx2_phy_get_pause_adv(struct bnx2
*bp
)
721 if ((bp
->req_flow_ctrl
& (FLOW_CTRL_RX
| FLOW_CTRL_TX
)) ==
722 (FLOW_CTRL_RX
| FLOW_CTRL_TX
)) {
724 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
725 adv
= ADVERTISE_1000XPAUSE
;
728 adv
= ADVERTISE_PAUSE_CAP
;
731 else if (bp
->req_flow_ctrl
& FLOW_CTRL_TX
) {
732 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
733 adv
= ADVERTISE_1000XPSE_ASYM
;
736 adv
= ADVERTISE_PAUSE_ASYM
;
739 else if (bp
->req_flow_ctrl
& FLOW_CTRL_RX
) {
740 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
741 adv
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
744 adv
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
751 bnx2_setup_serdes_phy(struct bnx2
*bp
)
756 if (!(bp
->autoneg
& AUTONEG_SPEED
)) {
759 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
760 new_bmcr
= bmcr
& ~BMCR_ANENABLE
;
761 new_bmcr
|= BMCR_SPEED1000
;
762 if (bp
->req_duplex
== DUPLEX_FULL
) {
763 new_bmcr
|= BMCR_FULLDPLX
;
766 new_bmcr
&= ~BMCR_FULLDPLX
;
768 if (new_bmcr
!= bmcr
) {
769 /* Force a link down visible on the other side */
771 bnx2_read_phy(bp
, MII_ADVERTISE
, &adv
);
772 adv
&= ~(ADVERTISE_1000XFULL
|
773 ADVERTISE_1000XHALF
);
774 bnx2_write_phy(bp
, MII_ADVERTISE
, adv
);
775 bnx2_write_phy(bp
, MII_BMCR
, bmcr
|
776 BMCR_ANRESTART
| BMCR_ANENABLE
);
779 netif_carrier_off(bp
->dev
);
781 bnx2_write_phy(bp
, MII_BMCR
, new_bmcr
);
786 if (bp
->advertising
& ADVERTISED_1000baseT_Full
)
787 new_adv
|= ADVERTISE_1000XFULL
;
789 new_adv
|= bnx2_phy_get_pause_adv(bp
);
791 bnx2_read_phy(bp
, MII_ADVERTISE
, &adv
);
792 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
794 bp
->serdes_an_pending
= 0;
795 if ((adv
!= new_adv
) || ((bmcr
& BMCR_ANENABLE
) == 0)) {
796 /* Force a link down visible on the other side */
800 bnx2_write_phy(bp
, MII_BMCR
, BMCR_LOOPBACK
);
801 for (i
= 0; i
< 110; i
++) {
806 bnx2_write_phy(bp
, MII_ADVERTISE
, new_adv
);
807 bnx2_write_phy(bp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
809 bp
->serdes_an_pending
= SERDES_AN_TIMEOUT
/ bp
->timer_interval
;
815 #define ETHTOOL_ALL_FIBRE_SPEED \
816 (ADVERTISED_1000baseT_Full)
818 #define ETHTOOL_ALL_COPPER_SPEED \
819 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
820 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
821 ADVERTISED_1000baseT_Full)
823 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
824 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
826 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
829 bnx2_setup_copper_phy(struct bnx2
*bp
)
834 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
836 if (bp
->autoneg
& AUTONEG_SPEED
) {
837 u32 adv_reg
, adv1000_reg
;
839 u32 new_adv1000_reg
= 0;
841 bnx2_read_phy(bp
, MII_ADVERTISE
, &adv_reg
);
842 adv_reg
&= (PHY_ALL_10_100_SPEED
| ADVERTISE_PAUSE_CAP
|
843 ADVERTISE_PAUSE_ASYM
);
845 bnx2_read_phy(bp
, MII_CTRL1000
, &adv1000_reg
);
846 adv1000_reg
&= PHY_ALL_1000_SPEED
;
848 if (bp
->advertising
& ADVERTISED_10baseT_Half
)
849 new_adv_reg
|= ADVERTISE_10HALF
;
850 if (bp
->advertising
& ADVERTISED_10baseT_Full
)
851 new_adv_reg
|= ADVERTISE_10FULL
;
852 if (bp
->advertising
& ADVERTISED_100baseT_Half
)
853 new_adv_reg
|= ADVERTISE_100HALF
;
854 if (bp
->advertising
& ADVERTISED_100baseT_Full
)
855 new_adv_reg
|= ADVERTISE_100FULL
;
856 if (bp
->advertising
& ADVERTISED_1000baseT_Full
)
857 new_adv1000_reg
|= ADVERTISE_1000FULL
;
859 new_adv_reg
|= ADVERTISE_CSMA
;
861 new_adv_reg
|= bnx2_phy_get_pause_adv(bp
);
863 if ((adv1000_reg
!= new_adv1000_reg
) ||
864 (adv_reg
!= new_adv_reg
) ||
865 ((bmcr
& BMCR_ANENABLE
) == 0)) {
867 bnx2_write_phy(bp
, MII_ADVERTISE
, new_adv_reg
);
868 bnx2_write_phy(bp
, MII_CTRL1000
, new_adv1000_reg
);
869 bnx2_write_phy(bp
, MII_BMCR
, BMCR_ANRESTART
|
872 else if (bp
->link_up
) {
873 /* Flow ctrl may have changed from auto to forced */
876 bnx2_resolve_flow_ctrl(bp
);
877 bnx2_set_mac_link(bp
);
883 if (bp
->req_line_speed
== SPEED_100
) {
884 new_bmcr
|= BMCR_SPEED100
;
886 if (bp
->req_duplex
== DUPLEX_FULL
) {
887 new_bmcr
|= BMCR_FULLDPLX
;
889 if (new_bmcr
!= bmcr
) {
893 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
894 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
896 if (bmsr
& BMSR_LSTATUS
) {
897 /* Force link down */
898 bnx2_write_phy(bp
, MII_BMCR
, BMCR_LOOPBACK
);
901 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
902 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
904 } while ((bmsr
& BMSR_LSTATUS
) && (i
< 620));
907 bnx2_write_phy(bp
, MII_BMCR
, new_bmcr
);
909 /* Normally, the new speed is setup after the link has
910 * gone down and up again. In some cases, link will not go
911 * down so we need to set up the new speed here.
913 if (bmsr
& BMSR_LSTATUS
) {
914 bp
->line_speed
= bp
->req_line_speed
;
915 bp
->duplex
= bp
->req_duplex
;
916 bnx2_resolve_flow_ctrl(bp
);
917 bnx2_set_mac_link(bp
);
924 bnx2_setup_phy(struct bnx2
*bp
)
926 if (bp
->loopback
== MAC_LOOPBACK
)
929 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
930 return (bnx2_setup_serdes_phy(bp
));
933 return (bnx2_setup_copper_phy(bp
));
938 bnx2_init_serdes_phy(struct bnx2
*bp
)
940 bp
->phy_flags
&= ~PHY_PARALLEL_DETECT_FLAG
;
942 if (CHIP_NUM(bp
) == CHIP_NUM_5706
) {
943 REG_WR(bp
, BNX2_MISC_UNUSED0
, 0x300);
946 if (bp
->dev
->mtu
> 1500) {
949 /* Set extended packet length bit */
950 bnx2_write_phy(bp
, 0x18, 0x7);
951 bnx2_read_phy(bp
, 0x18, &val
);
952 bnx2_write_phy(bp
, 0x18, (val
& 0xfff8) | 0x4000);
954 bnx2_write_phy(bp
, 0x1c, 0x6c00);
955 bnx2_read_phy(bp
, 0x1c, &val
);
956 bnx2_write_phy(bp
, 0x1c, (val
& 0x3ff) | 0xec02);
961 bnx2_write_phy(bp
, 0x18, 0x7);
962 bnx2_read_phy(bp
, 0x18, &val
);
963 bnx2_write_phy(bp
, 0x18, val
& ~0x4007);
965 bnx2_write_phy(bp
, 0x1c, 0x6c00);
966 bnx2_read_phy(bp
, 0x1c, &val
);
967 bnx2_write_phy(bp
, 0x1c, (val
& 0x3fd) | 0xec00);
974 bnx2_init_copper_phy(struct bnx2
*bp
)
976 bp
->phy_flags
|= PHY_CRC_FIX_FLAG
;
978 if (bp
->phy_flags
& PHY_CRC_FIX_FLAG
) {
979 bnx2_write_phy(bp
, 0x18, 0x0c00);
980 bnx2_write_phy(bp
, 0x17, 0x000a);
981 bnx2_write_phy(bp
, 0x15, 0x310b);
982 bnx2_write_phy(bp
, 0x17, 0x201f);
983 bnx2_write_phy(bp
, 0x15, 0x9506);
984 bnx2_write_phy(bp
, 0x17, 0x401f);
985 bnx2_write_phy(bp
, 0x15, 0x14e2);
986 bnx2_write_phy(bp
, 0x18, 0x0400);
989 if (bp
->dev
->mtu
> 1500) {
992 /* Set extended packet length bit */
993 bnx2_write_phy(bp
, 0x18, 0x7);
994 bnx2_read_phy(bp
, 0x18, &val
);
995 bnx2_write_phy(bp
, 0x18, val
| 0x4000);
997 bnx2_read_phy(bp
, 0x10, &val
);
998 bnx2_write_phy(bp
, 0x10, val
| 0x1);
1003 bnx2_write_phy(bp
, 0x18, 0x7);
1004 bnx2_read_phy(bp
, 0x18, &val
);
1005 bnx2_write_phy(bp
, 0x18, val
& ~0x4007);
1007 bnx2_read_phy(bp
, 0x10, &val
);
1008 bnx2_write_phy(bp
, 0x10, val
& ~0x1);
1016 bnx2_init_phy(struct bnx2
*bp
)
1021 bp
->phy_flags
&= ~PHY_INT_MODE_MASK_FLAG
;
1022 bp
->phy_flags
|= PHY_INT_MODE_LINK_READY_FLAG
;
1024 REG_WR(bp
, BNX2_EMAC_ATTENTION_ENA
, BNX2_EMAC_ATTENTION_ENA_LINK
);
1028 bnx2_read_phy(bp
, MII_PHYSID1
, &val
);
1029 bp
->phy_id
= val
<< 16;
1030 bnx2_read_phy(bp
, MII_PHYSID2
, &val
);
1031 bp
->phy_id
|= val
& 0xffff;
1033 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
1034 rc
= bnx2_init_serdes_phy(bp
);
1037 rc
= bnx2_init_copper_phy(bp
);
1046 bnx2_set_mac_loopback(struct bnx2
*bp
)
1050 mac_mode
= REG_RD(bp
, BNX2_EMAC_MODE
);
1051 mac_mode
&= ~BNX2_EMAC_MODE_PORT
;
1052 mac_mode
|= BNX2_EMAC_MODE_MAC_LOOP
| BNX2_EMAC_MODE_FORCE_LINK
;
1053 REG_WR(bp
, BNX2_EMAC_MODE
, mac_mode
);
1059 bnx2_fw_sync(struct bnx2
*bp
, u32 msg_data
)
1064 if (bp
->fw_timed_out
)
1068 msg_data
|= bp
->fw_wr_seq
;
1070 REG_WR_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_DRV_MB
, msg_data
);
1072 /* wait for an acknowledgement. */
1073 for (i
= 0; i
< (FW_ACK_TIME_OUT_MS
* 1000)/5; i
++) {
1076 val
= REG_RD_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_FW_MB
);
1078 if ((val
& BNX2_FW_MSG_ACK
) == (msg_data
& BNX2_DRV_MSG_SEQ
))
1082 /* If we timed out, inform the firmware that this is the case. */
1083 if (((val
& BNX2_FW_MSG_ACK
) != (msg_data
& BNX2_DRV_MSG_SEQ
)) &&
1084 ((msg_data
& BNX2_DRV_MSG_DATA
) != BNX2_DRV_MSG_DATA_WAIT0
)) {
1086 msg_data
&= ~BNX2_DRV_MSG_CODE
;
1087 msg_data
|= BNX2_DRV_MSG_CODE_FW_TIMEOUT
;
1089 REG_WR_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_DRV_MB
, msg_data
);
1091 bp
->fw_timed_out
= 1;
1100 bnx2_init_context(struct bnx2
*bp
)
1106 u32 vcid_addr
, pcid_addr
, offset
;
1110 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
1113 vcid_addr
= GET_PCID_ADDR(vcid
);
1115 new_vcid
= 0x60 + (vcid
& 0xf0) + (vcid
& 0x7);
1120 pcid_addr
= GET_PCID_ADDR(new_vcid
);
1123 vcid_addr
= GET_CID_ADDR(vcid
);
1124 pcid_addr
= vcid_addr
;
1127 REG_WR(bp
, BNX2_CTX_VIRT_ADDR
, 0x00);
1128 REG_WR(bp
, BNX2_CTX_PAGE_TBL
, pcid_addr
);
1130 /* Zero out the context. */
1131 for (offset
= 0; offset
< PHY_CTX_SIZE
; offset
+= 4) {
1132 CTX_WR(bp
, 0x00, offset
, 0);
1135 REG_WR(bp
, BNX2_CTX_VIRT_ADDR
, vcid_addr
);
1136 REG_WR(bp
, BNX2_CTX_PAGE_TBL
, pcid_addr
);
1141 bnx2_alloc_bad_rbuf(struct bnx2
*bp
)
1147 good_mbuf
= kmalloc(512 * sizeof(u16
), GFP_KERNEL
);
1148 if (good_mbuf
== NULL
) {
1149 printk(KERN_ERR PFX
"Failed to allocate memory in "
1150 "bnx2_alloc_bad_rbuf\n");
1154 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
,
1155 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE
);
1159 /* Allocate a bunch of mbufs and save the good ones in an array. */
1160 val
= REG_RD_IND(bp
, BNX2_RBUF_STATUS1
);
1161 while (val
& BNX2_RBUF_STATUS1_FREE_COUNT
) {
1162 REG_WR_IND(bp
, BNX2_RBUF_COMMAND
, BNX2_RBUF_COMMAND_ALLOC_REQ
);
1164 val
= REG_RD_IND(bp
, BNX2_RBUF_FW_BUF_ALLOC
);
1166 val
&= BNX2_RBUF_FW_BUF_ALLOC_VALUE
;
1168 /* The addresses with Bit 9 set are bad memory blocks. */
1169 if (!(val
& (1 << 9))) {
1170 good_mbuf
[good_mbuf_cnt
] = (u16
) val
;
1174 val
= REG_RD_IND(bp
, BNX2_RBUF_STATUS1
);
1177 /* Free the good ones back to the mbuf pool thus discarding
1178 * all the bad ones. */
1179 while (good_mbuf_cnt
) {
1182 val
= good_mbuf
[good_mbuf_cnt
];
1183 val
= (val
<< 9) | val
| 1;
1185 REG_WR_IND(bp
, BNX2_RBUF_FW_BUF_FREE
, val
);
1192 bnx2_set_mac_addr(struct bnx2
*bp
)
1195 u8
*mac_addr
= bp
->dev
->dev_addr
;
1197 val
= (mac_addr
[0] << 8) | mac_addr
[1];
1199 REG_WR(bp
, BNX2_EMAC_MAC_MATCH0
, val
);
1201 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
1202 (mac_addr
[4] << 8) | mac_addr
[5];
1204 REG_WR(bp
, BNX2_EMAC_MAC_MATCH1
, val
);
1208 bnx2_alloc_rx_skb(struct bnx2
*bp
, u16 index
)
1210 struct sk_buff
*skb
;
1211 struct sw_bd
*rx_buf
= &bp
->rx_buf_ring
[index
];
1213 struct rx_bd
*rxbd
= &bp
->rx_desc_ring
[index
];
1214 unsigned long align
;
1216 skb
= dev_alloc_skb(bp
->rx_buf_size
);
1221 if (unlikely((align
= (unsigned long) skb
->data
& 0x7))) {
1222 skb_reserve(skb
, 8 - align
);
1226 mapping
= pci_map_single(bp
->pdev
, skb
->data
, bp
->rx_buf_use_size
,
1227 PCI_DMA_FROMDEVICE
);
1230 pci_unmap_addr_set(rx_buf
, mapping
, mapping
);
1232 rxbd
->rx_bd_haddr_hi
= (u64
) mapping
>> 32;
1233 rxbd
->rx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
1235 bp
->rx_prod_bseq
+= bp
->rx_buf_use_size
;
1241 bnx2_phy_int(struct bnx2
*bp
)
1243 u32 new_link_state
, old_link_state
;
1245 new_link_state
= bp
->status_blk
->status_attn_bits
&
1246 STATUS_ATTN_BITS_LINK_STATE
;
1247 old_link_state
= bp
->status_blk
->status_attn_bits_ack
&
1248 STATUS_ATTN_BITS_LINK_STATE
;
1249 if (new_link_state
!= old_link_state
) {
1250 if (new_link_state
) {
1251 REG_WR(bp
, BNX2_PCICFG_STATUS_BIT_SET_CMD
,
1252 STATUS_ATTN_BITS_LINK_STATE
);
1255 REG_WR(bp
, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD
,
1256 STATUS_ATTN_BITS_LINK_STATE
);
1263 bnx2_tx_int(struct bnx2
*bp
)
1265 u16 hw_cons
, sw_cons
, sw_ring_cons
;
1268 hw_cons
= bp
->status_blk
->status_tx_quick_consumer_index0
;
1269 if ((hw_cons
& MAX_TX_DESC_CNT
) == MAX_TX_DESC_CNT
) {
1272 sw_cons
= bp
->tx_cons
;
1274 while (sw_cons
!= hw_cons
) {
1275 struct sw_bd
*tx_buf
;
1276 struct sk_buff
*skb
;
1279 sw_ring_cons
= TX_RING_IDX(sw_cons
);
1281 tx_buf
= &bp
->tx_buf_ring
[sw_ring_cons
];
1284 /* partial BD completions possible with TSO packets */
1285 if (skb_shinfo(skb
)->tso_size
) {
1286 u16 last_idx
, last_ring_idx
;
1288 last_idx
= sw_cons
+
1289 skb_shinfo(skb
)->nr_frags
+ 1;
1290 last_ring_idx
= sw_ring_cons
+
1291 skb_shinfo(skb
)->nr_frags
+ 1;
1292 if (unlikely(last_ring_idx
>= MAX_TX_DESC_CNT
)) {
1295 if (((s16
) ((s16
) last_idx
- (s16
) hw_cons
)) > 0) {
1300 pci_unmap_single(bp
->pdev
, pci_unmap_addr(tx_buf
, mapping
),
1301 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1304 last
= skb_shinfo(skb
)->nr_frags
;
1306 for (i
= 0; i
< last
; i
++) {
1307 sw_cons
= NEXT_TX_BD(sw_cons
);
1309 pci_unmap_page(bp
->pdev
,
1311 &bp
->tx_buf_ring
[TX_RING_IDX(sw_cons
)],
1313 skb_shinfo(skb
)->frags
[i
].size
,
1317 sw_cons
= NEXT_TX_BD(sw_cons
);
1319 tx_free_bd
+= last
+ 1;
1321 dev_kfree_skb_irq(skb
);
1323 hw_cons
= bp
->status_blk
->status_tx_quick_consumer_index0
;
1324 if ((hw_cons
& MAX_TX_DESC_CNT
) == MAX_TX_DESC_CNT
) {
1329 atomic_add(tx_free_bd
, &bp
->tx_avail_bd
);
1331 if (unlikely(netif_queue_stopped(bp
->dev
))) {
1332 unsigned long flags
;
1334 spin_lock_irqsave(&bp
->tx_lock
, flags
);
1335 if ((netif_queue_stopped(bp
->dev
)) &&
1336 (atomic_read(&bp
->tx_avail_bd
) > MAX_SKB_FRAGS
)) {
1338 netif_wake_queue(bp
->dev
);
1340 spin_unlock_irqrestore(&bp
->tx_lock
, flags
);
1343 bp
->tx_cons
= sw_cons
;
1348 bnx2_reuse_rx_skb(struct bnx2
*bp
, struct sk_buff
*skb
,
1351 struct sw_bd
*cons_rx_buf
= &bp
->rx_buf_ring
[cons
];
1352 struct sw_bd
*prod_rx_buf
= &bp
->rx_buf_ring
[prod
];
1353 struct rx_bd
*cons_bd
= &bp
->rx_desc_ring
[cons
];
1354 struct rx_bd
*prod_bd
= &bp
->rx_desc_ring
[prod
];
1356 pci_dma_sync_single_for_device(bp
->pdev
,
1357 pci_unmap_addr(cons_rx_buf
, mapping
),
1358 bp
->rx_offset
+ RX_COPY_THRESH
, PCI_DMA_FROMDEVICE
);
1360 prod_rx_buf
->skb
= cons_rx_buf
->skb
;
1361 pci_unmap_addr_set(prod_rx_buf
, mapping
,
1362 pci_unmap_addr(cons_rx_buf
, mapping
));
1364 memcpy(prod_bd
, cons_bd
, 8);
1366 bp
->rx_prod_bseq
+= bp
->rx_buf_use_size
;
1371 bnx2_rx_int(struct bnx2
*bp
, int budget
)
1373 u16 hw_cons
, sw_cons
, sw_ring_cons
, sw_prod
, sw_ring_prod
;
1374 struct l2_fhdr
*rx_hdr
;
1377 hw_cons
= bp
->status_blk
->status_rx_quick_consumer_index0
;
1378 if ((hw_cons
& MAX_RX_DESC_CNT
) == MAX_RX_DESC_CNT
) {
1381 sw_cons
= bp
->rx_cons
;
1382 sw_prod
= bp
->rx_prod
;
1384 /* Memory barrier necessary as speculative reads of the rx
1385 * buffer can be ahead of the index in the status block
1388 while (sw_cons
!= hw_cons
) {
1391 struct sw_bd
*rx_buf
;
1392 struct sk_buff
*skb
;
1394 sw_ring_cons
= RX_RING_IDX(sw_cons
);
1395 sw_ring_prod
= RX_RING_IDX(sw_prod
);
1397 rx_buf
= &bp
->rx_buf_ring
[sw_ring_cons
];
1399 pci_dma_sync_single_for_cpu(bp
->pdev
,
1400 pci_unmap_addr(rx_buf
, mapping
),
1401 bp
->rx_offset
+ RX_COPY_THRESH
, PCI_DMA_FROMDEVICE
);
1403 rx_hdr
= (struct l2_fhdr
*) skb
->data
;
1404 len
= rx_hdr
->l2_fhdr_pkt_len
- 4;
1406 if (rx_hdr
->l2_fhdr_errors
&
1407 (L2_FHDR_ERRORS_BAD_CRC
|
1408 L2_FHDR_ERRORS_PHY_DECODE
|
1409 L2_FHDR_ERRORS_ALIGNMENT
|
1410 L2_FHDR_ERRORS_TOO_SHORT
|
1411 L2_FHDR_ERRORS_GIANT_FRAME
)) {
1416 /* Since we don't have a jumbo ring, copy small packets
1419 if ((bp
->dev
->mtu
> 1500) && (len
<= RX_COPY_THRESH
)) {
1420 struct sk_buff
*new_skb
;
1422 new_skb
= dev_alloc_skb(len
+ 2);
1423 if (new_skb
== NULL
)
1427 memcpy(new_skb
->data
,
1428 skb
->data
+ bp
->rx_offset
- 2,
1431 skb_reserve(new_skb
, 2);
1432 skb_put(new_skb
, len
);
1433 new_skb
->dev
= bp
->dev
;
1435 bnx2_reuse_rx_skb(bp
, skb
,
1436 sw_ring_cons
, sw_ring_prod
);
1440 else if (bnx2_alloc_rx_skb(bp
, sw_ring_prod
) == 0) {
1441 pci_unmap_single(bp
->pdev
,
1442 pci_unmap_addr(rx_buf
, mapping
),
1443 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
1445 skb_reserve(skb
, bp
->rx_offset
);
1450 bnx2_reuse_rx_skb(bp
, skb
,
1451 sw_ring_cons
, sw_ring_prod
);
1455 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1457 if ((len
> (bp
->dev
->mtu
+ ETH_HLEN
)) &&
1458 (htons(skb
->protocol
) != 0x8100)) {
1460 dev_kfree_skb_irq(skb
);
1465 status
= rx_hdr
->l2_fhdr_status
;
1466 skb
->ip_summed
= CHECKSUM_NONE
;
1468 (status
& (L2_FHDR_STATUS_TCP_SEGMENT
|
1469 L2_FHDR_STATUS_UDP_DATAGRAM
))) {
1471 u16 cksum
= rx_hdr
->l2_fhdr_tcp_udp_xsum
;
1473 if (cksum
== 0xffff)
1474 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1478 if ((status
& L2_FHDR_STATUS_L2_VLAN_TAG
) && (bp
->vlgrp
!= 0)) {
1479 vlan_hwaccel_receive_skb(skb
, bp
->vlgrp
,
1480 rx_hdr
->l2_fhdr_vlan_tag
);
1484 netif_receive_skb(skb
);
1486 bp
->dev
->last_rx
= jiffies
;
1492 sw_cons
= NEXT_RX_BD(sw_cons
);
1493 sw_prod
= NEXT_RX_BD(sw_prod
);
1495 if ((rx_pkt
== budget
))
1498 bp
->rx_cons
= sw_cons
;
1499 bp
->rx_prod
= sw_prod
;
1501 REG_WR16(bp
, MB_RX_CID_ADDR
+ BNX2_L2CTX_HOST_BDIDX
, sw_prod
);
1503 REG_WR(bp
, MB_RX_CID_ADDR
+ BNX2_L2CTX_HOST_BSEQ
, bp
->rx_prod_bseq
);
1511 /* MSI ISR - The only difference between this and the INTx ISR
1512 * is that the MSI interrupt is always serviced.
1515 bnx2_msi(int irq
, void *dev_instance
, struct pt_regs
*regs
)
1517 struct net_device
*dev
= dev_instance
;
1518 struct bnx2
*bp
= dev
->priv
;
1520 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
1521 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM
|
1522 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
1524 /* Return here if interrupt is disabled. */
1525 if (unlikely(atomic_read(&bp
->intr_sem
) != 0)) {
1526 return IRQ_RETVAL(1);
1529 if (netif_rx_schedule_prep(dev
)) {
1530 __netif_rx_schedule(dev
);
1533 return IRQ_RETVAL(1);
1537 bnx2_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
)
1539 struct net_device
*dev
= dev_instance
;
1540 struct bnx2
*bp
= dev
->priv
;
1542 /* When using INTx, it is possible for the interrupt to arrive
1543 * at the CPU before the status block posted prior to the
1544 * interrupt. Reading a register will flush the status block.
1545 * When using MSI, the MSI message will always complete after
1546 * the status block write.
1548 if ((bp
->status_blk
->status_idx
== bp
->last_status_idx
) ||
1549 (REG_RD(bp
, BNX2_PCICFG_MISC_STATUS
) &
1550 BNX2_PCICFG_MISC_STATUS_INTA_VALUE
))
1551 return IRQ_RETVAL(0);
1553 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
1554 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM
|
1555 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
1557 /* Return here if interrupt is shared and is disabled. */
1558 if (unlikely(atomic_read(&bp
->intr_sem
) != 0)) {
1559 return IRQ_RETVAL(1);
1562 if (netif_rx_schedule_prep(dev
)) {
1563 __netif_rx_schedule(dev
);
1566 return IRQ_RETVAL(1);
1570 bnx2_poll(struct net_device
*dev
, int *budget
)
1572 struct bnx2
*bp
= dev
->priv
;
1575 bp
->last_status_idx
= bp
->status_blk
->status_idx
;
1578 if ((bp
->status_blk
->status_attn_bits
&
1579 STATUS_ATTN_BITS_LINK_STATE
) !=
1580 (bp
->status_blk
->status_attn_bits_ack
&
1581 STATUS_ATTN_BITS_LINK_STATE
)) {
1583 unsigned long flags
;
1585 spin_lock_irqsave(&bp
->phy_lock
, flags
);
1587 spin_unlock_irqrestore(&bp
->phy_lock
, flags
);
1590 if (bp
->status_blk
->status_tx_quick_consumer_index0
!= bp
->tx_cons
) {
1594 if (bp
->status_blk
->status_rx_quick_consumer_index0
!= bp
->rx_cons
) {
1595 int orig_budget
= *budget
;
1598 if (orig_budget
> dev
->quota
)
1599 orig_budget
= dev
->quota
;
1601 work_done
= bnx2_rx_int(bp
, orig_budget
);
1602 *budget
-= work_done
;
1603 dev
->quota
-= work_done
;
1605 if (work_done
>= orig_budget
) {
1611 netif_rx_complete(dev
);
1612 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
1613 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
1614 bp
->last_status_idx
);
1621 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1622 * from set_multicast.
1625 bnx2_set_rx_mode(struct net_device
*dev
)
1627 struct bnx2
*bp
= dev
->priv
;
1628 u32 rx_mode
, sort_mode
;
1630 unsigned long flags
;
1632 spin_lock_irqsave(&bp
->phy_lock
, flags
);
1634 rx_mode
= bp
->rx_mode
& ~(BNX2_EMAC_RX_MODE_PROMISCUOUS
|
1635 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
);
1636 sort_mode
= 1 | BNX2_RPM_SORT_USER0_BC_EN
;
1639 rx_mode
|= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
;
1642 rx_mode
|= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
;
1644 if (dev
->flags
& IFF_PROMISC
) {
1645 /* Promiscuous mode. */
1646 rx_mode
|= BNX2_EMAC_RX_MODE_PROMISCUOUS
;
1647 sort_mode
|= BNX2_RPM_SORT_USER0_PROM_EN
;
1649 else if (dev
->flags
& IFF_ALLMULTI
) {
1650 for (i
= 0; i
< NUM_MC_HASH_REGISTERS
; i
++) {
1651 REG_WR(bp
, BNX2_EMAC_MULTICAST_HASH0
+ (i
* 4),
1654 sort_mode
|= BNX2_RPM_SORT_USER0_MC_EN
;
1657 /* Accept one or more multicast(s). */
1658 struct dev_mc_list
*mclist
;
1659 u32 mc_filter
[NUM_MC_HASH_REGISTERS
];
1664 memset(mc_filter
, 0, 4 * NUM_MC_HASH_REGISTERS
);
1666 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
1667 i
++, mclist
= mclist
->next
) {
1669 crc
= ether_crc_le(ETH_ALEN
, mclist
->dmi_addr
);
1671 regidx
= (bit
& 0xe0) >> 5;
1673 mc_filter
[regidx
] |= (1 << bit
);
1676 for (i
= 0; i
< NUM_MC_HASH_REGISTERS
; i
++) {
1677 REG_WR(bp
, BNX2_EMAC_MULTICAST_HASH0
+ (i
* 4),
1681 sort_mode
|= BNX2_RPM_SORT_USER0_MC_HSH_EN
;
1684 if (rx_mode
!= bp
->rx_mode
) {
1685 bp
->rx_mode
= rx_mode
;
1686 REG_WR(bp
, BNX2_EMAC_RX_MODE
, rx_mode
);
1689 REG_WR(bp
, BNX2_RPM_SORT_USER0
, 0x0);
1690 REG_WR(bp
, BNX2_RPM_SORT_USER0
, sort_mode
);
1691 REG_WR(bp
, BNX2_RPM_SORT_USER0
, sort_mode
| BNX2_RPM_SORT_USER0_ENA
);
1693 spin_unlock_irqrestore(&bp
->phy_lock
, flags
);
1697 load_rv2p_fw(struct bnx2
*bp
, u32
*rv2p_code
, u32 rv2p_code_len
,
1704 for (i
= 0; i
< rv2p_code_len
; i
+= 8) {
1705 REG_WR(bp
, BNX2_RV2P_INSTR_HIGH
, *rv2p_code
);
1707 REG_WR(bp
, BNX2_RV2P_INSTR_LOW
, *rv2p_code
);
1710 if (rv2p_proc
== RV2P_PROC1
) {
1711 val
= (i
/ 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR
;
1712 REG_WR(bp
, BNX2_RV2P_PROC1_ADDR_CMD
, val
);
1715 val
= (i
/ 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR
;
1716 REG_WR(bp
, BNX2_RV2P_PROC2_ADDR_CMD
, val
);
1720 /* Reset the processor, un-stall is done later. */
1721 if (rv2p_proc
== RV2P_PROC1
) {
1722 REG_WR(bp
, BNX2_RV2P_COMMAND
, BNX2_RV2P_COMMAND_PROC1_RESET
);
1725 REG_WR(bp
, BNX2_RV2P_COMMAND
, BNX2_RV2P_COMMAND_PROC2_RESET
);
1730 load_cpu_fw(struct bnx2
*bp
, struct cpu_reg
*cpu_reg
, struct fw_info
*fw
)
1736 val
= REG_RD_IND(bp
, cpu_reg
->mode
);
1737 val
|= cpu_reg
->mode_value_halt
;
1738 REG_WR_IND(bp
, cpu_reg
->mode
, val
);
1739 REG_WR_IND(bp
, cpu_reg
->state
, cpu_reg
->state_value_clear
);
1741 /* Load the Text area. */
1742 offset
= cpu_reg
->spad_base
+ (fw
->text_addr
- cpu_reg
->mips_view_base
);
1746 for (j
= 0; j
< (fw
->text_len
/ 4); j
++, offset
+= 4) {
1747 REG_WR_IND(bp
, offset
, fw
->text
[j
]);
1751 /* Load the Data area. */
1752 offset
= cpu_reg
->spad_base
+ (fw
->data_addr
- cpu_reg
->mips_view_base
);
1756 for (j
= 0; j
< (fw
->data_len
/ 4); j
++, offset
+= 4) {
1757 REG_WR_IND(bp
, offset
, fw
->data
[j
]);
1761 /* Load the SBSS area. */
1762 offset
= cpu_reg
->spad_base
+ (fw
->sbss_addr
- cpu_reg
->mips_view_base
);
1766 for (j
= 0; j
< (fw
->sbss_len
/ 4); j
++, offset
+= 4) {
1767 REG_WR_IND(bp
, offset
, fw
->sbss
[j
]);
1771 /* Load the BSS area. */
1772 offset
= cpu_reg
->spad_base
+ (fw
->bss_addr
- cpu_reg
->mips_view_base
);
1776 for (j
= 0; j
< (fw
->bss_len
/4); j
++, offset
+= 4) {
1777 REG_WR_IND(bp
, offset
, fw
->bss
[j
]);
1781 /* Load the Read-Only area. */
1782 offset
= cpu_reg
->spad_base
+
1783 (fw
->rodata_addr
- cpu_reg
->mips_view_base
);
1787 for (j
= 0; j
< (fw
->rodata_len
/ 4); j
++, offset
+= 4) {
1788 REG_WR_IND(bp
, offset
, fw
->rodata
[j
]);
1792 /* Clear the pre-fetch instruction. */
1793 REG_WR_IND(bp
, cpu_reg
->inst
, 0);
1794 REG_WR_IND(bp
, cpu_reg
->pc
, fw
->start_addr
);
1796 /* Start the CPU. */
1797 val
= REG_RD_IND(bp
, cpu_reg
->mode
);
1798 val
&= ~cpu_reg
->mode_value_halt
;
1799 REG_WR_IND(bp
, cpu_reg
->state
, cpu_reg
->state_value_clear
);
1800 REG_WR_IND(bp
, cpu_reg
->mode
, val
);
1804 bnx2_init_cpus(struct bnx2
*bp
)
1806 struct cpu_reg cpu_reg
;
1809 /* Initialize the RV2P processor. */
1810 load_rv2p_fw(bp
, bnx2_rv2p_proc1
, sizeof(bnx2_rv2p_proc1
), RV2P_PROC1
);
1811 load_rv2p_fw(bp
, bnx2_rv2p_proc2
, sizeof(bnx2_rv2p_proc2
), RV2P_PROC2
);
1813 /* Initialize the RX Processor. */
1814 cpu_reg
.mode
= BNX2_RXP_CPU_MODE
;
1815 cpu_reg
.mode_value_halt
= BNX2_RXP_CPU_MODE_SOFT_HALT
;
1816 cpu_reg
.mode_value_sstep
= BNX2_RXP_CPU_MODE_STEP_ENA
;
1817 cpu_reg
.state
= BNX2_RXP_CPU_STATE
;
1818 cpu_reg
.state_value_clear
= 0xffffff;
1819 cpu_reg
.gpr0
= BNX2_RXP_CPU_REG_FILE
;
1820 cpu_reg
.evmask
= BNX2_RXP_CPU_EVENT_MASK
;
1821 cpu_reg
.pc
= BNX2_RXP_CPU_PROGRAM_COUNTER
;
1822 cpu_reg
.inst
= BNX2_RXP_CPU_INSTRUCTION
;
1823 cpu_reg
.bp
= BNX2_RXP_CPU_HW_BREAKPOINT
;
1824 cpu_reg
.spad_base
= BNX2_RXP_SCRATCH
;
1825 cpu_reg
.mips_view_base
= 0x8000000;
1827 fw
.ver_major
= bnx2_RXP_b06FwReleaseMajor
;
1828 fw
.ver_minor
= bnx2_RXP_b06FwReleaseMinor
;
1829 fw
.ver_fix
= bnx2_RXP_b06FwReleaseFix
;
1830 fw
.start_addr
= bnx2_RXP_b06FwStartAddr
;
1832 fw
.text_addr
= bnx2_RXP_b06FwTextAddr
;
1833 fw
.text_len
= bnx2_RXP_b06FwTextLen
;
1835 fw
.text
= bnx2_RXP_b06FwText
;
1837 fw
.data_addr
= bnx2_RXP_b06FwDataAddr
;
1838 fw
.data_len
= bnx2_RXP_b06FwDataLen
;
1840 fw
.data
= bnx2_RXP_b06FwData
;
1842 fw
.sbss_addr
= bnx2_RXP_b06FwSbssAddr
;
1843 fw
.sbss_len
= bnx2_RXP_b06FwSbssLen
;
1845 fw
.sbss
= bnx2_RXP_b06FwSbss
;
1847 fw
.bss_addr
= bnx2_RXP_b06FwBssAddr
;
1848 fw
.bss_len
= bnx2_RXP_b06FwBssLen
;
1850 fw
.bss
= bnx2_RXP_b06FwBss
;
1852 fw
.rodata_addr
= bnx2_RXP_b06FwRodataAddr
;
1853 fw
.rodata_len
= bnx2_RXP_b06FwRodataLen
;
1854 fw
.rodata_index
= 0;
1855 fw
.rodata
= bnx2_RXP_b06FwRodata
;
1857 load_cpu_fw(bp
, &cpu_reg
, &fw
);
1859 /* Initialize the TX Processor. */
1860 cpu_reg
.mode
= BNX2_TXP_CPU_MODE
;
1861 cpu_reg
.mode_value_halt
= BNX2_TXP_CPU_MODE_SOFT_HALT
;
1862 cpu_reg
.mode_value_sstep
= BNX2_TXP_CPU_MODE_STEP_ENA
;
1863 cpu_reg
.state
= BNX2_TXP_CPU_STATE
;
1864 cpu_reg
.state_value_clear
= 0xffffff;
1865 cpu_reg
.gpr0
= BNX2_TXP_CPU_REG_FILE
;
1866 cpu_reg
.evmask
= BNX2_TXP_CPU_EVENT_MASK
;
1867 cpu_reg
.pc
= BNX2_TXP_CPU_PROGRAM_COUNTER
;
1868 cpu_reg
.inst
= BNX2_TXP_CPU_INSTRUCTION
;
1869 cpu_reg
.bp
= BNX2_TXP_CPU_HW_BREAKPOINT
;
1870 cpu_reg
.spad_base
= BNX2_TXP_SCRATCH
;
1871 cpu_reg
.mips_view_base
= 0x8000000;
1873 fw
.ver_major
= bnx2_TXP_b06FwReleaseMajor
;
1874 fw
.ver_minor
= bnx2_TXP_b06FwReleaseMinor
;
1875 fw
.ver_fix
= bnx2_TXP_b06FwReleaseFix
;
1876 fw
.start_addr
= bnx2_TXP_b06FwStartAddr
;
1878 fw
.text_addr
= bnx2_TXP_b06FwTextAddr
;
1879 fw
.text_len
= bnx2_TXP_b06FwTextLen
;
1881 fw
.text
= bnx2_TXP_b06FwText
;
1883 fw
.data_addr
= bnx2_TXP_b06FwDataAddr
;
1884 fw
.data_len
= bnx2_TXP_b06FwDataLen
;
1886 fw
.data
= bnx2_TXP_b06FwData
;
1888 fw
.sbss_addr
= bnx2_TXP_b06FwSbssAddr
;
1889 fw
.sbss_len
= bnx2_TXP_b06FwSbssLen
;
1891 fw
.sbss
= bnx2_TXP_b06FwSbss
;
1893 fw
.bss_addr
= bnx2_TXP_b06FwBssAddr
;
1894 fw
.bss_len
= bnx2_TXP_b06FwBssLen
;
1896 fw
.bss
= bnx2_TXP_b06FwBss
;
1898 fw
.rodata_addr
= bnx2_TXP_b06FwRodataAddr
;
1899 fw
.rodata_len
= bnx2_TXP_b06FwRodataLen
;
1900 fw
.rodata_index
= 0;
1901 fw
.rodata
= bnx2_TXP_b06FwRodata
;
1903 load_cpu_fw(bp
, &cpu_reg
, &fw
);
1905 /* Initialize the TX Patch-up Processor. */
1906 cpu_reg
.mode
= BNX2_TPAT_CPU_MODE
;
1907 cpu_reg
.mode_value_halt
= BNX2_TPAT_CPU_MODE_SOFT_HALT
;
1908 cpu_reg
.mode_value_sstep
= BNX2_TPAT_CPU_MODE_STEP_ENA
;
1909 cpu_reg
.state
= BNX2_TPAT_CPU_STATE
;
1910 cpu_reg
.state_value_clear
= 0xffffff;
1911 cpu_reg
.gpr0
= BNX2_TPAT_CPU_REG_FILE
;
1912 cpu_reg
.evmask
= BNX2_TPAT_CPU_EVENT_MASK
;
1913 cpu_reg
.pc
= BNX2_TPAT_CPU_PROGRAM_COUNTER
;
1914 cpu_reg
.inst
= BNX2_TPAT_CPU_INSTRUCTION
;
1915 cpu_reg
.bp
= BNX2_TPAT_CPU_HW_BREAKPOINT
;
1916 cpu_reg
.spad_base
= BNX2_TPAT_SCRATCH
;
1917 cpu_reg
.mips_view_base
= 0x8000000;
1919 fw
.ver_major
= bnx2_TPAT_b06FwReleaseMajor
;
1920 fw
.ver_minor
= bnx2_TPAT_b06FwReleaseMinor
;
1921 fw
.ver_fix
= bnx2_TPAT_b06FwReleaseFix
;
1922 fw
.start_addr
= bnx2_TPAT_b06FwStartAddr
;
1924 fw
.text_addr
= bnx2_TPAT_b06FwTextAddr
;
1925 fw
.text_len
= bnx2_TPAT_b06FwTextLen
;
1927 fw
.text
= bnx2_TPAT_b06FwText
;
1929 fw
.data_addr
= bnx2_TPAT_b06FwDataAddr
;
1930 fw
.data_len
= bnx2_TPAT_b06FwDataLen
;
1932 fw
.data
= bnx2_TPAT_b06FwData
;
1934 fw
.sbss_addr
= bnx2_TPAT_b06FwSbssAddr
;
1935 fw
.sbss_len
= bnx2_TPAT_b06FwSbssLen
;
1937 fw
.sbss
= bnx2_TPAT_b06FwSbss
;
1939 fw
.bss_addr
= bnx2_TPAT_b06FwBssAddr
;
1940 fw
.bss_len
= bnx2_TPAT_b06FwBssLen
;
1942 fw
.bss
= bnx2_TPAT_b06FwBss
;
1944 fw
.rodata_addr
= bnx2_TPAT_b06FwRodataAddr
;
1945 fw
.rodata_len
= bnx2_TPAT_b06FwRodataLen
;
1946 fw
.rodata_index
= 0;
1947 fw
.rodata
= bnx2_TPAT_b06FwRodata
;
1949 load_cpu_fw(bp
, &cpu_reg
, &fw
);
1951 /* Initialize the Completion Processor. */
1952 cpu_reg
.mode
= BNX2_COM_CPU_MODE
;
1953 cpu_reg
.mode_value_halt
= BNX2_COM_CPU_MODE_SOFT_HALT
;
1954 cpu_reg
.mode_value_sstep
= BNX2_COM_CPU_MODE_STEP_ENA
;
1955 cpu_reg
.state
= BNX2_COM_CPU_STATE
;
1956 cpu_reg
.state_value_clear
= 0xffffff;
1957 cpu_reg
.gpr0
= BNX2_COM_CPU_REG_FILE
;
1958 cpu_reg
.evmask
= BNX2_COM_CPU_EVENT_MASK
;
1959 cpu_reg
.pc
= BNX2_COM_CPU_PROGRAM_COUNTER
;
1960 cpu_reg
.inst
= BNX2_COM_CPU_INSTRUCTION
;
1961 cpu_reg
.bp
= BNX2_COM_CPU_HW_BREAKPOINT
;
1962 cpu_reg
.spad_base
= BNX2_COM_SCRATCH
;
1963 cpu_reg
.mips_view_base
= 0x8000000;
1965 fw
.ver_major
= bnx2_COM_b06FwReleaseMajor
;
1966 fw
.ver_minor
= bnx2_COM_b06FwReleaseMinor
;
1967 fw
.ver_fix
= bnx2_COM_b06FwReleaseFix
;
1968 fw
.start_addr
= bnx2_COM_b06FwStartAddr
;
1970 fw
.text_addr
= bnx2_COM_b06FwTextAddr
;
1971 fw
.text_len
= bnx2_COM_b06FwTextLen
;
1973 fw
.text
= bnx2_COM_b06FwText
;
1975 fw
.data_addr
= bnx2_COM_b06FwDataAddr
;
1976 fw
.data_len
= bnx2_COM_b06FwDataLen
;
1978 fw
.data
= bnx2_COM_b06FwData
;
1980 fw
.sbss_addr
= bnx2_COM_b06FwSbssAddr
;
1981 fw
.sbss_len
= bnx2_COM_b06FwSbssLen
;
1983 fw
.sbss
= bnx2_COM_b06FwSbss
;
1985 fw
.bss_addr
= bnx2_COM_b06FwBssAddr
;
1986 fw
.bss_len
= bnx2_COM_b06FwBssLen
;
1988 fw
.bss
= bnx2_COM_b06FwBss
;
1990 fw
.rodata_addr
= bnx2_COM_b06FwRodataAddr
;
1991 fw
.rodata_len
= bnx2_COM_b06FwRodataLen
;
1992 fw
.rodata_index
= 0;
1993 fw
.rodata
= bnx2_COM_b06FwRodata
;
1995 load_cpu_fw(bp
, &cpu_reg
, &fw
);
2000 bnx2_set_power_state(struct bnx2
*bp
, int state
)
2004 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2010 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
,
2011 (pmcsr
& ~PCI_PM_CTRL_STATE_MASK
) |
2012 PCI_PM_CTRL_PME_STATUS
);
2014 if (pmcsr
& PCI_PM_CTRL_STATE_MASK
)
2015 /* delay required during transition out of D3hot */
2018 val
= REG_RD(bp
, BNX2_EMAC_MODE
);
2019 val
|= BNX2_EMAC_MODE_MPKT_RCVD
| BNX2_EMAC_MODE_ACPI_RCVD
;
2020 val
&= ~BNX2_EMAC_MODE_MPKT
;
2021 REG_WR(bp
, BNX2_EMAC_MODE
, val
);
2023 val
= REG_RD(bp
, BNX2_RPM_CONFIG
);
2024 val
&= ~BNX2_RPM_CONFIG_ACPI_ENA
;
2025 REG_WR(bp
, BNX2_RPM_CONFIG
, val
);
2036 autoneg
= bp
->autoneg
;
2037 advertising
= bp
->advertising
;
2039 bp
->autoneg
= AUTONEG_SPEED
;
2040 bp
->advertising
= ADVERTISED_10baseT_Half
|
2041 ADVERTISED_10baseT_Full
|
2042 ADVERTISED_100baseT_Half
|
2043 ADVERTISED_100baseT_Full
|
2046 bnx2_setup_copper_phy(bp
);
2048 bp
->autoneg
= autoneg
;
2049 bp
->advertising
= advertising
;
2051 bnx2_set_mac_addr(bp
);
2053 val
= REG_RD(bp
, BNX2_EMAC_MODE
);
2055 /* Enable port mode. */
2056 val
&= ~BNX2_EMAC_MODE_PORT
;
2057 val
|= BNX2_EMAC_MODE_PORT_MII
|
2058 BNX2_EMAC_MODE_MPKT_RCVD
|
2059 BNX2_EMAC_MODE_ACPI_RCVD
|
2060 BNX2_EMAC_MODE_FORCE_LINK
|
2061 BNX2_EMAC_MODE_MPKT
;
2063 REG_WR(bp
, BNX2_EMAC_MODE
, val
);
2065 /* receive all multicast */
2066 for (i
= 0; i
< NUM_MC_HASH_REGISTERS
; i
++) {
2067 REG_WR(bp
, BNX2_EMAC_MULTICAST_HASH0
+ (i
* 4),
2070 REG_WR(bp
, BNX2_EMAC_RX_MODE
,
2071 BNX2_EMAC_RX_MODE_SORT_MODE
);
2073 val
= 1 | BNX2_RPM_SORT_USER0_BC_EN
|
2074 BNX2_RPM_SORT_USER0_MC_EN
;
2075 REG_WR(bp
, BNX2_RPM_SORT_USER0
, 0x0);
2076 REG_WR(bp
, BNX2_RPM_SORT_USER0
, val
);
2077 REG_WR(bp
, BNX2_RPM_SORT_USER0
, val
|
2078 BNX2_RPM_SORT_USER0_ENA
);
2080 /* Need to enable EMAC and RPM for WOL. */
2081 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
,
2082 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE
|
2083 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE
|
2084 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE
);
2086 val
= REG_RD(bp
, BNX2_RPM_CONFIG
);
2087 val
&= ~BNX2_RPM_CONFIG_ACPI_ENA
;
2088 REG_WR(bp
, BNX2_RPM_CONFIG
, val
);
2090 wol_msg
= BNX2_DRV_MSG_CODE_SUSPEND_WOL
;
2093 wol_msg
= BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL
;
2096 bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT3
| wol_msg
);
2098 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
2099 if ((CHIP_ID(bp
) == CHIP_ID_5706_A0
) ||
2100 (CHIP_ID(bp
) == CHIP_ID_5706_A1
)) {
2109 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
2111 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
,
2114 /* No more memory access after this point until
2115 * device is brought back to D0.
2127 bnx2_acquire_nvram_lock(struct bnx2
*bp
)
2132 /* Request access to the flash interface. */
2133 REG_WR(bp
, BNX2_NVM_SW_ARB
, BNX2_NVM_SW_ARB_ARB_REQ_SET2
);
2134 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
2135 val
= REG_RD(bp
, BNX2_NVM_SW_ARB
);
2136 if (val
& BNX2_NVM_SW_ARB_ARB_ARB2
)
2142 if (j
>= NVRAM_TIMEOUT_COUNT
)
2149 bnx2_release_nvram_lock(struct bnx2
*bp
)
2154 /* Relinquish nvram interface. */
2155 REG_WR(bp
, BNX2_NVM_SW_ARB
, BNX2_NVM_SW_ARB_ARB_REQ_CLR2
);
2157 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
2158 val
= REG_RD(bp
, BNX2_NVM_SW_ARB
);
2159 if (!(val
& BNX2_NVM_SW_ARB_ARB_ARB2
))
2165 if (j
>= NVRAM_TIMEOUT_COUNT
)
2173 bnx2_enable_nvram_write(struct bnx2
*bp
)
2177 val
= REG_RD(bp
, BNX2_MISC_CFG
);
2178 REG_WR(bp
, BNX2_MISC_CFG
, val
| BNX2_MISC_CFG_NVM_WR_EN_PCI
);
2180 if (!bp
->flash_info
->buffered
) {
2183 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
2184 REG_WR(bp
, BNX2_NVM_COMMAND
,
2185 BNX2_NVM_COMMAND_WREN
| BNX2_NVM_COMMAND_DOIT
);
2187 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
2190 val
= REG_RD(bp
, BNX2_NVM_COMMAND
);
2191 if (val
& BNX2_NVM_COMMAND_DONE
)
2195 if (j
>= NVRAM_TIMEOUT_COUNT
)
2202 bnx2_disable_nvram_write(struct bnx2
*bp
)
2206 val
= REG_RD(bp
, BNX2_MISC_CFG
);
2207 REG_WR(bp
, BNX2_MISC_CFG
, val
& ~BNX2_MISC_CFG_NVM_WR_EN
);
2212 bnx2_enable_nvram_access(struct bnx2
*bp
)
2216 val
= REG_RD(bp
, BNX2_NVM_ACCESS_ENABLE
);
2217 /* Enable both bits, even on read. */
2218 REG_WR(bp
, BNX2_NVM_ACCESS_ENABLE
,
2219 val
| BNX2_NVM_ACCESS_ENABLE_EN
| BNX2_NVM_ACCESS_ENABLE_WR_EN
);
2223 bnx2_disable_nvram_access(struct bnx2
*bp
)
2227 val
= REG_RD(bp
, BNX2_NVM_ACCESS_ENABLE
);
2228 /* Disable both bits, even after read. */
2229 REG_WR(bp
, BNX2_NVM_ACCESS_ENABLE
,
2230 val
& ~(BNX2_NVM_ACCESS_ENABLE_EN
|
2231 BNX2_NVM_ACCESS_ENABLE_WR_EN
));
2235 bnx2_nvram_erase_page(struct bnx2
*bp
, u32 offset
)
2240 if (bp
->flash_info
->buffered
)
2241 /* Buffered flash, no erase needed */
2244 /* Build an erase command */
2245 cmd
= BNX2_NVM_COMMAND_ERASE
| BNX2_NVM_COMMAND_WR
|
2246 BNX2_NVM_COMMAND_DOIT
;
2248 /* Need to clear DONE bit separately. */
2249 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
2251 /* Address of the NVRAM to read from. */
2252 REG_WR(bp
, BNX2_NVM_ADDR
, offset
& BNX2_NVM_ADDR_NVM_ADDR_VALUE
);
2254 /* Issue an erase command. */
2255 REG_WR(bp
, BNX2_NVM_COMMAND
, cmd
);
2257 /* Wait for completion. */
2258 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
2263 val
= REG_RD(bp
, BNX2_NVM_COMMAND
);
2264 if (val
& BNX2_NVM_COMMAND_DONE
)
2268 if (j
>= NVRAM_TIMEOUT_COUNT
)
2275 bnx2_nvram_read_dword(struct bnx2
*bp
, u32 offset
, u8
*ret_val
, u32 cmd_flags
)
2280 /* Build the command word. */
2281 cmd
= BNX2_NVM_COMMAND_DOIT
| cmd_flags
;
2283 /* Calculate an offset of a buffered flash. */
2284 if (bp
->flash_info
->buffered
) {
2285 offset
= ((offset
/ bp
->flash_info
->page_size
) <<
2286 bp
->flash_info
->page_bits
) +
2287 (offset
% bp
->flash_info
->page_size
);
2290 /* Need to clear DONE bit separately. */
2291 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
2293 /* Address of the NVRAM to read from. */
2294 REG_WR(bp
, BNX2_NVM_ADDR
, offset
& BNX2_NVM_ADDR_NVM_ADDR_VALUE
);
2296 /* Issue a read command. */
2297 REG_WR(bp
, BNX2_NVM_COMMAND
, cmd
);
2299 /* Wait for completion. */
2300 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
2305 val
= REG_RD(bp
, BNX2_NVM_COMMAND
);
2306 if (val
& BNX2_NVM_COMMAND_DONE
) {
2307 val
= REG_RD(bp
, BNX2_NVM_READ
);
2309 val
= be32_to_cpu(val
);
2310 memcpy(ret_val
, &val
, 4);
2314 if (j
>= NVRAM_TIMEOUT_COUNT
)
2322 bnx2_nvram_write_dword(struct bnx2
*bp
, u32 offset
, u8
*val
, u32 cmd_flags
)
2327 /* Build the command word. */
2328 cmd
= BNX2_NVM_COMMAND_DOIT
| BNX2_NVM_COMMAND_WR
| cmd_flags
;
2330 /* Calculate an offset of a buffered flash. */
2331 if (bp
->flash_info
->buffered
) {
2332 offset
= ((offset
/ bp
->flash_info
->page_size
) <<
2333 bp
->flash_info
->page_bits
) +
2334 (offset
% bp
->flash_info
->page_size
);
2337 /* Need to clear DONE bit separately. */
2338 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
2340 memcpy(&val32
, val
, 4);
2341 val32
= cpu_to_be32(val32
);
2343 /* Write the data. */
2344 REG_WR(bp
, BNX2_NVM_WRITE
, val32
);
2346 /* Address of the NVRAM to write to. */
2347 REG_WR(bp
, BNX2_NVM_ADDR
, offset
& BNX2_NVM_ADDR_NVM_ADDR_VALUE
);
2349 /* Issue the write command. */
2350 REG_WR(bp
, BNX2_NVM_COMMAND
, cmd
);
2352 /* Wait for completion. */
2353 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
2356 if (REG_RD(bp
, BNX2_NVM_COMMAND
) & BNX2_NVM_COMMAND_DONE
)
2359 if (j
>= NVRAM_TIMEOUT_COUNT
)
2366 bnx2_init_nvram(struct bnx2
*bp
)
2369 int j
, entry_count
, rc
;
2370 struct flash_spec
*flash
;
2372 /* Determine the selected interface. */
2373 val
= REG_RD(bp
, BNX2_NVM_CFG1
);
2375 entry_count
= sizeof(flash_table
) / sizeof(struct flash_spec
);
2378 if (val
& 0x40000000) {
2380 /* Flash interface has been reconfigured */
2381 for (j
= 0, flash
= &flash_table
[0]; j
< entry_count
;
2384 if (val
== flash
->config1
) {
2385 bp
->flash_info
= flash
;
2391 /* Not yet been reconfigured */
2393 for (j
= 0, flash
= &flash_table
[0]; j
< entry_count
;
2396 if ((val
& FLASH_STRAP_MASK
) == flash
->strapping
) {
2397 bp
->flash_info
= flash
;
2399 /* Request access to the flash interface. */
2400 if ((rc
= bnx2_acquire_nvram_lock(bp
)) != 0)
2403 /* Enable access to flash interface */
2404 bnx2_enable_nvram_access(bp
);
2406 /* Reconfigure the flash interface */
2407 REG_WR(bp
, BNX2_NVM_CFG1
, flash
->config1
);
2408 REG_WR(bp
, BNX2_NVM_CFG2
, flash
->config2
);
2409 REG_WR(bp
, BNX2_NVM_CFG3
, flash
->config3
);
2410 REG_WR(bp
, BNX2_NVM_WRITE1
, flash
->write1
);
2412 /* Disable access to flash interface */
2413 bnx2_disable_nvram_access(bp
);
2414 bnx2_release_nvram_lock(bp
);
2419 } /* if (val & 0x40000000) */
2421 if (j
== entry_count
) {
2422 bp
->flash_info
= NULL
;
2423 printk(KERN_ALERT
"Unknown flash/EEPROM type.\n");
2431 bnx2_nvram_read(struct bnx2
*bp
, u32 offset
, u8
*ret_buf
,
2435 u32 cmd_flags
, offset32
, len32
, extra
;
2440 /* Request access to the flash interface. */
2441 if ((rc
= bnx2_acquire_nvram_lock(bp
)) != 0)
2444 /* Enable access to flash interface */
2445 bnx2_enable_nvram_access(bp
);
2458 pre_len
= 4 - (offset
& 3);
2460 if (pre_len
>= len32
) {
2462 cmd_flags
= BNX2_NVM_COMMAND_FIRST
|
2463 BNX2_NVM_COMMAND_LAST
;
2466 cmd_flags
= BNX2_NVM_COMMAND_FIRST
;
2469 rc
= bnx2_nvram_read_dword(bp
, offset32
, buf
, cmd_flags
);
2474 memcpy(ret_buf
, buf
+ (offset
& 3), pre_len
);
2481 extra
= 4 - (len32
& 3);
2482 len32
= (len32
+ 4) & ~3;
2489 cmd_flags
= BNX2_NVM_COMMAND_LAST
;
2491 cmd_flags
= BNX2_NVM_COMMAND_FIRST
|
2492 BNX2_NVM_COMMAND_LAST
;
2494 rc
= bnx2_nvram_read_dword(bp
, offset32
, buf
, cmd_flags
);
2496 memcpy(ret_buf
, buf
, 4 - extra
);
2498 else if (len32
> 0) {
2501 /* Read the first word. */
2505 cmd_flags
= BNX2_NVM_COMMAND_FIRST
;
2507 rc
= bnx2_nvram_read_dword(bp
, offset32
, ret_buf
, cmd_flags
);
2509 /* Advance to the next dword. */
2514 while (len32
> 4 && rc
== 0) {
2515 rc
= bnx2_nvram_read_dword(bp
, offset32
, ret_buf
, 0);
2517 /* Advance to the next dword. */
2526 cmd_flags
= BNX2_NVM_COMMAND_LAST
;
2527 rc
= bnx2_nvram_read_dword(bp
, offset32
, buf
, cmd_flags
);
2529 memcpy(ret_buf
, buf
, 4 - extra
);
2532 /* Disable access to flash interface */
2533 bnx2_disable_nvram_access(bp
);
2535 bnx2_release_nvram_lock(bp
);
2541 bnx2_nvram_write(struct bnx2
*bp
, u32 offset
, u8
*data_buf
,
2544 u32 written
, offset32
, len32
;
2545 u8
*buf
, start
[4], end
[4];
2547 int align_start
, align_end
;
2552 align_start
= align_end
= 0;
2554 if ((align_start
= (offset32
& 3))) {
2556 len32
+= align_start
;
2557 if ((rc
= bnx2_nvram_read(bp
, offset32
, start
, 4)))
2562 if ((len32
> 4) || !align_start
) {
2563 align_end
= 4 - (len32
& 3);
2565 if ((rc
= bnx2_nvram_read(bp
, offset32
+ len32
- 4,
2572 if (align_start
|| align_end
) {
2573 buf
= kmalloc(len32
, GFP_KERNEL
);
2577 memcpy(buf
, start
, 4);
2580 memcpy(buf
+ len32
- 4, end
, 4);
2582 memcpy(buf
+ align_start
, data_buf
, buf_size
);
2586 while ((written
< len32
) && (rc
== 0)) {
2587 u32 page_start
, page_end
, data_start
, data_end
;
2588 u32 addr
, cmd_flags
;
2590 u8 flash_buffer
[264];
2592 /* Find the page_start addr */
2593 page_start
= offset32
+ written
;
2594 page_start
-= (page_start
% bp
->flash_info
->page_size
);
2595 /* Find the page_end addr */
2596 page_end
= page_start
+ bp
->flash_info
->page_size
;
2597 /* Find the data_start addr */
2598 data_start
= (written
== 0) ? offset32
: page_start
;
2599 /* Find the data_end addr */
2600 data_end
= (page_end
> offset32
+ len32
) ?
2601 (offset32
+ len32
) : page_end
;
2603 /* Request access to the flash interface. */
2604 if ((rc
= bnx2_acquire_nvram_lock(bp
)) != 0)
2605 goto nvram_write_end
;
2607 /* Enable access to flash interface */
2608 bnx2_enable_nvram_access(bp
);
2610 cmd_flags
= BNX2_NVM_COMMAND_FIRST
;
2611 if (bp
->flash_info
->buffered
== 0) {
2614 /* Read the whole page into the buffer
2615 * (non-buffer flash only) */
2616 for (j
= 0; j
< bp
->flash_info
->page_size
; j
+= 4) {
2617 if (j
== (bp
->flash_info
->page_size
- 4)) {
2618 cmd_flags
|= BNX2_NVM_COMMAND_LAST
;
2620 rc
= bnx2_nvram_read_dword(bp
,
2626 goto nvram_write_end
;
2632 /* Enable writes to flash interface (unlock write-protect) */
2633 if ((rc
= bnx2_enable_nvram_write(bp
)) != 0)
2634 goto nvram_write_end
;
2636 /* Erase the page */
2637 if ((rc
= bnx2_nvram_erase_page(bp
, page_start
)) != 0)
2638 goto nvram_write_end
;
2640 /* Re-enable the write again for the actual write */
2641 bnx2_enable_nvram_write(bp
);
2643 /* Loop to write back the buffer data from page_start to
2646 if (bp
->flash_info
->buffered
== 0) {
2647 for (addr
= page_start
; addr
< data_start
;
2648 addr
+= 4, i
+= 4) {
2650 rc
= bnx2_nvram_write_dword(bp
, addr
,
2651 &flash_buffer
[i
], cmd_flags
);
2654 goto nvram_write_end
;
2660 /* Loop to write the new data from data_start to data_end */
2661 for (addr
= data_start
; addr
< data_end
; addr
+= 4, i
++) {
2662 if ((addr
== page_end
- 4) ||
2663 ((bp
->flash_info
->buffered
) &&
2664 (addr
== data_end
- 4))) {
2666 cmd_flags
|= BNX2_NVM_COMMAND_LAST
;
2668 rc
= bnx2_nvram_write_dword(bp
, addr
, buf
,
2672 goto nvram_write_end
;
2678 /* Loop to write back the buffer data from data_end
2680 if (bp
->flash_info
->buffered
== 0) {
2681 for (addr
= data_end
; addr
< page_end
;
2682 addr
+= 4, i
+= 4) {
2684 if (addr
== page_end
-4) {
2685 cmd_flags
= BNX2_NVM_COMMAND_LAST
;
2687 rc
= bnx2_nvram_write_dword(bp
, addr
,
2688 &flash_buffer
[i
], cmd_flags
);
2691 goto nvram_write_end
;
2697 /* Disable writes to flash interface (lock write-protect) */
2698 bnx2_disable_nvram_write(bp
);
2700 /* Disable access to flash interface */
2701 bnx2_disable_nvram_access(bp
);
2702 bnx2_release_nvram_lock(bp
);
2704 /* Increment written */
2705 written
+= data_end
- data_start
;
2709 if (align_start
|| align_end
)
2715 bnx2_reset_chip(struct bnx2
*bp
, u32 reset_code
)
2720 /* Wait for the current PCI transaction to complete before
2721 * issuing a reset. */
2722 REG_WR(bp
, BNX2_MISC_ENABLE_CLR_BITS
,
2723 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
|
2724 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
|
2725 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
|
2726 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
);
2727 val
= REG_RD(bp
, BNX2_MISC_ENABLE_CLR_BITS
);
2730 /* Deposit a driver reset signature so the firmware knows that
2731 * this is a soft reset. */
2732 REG_WR_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_DRV_RESET_SIGNATURE
,
2733 BNX2_DRV_RESET_SIGNATURE_MAGIC
);
2735 bp
->fw_timed_out
= 0;
2737 /* Wait for the firmware to tell us it is ok to issue a reset. */
2738 bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT0
| reset_code
);
2740 /* Do a dummy read to force the chip to complete all current transaction
2741 * before we issue a reset. */
2742 val
= REG_RD(bp
, BNX2_MISC_ID
);
2744 val
= BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
|
2745 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
|
2746 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
;
2749 REG_WR(bp
, BNX2_PCICFG_MISC_CONFIG
, val
);
2751 if ((CHIP_ID(bp
) == CHIP_ID_5706_A0
) ||
2752 (CHIP_ID(bp
) == CHIP_ID_5706_A1
))
2755 /* Reset takes approximate 30 usec */
2756 for (i
= 0; i
< 10; i
++) {
2757 val
= REG_RD(bp
, BNX2_PCICFG_MISC_CONFIG
);
2758 if ((val
& (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
|
2759 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
)) == 0) {
2765 if (val
& (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
|
2766 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
)) {
2767 printk(KERN_ERR PFX
"Chip reset did not complete\n");
2771 /* Make sure byte swapping is properly configured. */
2772 val
= REG_RD(bp
, BNX2_PCI_SWAP_DIAG0
);
2773 if (val
!= 0x01020304) {
2774 printk(KERN_ERR PFX
"Chip not in correct endian mode\n");
2778 bp
->fw_timed_out
= 0;
2780 /* Wait for the firmware to finish its initialization. */
2781 bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT1
| reset_code
);
2783 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
2784 /* Adjust the voltage regular to two steps lower. The default
2785 * of this register is 0x0000000e. */
2786 REG_WR(bp
, BNX2_MISC_VREG_CONTROL
, 0x000000fa);
2788 /* Remove bad rbuf memory from the free pool. */
2789 rc
= bnx2_alloc_bad_rbuf(bp
);
2796 bnx2_init_chip(struct bnx2
*bp
)
2800 /* Make sure the interrupt is not active. */
2801 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
, BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
2803 val
= BNX2_DMA_CONFIG_DATA_BYTE_SWAP
|
2804 BNX2_DMA_CONFIG_DATA_WORD_SWAP
|
2806 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
|
2808 BNX2_DMA_CONFIG_CNTL_WORD_SWAP
|
2809 DMA_READ_CHANS
<< 12 |
2810 DMA_WRITE_CHANS
<< 16;
2812 val
|= (0x2 << 20) | (1 << 11);
2814 if ((bp
->flags
& PCIX_FLAG
) && (bp
->bus_speed_mhz
= 133))
2817 if ((CHIP_NUM(bp
) == CHIP_NUM_5706
) &&
2818 (CHIP_ID(bp
) != CHIP_ID_5706_A0
) && !(bp
->flags
& PCIX_FLAG
))
2819 val
|= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA
;
2821 REG_WR(bp
, BNX2_DMA_CONFIG
, val
);
2823 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
2824 val
= REG_RD(bp
, BNX2_TDMA_CONFIG
);
2825 val
|= BNX2_TDMA_CONFIG_ONE_DMA
;
2826 REG_WR(bp
, BNX2_TDMA_CONFIG
, val
);
2829 if (bp
->flags
& PCIX_FLAG
) {
2832 pci_read_config_word(bp
->pdev
, bp
->pcix_cap
+ PCI_X_CMD
,
2834 pci_write_config_word(bp
->pdev
, bp
->pcix_cap
+ PCI_X_CMD
,
2835 val16
& ~PCI_X_CMD_ERO
);
2838 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
,
2839 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE
|
2840 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE
|
2841 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE
);
2843 /* Initialize context mapping and zero out the quick contexts. The
2844 * context block must have already been enabled. */
2845 bnx2_init_context(bp
);
2848 bnx2_init_nvram(bp
);
2850 bnx2_set_mac_addr(bp
);
2852 val
= REG_RD(bp
, BNX2_MQ_CONFIG
);
2853 val
&= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
;
2854 val
|= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256
;
2855 REG_WR(bp
, BNX2_MQ_CONFIG
, val
);
2857 val
= 0x10000 + (MAX_CID_CNT
* MB_KERNEL_CTX_SIZE
);
2858 REG_WR(bp
, BNX2_MQ_KNL_BYP_WIND_START
, val
);
2859 REG_WR(bp
, BNX2_MQ_KNL_WIND_END
, val
);
2861 val
= (BCM_PAGE_BITS
- 8) << 24;
2862 REG_WR(bp
, BNX2_RV2P_CONFIG
, val
);
2864 /* Configure page size. */
2865 val
= REG_RD(bp
, BNX2_TBDR_CONFIG
);
2866 val
&= ~BNX2_TBDR_CONFIG_PAGE_SIZE
;
2867 val
|= (BCM_PAGE_BITS
- 8) << 24 | 0x40;
2868 REG_WR(bp
, BNX2_TBDR_CONFIG
, val
);
2870 val
= bp
->mac_addr
[0] +
2871 (bp
->mac_addr
[1] << 8) +
2872 (bp
->mac_addr
[2] << 16) +
2874 (bp
->mac_addr
[4] << 8) +
2875 (bp
->mac_addr
[5] << 16);
2876 REG_WR(bp
, BNX2_EMAC_BACKOFF_SEED
, val
);
2878 /* Program the MTU. Also include 4 bytes for CRC32. */
2879 val
= bp
->dev
->mtu
+ ETH_HLEN
+ 4;
2880 if (val
> (MAX_ETHERNET_PACKET_SIZE
+ 4))
2881 val
|= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
;
2882 REG_WR(bp
, BNX2_EMAC_RX_MTU_SIZE
, val
);
2884 bp
->last_status_idx
= 0;
2885 bp
->rx_mode
= BNX2_EMAC_RX_MODE_SORT_MODE
;
2887 /* Set up how to generate a link change interrupt. */
2888 REG_WR(bp
, BNX2_EMAC_ATTENTION_ENA
, BNX2_EMAC_ATTENTION_ENA_LINK
);
2890 REG_WR(bp
, BNX2_HC_STATUS_ADDR_L
,
2891 (u64
) bp
->status_blk_mapping
& 0xffffffff);
2892 REG_WR(bp
, BNX2_HC_STATUS_ADDR_H
, (u64
) bp
->status_blk_mapping
>> 32);
2894 REG_WR(bp
, BNX2_HC_STATISTICS_ADDR_L
,
2895 (u64
) bp
->stats_blk_mapping
& 0xffffffff);
2896 REG_WR(bp
, BNX2_HC_STATISTICS_ADDR_H
,
2897 (u64
) bp
->stats_blk_mapping
>> 32);
2899 REG_WR(bp
, BNX2_HC_TX_QUICK_CONS_TRIP
,
2900 (bp
->tx_quick_cons_trip_int
<< 16) | bp
->tx_quick_cons_trip
);
2902 REG_WR(bp
, BNX2_HC_RX_QUICK_CONS_TRIP
,
2903 (bp
->rx_quick_cons_trip_int
<< 16) | bp
->rx_quick_cons_trip
);
2905 REG_WR(bp
, BNX2_HC_COMP_PROD_TRIP
,
2906 (bp
->comp_prod_trip_int
<< 16) | bp
->comp_prod_trip
);
2908 REG_WR(bp
, BNX2_HC_TX_TICKS
, (bp
->tx_ticks_int
<< 16) | bp
->tx_ticks
);
2910 REG_WR(bp
, BNX2_HC_RX_TICKS
, (bp
->rx_ticks_int
<< 16) | bp
->rx_ticks
);
2912 REG_WR(bp
, BNX2_HC_COM_TICKS
,
2913 (bp
->com_ticks_int
<< 16) | bp
->com_ticks
);
2915 REG_WR(bp
, BNX2_HC_CMD_TICKS
,
2916 (bp
->cmd_ticks_int
<< 16) | bp
->cmd_ticks
);
2918 REG_WR(bp
, BNX2_HC_STATS_TICKS
, bp
->stats_ticks
& 0xffff00);
2919 REG_WR(bp
, BNX2_HC_STAT_COLLECT_TICKS
, 0xbb8); /* 3ms */
2921 if (CHIP_ID(bp
) == CHIP_ID_5706_A1
)
2922 REG_WR(bp
, BNX2_HC_CONFIG
, BNX2_HC_CONFIG_COLLECT_STATS
);
2924 REG_WR(bp
, BNX2_HC_CONFIG
, BNX2_HC_CONFIG_RX_TMR_MODE
|
2925 BNX2_HC_CONFIG_TX_TMR_MODE
|
2926 BNX2_HC_CONFIG_COLLECT_STATS
);
2929 /* Clear internal stats counters. */
2930 REG_WR(bp
, BNX2_HC_COMMAND
, BNX2_HC_COMMAND_CLR_STAT_NOW
);
2932 REG_WR(bp
, BNX2_HC_ATTN_BITS_ENABLE
, STATUS_ATTN_BITS_LINK_STATE
);
2934 /* Initialize the receive filter. */
2935 bnx2_set_rx_mode(bp
->dev
);
2937 bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT2
| BNX2_DRV_MSG_CODE_RESET
);
2939 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
, 0x5ffffff);
2940 REG_RD(bp
, BNX2_MISC_ENABLE_SET_BITS
);
2949 bnx2_init_tx_ring(struct bnx2
*bp
)
2954 txbd
= &bp
->tx_desc_ring
[MAX_TX_DESC_CNT
];
2956 txbd
->tx_bd_haddr_hi
= (u64
) bp
->tx_desc_mapping
>> 32;
2957 txbd
->tx_bd_haddr_lo
= (u64
) bp
->tx_desc_mapping
& 0xffffffff;
2961 bp
->tx_prod_bseq
= 0;
2962 atomic_set(&bp
->tx_avail_bd
, bp
->tx_ring_size
);
2964 val
= BNX2_L2CTX_TYPE_TYPE_L2
;
2965 val
|= BNX2_L2CTX_TYPE_SIZE_L2
;
2966 CTX_WR(bp
, GET_CID_ADDR(TX_CID
), BNX2_L2CTX_TYPE
, val
);
2968 val
= BNX2_L2CTX_CMD_TYPE_TYPE_L2
;
2970 CTX_WR(bp
, GET_CID_ADDR(TX_CID
), BNX2_L2CTX_CMD_TYPE
, val
);
2972 val
= (u64
) bp
->tx_desc_mapping
>> 32;
2973 CTX_WR(bp
, GET_CID_ADDR(TX_CID
), BNX2_L2CTX_TBDR_BHADDR_HI
, val
);
2975 val
= (u64
) bp
->tx_desc_mapping
& 0xffffffff;
2976 CTX_WR(bp
, GET_CID_ADDR(TX_CID
), BNX2_L2CTX_TBDR_BHADDR_LO
, val
);
2980 bnx2_init_rx_ring(struct bnx2
*bp
)
2984 u16 prod
, ring_prod
;
2987 /* 8 for CRC and VLAN */
2988 bp
->rx_buf_use_size
= bp
->dev
->mtu
+ ETH_HLEN
+ bp
->rx_offset
+ 8;
2989 /* 8 for alignment */
2990 bp
->rx_buf_size
= bp
->rx_buf_use_size
+ 8;
2992 ring_prod
= prod
= bp
->rx_prod
= 0;
2994 bp
->rx_prod_bseq
= 0;
2996 rxbd
= &bp
->rx_desc_ring
[0];
2997 for (i
= 0; i
< MAX_RX_DESC_CNT
; i
++, rxbd
++) {
2998 rxbd
->rx_bd_len
= bp
->rx_buf_use_size
;
2999 rxbd
->rx_bd_flags
= RX_BD_FLAGS_START
| RX_BD_FLAGS_END
;
3002 rxbd
->rx_bd_haddr_hi
= (u64
) bp
->rx_desc_mapping
>> 32;
3003 rxbd
->rx_bd_haddr_lo
= (u64
) bp
->rx_desc_mapping
& 0xffffffff;
3005 val
= BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE
;
3006 val
|= BNX2_L2CTX_CTX_TYPE_SIZE_L2
;
3008 CTX_WR(bp
, GET_CID_ADDR(RX_CID
), BNX2_L2CTX_CTX_TYPE
, val
);
3010 val
= (u64
) bp
->rx_desc_mapping
>> 32;
3011 CTX_WR(bp
, GET_CID_ADDR(RX_CID
), BNX2_L2CTX_NX_BDHADDR_HI
, val
);
3013 val
= (u64
) bp
->rx_desc_mapping
& 0xffffffff;
3014 CTX_WR(bp
, GET_CID_ADDR(RX_CID
), BNX2_L2CTX_NX_BDHADDR_LO
, val
);
3016 for ( ;ring_prod
< bp
->rx_ring_size
; ) {
3017 if (bnx2_alloc_rx_skb(bp
, ring_prod
) < 0) {
3020 prod
= NEXT_RX_BD(prod
);
3021 ring_prod
= RX_RING_IDX(prod
);
3025 REG_WR16(bp
, MB_RX_CID_ADDR
+ BNX2_L2CTX_HOST_BDIDX
, prod
);
3027 REG_WR(bp
, MB_RX_CID_ADDR
+ BNX2_L2CTX_HOST_BSEQ
, bp
->rx_prod_bseq
);
3031 bnx2_free_tx_skbs(struct bnx2
*bp
)
3035 if (bp
->tx_buf_ring
== NULL
)
3038 for (i
= 0; i
< TX_DESC_CNT
; ) {
3039 struct sw_bd
*tx_buf
= &bp
->tx_buf_ring
[i
];
3040 struct sk_buff
*skb
= tx_buf
->skb
;
3048 pci_unmap_single(bp
->pdev
, pci_unmap_addr(tx_buf
, mapping
),
3049 skb_headlen(skb
), PCI_DMA_TODEVICE
);
3053 last
= skb_shinfo(skb
)->nr_frags
;
3054 for (j
= 0; j
< last
; j
++) {
3055 tx_buf
= &bp
->tx_buf_ring
[i
+ j
+ 1];
3056 pci_unmap_page(bp
->pdev
,
3057 pci_unmap_addr(tx_buf
, mapping
),
3058 skb_shinfo(skb
)->frags
[j
].size
,
3061 dev_kfree_skb_any(skb
);
3068 bnx2_free_rx_skbs(struct bnx2
*bp
)
3072 if (bp
->rx_buf_ring
== NULL
)
3075 for (i
= 0; i
< RX_DESC_CNT
; i
++) {
3076 struct sw_bd
*rx_buf
= &bp
->rx_buf_ring
[i
];
3077 struct sk_buff
*skb
= rx_buf
->skb
;
3082 pci_unmap_single(bp
->pdev
, pci_unmap_addr(rx_buf
, mapping
),
3083 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
3087 dev_kfree_skb_any(skb
);
3092 bnx2_free_skbs(struct bnx2
*bp
)
3094 bnx2_free_tx_skbs(bp
);
3095 bnx2_free_rx_skbs(bp
);
3099 bnx2_reset_nic(struct bnx2
*bp
, u32 reset_code
)
3103 rc
= bnx2_reset_chip(bp
, reset_code
);
3109 bnx2_init_tx_ring(bp
);
3110 bnx2_init_rx_ring(bp
);
3115 bnx2_init_nic(struct bnx2
*bp
)
3119 if ((rc
= bnx2_reset_nic(bp
, BNX2_DRV_MSG_CODE_RESET
)) != 0)
3128 bnx2_test_registers(struct bnx2
*bp
)
3138 { 0x006c, 0, 0x00000000, 0x0000003f },
3139 { 0x0090, 0, 0xffffffff, 0x00000000 },
3140 { 0x0094, 0, 0x00000000, 0x00000000 },
3142 { 0x0404, 0, 0x00003f00, 0x00000000 },
3143 { 0x0418, 0, 0x00000000, 0xffffffff },
3144 { 0x041c, 0, 0x00000000, 0xffffffff },
3145 { 0x0420, 0, 0x00000000, 0x80ffffff },
3146 { 0x0424, 0, 0x00000000, 0x00000000 },
3147 { 0x0428, 0, 0x00000000, 0x00000001 },
3148 { 0x0450, 0, 0x00000000, 0x0000ffff },
3149 { 0x0454, 0, 0x00000000, 0xffffffff },
3150 { 0x0458, 0, 0x00000000, 0xffffffff },
3152 { 0x0808, 0, 0x00000000, 0xffffffff },
3153 { 0x0854, 0, 0x00000000, 0xffffffff },
3154 { 0x0868, 0, 0x00000000, 0x77777777 },
3155 { 0x086c, 0, 0x00000000, 0x77777777 },
3156 { 0x0870, 0, 0x00000000, 0x77777777 },
3157 { 0x0874, 0, 0x00000000, 0x77777777 },
3159 { 0x0c00, 0, 0x00000000, 0x00000001 },
3160 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3161 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3162 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3163 { 0x0c30, 0, 0x00000000, 0xffffffff },
3164 { 0x0c34, 0, 0x00000000, 0xffffffff },
3165 { 0x0c38, 0, 0x00000000, 0xffffffff },
3166 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3167 { 0x0c40, 0, 0x00000000, 0xffffffff },
3168 { 0x0c44, 0, 0x00000000, 0xffffffff },
3169 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3170 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3171 { 0x0c50, 0, 0x00000000, 0xffffffff },
3172 { 0x0c54, 0, 0x00000000, 0xffffffff },
3173 { 0x0c58, 0, 0x00000000, 0xffffffff },
3174 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3175 { 0x0c60, 0, 0x00000000, 0xffffffff },
3176 { 0x0c64, 0, 0x00000000, 0xffffffff },
3177 { 0x0c68, 0, 0x00000000, 0xffffffff },
3178 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3179 { 0x0c70, 0, 0x00000000, 0xffffffff },
3180 { 0x0c74, 0, 0x00000000, 0xffffffff },
3181 { 0x0c78, 0, 0x00000000, 0xffffffff },
3182 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3183 { 0x0c80, 0, 0x00000000, 0xffffffff },
3184 { 0x0c84, 0, 0x00000000, 0xffffffff },
3185 { 0x0c88, 0, 0x00000000, 0xffffffff },
3186 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3187 { 0x0c90, 0, 0x00000000, 0xffffffff },
3188 { 0x0c94, 0, 0x00000000, 0xffffffff },
3189 { 0x0c98, 0, 0x00000000, 0xffffffff },
3190 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3191 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3192 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3193 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3194 { 0x0cac, 0, 0x00000000, 0xffffffff },
3195 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3196 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3197 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3198 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3199 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3200 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3201 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3202 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3203 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3204 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3205 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3206 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3207 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3208 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3209 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3210 { 0x0cec, 0, 0x00000000, 0xffffffff },
3211 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3212 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3213 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3214 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3215 { 0x0d00, 0, 0x00000000, 0xffffffff },
3216 { 0x0d04, 0, 0x00000000, 0xffffffff },
3218 { 0x1000, 0, 0x00000000, 0x00000001 },
3219 { 0x1004, 0, 0x00000000, 0x000f0001 },
3220 { 0x1044, 0, 0x00000000, 0xffc003ff },
3221 { 0x1080, 0, 0x00000000, 0x0001ffff },
3222 { 0x1084, 0, 0x00000000, 0xffffffff },
3223 { 0x1088, 0, 0x00000000, 0xffffffff },
3224 { 0x108c, 0, 0x00000000, 0xffffffff },
3225 { 0x1090, 0, 0x00000000, 0xffffffff },
3226 { 0x1094, 0, 0x00000000, 0xffffffff },
3227 { 0x1098, 0, 0x00000000, 0xffffffff },
3228 { 0x109c, 0, 0x00000000, 0xffffffff },
3229 { 0x10a0, 0, 0x00000000, 0xffffffff },
3231 { 0x1408, 0, 0x01c00800, 0x00000000 },
3232 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3233 { 0x14a8, 0, 0x00000000, 0x000001ff },
3234 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3235 { 0x14b0, 0, 0x00000002, 0x00000001 },
3236 { 0x14b8, 0, 0x00000000, 0x00000000 },
3237 { 0x14c0, 0, 0x00000000, 0x00000009 },
3238 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3239 { 0x14cc, 0, 0x00000000, 0x00000001 },
3240 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3241 { 0x1500, 0, 0x00000000, 0xffffffff },
3242 { 0x1504, 0, 0x00000000, 0xffffffff },
3243 { 0x1508, 0, 0x00000000, 0xffffffff },
3244 { 0x150c, 0, 0x00000000, 0xffffffff },
3245 { 0x1510, 0, 0x00000000, 0xffffffff },
3246 { 0x1514, 0, 0x00000000, 0xffffffff },
3247 { 0x1518, 0, 0x00000000, 0xffffffff },
3248 { 0x151c, 0, 0x00000000, 0xffffffff },
3249 { 0x1520, 0, 0x00000000, 0xffffffff },
3250 { 0x1524, 0, 0x00000000, 0xffffffff },
3251 { 0x1528, 0, 0x00000000, 0xffffffff },
3252 { 0x152c, 0, 0x00000000, 0xffffffff },
3253 { 0x1530, 0, 0x00000000, 0xffffffff },
3254 { 0x1534, 0, 0x00000000, 0xffffffff },
3255 { 0x1538, 0, 0x00000000, 0xffffffff },
3256 { 0x153c, 0, 0x00000000, 0xffffffff },
3257 { 0x1540, 0, 0x00000000, 0xffffffff },
3258 { 0x1544, 0, 0x00000000, 0xffffffff },
3259 { 0x1548, 0, 0x00000000, 0xffffffff },
3260 { 0x154c, 0, 0x00000000, 0xffffffff },
3261 { 0x1550, 0, 0x00000000, 0xffffffff },
3262 { 0x1554, 0, 0x00000000, 0xffffffff },
3263 { 0x1558, 0, 0x00000000, 0xffffffff },
3264 { 0x1600, 0, 0x00000000, 0xffffffff },
3265 { 0x1604, 0, 0x00000000, 0xffffffff },
3266 { 0x1608, 0, 0x00000000, 0xffffffff },
3267 { 0x160c, 0, 0x00000000, 0xffffffff },
3268 { 0x1610, 0, 0x00000000, 0xffffffff },
3269 { 0x1614, 0, 0x00000000, 0xffffffff },
3270 { 0x1618, 0, 0x00000000, 0xffffffff },
3271 { 0x161c, 0, 0x00000000, 0xffffffff },
3272 { 0x1620, 0, 0x00000000, 0xffffffff },
3273 { 0x1624, 0, 0x00000000, 0xffffffff },
3274 { 0x1628, 0, 0x00000000, 0xffffffff },
3275 { 0x162c, 0, 0x00000000, 0xffffffff },
3276 { 0x1630, 0, 0x00000000, 0xffffffff },
3277 { 0x1634, 0, 0x00000000, 0xffffffff },
3278 { 0x1638, 0, 0x00000000, 0xffffffff },
3279 { 0x163c, 0, 0x00000000, 0xffffffff },
3280 { 0x1640, 0, 0x00000000, 0xffffffff },
3281 { 0x1644, 0, 0x00000000, 0xffffffff },
3282 { 0x1648, 0, 0x00000000, 0xffffffff },
3283 { 0x164c, 0, 0x00000000, 0xffffffff },
3284 { 0x1650, 0, 0x00000000, 0xffffffff },
3285 { 0x1654, 0, 0x00000000, 0xffffffff },
3287 { 0x1800, 0, 0x00000000, 0x00000001 },
3288 { 0x1804, 0, 0x00000000, 0x00000003 },
3289 { 0x1840, 0, 0x00000000, 0xffffffff },
3290 { 0x1844, 0, 0x00000000, 0xffffffff },
3291 { 0x1848, 0, 0x00000000, 0xffffffff },
3292 { 0x184c, 0, 0x00000000, 0xffffffff },
3293 { 0x1850, 0, 0x00000000, 0xffffffff },
3294 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3295 { 0x1904, 0, 0xffffffff, 0x00000000 },
3296 { 0x190c, 0, 0xffffffff, 0x00000000 },
3297 { 0x1914, 0, 0xffffffff, 0x00000000 },
3298 { 0x191c, 0, 0xffffffff, 0x00000000 },
3299 { 0x1924, 0, 0xffffffff, 0x00000000 },
3300 { 0x192c, 0, 0xffffffff, 0x00000000 },
3301 { 0x1934, 0, 0xffffffff, 0x00000000 },
3302 { 0x193c, 0, 0xffffffff, 0x00000000 },
3303 { 0x1944, 0, 0xffffffff, 0x00000000 },
3304 { 0x194c, 0, 0xffffffff, 0x00000000 },
3305 { 0x1954, 0, 0xffffffff, 0x00000000 },
3306 { 0x195c, 0, 0xffffffff, 0x00000000 },
3307 { 0x1964, 0, 0xffffffff, 0x00000000 },
3308 { 0x196c, 0, 0xffffffff, 0x00000000 },
3309 { 0x1974, 0, 0xffffffff, 0x00000000 },
3310 { 0x197c, 0, 0xffffffff, 0x00000000 },
3311 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3313 { 0x1c00, 0, 0x00000000, 0x00000001 },
3314 { 0x1c04, 0, 0x00000000, 0x00000003 },
3315 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3316 { 0x1c40, 0, 0x00000000, 0xffffffff },
3317 { 0x1c44, 0, 0x00000000, 0xffffffff },
3318 { 0x1c48, 0, 0x00000000, 0xffffffff },
3319 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3320 { 0x1c50, 0, 0x00000000, 0xffffffff },
3321 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3322 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3323 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3324 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3325 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3326 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3327 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3328 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3329 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3330 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3331 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3332 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3333 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3334 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3335 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3336 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3337 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3338 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3340 { 0x2004, 0, 0x00000000, 0x0337000f },
3341 { 0x2008, 0, 0xffffffff, 0x00000000 },
3342 { 0x200c, 0, 0xffffffff, 0x00000000 },
3343 { 0x2010, 0, 0xffffffff, 0x00000000 },
3344 { 0x2014, 0, 0x801fff80, 0x00000000 },
3345 { 0x2018, 0, 0x000003ff, 0x00000000 },
3347 { 0x2800, 0, 0x00000000, 0x00000001 },
3348 { 0x2804, 0, 0x00000000, 0x00003f01 },
3349 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3350 { 0x2810, 0, 0xffff0000, 0x00000000 },
3351 { 0x2814, 0, 0xffff0000, 0x00000000 },
3352 { 0x2818, 0, 0xffff0000, 0x00000000 },
3353 { 0x281c, 0, 0xffff0000, 0x00000000 },
3354 { 0x2834, 0, 0xffffffff, 0x00000000 },
3355 { 0x2840, 0, 0x00000000, 0xffffffff },
3356 { 0x2844, 0, 0x00000000, 0xffffffff },
3357 { 0x2848, 0, 0xffffffff, 0x00000000 },
3358 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3360 { 0x2c00, 0, 0x00000000, 0x00000011 },
3361 { 0x2c04, 0, 0x00000000, 0x00030007 },
3363 { 0x3000, 0, 0x00000000, 0x00000001 },
3364 { 0x3004, 0, 0x00000000, 0x007007ff },
3365 { 0x3008, 0, 0x00000003, 0x00000000 },
3366 { 0x300c, 0, 0xffffffff, 0x00000000 },
3367 { 0x3010, 0, 0xffffffff, 0x00000000 },
3368 { 0x3014, 0, 0xffffffff, 0x00000000 },
3369 { 0x3034, 0, 0xffffffff, 0x00000000 },
3370 { 0x3038, 0, 0xffffffff, 0x00000000 },
3371 { 0x3050, 0, 0x00000001, 0x00000000 },
3373 { 0x3c00, 0, 0x00000000, 0x00000001 },
3374 { 0x3c04, 0, 0x00000000, 0x00070000 },
3375 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3376 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3377 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3378 { 0x3c14, 0, 0x00000000, 0xffffffff },
3379 { 0x3c18, 0, 0x00000000, 0xffffffff },
3380 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3381 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3382 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3383 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3384 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3385 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3386 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3387 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3388 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3389 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3390 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3391 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3392 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3393 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3394 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3395 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3396 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3397 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3398 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3399 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3400 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3401 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3402 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3403 { 0x3c78, 0, 0x00000000, 0x00000000 },
3404 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3405 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3406 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3407 { 0x3c88, 0, 0x00000000, 0xffffffff },
3408 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3410 { 0x4000, 0, 0x00000000, 0x00000001 },
3411 { 0x4004, 0, 0x00000000, 0x00030000 },
3412 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3413 { 0x400c, 0, 0xffffffff, 0x00000000 },
3414 { 0x4088, 0, 0x00000000, 0x00070303 },
3416 { 0x4400, 0, 0x00000000, 0x00000001 },
3417 { 0x4404, 0, 0x00000000, 0x00003f01 },
3418 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3419 { 0x440c, 0, 0xffffffff, 0x00000000 },
3420 { 0x4410, 0, 0xffff, 0x0000 },
3421 { 0x4414, 0, 0xffff, 0x0000 },
3422 { 0x4418, 0, 0xffff, 0x0000 },
3423 { 0x441c, 0, 0xffff, 0x0000 },
3424 { 0x4428, 0, 0xffffffff, 0x00000000 },
3425 { 0x442c, 0, 0xffffffff, 0x00000000 },
3426 { 0x4430, 0, 0xffffffff, 0x00000000 },
3427 { 0x4434, 0, 0xffffffff, 0x00000000 },
3428 { 0x4438, 0, 0xffffffff, 0x00000000 },
3429 { 0x443c, 0, 0xffffffff, 0x00000000 },
3430 { 0x4440, 0, 0xffffffff, 0x00000000 },
3431 { 0x4444, 0, 0xffffffff, 0x00000000 },
3433 { 0x4c00, 0, 0x00000000, 0x00000001 },
3434 { 0x4c04, 0, 0x00000000, 0x0000003f },
3435 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3436 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3437 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3438 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3439 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3440 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3441 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3442 { 0x4c50, 0, 0x00000000, 0xffffffff },
3444 { 0x5004, 0, 0x00000000, 0x0000007f },
3445 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3446 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3448 { 0x5400, 0, 0x00000008, 0x00000001 },
3449 { 0x5404, 0, 0x00000000, 0x0000003f },
3450 { 0x5408, 0, 0x0000001f, 0x00000000 },
3451 { 0x540c, 0, 0xffffffff, 0x00000000 },
3452 { 0x5410, 0, 0xffffffff, 0x00000000 },
3453 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3454 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3455 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3456 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3457 { 0x5428, 0, 0x000000ff, 0x00000000 },
3458 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3459 { 0x5430, 0, 0x001fff80, 0x00000000 },
3460 { 0x5438, 0, 0xffffffff, 0x00000000 },
3461 { 0x543c, 0, 0xffffffff, 0x00000000 },
3462 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3464 { 0x5c00, 0, 0x00000000, 0x00000001 },
3465 { 0x5c04, 0, 0x00000000, 0x0003000f },
3466 { 0x5c08, 0, 0x00000003, 0x00000000 },
3467 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3468 { 0x5c10, 0, 0x00000000, 0xffffffff },
3469 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3470 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3471 { 0x5c88, 0, 0x00000000, 0x00077373 },
3472 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3474 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3475 { 0x680c, 0, 0xffffffff, 0x00000000 },
3476 { 0x6810, 0, 0xffffffff, 0x00000000 },
3477 { 0x6814, 0, 0xffffffff, 0x00000000 },
3478 { 0x6818, 0, 0xffffffff, 0x00000000 },
3479 { 0x681c, 0, 0xffffffff, 0x00000000 },
3480 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3481 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3482 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3483 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3484 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3485 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3486 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3487 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3488 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3489 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3490 { 0x684c, 0, 0xffffffff, 0x00000000 },
3491 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3492 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3493 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3494 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3495 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3496 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3498 { 0xffff, 0, 0x00000000, 0x00000000 },
3502 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
3503 u32 offset
, rw_mask
, ro_mask
, save_val
, val
;
3505 offset
= (u32
) reg_tbl
[i
].offset
;
3506 rw_mask
= reg_tbl
[i
].rw_mask
;
3507 ro_mask
= reg_tbl
[i
].ro_mask
;
3509 save_val
= readl(bp
->regview
+ offset
);
3511 writel(0, bp
->regview
+ offset
);
3513 val
= readl(bp
->regview
+ offset
);
3514 if ((val
& rw_mask
) != 0) {
3518 if ((val
& ro_mask
) != (save_val
& ro_mask
)) {
3522 writel(0xffffffff, bp
->regview
+ offset
);
3524 val
= readl(bp
->regview
+ offset
);
3525 if ((val
& rw_mask
) != rw_mask
) {
3529 if ((val
& ro_mask
) != (save_val
& ro_mask
)) {
3533 writel(save_val
, bp
->regview
+ offset
);
3537 writel(save_val
, bp
->regview
+ offset
);
3545 bnx2_do_mem_test(struct bnx2
*bp
, u32 start
, u32 size
)
3547 static u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0x55555555,
3548 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3551 for (i
= 0; i
< sizeof(test_pattern
) / 4; i
++) {
3554 for (offset
= 0; offset
< size
; offset
+= 4) {
3556 REG_WR_IND(bp
, start
+ offset
, test_pattern
[i
]);
3558 if (REG_RD_IND(bp
, start
+ offset
) !=
3568 bnx2_test_memory(struct bnx2
*bp
)
3576 { 0x60000, 0x4000 },
3577 { 0xa0000, 0x4000 },
3578 { 0xe0000, 0x4000 },
3579 { 0x120000, 0x4000 },
3580 { 0x1a0000, 0x4000 },
3581 { 0x160000, 0x4000 },
3585 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
3586 if ((ret
= bnx2_do_mem_test(bp
, mem_tbl
[i
].offset
,
3587 mem_tbl
[i
].len
)) != 0) {
3596 bnx2_test_loopback(struct bnx2
*bp
)
3598 unsigned int pkt_size
, num_pkts
, i
;
3599 struct sk_buff
*skb
, *rx_skb
;
3600 unsigned char *packet
;
3601 u16 rx_start_idx
, rx_idx
, send_idx
;
3605 struct sw_bd
*rx_buf
;
3606 struct l2_fhdr
*rx_hdr
;
3609 if (!netif_running(bp
->dev
))
3612 bp
->loopback
= MAC_LOOPBACK
;
3613 bnx2_reset_nic(bp
, BNX2_DRV_MSG_CODE_DIAG
);
3614 bnx2_set_mac_loopback(bp
);
3617 skb
= dev_alloc_skb(pkt_size
);
3618 packet
= skb_put(skb
, pkt_size
);
3619 memcpy(packet
, bp
->mac_addr
, 6);
3620 memset(packet
+ 6, 0x0, 8);
3621 for (i
= 14; i
< pkt_size
; i
++)
3622 packet
[i
] = (unsigned char) (i
& 0xff);
3624 map
= pci_map_single(bp
->pdev
, skb
->data
, pkt_size
,
3627 val
= REG_RD(bp
, BNX2_HC_COMMAND
);
3628 REG_WR(bp
, BNX2_HC_COMMAND
, val
| BNX2_HC_COMMAND_COAL_NOW_WO_INT
);
3629 REG_RD(bp
, BNX2_HC_COMMAND
);
3632 rx_start_idx
= bp
->status_blk
->status_rx_quick_consumer_index0
;
3638 txbd
= &bp
->tx_desc_ring
[send_idx
];
3640 txbd
->tx_bd_haddr_hi
= (u64
) map
>> 32;
3641 txbd
->tx_bd_haddr_lo
= (u64
) map
& 0xffffffff;
3642 txbd
->tx_bd_mss_nbytes
= pkt_size
;
3643 txbd
->tx_bd_vlan_tag_flags
= TX_BD_FLAGS_START
| TX_BD_FLAGS_END
;
3646 send_idx
= NEXT_TX_BD(send_idx
);
3648 send_bseq
+= pkt_size
;
3650 REG_WR16(bp
, MB_TX_CID_ADDR
+ BNX2_L2CTX_TX_HOST_BIDX
, send_idx
);
3651 REG_WR(bp
, MB_TX_CID_ADDR
+ BNX2_L2CTX_TX_HOST_BSEQ
, send_bseq
);
3656 val
= REG_RD(bp
, BNX2_HC_COMMAND
);
3657 REG_WR(bp
, BNX2_HC_COMMAND
, val
| BNX2_HC_COMMAND_COAL_NOW_WO_INT
);
3658 REG_RD(bp
, BNX2_HC_COMMAND
);
3662 pci_unmap_single(bp
->pdev
, map
, pkt_size
, PCI_DMA_TODEVICE
);
3663 dev_kfree_skb_irq(skb
);
3665 if (bp
->status_blk
->status_tx_quick_consumer_index0
!= send_idx
) {
3666 goto loopback_test_done
;
3669 rx_idx
= bp
->status_blk
->status_rx_quick_consumer_index0
;
3670 if (rx_idx
!= rx_start_idx
+ num_pkts
) {
3671 goto loopback_test_done
;
3674 rx_buf
= &bp
->rx_buf_ring
[rx_start_idx
];
3675 rx_skb
= rx_buf
->skb
;
3677 rx_hdr
= (struct l2_fhdr
*) rx_skb
->data
;
3678 skb_reserve(rx_skb
, bp
->rx_offset
);
3680 pci_dma_sync_single_for_cpu(bp
->pdev
,
3681 pci_unmap_addr(rx_buf
, mapping
),
3682 bp
->rx_buf_size
, PCI_DMA_FROMDEVICE
);
3684 if (rx_hdr
->l2_fhdr_errors
&
3685 (L2_FHDR_ERRORS_BAD_CRC
|
3686 L2_FHDR_ERRORS_PHY_DECODE
|
3687 L2_FHDR_ERRORS_ALIGNMENT
|
3688 L2_FHDR_ERRORS_TOO_SHORT
|
3689 L2_FHDR_ERRORS_GIANT_FRAME
)) {
3691 goto loopback_test_done
;
3694 if ((rx_hdr
->l2_fhdr_pkt_len
- 4) != pkt_size
) {
3695 goto loopback_test_done
;
3698 for (i
= 14; i
< pkt_size
; i
++) {
3699 if (*(rx_skb
->data
+ i
) != (unsigned char) (i
& 0xff)) {
3700 goto loopback_test_done
;
3711 #define NVRAM_SIZE 0x200
3712 #define CRC32_RESIDUAL 0xdebb20e3
3715 bnx2_test_nvram(struct bnx2
*bp
)
3717 u32 buf
[NVRAM_SIZE
/ 4];
3718 u8
*data
= (u8
*) buf
;
3722 if ((rc
= bnx2_nvram_read(bp
, 0, data
, 4)) != 0)
3723 goto test_nvram_done
;
3725 magic
= be32_to_cpu(buf
[0]);
3726 if (magic
!= 0x669955aa) {
3728 goto test_nvram_done
;
3731 if ((rc
= bnx2_nvram_read(bp
, 0x100, data
, NVRAM_SIZE
)) != 0)
3732 goto test_nvram_done
;
3734 csum
= ether_crc_le(0x100, data
);
3735 if (csum
!= CRC32_RESIDUAL
) {
3737 goto test_nvram_done
;
3740 csum
= ether_crc_le(0x100, data
+ 0x100);
3741 if (csum
!= CRC32_RESIDUAL
) {
3750 bnx2_test_link(struct bnx2
*bp
)
3754 spin_lock_irq(&bp
->phy_lock
);
3755 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
3756 bnx2_read_phy(bp
, MII_BMSR
, &bmsr
);
3757 spin_unlock_irq(&bp
->phy_lock
);
3759 if (bmsr
& BMSR_LSTATUS
) {
3766 bnx2_test_intr(struct bnx2
*bp
)
3772 if (!netif_running(bp
->dev
))
3775 status_idx
= REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
) & 0xffff;
3777 /* This register is not touched during run-time. */
3778 val
= REG_RD(bp
, BNX2_HC_COMMAND
);
3779 REG_WR(bp
, BNX2_HC_COMMAND
, val
| BNX2_HC_COMMAND_COAL_NOW
);
3780 REG_RD(bp
, BNX2_HC_COMMAND
);
3782 for (i
= 0; i
< 10; i
++) {
3783 if ((REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
) & 0xffff) !=
3789 msleep_interruptible(10);
3798 bnx2_timer(unsigned long data
)
3800 struct bnx2
*bp
= (struct bnx2
*) data
;
3803 if (atomic_read(&bp
->intr_sem
) != 0)
3804 goto bnx2_restart_timer
;
3806 msg
= (u32
) ++bp
->fw_drv_pulse_wr_seq
;
3807 REG_WR_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_DRV_PULSE_MB
, msg
);
3809 if ((bp
->phy_flags
& PHY_SERDES_FLAG
) &&
3810 (CHIP_NUM(bp
) == CHIP_NUM_5706
)) {
3811 unsigned long flags
;
3813 spin_lock_irqsave(&bp
->phy_lock
, flags
);
3814 if (bp
->serdes_an_pending
) {
3815 bp
->serdes_an_pending
--;
3817 else if ((bp
->link_up
== 0) && (bp
->autoneg
& AUTONEG_SPEED
)) {
3820 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
3822 if (bmcr
& BMCR_ANENABLE
) {
3825 bnx2_write_phy(bp
, 0x1c, 0x7c00);
3826 bnx2_read_phy(bp
, 0x1c, &phy1
);
3828 bnx2_write_phy(bp
, 0x17, 0x0f01);
3829 bnx2_read_phy(bp
, 0x15, &phy2
);
3830 bnx2_write_phy(bp
, 0x17, 0x0f01);
3831 bnx2_read_phy(bp
, 0x15, &phy2
);
3833 if ((phy1
& 0x10) && /* SIGNAL DETECT */
3834 !(phy2
& 0x20)) { /* no CONFIG */
3836 bmcr
&= ~BMCR_ANENABLE
;
3837 bmcr
|= BMCR_SPEED1000
|
3839 bnx2_write_phy(bp
, MII_BMCR
, bmcr
);
3841 PHY_PARALLEL_DETECT_FLAG
;
3845 else if ((bp
->link_up
) && (bp
->autoneg
& AUTONEG_SPEED
) &&
3846 (bp
->phy_flags
& PHY_PARALLEL_DETECT_FLAG
)) {
3849 bnx2_write_phy(bp
, 0x17, 0x0f01);
3850 bnx2_read_phy(bp
, 0x15, &phy2
);
3854 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
3855 bmcr
|= BMCR_ANENABLE
;
3856 bnx2_write_phy(bp
, MII_BMCR
, bmcr
);
3858 bp
->phy_flags
&= ~PHY_PARALLEL_DETECT_FLAG
;
3863 spin_unlock_irqrestore(&bp
->phy_lock
, flags
);
3867 bp
->timer
.expires
= RUN_AT(bp
->timer_interval
);
3869 add_timer(&bp
->timer
);
3872 /* Called with rtnl_lock */
3874 bnx2_open(struct net_device
*dev
)
3876 struct bnx2
*bp
= dev
->priv
;
3879 bnx2_set_power_state(bp
, 0);
3880 bnx2_disable_int(bp
);
3882 rc
= bnx2_alloc_mem(bp
);
3886 if ((CHIP_ID(bp
) != CHIP_ID_5706_A0
) &&
3887 (CHIP_ID(bp
) != CHIP_ID_5706_A1
) &&
3890 if (pci_enable_msi(bp
->pdev
) == 0) {
3891 bp
->flags
|= USING_MSI_FLAG
;
3892 rc
= request_irq(bp
->pdev
->irq
, bnx2_msi
, 0, dev
->name
,
3896 rc
= request_irq(bp
->pdev
->irq
, bnx2_interrupt
,
3897 SA_SHIRQ
, dev
->name
, dev
);
3901 rc
= request_irq(bp
->pdev
->irq
, bnx2_interrupt
, SA_SHIRQ
,
3909 rc
= bnx2_init_nic(bp
);
3912 free_irq(bp
->pdev
->irq
, dev
);
3913 if (bp
->flags
& USING_MSI_FLAG
) {
3914 pci_disable_msi(bp
->pdev
);
3915 bp
->flags
&= ~USING_MSI_FLAG
;
3922 init_timer(&bp
->timer
);
3924 bp
->timer
.expires
= RUN_AT(bp
->timer_interval
);
3925 bp
->timer
.data
= (unsigned long) bp
;
3926 bp
->timer
.function
= bnx2_timer
;
3927 add_timer(&bp
->timer
);
3929 atomic_set(&bp
->intr_sem
, 0);
3931 bnx2_enable_int(bp
);
3933 if (bp
->flags
& USING_MSI_FLAG
) {
3934 /* Test MSI to make sure it is working
3935 * If MSI test fails, go back to INTx mode
3937 if (bnx2_test_intr(bp
) != 0) {
3938 printk(KERN_WARNING PFX
"%s: No interrupt was generated"
3939 " using MSI, switching to INTx mode. Please"
3940 " report this failure to the PCI maintainer"
3941 " and include system chipset information.\n",
3944 bnx2_disable_int(bp
);
3945 free_irq(bp
->pdev
->irq
, dev
);
3946 pci_disable_msi(bp
->pdev
);
3947 bp
->flags
&= ~USING_MSI_FLAG
;
3949 rc
= bnx2_init_nic(bp
);
3952 rc
= request_irq(bp
->pdev
->irq
, bnx2_interrupt
,
3953 SA_SHIRQ
, dev
->name
, dev
);
3958 del_timer_sync(&bp
->timer
);
3961 bnx2_enable_int(bp
);
3964 if (bp
->flags
& USING_MSI_FLAG
) {
3965 printk(KERN_INFO PFX
"%s: using MSI\n", dev
->name
);
3968 netif_start_queue(dev
);
3974 bnx2_reset_task(void *data
)
3976 struct bnx2
*bp
= data
;
3978 if (!netif_running(bp
->dev
))
3981 bp
->in_reset_task
= 1;
3982 bnx2_netif_stop(bp
);
3986 atomic_set(&bp
->intr_sem
, 1);
3987 bnx2_netif_start(bp
);
3988 bp
->in_reset_task
= 0;
3992 bnx2_tx_timeout(struct net_device
*dev
)
3994 struct bnx2
*bp
= dev
->priv
;
3996 /* This allows the netif to be shutdown gracefully before resetting */
3997 schedule_work(&bp
->reset_task
);
4001 /* Called with rtnl_lock */
4003 bnx2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*vlgrp
)
4005 struct bnx2
*bp
= dev
->priv
;
4007 bnx2_netif_stop(bp
);
4010 bnx2_set_rx_mode(dev
);
4012 bnx2_netif_start(bp
);
4015 /* Called with rtnl_lock */
4017 bnx2_vlan_rx_kill_vid(struct net_device
*dev
, uint16_t vid
)
4019 struct bnx2
*bp
= dev
->priv
;
4021 bnx2_netif_stop(bp
);
4024 bp
->vlgrp
->vlan_devices
[vid
] = NULL
;
4025 bnx2_set_rx_mode(dev
);
4027 bnx2_netif_start(bp
);
4031 /* Called with dev->xmit_lock.
4032 * hard_start_xmit is pseudo-lockless - a lock is only required when
4033 * the tx queue is full. This way, we get the benefit of lockless
4034 * operations most of the time without the complexities to handle
4035 * netif_stop_queue/wake_queue race conditions.
4038 bnx2_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
4040 struct bnx2
*bp
= dev
->priv
;
4043 struct sw_bd
*tx_buf
;
4044 u32 len
, vlan_tag_flags
, last_frag
, mss
;
4045 u16 prod
, ring_prod
;
4048 if (unlikely(atomic_read(&bp
->tx_avail_bd
) <
4049 (skb_shinfo(skb
)->nr_frags
+ 1))) {
4051 netif_stop_queue(dev
);
4052 printk(KERN_ERR PFX
"%s: BUG! Tx ring full when queue awake!\n",
4055 return NETDEV_TX_BUSY
;
4057 len
= skb_headlen(skb
);
4059 ring_prod
= TX_RING_IDX(prod
);
4062 if (skb
->ip_summed
== CHECKSUM_HW
) {
4063 vlan_tag_flags
|= TX_BD_FLAGS_TCP_UDP_CKSUM
;
4066 if (bp
->vlgrp
!= 0 && vlan_tx_tag_present(skb
)) {
4068 (TX_BD_FLAGS_VLAN_TAG
| (vlan_tx_tag_get(skb
) << 16));
4071 if ((mss
= skb_shinfo(skb
)->tso_size
) &&
4072 (skb
->len
> (bp
->dev
->mtu
+ ETH_HLEN
))) {
4073 u32 tcp_opt_len
, ip_tcp_len
;
4075 if (skb_header_cloned(skb
) &&
4076 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
4078 return NETDEV_TX_OK
;
4081 tcp_opt_len
= ((skb
->h
.th
->doff
- 5) * 4);
4082 vlan_tag_flags
|= TX_BD_FLAGS_SW_LSO
;
4085 if (skb
->h
.th
->doff
> 5) {
4086 tcp_opt_len
= (skb
->h
.th
->doff
- 5) << 2;
4088 ip_tcp_len
= (skb
->nh
.iph
->ihl
<< 2) + sizeof(struct tcphdr
);
4090 skb
->nh
.iph
->check
= 0;
4091 skb
->nh
.iph
->tot_len
= ntohs(mss
+ ip_tcp_len
+ tcp_opt_len
);
4093 ~csum_tcpudp_magic(skb
->nh
.iph
->saddr
,
4097 if (tcp_opt_len
|| (skb
->nh
.iph
->ihl
> 5)) {
4098 vlan_tag_flags
|= ((skb
->nh
.iph
->ihl
- 5) +
4099 (tcp_opt_len
>> 2)) << 8;
4108 mapping
= pci_map_single(bp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
4110 tx_buf
= &bp
->tx_buf_ring
[ring_prod
];
4112 pci_unmap_addr_set(tx_buf
, mapping
, mapping
);
4114 txbd
= &bp
->tx_desc_ring
[ring_prod
];
4116 txbd
->tx_bd_haddr_hi
= (u64
) mapping
>> 32;
4117 txbd
->tx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
4118 txbd
->tx_bd_mss_nbytes
= len
| (mss
<< 16);
4119 txbd
->tx_bd_vlan_tag_flags
= vlan_tag_flags
| TX_BD_FLAGS_START
;
4121 last_frag
= skb_shinfo(skb
)->nr_frags
;
4123 for (i
= 0; i
< last_frag
; i
++) {
4124 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4126 prod
= NEXT_TX_BD(prod
);
4127 ring_prod
= TX_RING_IDX(prod
);
4128 txbd
= &bp
->tx_desc_ring
[ring_prod
];
4131 mapping
= pci_map_page(bp
->pdev
, frag
->page
, frag
->page_offset
,
4132 len
, PCI_DMA_TODEVICE
);
4133 pci_unmap_addr_set(&bp
->tx_buf_ring
[ring_prod
],
4136 txbd
->tx_bd_haddr_hi
= (u64
) mapping
>> 32;
4137 txbd
->tx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
4138 txbd
->tx_bd_mss_nbytes
= len
| (mss
<< 16);
4139 txbd
->tx_bd_vlan_tag_flags
= vlan_tag_flags
;
4142 txbd
->tx_bd_vlan_tag_flags
|= TX_BD_FLAGS_END
;
4144 prod
= NEXT_TX_BD(prod
);
4145 bp
->tx_prod_bseq
+= skb
->len
;
4147 atomic_sub(last_frag
+ 1, &bp
->tx_avail_bd
);
4149 REG_WR16(bp
, MB_TX_CID_ADDR
+ BNX2_L2CTX_TX_HOST_BIDX
, prod
);
4150 REG_WR(bp
, MB_TX_CID_ADDR
+ BNX2_L2CTX_TX_HOST_BSEQ
, bp
->tx_prod_bseq
);
4155 dev
->trans_start
= jiffies
;
4157 if (unlikely(atomic_read(&bp
->tx_avail_bd
) <= MAX_SKB_FRAGS
)) {
4158 unsigned long flags
;
4160 spin_lock_irqsave(&bp
->tx_lock
, flags
);
4161 if (atomic_read(&bp
->tx_avail_bd
) <= MAX_SKB_FRAGS
) {
4162 netif_stop_queue(dev
);
4164 if (atomic_read(&bp
->tx_avail_bd
) > MAX_SKB_FRAGS
)
4165 netif_wake_queue(dev
);
4167 spin_unlock_irqrestore(&bp
->tx_lock
, flags
);
4170 return NETDEV_TX_OK
;
4173 /* Called with rtnl_lock */
4175 bnx2_close(struct net_device
*dev
)
4177 struct bnx2
*bp
= dev
->priv
;
4180 /* Calling flush_scheduled_work() may deadlock because
4181 * linkwatch_event() may be on the workqueue and it will try to get
4182 * the rtnl_lock which we are holding.
4184 while (bp
->in_reset_task
)
4187 bnx2_netif_stop(bp
);
4188 del_timer_sync(&bp
->timer
);
4190 reset_code
= BNX2_DRV_MSG_CODE_SUSPEND_WOL
;
4192 reset_code
= BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL
;
4193 bnx2_reset_chip(bp
, reset_code
);
4194 free_irq(bp
->pdev
->irq
, dev
);
4195 if (bp
->flags
& USING_MSI_FLAG
) {
4196 pci_disable_msi(bp
->pdev
);
4197 bp
->flags
&= ~USING_MSI_FLAG
;
4202 netif_carrier_off(bp
->dev
);
4203 bnx2_set_power_state(bp
, 3);
4207 #define GET_NET_STATS64(ctr) \
4208 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4209 (unsigned long) (ctr##_lo)
4211 #define GET_NET_STATS32(ctr) \
4214 #if (BITS_PER_LONG == 64)
4215 #define GET_NET_STATS GET_NET_STATS64
4217 #define GET_NET_STATS GET_NET_STATS32
4220 static struct net_device_stats
*
4221 bnx2_get_stats(struct net_device
*dev
)
4223 struct bnx2
*bp
= dev
->priv
;
4224 struct statistics_block
*stats_blk
= bp
->stats_blk
;
4225 struct net_device_stats
*net_stats
= &bp
->net_stats
;
4227 if (bp
->stats_blk
== NULL
) {
4230 net_stats
->rx_packets
=
4231 GET_NET_STATS(stats_blk
->stat_IfHCInUcastPkts
) +
4232 GET_NET_STATS(stats_blk
->stat_IfHCInMulticastPkts
) +
4233 GET_NET_STATS(stats_blk
->stat_IfHCInBroadcastPkts
);
4235 net_stats
->tx_packets
=
4236 GET_NET_STATS(stats_blk
->stat_IfHCOutUcastPkts
) +
4237 GET_NET_STATS(stats_blk
->stat_IfHCOutMulticastPkts
) +
4238 GET_NET_STATS(stats_blk
->stat_IfHCOutBroadcastPkts
);
4240 net_stats
->rx_bytes
=
4241 GET_NET_STATS(stats_blk
->stat_IfHCInOctets
);
4243 net_stats
->tx_bytes
=
4244 GET_NET_STATS(stats_blk
->stat_IfHCOutOctets
);
4246 net_stats
->multicast
=
4247 GET_NET_STATS(stats_blk
->stat_IfHCOutMulticastPkts
);
4249 net_stats
->collisions
=
4250 (unsigned long) stats_blk
->stat_EtherStatsCollisions
;
4252 net_stats
->rx_length_errors
=
4253 (unsigned long) (stats_blk
->stat_EtherStatsUndersizePkts
+
4254 stats_blk
->stat_EtherStatsOverrsizePkts
);
4256 net_stats
->rx_over_errors
=
4257 (unsigned long) stats_blk
->stat_IfInMBUFDiscards
;
4259 net_stats
->rx_frame_errors
=
4260 (unsigned long) stats_blk
->stat_Dot3StatsAlignmentErrors
;
4262 net_stats
->rx_crc_errors
=
4263 (unsigned long) stats_blk
->stat_Dot3StatsFCSErrors
;
4265 net_stats
->rx_errors
= net_stats
->rx_length_errors
+
4266 net_stats
->rx_over_errors
+ net_stats
->rx_frame_errors
+
4267 net_stats
->rx_crc_errors
;
4269 net_stats
->tx_aborted_errors
=
4270 (unsigned long) (stats_blk
->stat_Dot3StatsExcessiveCollisions
+
4271 stats_blk
->stat_Dot3StatsLateCollisions
);
4273 if (CHIP_NUM(bp
) == CHIP_NUM_5706
)
4274 net_stats
->tx_carrier_errors
= 0;
4276 net_stats
->tx_carrier_errors
=
4278 stats_blk
->stat_Dot3StatsCarrierSenseErrors
;
4281 net_stats
->tx_errors
=
4283 stats_blk
->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4285 net_stats
->tx_aborted_errors
+
4286 net_stats
->tx_carrier_errors
;
4291 /* All ethtool functions called with rtnl_lock */
4294 bnx2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
4296 struct bnx2
*bp
= dev
->priv
;
4298 cmd
->supported
= SUPPORTED_Autoneg
;
4299 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
4300 cmd
->supported
|= SUPPORTED_1000baseT_Full
|
4303 cmd
->port
= PORT_FIBRE
;
4306 cmd
->supported
|= SUPPORTED_10baseT_Half
|
4307 SUPPORTED_10baseT_Full
|
4308 SUPPORTED_100baseT_Half
|
4309 SUPPORTED_100baseT_Full
|
4310 SUPPORTED_1000baseT_Full
|
4313 cmd
->port
= PORT_TP
;
4316 cmd
->advertising
= bp
->advertising
;
4318 if (bp
->autoneg
& AUTONEG_SPEED
) {
4319 cmd
->autoneg
= AUTONEG_ENABLE
;
4322 cmd
->autoneg
= AUTONEG_DISABLE
;
4325 if (netif_carrier_ok(dev
)) {
4326 cmd
->speed
= bp
->line_speed
;
4327 cmd
->duplex
= bp
->duplex
;
4334 cmd
->transceiver
= XCVR_INTERNAL
;
4335 cmd
->phy_address
= bp
->phy_addr
;
4341 bnx2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
4343 struct bnx2
*bp
= dev
->priv
;
4344 u8 autoneg
= bp
->autoneg
;
4345 u8 req_duplex
= bp
->req_duplex
;
4346 u16 req_line_speed
= bp
->req_line_speed
;
4347 u32 advertising
= bp
->advertising
;
4349 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
4350 autoneg
|= AUTONEG_SPEED
;
4352 cmd
->advertising
&= ETHTOOL_ALL_COPPER_SPEED
;
4354 /* allow advertising 1 speed */
4355 if ((cmd
->advertising
== ADVERTISED_10baseT_Half
) ||
4356 (cmd
->advertising
== ADVERTISED_10baseT_Full
) ||
4357 (cmd
->advertising
== ADVERTISED_100baseT_Half
) ||
4358 (cmd
->advertising
== ADVERTISED_100baseT_Full
)) {
4360 if (bp
->phy_flags
& PHY_SERDES_FLAG
)
4363 advertising
= cmd
->advertising
;
4366 else if (cmd
->advertising
== ADVERTISED_1000baseT_Full
) {
4367 advertising
= cmd
->advertising
;
4369 else if (cmd
->advertising
== ADVERTISED_1000baseT_Half
) {
4373 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
4374 advertising
= ETHTOOL_ALL_FIBRE_SPEED
;
4377 advertising
= ETHTOOL_ALL_COPPER_SPEED
;
4380 advertising
|= ADVERTISED_Autoneg
;
4383 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
4384 if ((cmd
->speed
!= SPEED_1000
) ||
4385 (cmd
->duplex
!= DUPLEX_FULL
)) {
4389 else if (cmd
->speed
== SPEED_1000
) {
4392 autoneg
&= ~AUTONEG_SPEED
;
4393 req_line_speed
= cmd
->speed
;
4394 req_duplex
= cmd
->duplex
;
4398 bp
->autoneg
= autoneg
;
4399 bp
->advertising
= advertising
;
4400 bp
->req_line_speed
= req_line_speed
;
4401 bp
->req_duplex
= req_duplex
;
4403 spin_lock_irq(&bp
->phy_lock
);
4407 spin_unlock_irq(&bp
->phy_lock
);
4413 bnx2_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4415 struct bnx2
*bp
= dev
->priv
;
4417 strcpy(info
->driver
, DRV_MODULE_NAME
);
4418 strcpy(info
->version
, DRV_MODULE_VERSION
);
4419 strcpy(info
->bus_info
, pci_name(bp
->pdev
));
4420 info
->fw_version
[0] = ((bp
->fw_ver
& 0xff000000) >> 24) + '0';
4421 info
->fw_version
[2] = ((bp
->fw_ver
& 0xff0000) >> 16) + '0';
4422 info
->fw_version
[4] = ((bp
->fw_ver
& 0xff00) >> 8) + '0';
4423 info
->fw_version
[6] = (bp
->fw_ver
& 0xff) + '0';
4424 info
->fw_version
[1] = info
->fw_version
[3] = info
->fw_version
[5] = '.';
4425 info
->fw_version
[7] = 0;
4429 bnx2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
4431 struct bnx2
*bp
= dev
->priv
;
4433 if (bp
->flags
& NO_WOL_FLAG
) {
4438 wol
->supported
= WAKE_MAGIC
;
4440 wol
->wolopts
= WAKE_MAGIC
;
4444 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
4448 bnx2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
4450 struct bnx2
*bp
= dev
->priv
;
4452 if (wol
->wolopts
& ~WAKE_MAGIC
)
4455 if (wol
->wolopts
& WAKE_MAGIC
) {
4456 if (bp
->flags
& NO_WOL_FLAG
)
4468 bnx2_nway_reset(struct net_device
*dev
)
4470 struct bnx2
*bp
= dev
->priv
;
4473 if (!(bp
->autoneg
& AUTONEG_SPEED
)) {
4477 spin_lock_irq(&bp
->phy_lock
);
4479 /* Force a link down visible on the other side */
4480 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
4481 bnx2_write_phy(bp
, MII_BMCR
, BMCR_LOOPBACK
);
4482 spin_unlock_irq(&bp
->phy_lock
);
4486 spin_lock_irq(&bp
->phy_lock
);
4487 if (CHIP_NUM(bp
) == CHIP_NUM_5706
) {
4488 bp
->serdes_an_pending
= SERDES_AN_TIMEOUT
/
4493 bnx2_read_phy(bp
, MII_BMCR
, &bmcr
);
4494 bmcr
&= ~BMCR_LOOPBACK
;
4495 bnx2_write_phy(bp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
| BMCR_ANENABLE
);
4497 spin_unlock_irq(&bp
->phy_lock
);
4503 bnx2_get_eeprom_len(struct net_device
*dev
)
4505 struct bnx2
*bp
= dev
->priv
;
4507 if (bp
->flash_info
== 0)
4510 return (int) bp
->flash_info
->total_size
;
4514 bnx2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4517 struct bnx2
*bp
= dev
->priv
;
4520 if (eeprom
->offset
> bp
->flash_info
->total_size
)
4523 if ((eeprom
->offset
+ eeprom
->len
) > bp
->flash_info
->total_size
)
4524 eeprom
->len
= bp
->flash_info
->total_size
- eeprom
->offset
;
4526 rc
= bnx2_nvram_read(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
4532 bnx2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4535 struct bnx2
*bp
= dev
->priv
;
4538 if (eeprom
->offset
> bp
->flash_info
->total_size
)
4541 if ((eeprom
->offset
+ eeprom
->len
) > bp
->flash_info
->total_size
)
4542 eeprom
->len
= bp
->flash_info
->total_size
- eeprom
->offset
;
4544 rc
= bnx2_nvram_write(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
4550 bnx2_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*coal
)
4552 struct bnx2
*bp
= dev
->priv
;
4554 memset(coal
, 0, sizeof(struct ethtool_coalesce
));
4556 coal
->rx_coalesce_usecs
= bp
->rx_ticks
;
4557 coal
->rx_max_coalesced_frames
= bp
->rx_quick_cons_trip
;
4558 coal
->rx_coalesce_usecs_irq
= bp
->rx_ticks_int
;
4559 coal
->rx_max_coalesced_frames_irq
= bp
->rx_quick_cons_trip_int
;
4561 coal
->tx_coalesce_usecs
= bp
->tx_ticks
;
4562 coal
->tx_max_coalesced_frames
= bp
->tx_quick_cons_trip
;
4563 coal
->tx_coalesce_usecs_irq
= bp
->tx_ticks_int
;
4564 coal
->tx_max_coalesced_frames_irq
= bp
->tx_quick_cons_trip_int
;
4566 coal
->stats_block_coalesce_usecs
= bp
->stats_ticks
;
4572 bnx2_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*coal
)
4574 struct bnx2
*bp
= dev
->priv
;
4576 bp
->rx_ticks
= (u16
) coal
->rx_coalesce_usecs
;
4577 if (bp
->rx_ticks
> 0x3ff) bp
->rx_ticks
= 0x3ff;
4579 bp
->rx_quick_cons_trip
= (u16
) coal
->rx_max_coalesced_frames
;
4580 if (bp
->rx_quick_cons_trip
> 0xff) bp
->rx_quick_cons_trip
= 0xff;
4582 bp
->rx_ticks_int
= (u16
) coal
->rx_coalesce_usecs_irq
;
4583 if (bp
->rx_ticks_int
> 0x3ff) bp
->rx_ticks_int
= 0x3ff;
4585 bp
->rx_quick_cons_trip_int
= (u16
) coal
->rx_max_coalesced_frames_irq
;
4586 if (bp
->rx_quick_cons_trip_int
> 0xff)
4587 bp
->rx_quick_cons_trip_int
= 0xff;
4589 bp
->tx_ticks
= (u16
) coal
->tx_coalesce_usecs
;
4590 if (bp
->tx_ticks
> 0x3ff) bp
->tx_ticks
= 0x3ff;
4592 bp
->tx_quick_cons_trip
= (u16
) coal
->tx_max_coalesced_frames
;
4593 if (bp
->tx_quick_cons_trip
> 0xff) bp
->tx_quick_cons_trip
= 0xff;
4595 bp
->tx_ticks_int
= (u16
) coal
->tx_coalesce_usecs_irq
;
4596 if (bp
->tx_ticks_int
> 0x3ff) bp
->tx_ticks_int
= 0x3ff;
4598 bp
->tx_quick_cons_trip_int
= (u16
) coal
->tx_max_coalesced_frames_irq
;
4599 if (bp
->tx_quick_cons_trip_int
> 0xff) bp
->tx_quick_cons_trip_int
=
4602 bp
->stats_ticks
= coal
->stats_block_coalesce_usecs
;
4603 if (bp
->stats_ticks
> 0xffff00) bp
->stats_ticks
= 0xffff00;
4604 bp
->stats_ticks
&= 0xffff00;
4606 if (netif_running(bp
->dev
)) {
4607 bnx2_netif_stop(bp
);
4609 bnx2_netif_start(bp
);
4616 bnx2_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
4618 struct bnx2
*bp
= dev
->priv
;
4620 ering
->rx_max_pending
= MAX_RX_DESC_CNT
;
4621 ering
->rx_mini_max_pending
= 0;
4622 ering
->rx_jumbo_max_pending
= 0;
4624 ering
->rx_pending
= bp
->rx_ring_size
;
4625 ering
->rx_mini_pending
= 0;
4626 ering
->rx_jumbo_pending
= 0;
4628 ering
->tx_max_pending
= MAX_TX_DESC_CNT
;
4629 ering
->tx_pending
= bp
->tx_ring_size
;
4633 bnx2_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
4635 struct bnx2
*bp
= dev
->priv
;
4637 if ((ering
->rx_pending
> MAX_RX_DESC_CNT
) ||
4638 (ering
->tx_pending
> MAX_TX_DESC_CNT
) ||
4639 (ering
->tx_pending
<= MAX_SKB_FRAGS
)) {
4643 bp
->rx_ring_size
= ering
->rx_pending
;
4644 bp
->tx_ring_size
= ering
->tx_pending
;
4646 if (netif_running(bp
->dev
)) {
4647 bnx2_netif_stop(bp
);
4649 bnx2_netif_start(bp
);
4656 bnx2_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
4658 struct bnx2
*bp
= dev
->priv
;
4660 epause
->autoneg
= ((bp
->autoneg
& AUTONEG_FLOW_CTRL
) != 0);
4661 epause
->rx_pause
= ((bp
->flow_ctrl
& FLOW_CTRL_RX
) != 0);
4662 epause
->tx_pause
= ((bp
->flow_ctrl
& FLOW_CTRL_TX
) != 0);
4666 bnx2_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
4668 struct bnx2
*bp
= dev
->priv
;
4670 bp
->req_flow_ctrl
= 0;
4671 if (epause
->rx_pause
)
4672 bp
->req_flow_ctrl
|= FLOW_CTRL_RX
;
4673 if (epause
->tx_pause
)
4674 bp
->req_flow_ctrl
|= FLOW_CTRL_TX
;
4676 if (epause
->autoneg
) {
4677 bp
->autoneg
|= AUTONEG_FLOW_CTRL
;
4680 bp
->autoneg
&= ~AUTONEG_FLOW_CTRL
;
4683 spin_lock_irq(&bp
->phy_lock
);
4687 spin_unlock_irq(&bp
->phy_lock
);
4693 bnx2_get_rx_csum(struct net_device
*dev
)
4695 struct bnx2
*bp
= dev
->priv
;
4701 bnx2_set_rx_csum(struct net_device
*dev
, u32 data
)
4703 struct bnx2
*bp
= dev
->priv
;
4709 #define BNX2_NUM_STATS 45
4712 char string
[ETH_GSTRING_LEN
];
4713 } bnx2_stats_str_arr
[BNX2_NUM_STATS
] = {
4715 { "rx_error_bytes" },
4717 { "tx_error_bytes" },
4718 { "rx_ucast_packets" },
4719 { "rx_mcast_packets" },
4720 { "rx_bcast_packets" },
4721 { "tx_ucast_packets" },
4722 { "tx_mcast_packets" },
4723 { "tx_bcast_packets" },
4724 { "tx_mac_errors" },
4725 { "tx_carrier_errors" },
4726 { "rx_crc_errors" },
4727 { "rx_align_errors" },
4728 { "tx_single_collisions" },
4729 { "tx_multi_collisions" },
4731 { "tx_excess_collisions" },
4732 { "tx_late_collisions" },
4733 { "tx_total_collisions" },
4736 { "rx_undersize_packets" },
4737 { "rx_oversize_packets" },
4738 { "rx_64_byte_packets" },
4739 { "rx_65_to_127_byte_packets" },
4740 { "rx_128_to_255_byte_packets" },
4741 { "rx_256_to_511_byte_packets" },
4742 { "rx_512_to_1023_byte_packets" },
4743 { "rx_1024_to_1522_byte_packets" },
4744 { "rx_1523_to_9022_byte_packets" },
4745 { "tx_64_byte_packets" },
4746 { "tx_65_to_127_byte_packets" },
4747 { "tx_128_to_255_byte_packets" },
4748 { "tx_256_to_511_byte_packets" },
4749 { "tx_512_to_1023_byte_packets" },
4750 { "tx_1024_to_1522_byte_packets" },
4751 { "tx_1523_to_9022_byte_packets" },
4752 { "rx_xon_frames" },
4753 { "rx_xoff_frames" },
4754 { "tx_xon_frames" },
4755 { "tx_xoff_frames" },
4756 { "rx_mac_ctrl_frames" },
4757 { "rx_filtered_packets" },
4761 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4763 static unsigned long bnx2_stats_offset_arr
[BNX2_NUM_STATS
] = {
4764 STATS_OFFSET32(stat_IfHCInOctets_hi
),
4765 STATS_OFFSET32(stat_IfHCInBadOctets_hi
),
4766 STATS_OFFSET32(stat_IfHCOutOctets_hi
),
4767 STATS_OFFSET32(stat_IfHCOutBadOctets_hi
),
4768 STATS_OFFSET32(stat_IfHCInUcastPkts_hi
),
4769 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi
),
4770 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi
),
4771 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi
),
4772 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi
),
4773 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi
),
4774 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors
),
4775 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors
),
4776 STATS_OFFSET32(stat_Dot3StatsFCSErrors
),
4777 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors
),
4778 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames
),
4779 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames
),
4780 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions
),
4781 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions
),
4782 STATS_OFFSET32(stat_Dot3StatsLateCollisions
),
4783 STATS_OFFSET32(stat_EtherStatsCollisions
),
4784 STATS_OFFSET32(stat_EtherStatsFragments
),
4785 STATS_OFFSET32(stat_EtherStatsJabbers
),
4786 STATS_OFFSET32(stat_EtherStatsUndersizePkts
),
4787 STATS_OFFSET32(stat_EtherStatsOverrsizePkts
),
4788 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets
),
4789 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets
),
4790 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets
),
4791 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets
),
4792 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets
),
4793 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets
),
4794 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets
),
4795 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets
),
4796 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets
),
4797 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets
),
4798 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets
),
4799 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets
),
4800 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets
),
4801 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets
),
4802 STATS_OFFSET32(stat_XonPauseFramesReceived
),
4803 STATS_OFFSET32(stat_XoffPauseFramesReceived
),
4804 STATS_OFFSET32(stat_OutXonSent
),
4805 STATS_OFFSET32(stat_OutXoffSent
),
4806 STATS_OFFSET32(stat_MacControlFramesReceived
),
4807 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards
),
4808 STATS_OFFSET32(stat_IfInMBUFDiscards
),
4811 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4812 * skipped because of errata.
4814 static u8 bnx2_5706_stats_len_arr
[BNX2_NUM_STATS
] = {
4815 8,0,8,8,8,8,8,8,8,8,
4816 4,0,4,4,4,4,4,4,4,4,
4817 4,4,4,4,4,4,4,4,4,4,
4818 4,4,4,4,4,4,4,4,4,4,
4822 #define BNX2_NUM_TESTS 6
4825 char string
[ETH_GSTRING_LEN
];
4826 } bnx2_tests_str_arr
[BNX2_NUM_TESTS
] = {
4827 { "register_test (offline)" },
4828 { "memory_test (offline)" },
4829 { "loopback_test (offline)" },
4830 { "nvram_test (online)" },
4831 { "interrupt_test (online)" },
4832 { "link_test (online)" },
4836 bnx2_self_test_count(struct net_device
*dev
)
4838 return BNX2_NUM_TESTS
;
4842 bnx2_self_test(struct net_device
*dev
, struct ethtool_test
*etest
, u64
*buf
)
4844 struct bnx2
*bp
= dev
->priv
;
4846 memset(buf
, 0, sizeof(u64
) * BNX2_NUM_TESTS
);
4847 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
4848 bnx2_netif_stop(bp
);
4849 bnx2_reset_chip(bp
, BNX2_DRV_MSG_CODE_DIAG
);
4852 if (bnx2_test_registers(bp
) != 0) {
4854 etest
->flags
|= ETH_TEST_FL_FAILED
;
4856 if (bnx2_test_memory(bp
) != 0) {
4858 etest
->flags
|= ETH_TEST_FL_FAILED
;
4860 if (bnx2_test_loopback(bp
) != 0) {
4862 etest
->flags
|= ETH_TEST_FL_FAILED
;
4865 if (!netif_running(bp
->dev
)) {
4866 bnx2_reset_chip(bp
, BNX2_DRV_MSG_CODE_RESET
);
4870 bnx2_netif_start(bp
);
4873 /* wait for link up */
4874 msleep_interruptible(3000);
4875 if ((!bp
->link_up
) && !(bp
->phy_flags
& PHY_SERDES_FLAG
))
4876 msleep_interruptible(4000);
4879 if (bnx2_test_nvram(bp
) != 0) {
4881 etest
->flags
|= ETH_TEST_FL_FAILED
;
4883 if (bnx2_test_intr(bp
) != 0) {
4885 etest
->flags
|= ETH_TEST_FL_FAILED
;
4888 if (bnx2_test_link(bp
) != 0) {
4890 etest
->flags
|= ETH_TEST_FL_FAILED
;
4896 bnx2_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
4898 switch (stringset
) {
4900 memcpy(buf
, bnx2_stats_str_arr
,
4901 sizeof(bnx2_stats_str_arr
));
4904 memcpy(buf
, bnx2_tests_str_arr
,
4905 sizeof(bnx2_tests_str_arr
));
4911 bnx2_get_stats_count(struct net_device
*dev
)
4913 return BNX2_NUM_STATS
;
4917 bnx2_get_ethtool_stats(struct net_device
*dev
,
4918 struct ethtool_stats
*stats
, u64
*buf
)
4920 struct bnx2
*bp
= dev
->priv
;
4922 u32
*hw_stats
= (u32
*) bp
->stats_blk
;
4923 u8
*stats_len_arr
= NULL
;
4925 if (hw_stats
== NULL
) {
4926 memset(buf
, 0, sizeof(u64
) * BNX2_NUM_STATS
);
4930 if (CHIP_NUM(bp
) == CHIP_NUM_5706
)
4931 stats_len_arr
= bnx2_5706_stats_len_arr
;
4933 for (i
= 0; i
< BNX2_NUM_STATS
; i
++) {
4934 if (stats_len_arr
[i
] == 0) {
4935 /* skip this counter */
4939 if (stats_len_arr
[i
] == 4) {
4940 /* 4-byte counter */
4942 *(hw_stats
+ bnx2_stats_offset_arr
[i
]);
4945 /* 8-byte counter */
4946 buf
[i
] = (((u64
) *(hw_stats
+
4947 bnx2_stats_offset_arr
[i
])) << 32) +
4948 *(hw_stats
+ bnx2_stats_offset_arr
[i
] + 1);
4953 bnx2_phys_id(struct net_device
*dev
, u32 data
)
4955 struct bnx2
*bp
= dev
->priv
;
4962 save
= REG_RD(bp
, BNX2_MISC_CFG
);
4963 REG_WR(bp
, BNX2_MISC_CFG
, BNX2_MISC_CFG_LEDMODE_MAC
);
4965 for (i
= 0; i
< (data
* 2); i
++) {
4967 REG_WR(bp
, BNX2_EMAC_LED
, BNX2_EMAC_LED_OVERRIDE
);
4970 REG_WR(bp
, BNX2_EMAC_LED
, BNX2_EMAC_LED_OVERRIDE
|
4971 BNX2_EMAC_LED_1000MB_OVERRIDE
|
4972 BNX2_EMAC_LED_100MB_OVERRIDE
|
4973 BNX2_EMAC_LED_10MB_OVERRIDE
|
4974 BNX2_EMAC_LED_TRAFFIC_OVERRIDE
|
4975 BNX2_EMAC_LED_TRAFFIC
);
4977 msleep_interruptible(500);
4978 if (signal_pending(current
))
4981 REG_WR(bp
, BNX2_EMAC_LED
, 0);
4982 REG_WR(bp
, BNX2_MISC_CFG
, save
);
4986 static struct ethtool_ops bnx2_ethtool_ops
= {
4987 .get_settings
= bnx2_get_settings
,
4988 .set_settings
= bnx2_set_settings
,
4989 .get_drvinfo
= bnx2_get_drvinfo
,
4990 .get_wol
= bnx2_get_wol
,
4991 .set_wol
= bnx2_set_wol
,
4992 .nway_reset
= bnx2_nway_reset
,
4993 .get_link
= ethtool_op_get_link
,
4994 .get_eeprom_len
= bnx2_get_eeprom_len
,
4995 .get_eeprom
= bnx2_get_eeprom
,
4996 .set_eeprom
= bnx2_set_eeprom
,
4997 .get_coalesce
= bnx2_get_coalesce
,
4998 .set_coalesce
= bnx2_set_coalesce
,
4999 .get_ringparam
= bnx2_get_ringparam
,
5000 .set_ringparam
= bnx2_set_ringparam
,
5001 .get_pauseparam
= bnx2_get_pauseparam
,
5002 .set_pauseparam
= bnx2_set_pauseparam
,
5003 .get_rx_csum
= bnx2_get_rx_csum
,
5004 .set_rx_csum
= bnx2_set_rx_csum
,
5005 .get_tx_csum
= ethtool_op_get_tx_csum
,
5006 .set_tx_csum
= ethtool_op_set_tx_csum
,
5007 .get_sg
= ethtool_op_get_sg
,
5008 .set_sg
= ethtool_op_set_sg
,
5010 .get_tso
= ethtool_op_get_tso
,
5011 .set_tso
= ethtool_op_set_tso
,
5013 .self_test_count
= bnx2_self_test_count
,
5014 .self_test
= bnx2_self_test
,
5015 .get_strings
= bnx2_get_strings
,
5016 .phys_id
= bnx2_phys_id
,
5017 .get_stats_count
= bnx2_get_stats_count
,
5018 .get_ethtool_stats
= bnx2_get_ethtool_stats
,
5021 /* Called with rtnl_lock */
5023 bnx2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5025 struct mii_ioctl_data
*data
= if_mii(ifr
);
5026 struct bnx2
*bp
= dev
->priv
;
5031 data
->phy_id
= bp
->phy_addr
;
5037 spin_lock_irq(&bp
->phy_lock
);
5038 err
= bnx2_read_phy(bp
, data
->reg_num
& 0x1f, &mii_regval
);
5039 spin_unlock_irq(&bp
->phy_lock
);
5041 data
->val_out
= mii_regval
;
5047 if (!capable(CAP_NET_ADMIN
))
5050 spin_lock_irq(&bp
->phy_lock
);
5051 err
= bnx2_write_phy(bp
, data
->reg_num
& 0x1f, data
->val_in
);
5052 spin_unlock_irq(&bp
->phy_lock
);
5063 /* Called with rtnl_lock */
5065 bnx2_change_mac_addr(struct net_device
*dev
, void *p
)
5067 struct sockaddr
*addr
= p
;
5068 struct bnx2
*bp
= dev
->priv
;
5070 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5071 if (netif_running(dev
))
5072 bnx2_set_mac_addr(bp
);
5077 /* Called with rtnl_lock */
5079 bnx2_change_mtu(struct net_device
*dev
, int new_mtu
)
5081 struct bnx2
*bp
= dev
->priv
;
5083 if (((new_mtu
+ ETH_HLEN
) > MAX_ETHERNET_JUMBO_PACKET_SIZE
) ||
5084 ((new_mtu
+ ETH_HLEN
) < MIN_ETHERNET_PACKET_SIZE
))
5088 if (netif_running(dev
)) {
5089 bnx2_netif_stop(bp
);
5093 bnx2_netif_start(bp
);
5098 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5100 poll_bnx2(struct net_device
*dev
)
5102 struct bnx2
*bp
= dev
->priv
;
5104 disable_irq(bp
->pdev
->irq
);
5105 bnx2_interrupt(bp
->pdev
->irq
, dev
, NULL
);
5106 enable_irq(bp
->pdev
->irq
);
5110 static int __devinit
5111 bnx2_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5114 unsigned long mem_len
;
5118 SET_MODULE_OWNER(dev
);
5119 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5125 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5126 rc
= pci_enable_device(pdev
);
5128 printk(KERN_ERR PFX
"Cannot enable PCI device, aborting.");
5132 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5133 printk(KERN_ERR PFX
"Cannot find PCI device base address, "
5136 goto err_out_disable
;
5139 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5141 printk(KERN_ERR PFX
"Cannot obtain PCI resources, aborting.\n");
5142 goto err_out_disable
;
5145 pci_set_master(pdev
);
5147 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
5148 if (bp
->pm_cap
== 0) {
5149 printk(KERN_ERR PFX
"Cannot find power management capability, "
5152 goto err_out_release
;
5155 bp
->pcix_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PCIX
);
5156 if (bp
->pcix_cap
== 0) {
5157 printk(KERN_ERR PFX
"Cannot find PCIX capability, aborting.\n");
5159 goto err_out_release
;
5162 if (pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) == 0) {
5163 bp
->flags
|= USING_DAC_FLAG
;
5164 if (pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
) != 0) {
5165 printk(KERN_ERR PFX
"pci_set_consistent_dma_mask "
5166 "failed, aborting.\n");
5168 goto err_out_release
;
5171 else if (pci_set_dma_mask(pdev
, DMA_32BIT_MASK
) != 0) {
5172 printk(KERN_ERR PFX
"System does not support DMA, aborting.\n");
5174 goto err_out_release
;
5180 spin_lock_init(&bp
->phy_lock
);
5181 spin_lock_init(&bp
->tx_lock
);
5182 INIT_WORK(&bp
->reset_task
, bnx2_reset_task
, bp
);
5184 dev
->base_addr
= dev
->mem_start
= pci_resource_start(pdev
, 0);
5185 mem_len
= MB_GET_CID_ADDR(17);
5186 dev
->mem_end
= dev
->mem_start
+ mem_len
;
5187 dev
->irq
= pdev
->irq
;
5189 bp
->regview
= ioremap_nocache(dev
->base_addr
, mem_len
);
5192 printk(KERN_ERR PFX
"Cannot map register space, aborting.\n");
5194 goto err_out_release
;
5197 /* Configure byte swap and enable write to the reg_window registers.
5198 * Rely on CPU to do target byte swapping on big endian systems
5199 * The chip's target access swapping will not swap all accesses
5201 pci_write_config_dword(bp
->pdev
, BNX2_PCICFG_MISC_CONFIG
,
5202 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
|
5203 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
);
5205 bnx2_set_power_state(bp
, 0);
5207 bp
->chip_id
= REG_RD(bp
, BNX2_MISC_ID
);
5211 /* Get bus information. */
5212 reg
= REG_RD(bp
, BNX2_PCICFG_MISC_STATUS
);
5213 if (reg
& BNX2_PCICFG_MISC_STATUS_PCIX_DET
) {
5216 bp
->flags
|= PCIX_FLAG
;
5218 clkreg
= REG_RD(bp
, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS
);
5220 clkreg
&= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET
;
5222 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ
:
5223 bp
->bus_speed_mhz
= 133;
5226 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ
:
5227 bp
->bus_speed_mhz
= 100;
5230 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ
:
5231 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ
:
5232 bp
->bus_speed_mhz
= 66;
5235 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ
:
5236 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ
:
5237 bp
->bus_speed_mhz
= 50;
5240 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW
:
5241 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ
:
5242 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ
:
5243 bp
->bus_speed_mhz
= 33;
5248 if (reg
& BNX2_PCICFG_MISC_STATUS_M66EN
)
5249 bp
->bus_speed_mhz
= 66;
5251 bp
->bus_speed_mhz
= 33;
5254 if (reg
& BNX2_PCICFG_MISC_STATUS_32BIT_DET
)
5255 bp
->flags
|= PCI_32BIT_FLAG
;
5257 /* 5706A0 may falsely detect SERR and PERR. */
5258 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
5259 reg
= REG_RD(bp
, PCI_COMMAND
);
5260 reg
&= ~(PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
5261 REG_WR(bp
, PCI_COMMAND
, reg
);
5263 else if ((CHIP_ID(bp
) == CHIP_ID_5706_A1
) &&
5264 !(bp
->flags
& PCIX_FLAG
)) {
5266 printk(KERN_ERR PFX
"5706 A1 can only be used in a PCIX bus, "
5271 bnx2_init_nvram(bp
);
5273 /* Get the permanent MAC address. First we need to make sure the
5274 * firmware is actually running.
5276 reg
= REG_RD_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_DEV_INFO_SIGNATURE
);
5278 if ((reg
& BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
) !=
5279 BNX2_DEV_INFO_SIGNATURE_MAGIC
) {
5280 printk(KERN_ERR PFX
"Firmware not running, aborting.\n");
5285 bp
->fw_ver
= REG_RD_IND(bp
, HOST_VIEW_SHMEM_BASE
+
5286 BNX2_DEV_INFO_BC_REV
);
5288 reg
= REG_RD_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_PORT_HW_CFG_MAC_UPPER
);
5289 bp
->mac_addr
[0] = (u8
) (reg
>> 8);
5290 bp
->mac_addr
[1] = (u8
) reg
;
5292 reg
= REG_RD_IND(bp
, HOST_VIEW_SHMEM_BASE
+ BNX2_PORT_HW_CFG_MAC_LOWER
);
5293 bp
->mac_addr
[2] = (u8
) (reg
>> 24);
5294 bp
->mac_addr
[3] = (u8
) (reg
>> 16);
5295 bp
->mac_addr
[4] = (u8
) (reg
>> 8);
5296 bp
->mac_addr
[5] = (u8
) reg
;
5298 bp
->tx_ring_size
= MAX_TX_DESC_CNT
;
5299 bp
->rx_ring_size
= 100;
5303 bp
->rx_offset
= sizeof(struct l2_fhdr
) + 2;
5305 bp
->tx_quick_cons_trip_int
= 20;
5306 bp
->tx_quick_cons_trip
= 20;
5307 bp
->tx_ticks_int
= 80;
5310 bp
->rx_quick_cons_trip_int
= 6;
5311 bp
->rx_quick_cons_trip
= 6;
5312 bp
->rx_ticks_int
= 18;
5315 bp
->stats_ticks
= 1000000 & 0xffff00;
5317 bp
->timer_interval
= HZ
;
5319 /* Disable WOL support if we are running on a SERDES chip. */
5320 if (CHIP_BOND_ID(bp
) & CHIP_BOND_ID_SERDES_BIT
) {
5321 bp
->phy_flags
|= PHY_SERDES_FLAG
;
5322 bp
->flags
|= NO_WOL_FLAG
;
5325 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
5326 bp
->tx_quick_cons_trip_int
=
5327 bp
->tx_quick_cons_trip
;
5328 bp
->tx_ticks_int
= bp
->tx_ticks
;
5329 bp
->rx_quick_cons_trip_int
=
5330 bp
->rx_quick_cons_trip
;
5331 bp
->rx_ticks_int
= bp
->rx_ticks
;
5332 bp
->comp_prod_trip_int
= bp
->comp_prod_trip
;
5333 bp
->com_ticks_int
= bp
->com_ticks
;
5334 bp
->cmd_ticks_int
= bp
->cmd_ticks
;
5337 bp
->autoneg
= AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
;
5338 bp
->req_line_speed
= 0;
5339 if (bp
->phy_flags
& PHY_SERDES_FLAG
) {
5340 bp
->advertising
= ETHTOOL_ALL_FIBRE_SPEED
| ADVERTISED_Autoneg
;
5343 bp
->advertising
= ETHTOOL_ALL_COPPER_SPEED
| ADVERTISED_Autoneg
;
5346 bp
->req_flow_ctrl
= FLOW_CTRL_RX
| FLOW_CTRL_TX
;
5352 iounmap(bp
->regview
);
5356 pci_release_regions(pdev
);
5359 pci_disable_device(pdev
);
5360 pci_set_drvdata(pdev
, NULL
);
5366 static int __devinit
5367 bnx2_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5369 static int version_printed
= 0;
5370 struct net_device
*dev
= NULL
;
5374 if (version_printed
++ == 0)
5375 printk(KERN_INFO
"%s", version
);
5377 /* dev zeroed in init_etherdev */
5378 dev
= alloc_etherdev(sizeof(*bp
));
5383 rc
= bnx2_init_board(pdev
, dev
);
5389 dev
->open
= bnx2_open
;
5390 dev
->hard_start_xmit
= bnx2_start_xmit
;
5391 dev
->stop
= bnx2_close
;
5392 dev
->get_stats
= bnx2_get_stats
;
5393 dev
->set_multicast_list
= bnx2_set_rx_mode
;
5394 dev
->do_ioctl
= bnx2_ioctl
;
5395 dev
->set_mac_address
= bnx2_change_mac_addr
;
5396 dev
->change_mtu
= bnx2_change_mtu
;
5397 dev
->tx_timeout
= bnx2_tx_timeout
;
5398 dev
->watchdog_timeo
= TX_TIMEOUT
;
5400 dev
->vlan_rx_register
= bnx2_vlan_rx_register
;
5401 dev
->vlan_rx_kill_vid
= bnx2_vlan_rx_kill_vid
;
5403 dev
->poll
= bnx2_poll
;
5404 dev
->ethtool_ops
= &bnx2_ethtool_ops
;
5409 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5410 dev
->poll_controller
= poll_bnx2
;
5413 if ((rc
= register_netdev(dev
))) {
5414 printk(KERN_ERR PFX
"Cannot register net device\n");
5416 iounmap(bp
->regview
);
5417 pci_release_regions(pdev
);
5418 pci_disable_device(pdev
);
5419 pci_set_drvdata(pdev
, NULL
);
5424 pci_set_drvdata(pdev
, dev
);
5426 memcpy(dev
->dev_addr
, bp
->mac_addr
, 6);
5427 bp
->name
= board_info
[ent
->driver_data
].name
,
5428 printk(KERN_INFO
"%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5432 ((CHIP_ID(bp
) & 0xf000) >> 12) + 'A',
5433 ((CHIP_ID(bp
) & 0x0ff0) >> 4),
5434 ((bp
->flags
& PCIX_FLAG
) ? "-X" : ""),
5435 ((bp
->flags
& PCI_32BIT_FLAG
) ? "32-bit" : "64-bit"),
5440 printk("node addr ");
5441 for (i
= 0; i
< 6; i
++)
5442 printk("%2.2x", dev
->dev_addr
[i
]);
5445 dev
->features
|= NETIF_F_SG
;
5446 if (bp
->flags
& USING_DAC_FLAG
)
5447 dev
->features
|= NETIF_F_HIGHDMA
;
5448 dev
->features
|= NETIF_F_IP_CSUM
;
5450 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
5453 dev
->features
|= NETIF_F_TSO
;
5456 netif_carrier_off(bp
->dev
);
5461 static void __devexit
5462 bnx2_remove_one(struct pci_dev
*pdev
)
5464 struct net_device
*dev
= pci_get_drvdata(pdev
);
5465 struct bnx2
*bp
= dev
->priv
;
5467 flush_scheduled_work();
5469 unregister_netdev(dev
);
5472 iounmap(bp
->regview
);
5475 pci_release_regions(pdev
);
5476 pci_disable_device(pdev
);
5477 pci_set_drvdata(pdev
, NULL
);
5481 bnx2_suspend(struct pci_dev
*pdev
, u32 state
)
5483 struct net_device
*dev
= pci_get_drvdata(pdev
);
5484 struct bnx2
*bp
= dev
->priv
;
5487 if (!netif_running(dev
))
5490 bnx2_netif_stop(bp
);
5491 netif_device_detach(dev
);
5492 del_timer_sync(&bp
->timer
);
5494 reset_code
= BNX2_DRV_MSG_CODE_SUSPEND_WOL
;
5496 reset_code
= BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL
;
5497 bnx2_reset_chip(bp
, reset_code
);
5499 bnx2_set_power_state(bp
, state
);
5504 bnx2_resume(struct pci_dev
*pdev
)
5506 struct net_device
*dev
= pci_get_drvdata(pdev
);
5507 struct bnx2
*bp
= dev
->priv
;
5509 if (!netif_running(dev
))
5512 bnx2_set_power_state(bp
, 0);
5513 netif_device_attach(dev
);
5515 bnx2_netif_start(bp
);
5519 static struct pci_driver bnx2_pci_driver
= {
5520 .name
= DRV_MODULE_NAME
,
5521 .id_table
= bnx2_pci_tbl
,
5522 .probe
= bnx2_init_one
,
5523 .remove
= __devexit_p(bnx2_remove_one
),
5524 .suspend
= bnx2_suspend
,
5525 .resume
= bnx2_resume
,
5528 static int __init
bnx2_init(void)
5530 return pci_module_init(&bnx2_pci_driver
);
5533 static void __exit
bnx2_cleanup(void)
5535 pci_unregister_driver(&bnx2_pci_driver
);
5538 module_init(bnx2_init
);
5539 module_exit(bnx2_cleanup
);