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16dc2c9df8b72c0665d73f54b6e8de9307e0a9c3
[deliverable/linux.git] / drivers / net / bnx2x / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
19
20 /* compilation time flags */
21
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
25
26 #define DRV_MODULE_VERSION "1.70.00-0"
27 #define DRV_MODULE_RELDATE "2011/06/13"
28 #define BNX2X_BC_VER 0x040200
29
30 #if defined(CONFIG_DCB)
31 #define BCM_DCBNL
32 #endif
33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
34 #define BCM_CNIC 1
35 #include "../cnic_if.h"
36 #endif
37
38 #ifdef BCM_CNIC
39 #define BNX2X_MIN_MSIX_VEC_CNT 3
40 #define BNX2X_MSIX_VEC_FP_START 2
41 #else
42 #define BNX2X_MIN_MSIX_VEC_CNT 2
43 #define BNX2X_MSIX_VEC_FP_START 1
44 #endif
45
46 #include <linux/mdio.h>
47
48 #include "bnx2x_reg.h"
49 #include "bnx2x_fw_defs.h"
50 #include "bnx2x_hsi.h"
51 #include "bnx2x_link.h"
52 #include "bnx2x_sp.h"
53 #include "bnx2x_dcb.h"
54 #include "bnx2x_stats.h"
55
56 /* error/debug prints */
57
58 #define DRV_MODULE_NAME "bnx2x"
59
60 /* for messages that are currently off */
61 #define BNX2X_MSG_OFF 0
62 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
64 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
67 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
68
69 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
70
71 /* regular debug print */
72 #define DP(__mask, __fmt, __args...) \
73 do { \
74 if (bp->msg_enable & (__mask)) \
75 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
76 __func__, __LINE__, \
77 bp->dev ? (bp->dev->name) : "?", \
78 ##__args); \
79 } while (0)
80
81 #define DP_CONT(__mask, __fmt, __args...) \
82 do { \
83 if (bp->msg_enable & (__mask)) \
84 pr_cont(__fmt, ##__args); \
85 } while (0)
86
87 /* errors debug print */
88 #define BNX2X_DBG_ERR(__fmt, __args...) \
89 do { \
90 if (netif_msg_probe(bp)) \
91 pr_err("[%s:%d(%s)]" __fmt, \
92 __func__, __LINE__, \
93 bp->dev ? (bp->dev->name) : "?", \
94 ##__args); \
95 } while (0)
96
97 /* for errors (never masked) */
98 #define BNX2X_ERR(__fmt, __args...) \
99 do { \
100 pr_err("[%s:%d(%s)]" __fmt, \
101 __func__, __LINE__, \
102 bp->dev ? (bp->dev->name) : "?", \
103 ##__args); \
104 } while (0)
105
106 #define BNX2X_ERROR(__fmt, __args...) do { \
107 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
108 } while (0)
109
110
111 /* before we have a dev->name use dev_info() */
112 #define BNX2X_DEV_INFO(__fmt, __args...) \
113 do { \
114 if (netif_msg_probe(bp)) \
115 dev_info(&bp->pdev->dev, __fmt, ##__args); \
116 } while (0)
117
118 #define BNX2X_MAC_FMT "%pM"
119 #define BNX2X_MAC_PRN_LIST(mac) (mac)
120
121
122 #ifdef BNX2X_STOP_ON_ERROR
123 #define bnx2x_panic() do { \
124 bp->panic = 1; \
125 BNX2X_ERR("driver assert\n"); \
126 bnx2x_int_disable(bp); \
127 bnx2x_panic_dump(bp); \
128 } while (0)
129 #else
130 #define bnx2x_panic() do { \
131 bp->panic = 1; \
132 BNX2X_ERR("driver assert\n"); \
133 bnx2x_panic_dump(bp); \
134 } while (0)
135 #endif
136
137 #define bnx2x_mc_addr(ha) ((ha)->addr)
138 #define bnx2x_uc_addr(ha) ((ha)->addr)
139
140 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
141 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
142 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
143
144
145 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
146
147 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
148 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
149 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
150
151 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
152 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
153 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
154
155 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
156 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
157
158 #define REG_RD_DMAE(bp, offset, valp, len32) \
159 do { \
160 bnx2x_read_dmae(bp, offset, len32);\
161 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
162 } while (0)
163
164 #define REG_WR_DMAE(bp, offset, valp, len32) \
165 do { \
166 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
167 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
168 offset, len32); \
169 } while (0)
170
171 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
172 REG_WR_DMAE(bp, offset, valp, len32)
173
174 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
175 do { \
176 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
177 bnx2x_write_big_buf_wb(bp, addr, len32); \
178 } while (0)
179
180 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
181 offsetof(struct shmem_region, field))
182 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
183 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
184
185 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
186 offsetof(struct shmem2_region, field))
187 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
188 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
189 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
190 offsetof(struct mf_cfg, field))
191 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
192 offsetof(struct mf2_cfg, field))
193
194 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
195 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
196 MF_CFG_ADDR(bp, field), (val))
197 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
198
199 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
200 (SHMEM2_RD((bp), size) > \
201 offsetof(struct shmem2_region, field)))
202
203 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
204 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
205
206 /* SP SB indices */
207
208 /* General SP events - stats query, cfc delete, etc */
209 #define HC_SP_INDEX_ETH_DEF_CONS 3
210
211 /* EQ completions */
212 #define HC_SP_INDEX_EQ_CONS 7
213
214 /* FCoE L2 connection completions */
215 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
216 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
217 /* iSCSI L2 */
218 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
219 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
220
221 /* Special clients parameters */
222
223 /* SB indices */
224 /* FCoE L2 */
225 #define BNX2X_FCOE_L2_RX_INDEX \
226 (&bp->def_status_blk->sp_sb.\
227 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
228
229 #define BNX2X_FCOE_L2_TX_INDEX \
230 (&bp->def_status_blk->sp_sb.\
231 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
232
233 /**
234 * CIDs and CLIDs:
235 * CLIDs below is a CLID for func 0, then the CLID for other
236 * functions will be calculated by the formula:
237 *
238 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
239 *
240 */
241 /* iSCSI L2 */
242 #define BNX2X_ISCSI_ETH_CL_ID_IDX 1
243 #define BNX2X_ISCSI_ETH_CID 17
244
245 /* FCoE L2 */
246 #define BNX2X_FCOE_ETH_CL_ID_IDX 2
247 #define BNX2X_FCOE_ETH_CID 18
248
249 /** Additional rings budgeting */
250 #ifdef BCM_CNIC
251 #define CNIC_CONTEXT_USE 1
252 #define FCOE_CONTEXT_USE 1
253 #else
254 #define CNIC_CONTEXT_USE 0
255 #define FCOE_CONTEXT_USE 0
256 #endif /* BCM_CNIC */
257 #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE)
258
259 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
260 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
261
262 #define SM_RX_ID 0
263 #define SM_TX_ID 1
264
265 /* fast path */
266
267 struct sw_rx_bd {
268 struct sk_buff *skb;
269 DEFINE_DMA_UNMAP_ADDR(mapping);
270 };
271
272 struct sw_tx_bd {
273 struct sk_buff *skb;
274 u16 first_bd;
275 u8 flags;
276 /* Set on the first BD descriptor when there is a split BD */
277 #define BNX2X_TSO_SPLIT_BD (1<<0)
278 };
279
280 struct sw_rx_page {
281 struct page *page;
282 DEFINE_DMA_UNMAP_ADDR(mapping);
283 };
284
285 union db_prod {
286 struct doorbell_set_prod data;
287 u32 raw;
288 };
289
290
291 /* MC hsi */
292 #define BCM_PAGE_SHIFT 12
293 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
294 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
295 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
296
297 #define PAGES_PER_SGE_SHIFT 0
298 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
299 #define SGE_PAGE_SIZE PAGE_SIZE
300 #define SGE_PAGE_SHIFT PAGE_SHIFT
301 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
302
303 /* SGE ring related macros */
304 #define NUM_RX_SGE_PAGES 2
305 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
306 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
307 /* RX_SGE_CNT is promised to be a power of 2 */
308 #define RX_SGE_MASK (RX_SGE_CNT - 1)
309 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
310 #define MAX_RX_SGE (NUM_RX_SGE - 1)
311 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
312 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
313 #define RX_SGE(x) ((x) & MAX_RX_SGE)
314
315 /* Manipulate a bit vector defined as an array of u64 */
316
317 /* Number of bits in one sge_mask array element */
318 #define BIT_VEC64_ELEM_SZ 64
319 #define BIT_VEC64_ELEM_SHIFT 6
320 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
321
322
323 #define __BIT_VEC64_SET_BIT(el, bit) \
324 do { \
325 el = ((el) | ((u64)0x1 << (bit))); \
326 } while (0)
327
328 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
329 do { \
330 el = ((el) & (~((u64)0x1 << (bit)))); \
331 } while (0)
332
333
334 #define BIT_VEC64_SET_BIT(vec64, idx) \
335 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
336 (idx) & BIT_VEC64_ELEM_MASK)
337
338 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
339 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
340 (idx) & BIT_VEC64_ELEM_MASK)
341
342 #define BIT_VEC64_TEST_BIT(vec64, idx) \
343 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
344 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
345
346 /* Creates a bitmask of all ones in less significant bits.
347 idx - index of the most significant bit in the created mask */
348 #define BIT_VEC64_ONES_MASK(idx) \
349 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
350 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
351
352 /*******************************************************/
353
354
355
356 /* Number of u64 elements in SGE mask array */
357 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
358 BIT_VEC64_ELEM_SZ)
359 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
360 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
361
362 union host_hc_status_block {
363 /* pointer to fp status block e1x */
364 struct host_hc_status_block_e1x *e1x_sb;
365 /* pointer to fp status block e2 */
366 struct host_hc_status_block_e2 *e2_sb;
367 };
368
369 struct bnx2x_agg_info {
370 /*
371 * First aggregation buffer is an skb, the following - are pages.
372 * We will preallocate the skbs for each aggregation when
373 * we open the interface and will replace the BD at the consumer
374 * with this one when we receive the TPA_START CQE in order to
375 * keep the Rx BD ring consistent.
376 */
377 struct sw_rx_bd first_buf;
378 u8 tpa_state;
379 #define BNX2X_TPA_START 1
380 #define BNX2X_TPA_STOP 2
381 #define BNX2X_TPA_ERROR 3
382 u8 placement_offset;
383 u16 parsing_flags;
384 u16 vlan_tag;
385 u16 len_on_bd;
386 };
387
388 #define Q_STATS_OFFSET32(stat_name) \
389 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
390
391 struct bnx2x_fastpath {
392 struct bnx2x *bp; /* parent */
393
394 #define BNX2X_NAPI_WEIGHT 128
395 struct napi_struct napi;
396 union host_hc_status_block status_blk;
397 /* chip independed shortcuts into sb structure */
398 __le16 *sb_index_values;
399 __le16 *sb_running_index;
400 /* chip independed shortcut into rx_prods_offset memory */
401 u32 ustorm_rx_prods_offset;
402
403 u32 rx_buf_size;
404
405 dma_addr_t status_blk_mapping;
406
407 struct sw_tx_bd *tx_buf_ring;
408
409 union eth_tx_bd_types *tx_desc_ring;
410 dma_addr_t tx_desc_mapping;
411
412 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
413 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
414
415 struct eth_rx_bd *rx_desc_ring;
416 dma_addr_t rx_desc_mapping;
417
418 union eth_rx_cqe *rx_comp_ring;
419 dma_addr_t rx_comp_mapping;
420
421 /* SGE ring */
422 struct eth_rx_sge *rx_sge_ring;
423 dma_addr_t rx_sge_mapping;
424
425 u64 sge_mask[RX_SGE_MASK_LEN];
426
427 u32 cid;
428
429 u8 index; /* number in fp array */
430 u8 cl_id; /* eth client id */
431 u8 cl_qzone_id;
432 u8 fw_sb_id; /* status block number in FW */
433 u8 igu_sb_id; /* status block number in HW */
434 union db_prod tx_db;
435
436 u16 tx_pkt_prod;
437 u16 tx_pkt_cons;
438 u16 tx_bd_prod;
439 u16 tx_bd_cons;
440 __le16 *tx_cons_sb;
441
442 __le16 fp_hc_idx;
443
444 u16 rx_bd_prod;
445 u16 rx_bd_cons;
446 u16 rx_comp_prod;
447 u16 rx_comp_cons;
448 u16 rx_sge_prod;
449 /* The last maximal completed SGE */
450 u16 last_max_sge;
451 __le16 *rx_cons_sb;
452 unsigned long tx_pkt,
453 rx_pkt,
454 rx_calls;
455
456 /* TPA related */
457 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
458 u8 disable_tpa;
459 #ifdef BNX2X_STOP_ON_ERROR
460 u64 tpa_queue_used;
461 #endif
462
463 struct tstorm_per_queue_stats old_tclient;
464 struct ustorm_per_queue_stats old_uclient;
465 struct xstorm_per_queue_stats old_xclient;
466 struct bnx2x_eth_q_stats eth_q_stats;
467
468 /* The size is calculated using the following:
469 sizeof name field from netdev structure +
470 4 ('-Xx-' string) +
471 4 (for the digits and to make it DWORD aligned) */
472 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
473 char name[FP_NAME_SIZE];
474
475 /* MACs object */
476 struct bnx2x_vlan_mac_obj mac_obj;
477
478 /* Queue State object */
479 struct bnx2x_queue_sp_obj q_obj;
480
481 };
482
483 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
484
485 /* Use 2500 as a mini-jumbo MTU for FCoE */
486 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
487
488 /* FCoE L2 `fastpath' entry is right after the eth entries */
489 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
490 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
491 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
492
493
494 #ifdef BCM_CNIC
495 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
496 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
497 #else
498 #define IS_FCOE_FP(fp) false
499 #define IS_FCOE_IDX(idx) false
500 #endif
501
502
503 /* MC hsi */
504 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
505 #define RX_COPY_THRESH 92
506
507 #define NUM_TX_RINGS 16
508 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
509 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
510 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
511 #define MAX_TX_BD (NUM_TX_BD - 1)
512 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
513 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
514 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
515 #define TX_BD(x) ((x) & MAX_TX_BD)
516 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
517
518 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
519 #define NUM_RX_RINGS 8
520 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
521 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
522 #define RX_DESC_MASK (RX_DESC_CNT - 1)
523 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
524 #define MAX_RX_BD (NUM_RX_BD - 1)
525 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
526 #define MIN_RX_AVAIL 128
527
528 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
529 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
530 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
531 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
532 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
533 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
534 MIN_RX_AVAIL))
535
536 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
537 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
538 #define RX_BD(x) ((x) & MAX_RX_BD)
539
540 /*
541 * As long as CQE is X times bigger than BD entry we have to allocate X times
542 * more pages for CQ ring in order to keep it balanced with BD ring
543 */
544 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
545 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
546 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
547 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
548 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
549 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
550 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
551 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
552 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
553 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
554
555
556 /* This is needed for determining of last_max */
557 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
558 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
559
560
561 #define BNX2X_SWCID_SHIFT 17
562 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
563
564 /* used on a CID received from the HW */
565 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
566 #define CQE_CMD(x) (le32_to_cpu(x) >> \
567 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
568
569 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
570 le32_to_cpu((bd)->addr_lo))
571 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
572
573 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
574 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
575 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
576 #error "Min DB doorbell stride is 8"
577 #endif
578 #define DPM_TRIGER_TYPE 0x40
579 #define DOORBELL(bp, cid, val) \
580 do { \
581 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
582 DPM_TRIGER_TYPE); \
583 } while (0)
584
585
586 /* TX CSUM helpers */
587 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
588 skb->csum_offset)
589 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
590 skb->csum_offset))
591
592 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
593
594 #define XMIT_PLAIN 0
595 #define XMIT_CSUM_V4 0x1
596 #define XMIT_CSUM_V6 0x2
597 #define XMIT_CSUM_TCP 0x4
598 #define XMIT_GSO_V4 0x8
599 #define XMIT_GSO_V6 0x10
600
601 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
602 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
603
604
605 /* stuff added to make the code fit 80Col */
606 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
607 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
608 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
609 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
610 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
611
612 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
613
614 #define BNX2X_IP_CSUM_ERR(cqe) \
615 (!((cqe)->fast_path_cqe.status_flags & \
616 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
617 ((cqe)->fast_path_cqe.type_error_flags & \
618 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
619
620 #define BNX2X_L4_CSUM_ERR(cqe) \
621 (!((cqe)->fast_path_cqe.status_flags & \
622 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
623 ((cqe)->fast_path_cqe.type_error_flags & \
624 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
625
626 #define BNX2X_RX_CSUM_OK(cqe) \
627 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
628
629 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
630 (((le16_to_cpu(flags) & \
631 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
632 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
633 == PRS_FLAG_OVERETH_IPV4)
634 #define BNX2X_RX_SUM_FIX(cqe) \
635 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
636
637
638 #define FP_USB_FUNC_OFF \
639 offsetof(struct cstorm_status_block_u, func)
640 #define FP_CSB_FUNC_OFF \
641 offsetof(struct cstorm_status_block_c, func)
642
643 #define HC_INDEX_TOE_RX_CQ_CONS 0 /* Formerly Ustorm TOE CQ index */
644 /* (HC_INDEX_U_TOE_RX_CQ_CONS) */
645 #define HC_INDEX_ETH_RX_CQ_CONS 1 /* Formerly Ustorm ETH CQ index */
646 /* (HC_INDEX_U_ETH_RX_CQ_CONS) */
647 #define HC_INDEX_ETH_RX_BD_CONS 2 /* Formerly Ustorm ETH BD index */
648 /* (HC_INDEX_U_ETH_RX_BD_CONS) */
649
650 #define HC_INDEX_TOE_TX_CQ_CONS 4 /* Formerly Cstorm TOE CQ index */
651 /* (HC_INDEX_C_TOE_TX_CQ_CONS) */
652 #define HC_INDEX_ETH_TX_CQ_CONS 5 /* Formerly Cstorm ETH CQ index */
653 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */
654
655 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_ETH_RX_CQ_CONS
656 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_ETH_RX_BD_CONS
657 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_ETH_TX_CQ_CONS
658
659 #define BNX2X_RX_SB_INDEX \
660 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
661
662 #define BNX2X_TX_SB_INDEX \
663 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
664
665 /* end of fast path */
666
667 /* common */
668
669 struct bnx2x_common {
670
671 u32 chip_id;
672 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
673 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
674
675 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
676 #define CHIP_NUM_57710 0x164e
677 #define CHIP_NUM_57711 0x164f
678 #define CHIP_NUM_57711E 0x1650
679 #define CHIP_NUM_57712 0x1662
680 #define CHIP_NUM_57712_MF 0x1663
681 #define CHIP_NUM_57713 0x1651
682 #define CHIP_NUM_57713E 0x1652
683 #define CHIP_NUM_57800 0x168a
684 #define CHIP_NUM_57800_MF 0x16a5
685 #define CHIP_NUM_57810 0x168e
686 #define CHIP_NUM_57810_MF 0x16ae
687 #define CHIP_NUM_57840 0x168d
688 #define CHIP_NUM_57840_MF 0x16ab
689 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
690 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
691 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
692 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
693 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
694 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
695 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
696 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
697 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
698 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
699 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
700 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
701 CHIP_IS_57711E(bp))
702 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
703 CHIP_IS_57712_MF(bp))
704 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
705 CHIP_IS_57800_MF(bp) || \
706 CHIP_IS_57810(bp) || \
707 CHIP_IS_57810_MF(bp) || \
708 CHIP_IS_57840(bp) || \
709 CHIP_IS_57840_MF(bp))
710 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
711 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
712 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
713
714 #define CHIP_REV_SHIFT 12
715 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
716 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
717 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
718 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
719 /* assume maximum 5 revisions */
720 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
721 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
722 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
723 !(CHIP_REV_VAL(bp) & 0x00001000))
724 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
725 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
726 (CHIP_REV_VAL(bp) & 0x00001000))
727
728 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
729 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
730
731 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
732 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
733 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
734 (CHIP_REV_SHIFT + 1)) \
735 << CHIP_REV_SHIFT)
736 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
737 CHIP_REV_SIM(bp) :\
738 CHIP_REV_VAL(bp))
739 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
740 (CHIP_REV(bp) == CHIP_REV_Bx))
741 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
742 (CHIP_REV(bp) == CHIP_REV_Ax))
743
744 int flash_size;
745 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
746 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
747 #define BNX2X_NVRAM_PAGE_SIZE 256
748
749 u32 shmem_base;
750 u32 shmem2_base;
751 u32 mf_cfg_base;
752 u32 mf2_cfg_base;
753
754 u32 hw_config;
755
756 u32 bc_ver;
757
758 u8 int_block;
759 #define INT_BLOCK_HC 0
760 #define INT_BLOCK_IGU 1
761 #define INT_BLOCK_MODE_NORMAL 0
762 #define INT_BLOCK_MODE_BW_COMP 2
763 #define CHIP_INT_MODE_IS_NBC(bp) \
764 (!CHIP_IS_E1x(bp) && \
765 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
766 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
767
768 u8 chip_port_mode;
769 #define CHIP_4_PORT_MODE 0x0
770 #define CHIP_2_PORT_MODE 0x1
771 #define CHIP_PORT_MODE_NONE 0x2
772 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
773 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
774 };
775
776 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
777 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
778 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
779
780 /* end of common */
781
782 /* port */
783
784 struct bnx2x_port {
785 u32 pmf;
786
787 u32 link_config[LINK_CONFIG_SIZE];
788
789 u32 supported[LINK_CONFIG_SIZE];
790 /* link settings - missing defines */
791 #define SUPPORTED_2500baseX_Full (1 << 15)
792
793 u32 advertising[LINK_CONFIG_SIZE];
794 /* link settings - missing defines */
795 #define ADVERTISED_2500baseX_Full (1 << 15)
796
797 u32 phy_addr;
798
799 /* used to synchronize phy accesses */
800 struct mutex phy_mutex;
801 int need_hw_lock;
802
803 u32 port_stx;
804
805 struct nig_stats old_nig_stats;
806 };
807
808 /* end of port */
809
810 #define STATS_OFFSET32(stat_name) \
811 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
812
813 /* slow path */
814
815 /* slow path work-queue */
816 extern struct workqueue_struct *bnx2x_wq;
817
818 #define BNX2X_MAX_NUM_OF_VFS 64
819 #define BNX2X_VF_ID_INVALID 0xFF
820
821 /*
822 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
823 * control by the number of fast-path status blocks supported by the
824 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
825 * status block represents an independent interrupts context that can
826 * serve a regular L2 networking queue. However special L2 queues such
827 * as the FCoE queue do not require a FP-SB and other components like
828 * the CNIC may consume FP-SB reducing the number of possible L2 queues
829 *
830 * If the maximum number of FP-SB available is X then:
831 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
832 * regular L2 queues is Y=X-1
833 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
834 * c. If the FCoE L2 queue is supported the actual number of L2 queues
835 * is Y+1
836 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
837 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
838 * FP interrupt context for the CNIC).
839 * e. The number of HW context (CID count) is always X or X+1 if FCoE
840 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
841 */
842
843 /* fast-path interrupt contexts E1x */
844 #define FP_SB_MAX_E1x 16
845 /* fast-path interrupt contexts E2 */
846 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
847
848 /*
849 * cid_cnt paramter below refers to the value returned by
850 * 'bnx2x_get_l2_cid_count()' routine
851 */
852
853 /*
854 * The number of FP context allocated by the driver == max number of regular
855 * L2 queues + 1 for the FCoE L2 queue
856 */
857 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE)
858
859 /*
860 * The number of FP-SB allocated by the driver == max number of regular L2
861 * queues + 1 for the CNIC which also consumes an FP-SB
862 */
863 #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
864 #define NUM_IGU_SB_REQUIRED(cid_cnt) \
865 (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
866
867 union cdu_context {
868 struct eth_context eth;
869 char pad[1024];
870 };
871
872 /* CDU host DB constants */
873 #define CDU_ILT_PAGE_SZ_HW 3
874 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
875 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
876
877 #ifdef BCM_CNIC
878 #define CNIC_ISCSI_CID_MAX 256
879 #define CNIC_FCOE_CID_MAX 2048
880 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
881 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
882 #endif
883
884 #define QM_ILT_PAGE_SZ_HW 0
885 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
886 #define QM_CID_ROUND 1024
887
888 #ifdef BCM_CNIC
889 /* TM (timers) host DB constants */
890 #define TM_ILT_PAGE_SZ_HW 0
891 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
892 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
893 #define TM_CONN_NUM 1024
894 #define TM_ILT_SZ (8 * TM_CONN_NUM)
895 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
896
897 /* SRC (Searcher) host DB constants */
898 #define SRC_ILT_PAGE_SZ_HW 0
899 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
900 #define SRC_HASH_BITS 10
901 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
902 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
903 #define SRC_T2_SZ SRC_ILT_SZ
904 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
905
906 #endif
907
908 #define MAX_DMAE_C 8
909
910 /* DMA memory not used in fastpath */
911 struct bnx2x_slowpath {
912 union {
913 struct mac_configuration_cmd e1x;
914 struct eth_classify_rules_ramrod_data e2;
915 } mac_rdata;
916
917
918 union {
919 struct tstorm_eth_mac_filter_config e1x;
920 struct eth_filter_rules_ramrod_data e2;
921 } rx_mode_rdata;
922
923 union {
924 struct mac_configuration_cmd e1;
925 struct eth_multicast_rules_ramrod_data e2;
926 } mcast_rdata;
927
928 struct eth_rss_update_ramrod_data rss_rdata;
929
930 /* Queue State related ramrods are always sent under rtnl_lock */
931 union {
932 struct client_init_ramrod_data init_data;
933 struct client_update_ramrod_data update_data;
934 } q_rdata;
935
936 union {
937 struct function_start_data func_start;
938 } func_rdata;
939
940 /* used by dmae command executer */
941 struct dmae_command dmae[MAX_DMAE_C];
942
943 u32 stats_comp;
944 union mac_stats mac_stats;
945 struct nig_stats nig_stats;
946 struct host_port_stats port_stats;
947 struct host_func_stats func_stats;
948 struct host_func_stats func_stats_base;
949
950 u32 wb_comp;
951 u32 wb_data[4];
952 /* pfc configuration for DCBX ramrod */
953 struct flow_control_configuration pfc_config;
954 };
955
956 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
957 #define bnx2x_sp_mapping(bp, var) \
958 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
959
960
961 /* attn group wiring */
962 #define MAX_DYNAMIC_ATTN_GRPS 8
963
964 struct attn_route {
965 u32 sig[5];
966 };
967
968 struct iro {
969 u32 base;
970 u16 m1;
971 u16 m2;
972 u16 m3;
973 u16 size;
974 };
975
976 struct hw_context {
977 union cdu_context *vcxt;
978 dma_addr_t cxt_mapping;
979 size_t size;
980 };
981
982 /* forward */
983 struct bnx2x_ilt;
984
985
986 enum bnx2x_recovery_state {
987 BNX2X_RECOVERY_DONE,
988 BNX2X_RECOVERY_INIT,
989 BNX2X_RECOVERY_WAIT,
990 BNX2X_RECOVERY_FAILED
991 };
992
993 /*
994 * Event queue (EQ or event ring) MC hsi
995 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
996 */
997 #define NUM_EQ_PAGES 1
998 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
999 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1000 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1001 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1002 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1003
1004 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1005 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1006 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1007
1008 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1009 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1010
1011 #define BNX2X_EQ_INDEX \
1012 (&bp->def_status_blk->sp_sb.\
1013 index_values[HC_SP_INDEX_EQ_CONS])
1014
1015 /* This is a data that will be used to create a link report message.
1016 * We will keep the data used for the last link report in order
1017 * to prevent reporting the same link parameters twice.
1018 */
1019 struct bnx2x_link_report_data {
1020 u16 line_speed; /* Effective line speed */
1021 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1022 };
1023
1024 enum {
1025 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1026 BNX2X_LINK_REPORT_LINK_DOWN,
1027 BNX2X_LINK_REPORT_RX_FC_ON,
1028 BNX2X_LINK_REPORT_TX_FC_ON,
1029 };
1030
1031 enum {
1032 BNX2X_PORT_QUERY_IDX,
1033 BNX2X_PF_QUERY_IDX,
1034 BNX2X_FIRST_QUEUE_QUERY_IDX,
1035 };
1036
1037 struct bnx2x_fw_stats_req {
1038 struct stats_query_header hdr;
1039 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1040 };
1041
1042 struct bnx2x_fw_stats_data {
1043 struct stats_counter storm_counters;
1044 struct per_port_stats port;
1045 struct per_pf_stats pf;
1046 struct per_queue_stats queue_stats[1];
1047 };
1048
1049 /* Public slow path states */
1050 enum {
1051 BNX2X_SP_RTNL_TX_TIMEOUT,
1052 };
1053
1054
1055 struct bnx2x {
1056 /* Fields used in the tx and intr/napi performance paths
1057 * are grouped together in the beginning of the structure
1058 */
1059 struct bnx2x_fastpath *fp;
1060 void __iomem *regview;
1061 void __iomem *doorbells;
1062 u16 db_size;
1063
1064 u8 pf_num; /* absolute PF number */
1065 u8 pfid; /* per-path PF number */
1066 int base_fw_ndsb; /**/
1067 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1068 #define BP_PORT(bp) (bp->pfid & 1)
1069 #define BP_FUNC(bp) (bp->pfid)
1070 #define BP_ABS_FUNC(bp) (bp->pf_num)
1071 #define BP_E1HVN(bp) (bp->pfid >> 1)
1072 #define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/
1073 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
1074 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
1075 BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
1076
1077 struct net_device *dev;
1078 struct pci_dev *pdev;
1079
1080 const struct iro *iro_arr;
1081 #define IRO (bp->iro_arr)
1082
1083 enum bnx2x_recovery_state recovery_state;
1084 int is_leader;
1085 struct msix_entry *msix_table;
1086
1087 int tx_ring_size;
1088
1089 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1090 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1091 #define ETH_MIN_PACKET_SIZE 60
1092 #define ETH_MAX_PACKET_SIZE 1500
1093 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1094
1095 /* Max supported alignment is 256 (8 shift) */
1096 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
1097 L1_CACHE_SHIFT : 8)
1098 /* FW use 2 Cache lines Alignment for start packet and size */
1099 #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT)
1100 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1101
1102 struct host_sp_status_block *def_status_blk;
1103 #define DEF_SB_IGU_ID 16
1104 #define DEF_SB_ID HC_SP_SB_ID
1105 __le16 def_idx;
1106 __le16 def_att_idx;
1107 u32 attn_state;
1108 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1109
1110 /* slow path ring */
1111 struct eth_spe *spq;
1112 dma_addr_t spq_mapping;
1113 u16 spq_prod_idx;
1114 struct eth_spe *spq_prod_bd;
1115 struct eth_spe *spq_last_bd;
1116 __le16 *dsb_sp_prod;
1117 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1118 /* used to synchronize spq accesses */
1119 spinlock_t spq_lock;
1120
1121 /* event queue */
1122 union event_ring_elem *eq_ring;
1123 dma_addr_t eq_mapping;
1124 u16 eq_prod;
1125 u16 eq_cons;
1126 __le16 *eq_cons_sb;
1127 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1128
1129
1130
1131 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1132 u16 stats_pending;
1133 /* Counter for completed statistics ramrods */
1134 u16 stats_comp;
1135
1136 /* End of fields used in the performance code paths */
1137
1138 int panic;
1139 int msg_enable;
1140
1141 u32 flags;
1142 #define PCIX_FLAG (1 << 0)
1143 #define PCI_32BIT_FLAG (1 << 1)
1144 #define ONE_PORT_FLAG (1 << 2)
1145 #define NO_WOL_FLAG (1 << 3)
1146 #define USING_DAC_FLAG (1 << 4)
1147 #define USING_MSIX_FLAG (1 << 5)
1148 #define USING_MSI_FLAG (1 << 6)
1149 #define DISABLE_MSI_FLAG (1 << 7)
1150 #define TPA_ENABLE_FLAG (1 << 8)
1151 #define NO_MCP_FLAG (1 << 9)
1152
1153 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1154 #define MF_FUNC_DIS (1 << 11)
1155 #define OWN_CNIC_IRQ (1 << 12)
1156 #define NO_ISCSI_OOO_FLAG (1 << 13)
1157 #define NO_ISCSI_FLAG (1 << 14)
1158 #define NO_FCOE_FLAG (1 << 15)
1159
1160 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1161 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1162 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1163
1164 int pm_cap;
1165 int mrrs;
1166
1167 struct delayed_work sp_task;
1168 struct delayed_work sp_rtnl_task;
1169
1170 struct delayed_work period_task;
1171 struct timer_list timer;
1172 int current_interval;
1173
1174 u16 fw_seq;
1175 u16 fw_drv_pulse_wr_seq;
1176 u32 func_stx;
1177
1178 struct link_params link_params;
1179 struct link_vars link_vars;
1180 u32 link_cnt;
1181 struct bnx2x_link_report_data last_reported_link;
1182
1183 struct mdio_if_info mdio;
1184
1185 struct bnx2x_common common;
1186 struct bnx2x_port port;
1187
1188 struct cmng_struct_per_port cmng;
1189 u32 vn_weight_sum;
1190 u32 mf_config[E1HVN_MAX];
1191 u32 mf2_config[E2_FUNC_MAX];
1192 u32 path_has_ovlan; /* E3 */
1193 u16 mf_ov;
1194 u8 mf_mode;
1195 #define IS_MF(bp) (bp->mf_mode != 0)
1196 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1197 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1198
1199 u8 wol;
1200
1201 int rx_ring_size;
1202
1203 u16 tx_quick_cons_trip_int;
1204 u16 tx_quick_cons_trip;
1205 u16 tx_ticks_int;
1206 u16 tx_ticks;
1207
1208 u16 rx_quick_cons_trip_int;
1209 u16 rx_quick_cons_trip;
1210 u16 rx_ticks_int;
1211 u16 rx_ticks;
1212 /* Maximal coalescing timeout in us */
1213 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1214
1215 u32 lin_cnt;
1216
1217 u16 state;
1218 #define BNX2X_STATE_CLOSED 0
1219 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1220 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1221 #define BNX2X_STATE_OPEN 0x3000
1222 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1223 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1224
1225 #define BNX2X_STATE_DIAG 0xe000
1226 #define BNX2X_STATE_ERROR 0xf000
1227
1228 int multi_mode;
1229 int num_queues;
1230 int disable_tpa;
1231
1232 u32 rx_mode;
1233 #define BNX2X_RX_MODE_NONE 0
1234 #define BNX2X_RX_MODE_NORMAL 1
1235 #define BNX2X_RX_MODE_ALLMULTI 2
1236 #define BNX2X_RX_MODE_PROMISC 3
1237 #define BNX2X_MAX_MULTICAST 64
1238
1239 u8 igu_dsb_id;
1240 u8 igu_base_sb;
1241 u8 igu_sb_cnt;
1242 dma_addr_t def_status_blk_mapping;
1243
1244 struct bnx2x_slowpath *slowpath;
1245 dma_addr_t slowpath_mapping;
1246
1247 /* Total number of FW statistics requests */
1248 u8 fw_stats_num;
1249
1250 /*
1251 * This is a memory buffer that will contain both statistics
1252 * ramrod request and data.
1253 */
1254 void *fw_stats;
1255 dma_addr_t fw_stats_mapping;
1256
1257 /*
1258 * FW statistics request shortcut (points at the
1259 * beginning of fw_stats buffer).
1260 */
1261 struct bnx2x_fw_stats_req *fw_stats_req;
1262 dma_addr_t fw_stats_req_mapping;
1263 int fw_stats_req_sz;
1264
1265 /*
1266 * FW statistics data shortcut (points at the begining of
1267 * fw_stats buffer + fw_stats_req_sz).
1268 */
1269 struct bnx2x_fw_stats_data *fw_stats_data;
1270 dma_addr_t fw_stats_data_mapping;
1271 int fw_stats_data_sz;
1272
1273 struct hw_context context;
1274
1275 struct bnx2x_ilt *ilt;
1276 #define BP_ILT(bp) ((bp)->ilt)
1277 #define ILT_MAX_LINES 256
1278
1279 int l2_cid_count;
1280 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1281 ILT_PAGE_CIDS))
1282 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1283
1284 int qm_cid_count;
1285
1286 int dropless_fc;
1287
1288 #ifdef BCM_CNIC
1289 u32 cnic_flags;
1290 #define BNX2X_CNIC_FLAG_MAC_SET 1
1291 void *t2;
1292 dma_addr_t t2_mapping;
1293 struct cnic_ops __rcu *cnic_ops;
1294 void *cnic_data;
1295 u32 cnic_tag;
1296 struct cnic_eth_dev cnic_eth_dev;
1297 union host_hc_status_block cnic_sb;
1298 dma_addr_t cnic_sb_mapping;
1299 struct eth_spe *cnic_kwq;
1300 struct eth_spe *cnic_kwq_prod;
1301 struct eth_spe *cnic_kwq_cons;
1302 struct eth_spe *cnic_kwq_last;
1303 u16 cnic_kwq_pending;
1304 u16 cnic_spq_pending;
1305 u8 fip_mac[ETH_ALEN];
1306 struct mutex cnic_mutex;
1307 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1308
1309 /* Start index of the "special" (CNIC related) L2 cleints */
1310 u8 cnic_base_cl_id;
1311 #endif
1312
1313 int dmae_ready;
1314 /* used to synchronize dmae accesses */
1315 spinlock_t dmae_lock;
1316
1317 /* used to protect the FW mail box */
1318 struct mutex fw_mb_mutex;
1319
1320 /* used to synchronize stats collecting */
1321 int stats_state;
1322
1323 /* used for synchronization of concurrent threads statistics handling */
1324 spinlock_t stats_lock;
1325
1326 /* used by dmae command loader */
1327 struct dmae_command stats_dmae;
1328 int executer_idx;
1329
1330 u16 stats_counter;
1331 struct bnx2x_eth_stats eth_stats;
1332
1333 struct z_stream_s *strm;
1334 void *gunzip_buf;
1335 dma_addr_t gunzip_mapping;
1336 int gunzip_outlen;
1337 #define FW_BUF_SIZE 0x8000
1338 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1339 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1340 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1341
1342 struct raw_op *init_ops;
1343 /* Init blocks offsets inside init_ops */
1344 u16 *init_ops_offsets;
1345 /* Data blob - has 32 bit granularity */
1346 u32 *init_data;
1347 u32 init_mode_flags;
1348 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1349 /* Zipped PRAM blobs - raw data */
1350 const u8 *tsem_int_table_data;
1351 const u8 *tsem_pram_data;
1352 const u8 *usem_int_table_data;
1353 const u8 *usem_pram_data;
1354 const u8 *xsem_int_table_data;
1355 const u8 *xsem_pram_data;
1356 const u8 *csem_int_table_data;
1357 const u8 *csem_pram_data;
1358 #define INIT_OPS(bp) (bp->init_ops)
1359 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1360 #define INIT_DATA(bp) (bp->init_data)
1361 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1362 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1363 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1364 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1365 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1366 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1367 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1368 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1369
1370 #define PHY_FW_VER_LEN 20
1371 char fw_ver[32];
1372 const struct firmware *firmware;
1373
1374 /* LLDP params */
1375 struct bnx2x_config_lldp_params lldp_config_params;
1376
1377 /* DCB support on/off */
1378 u16 dcb_state;
1379 #define BNX2X_DCB_STATE_OFF 0
1380 #define BNX2X_DCB_STATE_ON 1
1381
1382 /* DCBX engine mode */
1383 int dcbx_enabled;
1384 #define BNX2X_DCBX_ENABLED_OFF 0
1385 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1386 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1387 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1388
1389 bool dcbx_mode_uset;
1390
1391 struct bnx2x_config_dcbx_params dcbx_config_params;
1392 struct bnx2x_dcbx_port_params dcbx_port_params;
1393 int dcb_version;
1394
1395 /* CAM credit pools */
1396 struct bnx2x_credit_pool_obj macs_pool;
1397
1398 /* RX_MODE object */
1399 struct bnx2x_rx_mode_obj rx_mode_obj;
1400
1401 /* MCAST object */
1402 struct bnx2x_mcast_obj mcast_obj;
1403
1404 /* RSS configuration object */
1405 struct bnx2x_rss_config_obj rss_conf_obj;
1406
1407 /* Function State controlling object */
1408 struct bnx2x_func_sp_obj func_obj;
1409
1410 unsigned long sp_state;
1411
1412 /* operation indication for the sp_rtnl task */
1413 unsigned long sp_rtnl_state;
1414
1415 /* DCBX Negotation results */
1416 struct dcbx_features dcbx_local_feat;
1417 u32 dcbx_error;
1418
1419 #ifdef BCM_DCBNL
1420 struct dcbx_features dcbx_remote_feat;
1421 u32 dcbx_remote_flags;
1422 #endif
1423 u32 pending_max;
1424 };
1425
1426 /* Tx queues may be less or equal to Rx queues */
1427 extern int num_queues;
1428 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1429 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
1430
1431 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1432
1433 #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
1434
1435 #define RSS_IPV4_CAP_MASK \
1436 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1437
1438 #define RSS_IPV4_TCP_CAP_MASK \
1439 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1440
1441 #define RSS_IPV6_CAP_MASK \
1442 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1443
1444 #define RSS_IPV6_TCP_CAP_MASK \
1445 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1446
1447 /* func init flags */
1448 #define FUNC_FLG_RSS 0x0001
1449 #define FUNC_FLG_STATS 0x0002
1450 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1451 #define FUNC_FLG_TPA 0x0008
1452 #define FUNC_FLG_SPQ 0x0010
1453 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1454
1455
1456 struct bnx2x_func_init_params {
1457 /* dma */
1458 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1459 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1460
1461 u16 func_flgs;
1462 u16 func_id; /* abs fid */
1463 u16 pf_id;
1464 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1465 };
1466
1467 #define for_each_eth_queue(bp, var) \
1468 for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1469
1470 #define for_each_nondefault_eth_queue(bp, var) \
1471 for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1472
1473 #define for_each_queue(bp, var) \
1474 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1475 if (skip_queue(bp, var)) \
1476 continue; \
1477 else
1478
1479 #define for_each_rx_queue(bp, var) \
1480 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1481 if (skip_rx_queue(bp, var)) \
1482 continue; \
1483 else
1484
1485 #define for_each_tx_queue(bp, var) \
1486 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1487 if (skip_tx_queue(bp, var)) \
1488 continue; \
1489 else
1490
1491 #define for_each_nondefault_queue(bp, var) \
1492 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
1493 if (skip_queue(bp, var)) \
1494 continue; \
1495 else
1496
1497 /* skip rx queue
1498 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1499 */
1500 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1501
1502 /* skip tx queue
1503 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1504 */
1505 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1506
1507 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1508
1509
1510
1511
1512 /**
1513 * bnx2x_set_mac_one - configure a single MAC address
1514 *
1515 * @bp: driver handle
1516 * @mac: MAC to configure
1517 * @obj: MAC object handle
1518 * @set: if 'true' add a new MAC, otherwise - delete
1519 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1520 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1521 *
1522 * Configures one MAC according to provided parameters or continues the
1523 * execution of previously scheduled commands if RAMROD_CONT is set in
1524 * ramrod_flags.
1525 *
1526 * Returns zero if operation has successfully completed, a positive value if the
1527 * operation has been successfully scheduled and a negative - if a requested
1528 * operations has failed.
1529 */
1530 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1531 struct bnx2x_vlan_mac_obj *obj, bool set,
1532 int mac_type, unsigned long *ramrod_flags);
1533 /**
1534 * Deletes all MACs configured for the specific MAC object.
1535 *
1536 * @param bp Function driver instance
1537 * @param mac_obj MAC object to cleanup
1538 *
1539 * @return zero if all MACs were cleaned
1540 */
1541
1542 /**
1543 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1544 *
1545 * @bp: driver handle
1546 * @mac_obj: MAC object handle
1547 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1548 * @wait_for_comp: if 'true' block until completion
1549 *
1550 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1551 *
1552 * Returns zero if operation has successfully completed, a positive value if the
1553 * operation has been successfully scheduled and a negative - if a requested
1554 * operations has failed.
1555 */
1556 int bnx2x_del_all_macs(struct bnx2x *bp,
1557 struct bnx2x_vlan_mac_obj *mac_obj,
1558 int mac_type, bool wait_for_comp);
1559
1560 /* Init Function API */
1561 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1562 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1563 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1564 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1565 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1566 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1567
1568
1569 /* dmae */
1570 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1571 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1572 u32 len32);
1573 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1574 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1575 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1576 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1577 bool with_comp, u8 comp_type);
1578
1579
1580 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1581 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1582 u32 data_hi, u32 data_lo, int cmd_type);
1583 void bnx2x_update_coalesce(struct bnx2x *bp);
1584 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1585
1586 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1587 int wait)
1588 {
1589 u32 val;
1590
1591 do {
1592 val = REG_RD(bp, reg);
1593 if (val == expected)
1594 break;
1595 ms -= wait;
1596 msleep(wait);
1597
1598 } while (ms > 0);
1599
1600 return val;
1601 }
1602
1603 #define BNX2X_ILT_ZALLOC(x, y, size) \
1604 do { \
1605 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1606 if (x) \
1607 memset(x, 0, size); \
1608 } while (0)
1609
1610 #define BNX2X_ILT_FREE(x, y, size) \
1611 do { \
1612 if (x) { \
1613 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1614 x = NULL; \
1615 y = 0; \
1616 } \
1617 } while (0)
1618
1619 #define ILOG2(x) (ilog2((x)))
1620
1621 #define ILT_NUM_PAGE_ENTRIES (3072)
1622 /* In 57710/11 we use whole table since we have 8 func
1623 * In 57712 we have only 4 func, but use same size per func, then only half of
1624 * the table in use
1625 */
1626 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1627
1628 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1629 /*
1630 * the phys address is shifted right 12 bits and has an added
1631 * 1=valid bit added to the 53rd bit
1632 * then since this is a wide register(TM)
1633 * we split it into two 32 bit writes
1634 */
1635 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1636 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1637
1638 /* load/unload mode */
1639 #define LOAD_NORMAL 0
1640 #define LOAD_OPEN 1
1641 #define LOAD_DIAG 2
1642 #define UNLOAD_NORMAL 0
1643 #define UNLOAD_CLOSE 1
1644 #define UNLOAD_RECOVERY 2
1645
1646
1647 /* DMAE command defines */
1648 #define DMAE_TIMEOUT -1
1649 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1650 #define DMAE_NOT_RDY -3
1651 #define DMAE_PCI_ERR_FLAG 0x80000000
1652
1653 #define DMAE_SRC_PCI 0
1654 #define DMAE_SRC_GRC 1
1655
1656 #define DMAE_DST_NONE 0
1657 #define DMAE_DST_PCI 1
1658 #define DMAE_DST_GRC 2
1659
1660 #define DMAE_COMP_PCI 0
1661 #define DMAE_COMP_GRC 1
1662
1663 /* E2 and onward - PCI error handling in the completion */
1664
1665 #define DMAE_COMP_REGULAR 0
1666 #define DMAE_COM_SET_ERR 1
1667
1668 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1669 DMAE_COMMAND_SRC_SHIFT)
1670 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1671 DMAE_COMMAND_SRC_SHIFT)
1672
1673 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1674 DMAE_COMMAND_DST_SHIFT)
1675 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1676 DMAE_COMMAND_DST_SHIFT)
1677
1678 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1679 DMAE_COMMAND_C_DST_SHIFT)
1680 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1681 DMAE_COMMAND_C_DST_SHIFT)
1682
1683 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1684
1685 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1686 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1687 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1688 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1689
1690 #define DMAE_CMD_PORT_0 0
1691 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1692
1693 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1694 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1695 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1696
1697 #define DMAE_SRC_PF 0
1698 #define DMAE_SRC_VF 1
1699
1700 #define DMAE_DST_PF 0
1701 #define DMAE_DST_VF 1
1702
1703 #define DMAE_C_SRC 0
1704 #define DMAE_C_DST 1
1705
1706 #define DMAE_LEN32_RD_MAX 0x80
1707 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1708
1709 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1710 indicates eror */
1711
1712 #define MAX_DMAE_C_PER_PORT 8
1713 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1714 BP_E1HVN(bp))
1715 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1716 E1HVN_MAX)
1717
1718 /* PCIE link and speed */
1719 #define PCICFG_LINK_WIDTH 0x1f00000
1720 #define PCICFG_LINK_WIDTH_SHIFT 20
1721 #define PCICFG_LINK_SPEED 0xf0000
1722 #define PCICFG_LINK_SPEED_SHIFT 16
1723
1724
1725 #define BNX2X_NUM_TESTS 7
1726
1727 #define BNX2X_PHY_LOOPBACK 0
1728 #define BNX2X_MAC_LOOPBACK 1
1729 #define BNX2X_PHY_LOOPBACK_FAILED 1
1730 #define BNX2X_MAC_LOOPBACK_FAILED 2
1731 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1732 BNX2X_PHY_LOOPBACK_FAILED)
1733
1734
1735 #define STROM_ASSERT_ARRAY_SIZE 50
1736
1737
1738 /* must be used on a CID before placing it on a HW ring */
1739 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1740 (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \
1741 (x))
1742
1743 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1744 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1745
1746
1747 #define BNX2X_BTR 4
1748 #define MAX_SPQ_PENDING 8
1749
1750 /* CMNG constants, as derived from system spec calculations */
1751 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1752 #define DEF_MIN_RATE 100
1753 /* resolution of the rate shaping timer - 400 usec */
1754 #define RS_PERIODIC_TIMEOUT_USEC 400
1755 /* number of bytes in single QM arbitration cycle -
1756 * coefficient for calculating the fairness timer */
1757 #define QM_ARB_BYTES 160000
1758 /* resolution of Min algorithm 1:100 */
1759 #define MIN_RES 100
1760 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1761 #define MIN_ABOVE_THRESH 32768
1762 /* Fairness algorithm integration time coefficient -
1763 * for calculating the actual Tfair */
1764 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1765 /* Memory of fairness algorithm . 2 cycles */
1766 #define FAIR_MEM 2
1767
1768
1769 #define ATTN_NIG_FOR_FUNC (1L << 8)
1770 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1771 #define GPIO_2_FUNC (1L << 10)
1772 #define GPIO_3_FUNC (1L << 11)
1773 #define GPIO_4_FUNC (1L << 12)
1774 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1775 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1776 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1777 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1778 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1779 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1780
1781 #define ATTN_HARD_WIRED_MASK 0xff00
1782 #define ATTENTION_ID 4
1783
1784
1785 /* stuff added to make the code fit 80Col */
1786
1787 #define BNX2X_PMF_LINK_ASSERT \
1788 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1789
1790 #define BNX2X_MC_ASSERT_BITS \
1791 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1792 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1793 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1794 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1795
1796 #define BNX2X_MCP_ASSERT \
1797 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1798
1799 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1800 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1801 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1802 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1803 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1804 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1805 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1806
1807 #define HW_INTERRUT_ASSERT_SET_0 \
1808 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1809 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1810 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1811 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1812 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1813 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1814 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1815 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1816 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1817 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1818 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1819 #define HW_INTERRUT_ASSERT_SET_1 \
1820 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1821 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1822 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1823 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1824 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1825 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1826 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1827 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1828 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1829 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1830 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1831 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1832 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1833 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1834 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1835 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1836 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1837 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1838 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1839 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1840 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1841 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1842 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1843 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1844 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1845 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1846 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1847 #define HW_INTERRUT_ASSERT_SET_2 \
1848 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1849 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1850 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1851 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1852 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1853 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1854 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1855 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1856 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1857 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1858 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1859 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1860 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1861
1862 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1863 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1864 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1865 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1866
1867 #define RSS_FLAGS(bp) \
1868 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1869 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1870 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1871 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1872 (bp->multi_mode << \
1873 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1874 #define MULTI_MASK 0x7f
1875
1876
1877 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
1878 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
1879 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
1880 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
1881
1882 #define DEF_USB_IGU_INDEX_OFF \
1883 offsetof(struct cstorm_def_status_block_u, igu_index)
1884 #define DEF_CSB_IGU_INDEX_OFF \
1885 offsetof(struct cstorm_def_status_block_c, igu_index)
1886 #define DEF_XSB_IGU_INDEX_OFF \
1887 offsetof(struct xstorm_def_status_block, igu_index)
1888 #define DEF_TSB_IGU_INDEX_OFF \
1889 offsetof(struct tstorm_def_status_block, igu_index)
1890
1891 #define DEF_USB_SEGMENT_OFF \
1892 offsetof(struct cstorm_def_status_block_u, segment)
1893 #define DEF_CSB_SEGMENT_OFF \
1894 offsetof(struct cstorm_def_status_block_c, segment)
1895 #define DEF_XSB_SEGMENT_OFF \
1896 offsetof(struct xstorm_def_status_block, segment)
1897 #define DEF_TSB_SEGMENT_OFF \
1898 offsetof(struct tstorm_def_status_block, segment)
1899
1900 #define BNX2X_SP_DSB_INDEX \
1901 (&bp->def_status_blk->sp_sb.\
1902 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1903
1904 #define SET_FLAG(value, mask, flag) \
1905 do {\
1906 (value) &= ~(mask);\
1907 (value) |= ((flag) << (mask##_SHIFT));\
1908 } while (0)
1909
1910 #define GET_FLAG(value, mask) \
1911 (((value) & (mask)) >> (mask##_SHIFT))
1912
1913 #define GET_FIELD(value, fname) \
1914 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1915
1916 #define CAM_IS_INVALID(x) \
1917 (GET_FLAG(x.flags, \
1918 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1919 (T_ETH_MAC_COMMAND_INVALIDATE))
1920
1921 /* Number of u32 elements in MC hash array */
1922 #define MC_HASH_SIZE 8
1923 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1924 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1925
1926
1927 #ifndef PXP2_REG_PXP2_INT_STS
1928 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1929 #endif
1930
1931 #ifndef ETH_MAX_RX_CLIENTS_E2
1932 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1933 #endif
1934
1935 #define BNX2X_VPD_LEN 128
1936 #define VENDOR_ID_LEN 4
1937
1938 /* Congestion management fairness mode */
1939 #define CMNG_FNS_NONE 0
1940 #define CMNG_FNS_MINMAX 1
1941
1942 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1943 #define HC_SEG_ACCESS_ATTN 4
1944 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1945
1946 static const u32 dmae_reg_go_c[] = {
1947 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1948 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1949 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1950 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1951 };
1952
1953 void bnx2x_set_ethtool_ops(struct net_device *netdev);
1954 void bnx2x_notify_link_changed(struct bnx2x *bp);
1955 #endif /* bnx2x.h */
Linux kernel - Deliverables
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