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[deliverable/linux.git] / drivers / net / bnx2x / bnx2x_cmn.h
1 /* bnx2x_cmn.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #ifndef BNX2X_CMN_H
18 #define BNX2X_CMN_H
19
20 #include <linux/types.h>
21 #include <linux/netdevice.h>
22
23
24 #include "bnx2x.h"
25
26 extern int num_queues;
27
28 /************************ Macros ********************************/
29 #define BNX2X_PCI_FREE(x, y, size) \
30 do { \
31 if (x) { \
32 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
33 x = NULL; \
34 y = 0; \
35 } \
36 } while (0)
37
38 #define BNX2X_FREE(x) \
39 do { \
40 if (x) { \
41 kfree((void *)x); \
42 x = NULL; \
43 } \
44 } while (0)
45
46 #define BNX2X_PCI_ALLOC(x, y, size) \
47 do { \
48 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
49 if (x == NULL) \
50 goto alloc_mem_err; \
51 memset((void *)x, 0, size); \
52 } while (0)
53
54 #define BNX2X_ALLOC(x, size) \
55 do { \
56 x = kzalloc(size, GFP_KERNEL); \
57 if (x == NULL) \
58 goto alloc_mem_err; \
59 } while (0)
60
61 /*********************** Interfaces ****************************
62 * Functions that need to be implemented by each driver version
63 */
64
65 /**
66 * Initialize link parameters structure variables.
67 *
68 * @param bp
69 * @param load_mode
70 *
71 * @return u8
72 */
73 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
74
75 /**
76 * Configure hw according to link parameters structure.
77 *
78 * @param bp
79 */
80 void bnx2x_link_set(struct bnx2x *bp);
81
82 /**
83 * Query link status
84 *
85 * @param bp
86 * @param is_serdes
87 *
88 * @return 0 - link is UP
89 */
90 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
91
92 /**
93 * Handles link status change
94 *
95 * @param bp
96 */
97 void bnx2x__link_status_update(struct bnx2x *bp);
98
99 /**
100 * Report link status to upper layer
101 *
102 * @param bp
103 */
104 void bnx2x_link_report(struct bnx2x *bp);
105
106 /* None-atomic version of bnx2x_link_report() */
107 void __bnx2x_link_report(struct bnx2x *bp);
108
109 /**
110 * calculates MF speed according to current linespeed and MF
111 * configuration
112 *
113 * @param bp
114 *
115 * @return u16
116 */
117 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
118
119 /**
120 * MSI-X slowpath interrupt handler
121 *
122 * @param irq
123 * @param dev_instance
124 *
125 * @return irqreturn_t
126 */
127 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
128
129 /**
130 * non MSI-X interrupt handler
131 *
132 * @param irq
133 * @param dev_instance
134 *
135 * @return irqreturn_t
136 */
137 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
138 #ifdef BCM_CNIC
139
140 /**
141 * Send command to cnic driver
142 *
143 * @param bp
144 * @param cmd
145 */
146 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
147
148 /**
149 * Provides cnic information for proper interrupt handling
150 *
151 * @param bp
152 */
153 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
154 #endif
155
156 /**
157 * Enable HW interrupts.
158 *
159 * @param bp
160 */
161 void bnx2x_int_enable(struct bnx2x *bp);
162
163 /**
164 * Disable interrupts. This function ensures that there are no
165 * ISRs or SP DPCs (sp_task) are running after it returns.
166 *
167 * @param bp
168 * @param disable_hw if true, disable HW interrupts.
169 */
170 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
171
172 /**
173 * Loads device firmware
174 *
175 * @param bp
176 *
177 * @return int
178 */
179 int bnx2x_init_firmware(struct bnx2x *bp);
180
181 /**
182 * Init HW blocks according to current initialization stage:
183 * COMMON, PORT or FUNCTION.
184 *
185 * @param bp
186 * @param load_code: COMMON, PORT or FUNCTION
187 *
188 * @return int
189 */
190 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
191
192 /**
193 * Init driver internals:
194 * - rings
195 * - status blocks
196 * - etc.
197 *
198 * @param bp
199 * @param load_code COMMON, PORT or FUNCTION
200 */
201 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
202
203 /**
204 * Allocate driver's memory.
205 *
206 * @param bp
207 *
208 * @return int
209 */
210 int bnx2x_alloc_mem(struct bnx2x *bp);
211
212 /**
213 * Release driver's memory.
214 *
215 * @param bp
216 */
217 void bnx2x_free_mem(struct bnx2x *bp);
218
219 /**
220 * Setup eth Client.
221 *
222 * @param bp
223 * @param fp
224 * @param is_leading
225 *
226 * @return int
227 */
228 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
229 int is_leading);
230
231 /**
232 * Set number of queues according to mode
233 *
234 * @param bp
235 *
236 */
237 void bnx2x_set_num_queues(struct bnx2x *bp);
238
239 /**
240 * Cleanup chip internals:
241 * - Cleanup MAC configuration.
242 * - Close clients.
243 * - etc.
244 *
245 * @param bp
246 * @param unload_mode
247 */
248 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
249
250 /**
251 * Acquire HW lock.
252 *
253 * @param bp
254 * @param resource Resource bit which was locked
255 *
256 * @return int
257 */
258 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
259
260 /**
261 * Release HW lock.
262 *
263 * @param bp driver handle
264 * @param resource Resource bit which was locked
265 *
266 * @return int
267 */
268 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
269
270 /**
271 * Configure eth MAC address in the HW according to the value in
272 * netdev->dev_addr.
273 *
274 * @param bp driver handle
275 * @param set
276 */
277 void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
278
279 #ifdef BCM_CNIC
280 /**
281 * Set/Clear FIP MAC(s) at the next enties in the CAM after the ETH
282 * MAC(s). This function will wait until the ramdord completion
283 * returns.
284 *
285 * @param bp driver handle
286 * @param set set or clear the CAM entry
287 *
288 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
289 */
290 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
291
292 /**
293 * Set/Clear ALL_ENODE mcast MAC.
294 *
295 * @param bp
296 * @param set
297 *
298 * @return int
299 */
300 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
301 #endif
302
303 /**
304 * Set MAC filtering configurations.
305 *
306 * @remarks called with netif_tx_lock from dev_mcast.c
307 *
308 * @param dev net_device
309 */
310 void bnx2x_set_rx_mode(struct net_device *dev);
311
312 /**
313 * Configure MAC filtering rules in a FW.
314 *
315 * @param bp driver handle
316 */
317 void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
318
319 /* Parity errors related */
320 void bnx2x_inc_load_cnt(struct bnx2x *bp);
321 u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
322 bool bnx2x_chk_parity_attn(struct bnx2x *bp);
323 bool bnx2x_reset_is_done(struct bnx2x *bp);
324 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
325
326 /**
327 * Perform statistics handling according to event
328 *
329 * @param bp driver handle
330 * @param event bnx2x_stats_event
331 */
332 void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
333
334 /**
335 * Handle ramrods completion
336 *
337 * @param fp fastpath handle for the event
338 * @param rr_cqe eth_rx_cqe
339 */
340 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
341
342 /**
343 * Init/halt function before/after sending
344 * CLIENT_SETUP/CFC_DEL for the first/last client.
345 *
346 * @param bp
347 *
348 * @return int
349 */
350 int bnx2x_func_start(struct bnx2x *bp);
351
352 /**
353 * Prepare ILT configurations according to current driver
354 * parameters.
355 *
356 * @param bp
357 */
358 void bnx2x_ilt_set_info(struct bnx2x *bp);
359
360 /**
361 * Inintialize dcbx protocol
362 *
363 * @param bp
364 */
365 void bnx2x_dcbx_init(struct bnx2x *bp);
366
367 /**
368 * Set power state to the requested value. Currently only D0 and
369 * D3hot are supported.
370 *
371 * @param bp
372 * @param state D0 or D3hot
373 *
374 * @return int
375 */
376 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
377
378 /**
379 * Updates MAX part of MF configuration in HW
380 * (if required)
381 *
382 * @param bp
383 * @param value
384 */
385 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
386
387 /* dev_close main block */
388 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
389
390 /* dev_open main block */
391 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
392
393 /* hard_xmit callback */
394 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
395
396 /* select_queue callback */
397 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
398
399 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
400
401 /* NAPI poll Rx part */
402 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
403
404 /* NAPI poll Tx part */
405 int bnx2x_tx_int(struct bnx2x_fastpath *fp);
406
407 /* suspend/resume callbacks */
408 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
409 int bnx2x_resume(struct pci_dev *pdev);
410
411 /* Release IRQ vectors */
412 void bnx2x_free_irq(struct bnx2x *bp);
413
414 void bnx2x_free_fp_mem(struct bnx2x *bp);
415 int bnx2x_alloc_fp_mem(struct bnx2x *bp);
416
417 void bnx2x_init_rx_rings(struct bnx2x *bp);
418 void bnx2x_free_skbs(struct bnx2x *bp);
419 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
420 void bnx2x_netif_start(struct bnx2x *bp);
421
422 /**
423 * Fill msix_table, request vectors, update num_queues according
424 * to number of available vectors
425 *
426 * @param bp
427 *
428 * @return int
429 */
430 int bnx2x_enable_msix(struct bnx2x *bp);
431
432 /**
433 * Request msi mode from OS, updated internals accordingly
434 *
435 * @param bp
436 *
437 * @return int
438 */
439 int bnx2x_enable_msi(struct bnx2x *bp);
440
441 /**
442 * NAPI callback
443 *
444 * @param napi
445 * @param budget
446 *
447 * @return int
448 */
449 int bnx2x_poll(struct napi_struct *napi, int budget);
450
451 /**
452 * Allocate/release memories outsize main driver structure
453 *
454 * @param bp
455 *
456 * @return int
457 */
458 int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
459 void bnx2x_free_mem_bp(struct bnx2x *bp);
460
461 /**
462 * Change mtu netdev callback
463 *
464 * @param dev
465 * @param new_mtu
466 *
467 * @return int
468 */
469 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
470
471 u32 bnx2x_fix_features(struct net_device *dev, u32 features);
472 int bnx2x_set_features(struct net_device *dev, u32 features);
473
474 /**
475 * tx timeout netdev callback
476 *
477 * @param dev
478 * @param new_mtu
479 *
480 * @return int
481 */
482 void bnx2x_tx_timeout(struct net_device *dev);
483
484 #ifdef BCM_VLAN
485 /**
486 * vlan rx register netdev callback
487 *
488 * @param dev
489 * @param new_mtu
490 *
491 * @return int
492 */
493 void bnx2x_vlan_rx_register(struct net_device *dev,
494 struct vlan_group *vlgrp);
495
496 #endif
497
498 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
499 {
500 barrier(); /* status block is written to by the chip */
501 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
502 }
503
504 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
505 struct bnx2x_fastpath *fp,
506 u16 bd_prod, u16 rx_comp_prod,
507 u16 rx_sge_prod)
508 {
509 struct ustorm_eth_rx_producers rx_prods = {0};
510 int i;
511
512 /* Update producers */
513 rx_prods.bd_prod = bd_prod;
514 rx_prods.cqe_prod = rx_comp_prod;
515 rx_prods.sge_prod = rx_sge_prod;
516
517 /*
518 * Make sure that the BD and SGE data is updated before updating the
519 * producers since FW might read the BD/SGE right after the producer
520 * is updated.
521 * This is only applicable for weak-ordered memory model archs such
522 * as IA-64. The following barrier is also mandatory since FW will
523 * assumes BDs must have buffers.
524 */
525 wmb();
526
527 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
528 REG_WR(bp,
529 BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
530 ((u32 *)&rx_prods)[i]);
531
532 mmiowb(); /* keep prod updates ordered */
533
534 DP(NETIF_MSG_RX_STATUS,
535 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
536 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
537 }
538
539 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
540 u8 segment, u16 index, u8 op,
541 u8 update, u32 igu_addr)
542 {
543 struct igu_regular cmd_data = {0};
544
545 cmd_data.sb_id_and_flags =
546 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
547 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
548 (update << IGU_REGULAR_BUPDATE_SHIFT) |
549 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
550
551 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
552 cmd_data.sb_id_and_flags, igu_addr);
553 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
554
555 /* Make sure that ACK is written */
556 mmiowb();
557 barrier();
558 }
559
560 static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
561 u8 idu_sb_id, bool is_Pf)
562 {
563 u32 data, ctl, cnt = 100;
564 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
565 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
566 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
567 u32 sb_bit = 1 << (idu_sb_id%32);
568 u32 func_encode = BP_FUNC(bp) |
569 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
570 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
571
572 /* Not supported in BC mode */
573 if (CHIP_INT_MODE_IS_BC(bp))
574 return;
575
576 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
577 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
578 IGU_REGULAR_CLEANUP_SET |
579 IGU_REGULAR_BCLEANUP;
580
581 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
582 func_encode << IGU_CTRL_REG_FID_SHIFT |
583 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
584
585 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
586 data, igu_addr_data);
587 REG_WR(bp, igu_addr_data, data);
588 mmiowb();
589 barrier();
590 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
591 ctl, igu_addr_ctl);
592 REG_WR(bp, igu_addr_ctl, ctl);
593 mmiowb();
594 barrier();
595
596 /* wait for clean up to finish */
597 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
598 msleep(20);
599
600
601 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
602 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
603 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
604 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
605 }
606 }
607
608 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
609 u8 storm, u16 index, u8 op, u8 update)
610 {
611 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
612 COMMAND_REG_INT_ACK);
613 struct igu_ack_register igu_ack;
614
615 igu_ack.status_block_index = index;
616 igu_ack.sb_id_and_flags =
617 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
618 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
619 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
620 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
621
622 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
623 (*(u32 *)&igu_ack), hc_addr);
624 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
625
626 /* Make sure that ACK is written */
627 mmiowb();
628 barrier();
629 }
630
631 static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
632 u16 index, u8 op, u8 update)
633 {
634 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
635
636 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
637 igu_addr);
638 }
639
640 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
641 u16 index, u8 op, u8 update)
642 {
643 if (bp->common.int_block == INT_BLOCK_HC)
644 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
645 else {
646 u8 segment;
647
648 if (CHIP_INT_MODE_IS_BC(bp))
649 segment = storm;
650 else if (igu_sb_id != bp->igu_dsb_id)
651 segment = IGU_SEG_ACCESS_DEF;
652 else if (storm == ATTENTION_ID)
653 segment = IGU_SEG_ACCESS_ATTN;
654 else
655 segment = IGU_SEG_ACCESS_DEF;
656 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
657 }
658 }
659
660 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
661 {
662 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
663 COMMAND_REG_SIMD_MASK);
664 u32 result = REG_RD(bp, hc_addr);
665
666 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
667 result, hc_addr);
668
669 barrier();
670 return result;
671 }
672
673 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
674 {
675 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
676 u32 result = REG_RD(bp, igu_addr);
677
678 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
679 result, igu_addr);
680
681 barrier();
682 return result;
683 }
684
685 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
686 {
687 barrier();
688 if (bp->common.int_block == INT_BLOCK_HC)
689 return bnx2x_hc_ack_int(bp);
690 else
691 return bnx2x_igu_ack_int(bp);
692 }
693
694 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
695 {
696 /* Tell compiler that consumer and producer can change */
697 barrier();
698 return fp->tx_pkt_prod != fp->tx_pkt_cons;
699 }
700
701 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
702 {
703 s16 used;
704 u16 prod;
705 u16 cons;
706
707 prod = fp->tx_bd_prod;
708 cons = fp->tx_bd_cons;
709
710 /* NUM_TX_RINGS = number of "next-page" entries
711 It will be used as a threshold */
712 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
713
714 #ifdef BNX2X_STOP_ON_ERROR
715 WARN_ON(used < 0);
716 WARN_ON(used > fp->bp->tx_ring_size);
717 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
718 #endif
719
720 return (s16)(fp->bp->tx_ring_size) - used;
721 }
722
723 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
724 {
725 u16 hw_cons;
726
727 /* Tell compiler that status block fields can change */
728 barrier();
729 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
730 return hw_cons != fp->tx_pkt_cons;
731 }
732
733 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
734 {
735 u16 rx_cons_sb;
736
737 /* Tell compiler that status block fields can change */
738 barrier();
739 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
740 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
741 rx_cons_sb++;
742 return (fp->rx_comp_cons != rx_cons_sb);
743 }
744
745 /**
746 * disables tx from stack point of view
747 *
748 * @param bp
749 */
750 static inline void bnx2x_tx_disable(struct bnx2x *bp)
751 {
752 netif_tx_disable(bp->dev);
753 netif_carrier_off(bp->dev);
754 }
755
756 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
757 struct bnx2x_fastpath *fp, u16 index)
758 {
759 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
760 struct page *page = sw_buf->page;
761 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
762
763 /* Skip "next page" elements */
764 if (!page)
765 return;
766
767 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
768 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
769 __free_pages(page, PAGES_PER_SGE_SHIFT);
770
771 sw_buf->page = NULL;
772 sge->addr_hi = 0;
773 sge->addr_lo = 0;
774 }
775
776 static inline void bnx2x_add_all_napi(struct bnx2x *bp)
777 {
778 int i;
779
780 /* Add NAPI objects */
781 for_each_napi_queue(bp, i)
782 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
783 bnx2x_poll, BNX2X_NAPI_WEIGHT);
784 }
785
786 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
787 {
788 int i;
789
790 for_each_napi_queue(bp, i)
791 netif_napi_del(&bnx2x_fp(bp, i, napi));
792 }
793
794 static inline void bnx2x_disable_msi(struct bnx2x *bp)
795 {
796 if (bp->flags & USING_MSIX_FLAG) {
797 pci_disable_msix(bp->pdev);
798 bp->flags &= ~USING_MSIX_FLAG;
799 } else if (bp->flags & USING_MSI_FLAG) {
800 pci_disable_msi(bp->pdev);
801 bp->flags &= ~USING_MSI_FLAG;
802 }
803 }
804
805 static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
806 {
807 return num_queues ?
808 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
809 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
810 }
811
812 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
813 {
814 int i, j;
815
816 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
817 int idx = RX_SGE_CNT * i - 1;
818
819 for (j = 0; j < 2; j++) {
820 SGE_MASK_CLEAR_BIT(fp, idx);
821 idx--;
822 }
823 }
824 }
825
826 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
827 {
828 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
829 memset(fp->sge_mask, 0xff,
830 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
831
832 /* Clear the two last indices in the page to 1:
833 these are the indices that correspond to the "next" element,
834 hence will never be indicated and should be removed from
835 the calculations. */
836 bnx2x_clear_sge_mask_next_elems(fp);
837 }
838
839 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
840 struct bnx2x_fastpath *fp, u16 index)
841 {
842 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
843 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
844 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
845 dma_addr_t mapping;
846
847 if (unlikely(page == NULL))
848 return -ENOMEM;
849
850 mapping = dma_map_page(&bp->pdev->dev, page, 0,
851 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
852 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
853 __free_pages(page, PAGES_PER_SGE_SHIFT);
854 return -ENOMEM;
855 }
856
857 sw_buf->page = page;
858 dma_unmap_addr_set(sw_buf, mapping, mapping);
859
860 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
861 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
862
863 return 0;
864 }
865
866 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
867 struct bnx2x_fastpath *fp, u16 index)
868 {
869 struct sk_buff *skb;
870 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
871 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
872 dma_addr_t mapping;
873
874 skb = netdev_alloc_skb(bp->dev, fp->rx_buf_size);
875 if (unlikely(skb == NULL))
876 return -ENOMEM;
877
878 mapping = dma_map_single(&bp->pdev->dev, skb->data, fp->rx_buf_size,
879 DMA_FROM_DEVICE);
880 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
881 dev_kfree_skb(skb);
882 return -ENOMEM;
883 }
884
885 rx_buf->skb = skb;
886 dma_unmap_addr_set(rx_buf, mapping, mapping);
887
888 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
889 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
890
891 return 0;
892 }
893
894 /* note that we are not allocating a new skb,
895 * we are just moving one from cons to prod
896 * we are not creating a new mapping,
897 * so there is no need to check for dma_mapping_error().
898 */
899 static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
900 u16 cons, u16 prod)
901 {
902 struct bnx2x *bp = fp->bp;
903 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
904 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
905 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
906 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
907
908 dma_sync_single_for_device(&bp->pdev->dev,
909 dma_unmap_addr(cons_rx_buf, mapping),
910 RX_COPY_THRESH, DMA_FROM_DEVICE);
911
912 prod_rx_buf->skb = cons_rx_buf->skb;
913 dma_unmap_addr_set(prod_rx_buf, mapping,
914 dma_unmap_addr(cons_rx_buf, mapping));
915 *prod_bd = *cons_bd;
916 }
917
918 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
919 struct bnx2x_fastpath *fp, int last)
920 {
921 int i;
922
923 if (fp->disable_tpa)
924 return;
925
926 for (i = 0; i < last; i++)
927 bnx2x_free_rx_sge(bp, fp, i);
928 }
929
930 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
931 struct bnx2x_fastpath *fp, int last)
932 {
933 int i;
934
935 for (i = 0; i < last; i++) {
936 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
937 struct sk_buff *skb = rx_buf->skb;
938
939 if (skb == NULL) {
940 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
941 continue;
942 }
943
944 if (fp->tpa_state[i] == BNX2X_TPA_START)
945 dma_unmap_single(&bp->pdev->dev,
946 dma_unmap_addr(rx_buf, mapping),
947 fp->rx_buf_size, DMA_FROM_DEVICE);
948
949 dev_kfree_skb(skb);
950 rx_buf->skb = NULL;
951 }
952 }
953
954 static inline void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
955 {
956 int i;
957
958 for (i = 1; i <= NUM_TX_RINGS; i++) {
959 struct eth_tx_next_bd *tx_next_bd =
960 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
961
962 tx_next_bd->addr_hi =
963 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
964 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
965 tx_next_bd->addr_lo =
966 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
967 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
968 }
969
970 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
971 fp->tx_db.data.zero_fill1 = 0;
972 fp->tx_db.data.prod = 0;
973
974 fp->tx_pkt_prod = 0;
975 fp->tx_pkt_cons = 0;
976 fp->tx_bd_prod = 0;
977 fp->tx_bd_cons = 0;
978 fp->tx_pkt = 0;
979 }
980
981 static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
982 {
983 int i;
984
985 for_each_tx_queue(bp, i)
986 bnx2x_init_tx_ring_one(&bp->fp[i]);
987 }
988
989 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
990 {
991 int i;
992
993 for (i = 1; i <= NUM_RX_RINGS; i++) {
994 struct eth_rx_bd *rx_bd;
995
996 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
997 rx_bd->addr_hi =
998 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
999 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1000 rx_bd->addr_lo =
1001 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1002 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1003 }
1004 }
1005
1006 static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1007 {
1008 int i;
1009
1010 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1011 struct eth_rx_sge *sge;
1012
1013 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1014 sge->addr_hi =
1015 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1016 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1017
1018 sge->addr_lo =
1019 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1020 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1021 }
1022 }
1023
1024 static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
1025 {
1026 int i;
1027 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
1028 struct eth_rx_cqe_next_page *nextpg;
1029
1030 nextpg = (struct eth_rx_cqe_next_page *)
1031 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
1032 nextpg->addr_hi =
1033 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
1034 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
1035 nextpg->addr_lo =
1036 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
1037 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
1038 }
1039 }
1040
1041 /* Returns the number of actually allocated BDs */
1042 static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
1043 int rx_ring_size)
1044 {
1045 struct bnx2x *bp = fp->bp;
1046 u16 ring_prod, cqe_ring_prod;
1047 int i;
1048
1049 fp->rx_comp_cons = 0;
1050 cqe_ring_prod = ring_prod = 0;
1051
1052 /* This routine is called only during fo init so
1053 * fp->eth_q_stats.rx_skb_alloc_failed = 0
1054 */
1055 for (i = 0; i < rx_ring_size; i++) {
1056 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
1057 fp->eth_q_stats.rx_skb_alloc_failed++;
1058 continue;
1059 }
1060 ring_prod = NEXT_RX_IDX(ring_prod);
1061 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
1062 WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed));
1063 }
1064
1065 if (fp->eth_q_stats.rx_skb_alloc_failed)
1066 BNX2X_ERR("was only able to allocate "
1067 "%d rx skbs on queue[%d]\n",
1068 (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index);
1069
1070 fp->rx_bd_prod = ring_prod;
1071 /* Limit the CQE producer by the CQE ring size */
1072 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
1073 cqe_ring_prod);
1074 fp->rx_pkt = fp->rx_calls = 0;
1075
1076 return i - fp->eth_q_stats.rx_skb_alloc_failed;
1077 }
1078
1079 #ifdef BCM_CNIC
1080 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1081 {
1082 bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
1083 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
1084 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
1085 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
1086 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
1087 bnx2x_fcoe(bp, bp) = bp;
1088 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
1089 bnx2x_fcoe(bp, index) = FCOE_IDX;
1090 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
1091 bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
1092 /* qZone id equals to FW (per path) client id */
1093 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
1094 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
1095 ETH_MAX_RX_CLIENTS_E1H);
1096 /* init shortcut */
1097 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
1098 USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
1099 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
1100
1101 }
1102 #endif
1103
1104 static inline void __storm_memset_struct(struct bnx2x *bp,
1105 u32 addr, size_t size, u32 *data)
1106 {
1107 int i;
1108 for (i = 0; i < size/4; i++)
1109 REG_WR(bp, addr + (i * 4), data[i]);
1110 }
1111
1112 static inline void storm_memset_mac_filters(struct bnx2x *bp,
1113 struct tstorm_eth_mac_filter_config *mac_filters,
1114 u16 abs_fid)
1115 {
1116 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
1117
1118 u32 addr = BAR_TSTRORM_INTMEM +
1119 TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
1120
1121 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
1122 }
1123
1124 static inline void storm_memset_cmng(struct bnx2x *bp,
1125 struct cmng_struct_per_port *cmng,
1126 u8 port)
1127 {
1128 size_t size =
1129 sizeof(struct rate_shaping_vars_per_port) +
1130 sizeof(struct fairness_vars_per_port) +
1131 sizeof(struct safc_struct_per_port) +
1132 sizeof(struct pfc_struct_per_port);
1133
1134 u32 addr = BAR_XSTRORM_INTMEM +
1135 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
1136
1137 __storm_memset_struct(bp, addr, size, (u32 *)cmng);
1138
1139 addr += size + 4 /* SKIP DCB+LLFC */;
1140 size = sizeof(struct cmng_struct_per_port) -
1141 size /* written */ - 4 /*skipped*/;
1142
1143 __storm_memset_struct(bp, addr, size,
1144 (u32 *)(cmng->traffic_type_to_priority_cos));
1145 }
1146
1147 /* HW Lock for shared dual port PHYs */
1148 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1149 void bnx2x_release_phy_lock(struct bnx2x *bp);
1150
1151 /**
1152 * Extracts MAX BW part from MF configuration.
1153 *
1154 * @param bp
1155 * @param mf_cfg
1156 *
1157 * @return u16
1158 */
1159 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1160 {
1161 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1162 FUNC_MF_CFG_MAX_BW_SHIFT;
1163 if (!max_cfg) {
1164 BNX2X_ERR("Illegal configuration detected for Max BW - "
1165 "using 100 instead\n");
1166 max_cfg = 100;
1167 }
1168 return max_cfg;
1169 }
1170
1171 #endif /* BNX2X_CMN_H */
Linux kernel - Deliverables
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