drivers/net/bnx2x.h

   1 /* bnx2x.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  */
  13
  14 #ifndef BNX2X_H
  15 #define BNX2X_H
  16
  17 /* compilation time flags */
  18
  19 /* define this to make the driver freeze on error to allow getting debug info
  20  * (you will need to reboot afterwards) */
  21 /* #define BNX2X_STOP_ON_ERROR */
  22
  23 /* error/debug prints */
  24
  25 #define DRV_MODULE_NAME         "bnx2x"
  26 #define PFX DRV_MODULE_NAME     ": "
  27
  28 /* for messages that are currently off */
  29 #define BNX2X_MSG_OFF                   0
  30 #define BNX2X_MSG_MCP                   0x010000 /* was: NETIF_MSG_HW */
  31 #define BNX2X_MSG_STATS                 0x020000 /* was: NETIF_MSG_TIMER */
  32 #define BNX2X_MSG_NVM                   0x040000 /* was: NETIF_MSG_HW */
  33 #define BNX2X_MSG_DMAE                  0x080000 /* was: NETIF_MSG_HW */
  34 #define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
  35 #define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
  36
  37 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
  38
  39 /* regular debug print */
  40 #define DP(__mask, __fmt, __args...) do { \
  41         if (bp->msglevel & (__mask)) \
  42                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  43                         bp->dev ? (bp->dev->name) : "?", ##__args); \
  44         } while (0)
  45
  46 /* errors debug print */
  47 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
  48         if (bp->msglevel & NETIF_MSG_PROBE) \
  49                 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  50                         bp->dev ? (bp->dev->name) : "?", ##__args); \
  51         } while (0)
  52
  53 /* for errors (never masked) */
  54 #define BNX2X_ERR(__fmt, __args...) do { \
  55         printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  56                 bp->dev ? (bp->dev->name) : "?", ##__args); \
  57         } while (0)
  58
  59 /* before we have a dev->name use dev_info() */
  60 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
  61         if (bp->msglevel & NETIF_MSG_PROBE) \
  62                 dev_info(&bp->pdev->dev, __fmt, ##__args); \
  63         } while (0)
  64
  65
  66 #ifdef BNX2X_STOP_ON_ERROR
  67 #define bnx2x_panic() do { \
  68                 bp->panic = 1; \
  69                 BNX2X_ERR("driver assert\n"); \
  70                 bnx2x_int_disable(bp); \
  71                 bnx2x_panic_dump(bp); \
  72         } while (0)
  73 #else
  74 #define bnx2x_panic() do { \
  75                 BNX2X_ERR("driver assert\n"); \
  76                 bnx2x_panic_dump(bp); \
  77         } while (0)
  78 #endif
  79
  80
  81 #ifdef NETIF_F_HW_VLAN_TX
  82 #define BCM_VLAN                        1
  83 #endif
  84
  85
  86 #define U64_LO(x)                       (u32)(((u64)(x)) & 0xffffffff)
  87 #define U64_HI(x)                       (u32)(((u64)(x)) >> 32)
  88 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
  89
  90
  91 #define REG_ADDR(bp, offset)            (bp->regview + offset)
  92
  93 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
  94 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
  95 #define REG_RD64(bp, offset)            readq(REG_ADDR(bp, offset))
  96
  97 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
  98 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
  99 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
 100 #define REG_WR32(bp, offset, val)       REG_WR(bp, offset, val)
 101
 102 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
 103 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
 104
 105 #define REG_RD_DMAE(bp, offset, valp, len32) \
 106         do { \
 107                 bnx2x_read_dmae(bp, offset, len32);\
 108                 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
 109         } while (0)
 110
 111 #define REG_WR_DMAE(bp, offset, valp, len32) \
 112         do { \
 113                 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
 114                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
 115                                  offset, len32); \
 116         } while (0)
 117
 118 #define SHMEM_ADDR(bp, field)           (bp->common.shmem_base + \
 119                                          offsetof(struct shmem_region, field))
 120 #define SHMEM_RD(bp, field)             REG_RD(bp, SHMEM_ADDR(bp, field))
 121 #define SHMEM_WR(bp, field, val)        REG_WR(bp, SHMEM_ADDR(bp, field), val)
 122
 123 #define EMAC_RD(bp, reg)                REG_RD(bp, emac_base + reg)
 124 #define EMAC_WR(bp, reg, val)           REG_WR(bp, emac_base + reg, val)
 125
 126
 127 /* fast path */
 128
 129 struct sw_rx_bd {
 130         struct sk_buff  *skb;
 131         DECLARE_PCI_UNMAP_ADDR(mapping)
 132 };
 133
 134 struct sw_tx_bd {
 135         struct sk_buff  *skb;
 136         u16             first_bd;
 137 };
 138
 139 struct sw_rx_page {
 140         struct page     *page;
 141         DECLARE_PCI_UNMAP_ADDR(mapping)
 142 };
 143
 144
 145 /* MC hsi */
 146 #define BCM_PAGE_SHIFT                  12
 147 #define BCM_PAGE_SIZE                   (1 << BCM_PAGE_SHIFT)
 148 #define BCM_PAGE_MASK                   (~(BCM_PAGE_SIZE - 1))
 149 #define BCM_PAGE_ALIGN(addr)    (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
 150
 151 #define PAGES_PER_SGE_SHIFT             0
 152 #define PAGES_PER_SGE                   (1 << PAGES_PER_SGE_SHIFT)
 153
 154 /* SGE ring related macros */
 155 #define NUM_RX_SGE_PAGES                2
 156 #define RX_SGE_CNT              (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 157 #define MAX_RX_SGE_CNT                  (RX_SGE_CNT - 2)
 158 /* RX_SGE_CNT is promised to be a power of 2 */
 159 #define RX_SGE_MASK                     (RX_SGE_CNT - 1)
 160 #define NUM_RX_SGE                      (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 161 #define MAX_RX_SGE                      (NUM_RX_SGE - 1)
 162 #define NEXT_SGE_IDX(x)         ((((x) & RX_SGE_MASK) == \
 163                                   (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
 164 #define RX_SGE(x)                       ((x) & MAX_RX_SGE)
 165
 166 /* SGE producer mask related macros */
 167 /* Number of bits in one sge_mask array element */
 168 #define RX_SGE_MASK_ELEM_SZ             64
 169 #define RX_SGE_MASK_ELEM_SHIFT          6
 170 #define RX_SGE_MASK_ELEM_MASK           ((u64)RX_SGE_MASK_ELEM_SZ - 1)
 171
 172 /* Creates a bitmask of all ones in less significant bits.
 173    idx - index of the most significant bit in the created mask */
 174 #define RX_SGE_ONES_MASK(idx) \
 175                 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
 176 #define RX_SGE_MASK_ELEM_ONE_MASK       ((u64)(~0))
 177
 178 /* Number of u64 elements in SGE mask array */
 179 #define RX_SGE_MASK_LEN                 ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
 180                                          RX_SGE_MASK_ELEM_SZ)
 181 #define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 182 #define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 183
 184
 185 struct bnx2x_fastpath {
 186
 187         struct napi_struct      napi;
 188
 189         struct host_status_block *status_blk;
 190         dma_addr_t              status_blk_mapping;
 191
 192         struct eth_tx_db_data   *hw_tx_prods;
 193         dma_addr_t              tx_prods_mapping;
 194
 195         struct sw_tx_bd         *tx_buf_ring;
 196
 197         struct eth_tx_bd        *tx_desc_ring;
 198         dma_addr_t              tx_desc_mapping;
 199
 200         struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
 201         struct sw_rx_page       *rx_page_ring;  /* SGE pages mappings ring */
 202
 203         struct eth_rx_bd        *rx_desc_ring;
 204         dma_addr_t              rx_desc_mapping;
 205
 206         union eth_rx_cqe        *rx_comp_ring;
 207         dma_addr_t              rx_comp_mapping;
 208
 209         /* SGE ring */
 210         struct eth_rx_sge       *rx_sge_ring;
 211         dma_addr_t              rx_sge_mapping;
 212
 213         u64                     sge_mask[RX_SGE_MASK_LEN];
 214
 215         int                     state;
 216 #define BNX2X_FP_STATE_CLOSED           0
 217 #define BNX2X_FP_STATE_IRQ              0x80000
 218 #define BNX2X_FP_STATE_OPENING          0x90000
 219 #define BNX2X_FP_STATE_OPEN             0xa0000
 220 #define BNX2X_FP_STATE_HALTING          0xb0000
 221 #define BNX2X_FP_STATE_HALTED           0xc0000
 222
 223         u8                      index;  /* number in fp array */
 224         u8                      cl_id;  /* eth client id */
 225         u8                      sb_id;  /* status block number in HW */
 226 #define FP_IDX(fp)                      (fp->index)
 227 #define FP_CL_ID(fp)                    (fp->cl_id)
 228 #define BP_CL_ID(bp)                    (bp->fp[0].cl_id)
 229 #define FP_SB_ID(fp)                    (fp->sb_id)
 230 #define CNIC_SB_ID                      0
 231
 232         u16                     tx_pkt_prod;
 233         u16                     tx_pkt_cons;
 234         u16                     tx_bd_prod;
 235         u16                     tx_bd_cons;
 236         u16                     *tx_cons_sb;
 237
 238         u16                     fp_c_idx;
 239         u16                     fp_u_idx;
 240
 241         u16                     rx_bd_prod;
 242         u16                     rx_bd_cons;
 243         u16                     rx_comp_prod;
 244         u16                     rx_comp_cons;
 245         u16                     rx_sge_prod;
 246         /* The last maximal completed SGE */
 247         u16                     last_max_sge;
 248         u16                     *rx_cons_sb;
 249         u16                     *rx_bd_cons_sb;
 250
 251         unsigned long           tx_pkt,
 252                                 rx_pkt,
 253                                 rx_calls;
 254         /* TPA related */
 255         struct sw_rx_bd         tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
 256         u8                      tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
 257 #define BNX2X_TPA_START                 1
 258 #define BNX2X_TPA_STOP                  2
 259         u8                      disable_tpa;
 260 #ifdef BNX2X_STOP_ON_ERROR
 261         u64                     tpa_queue_used;
 262 #endif
 263
 264         struct bnx2x            *bp; /* parent */
 265 };
 266
 267 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
 268
 269 #define BNX2X_HAS_TX_WORK(fp) \
 270                         ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
 271                          (fp->tx_pkt_prod != fp->tx_pkt_cons))
 272
 273 #define BNX2X_HAS_RX_WORK(fp) \
 274                         (fp->rx_comp_cons != rx_cons_sb)
 275
 276 #define BNX2X_HAS_WORK(fp)      (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
 277
 278
 279 /* MC hsi */
 280 #define MAX_FETCH_BD                    13      /* HW max BDs per packet */
 281 #define RX_COPY_THRESH                  92
 282
 283 #define NUM_TX_RINGS                    16
 284 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
 285 #define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
 286 #define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
 287 #define MAX_TX_BD                       (NUM_TX_BD - 1)
 288 #define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 289 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
 290                                   (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 291 #define TX_BD(x)                        ((x) & MAX_TX_BD)
 292 #define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
 293
 294 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
 295 #define NUM_RX_RINGS                    8
 296 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
 297 #define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
 298 #define RX_DESC_MASK                    (RX_DESC_CNT - 1)
 299 #define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
 300 #define MAX_RX_BD                       (NUM_RX_BD - 1)
 301 #define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
 302 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
 303                                   (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
 304 #define RX_BD(x)                        ((x) & MAX_RX_BD)
 305
 306 /* As long as CQE is 4 times bigger than BD entry we have to allocate
 307    4 times more pages for CQ ring in order to keep it balanced with
 308    BD ring */
 309 #define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 4)
 310 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
 311 #define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
 312 #define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
 313 #define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
 314 #define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 315 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
 316                                   (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 317 #define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
 318
 319
 320 /* This is needed for determining of last_max */
 321 #define SUB_S16(a, b)                   (s16)((s16)(a) - (s16)(b))
 322
 323 #define __SGE_MASK_SET_BIT(el, bit) \
 324         do { \
 325                 el = ((el) | ((u64)0x1 << (bit))); \
 326         } while (0)
 327
 328 #define __SGE_MASK_CLEAR_BIT(el, bit) \
 329         do { \
 330                 el = ((el) & (~((u64)0x1 << (bit)))); \
 331         } while (0)
 332
 333 #define SGE_MASK_SET_BIT(fp, idx) \
 334         __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
 335                            ((idx) & RX_SGE_MASK_ELEM_MASK))
 336
 337 #define SGE_MASK_CLEAR_BIT(fp, idx) \
 338         __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
 339                              ((idx) & RX_SGE_MASK_ELEM_MASK))
 340
 341
 342 /* used on a CID received from the HW */
 343 #define SW_CID(x)                       (le32_to_cpu(x) & \
 344                                          (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
 345 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
 346                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 347
 348 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
 349                                                  le32_to_cpu((bd)->addr_lo))
 350 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
 351
 352
 353 #define DPM_TRIGER_TYPE                 0x40
 354 #define DOORBELL(bp, cid, val) \
 355         do { \
 356                 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
 357                        DPM_TRIGER_TYPE); \
 358         } while (0)
 359
 360
 361 /* TX CSUM helpers */
 362 #define SKB_CS_OFF(skb)         (offsetof(struct tcphdr, check) - \
 363                                  skb->csum_offset)
 364 #define SKB_CS(skb)             (*(u16 *)(skb_transport_header(skb) + \
 365                                           skb->csum_offset))
 366
 367 #define pbd_tcp_flags(skb)      (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
 368
 369 #define XMIT_PLAIN                      0
 370 #define XMIT_CSUM_V4                    0x1
 371 #define XMIT_CSUM_V6                    0x2
 372 #define XMIT_CSUM_TCP                   0x4
 373 #define XMIT_GSO_V4                     0x8
 374 #define XMIT_GSO_V6                     0x10
 375
 376 #define XMIT_CSUM                       (XMIT_CSUM_V4 | XMIT_CSUM_V6)
 377 #define XMIT_GSO                        (XMIT_GSO_V4 | XMIT_GSO_V6)
 378
 379
 380 /* stuff added to make the code fit 80Col */
 381
 382 #define CQE_TYPE(cqe_fp_flags)  ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
 383
 384 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
 385 #define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
 386 #define TPA_TYPE(cqe_fp_flags)          ((cqe_fp_flags) & \
 387                                          (TPA_TYPE_START | TPA_TYPE_END))
 388
 389 #define ETH_RX_ERROR_FALGS              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
 390
 391 #define BNX2X_IP_CSUM_ERR(cqe) \
 392                         (!((cqe)->fast_path_cqe.status_flags & \
 393                            ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
 394                          ((cqe)->fast_path_cqe.type_error_flags & \
 395                           ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
 396
 397 #define BNX2X_L4_CSUM_ERR(cqe) \
 398                         (!((cqe)->fast_path_cqe.status_flags & \
 399                            ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
 400                          ((cqe)->fast_path_cqe.type_error_flags & \
 401                           ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
 402
 403 #define BNX2X_RX_CSUM_OK(cqe) \
 404                         (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
 405
 406 #define BNX2X_RX_SUM_FIX(cqe) \
 407                         ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
 408                           PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
 409                          (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
 410
 411
 412 #define FP_USB_FUNC_OFF                 (2 + 2*HC_USTORM_SB_NUM_INDICES)
 413 #define FP_CSB_FUNC_OFF                 (2 + 2*HC_CSTORM_SB_NUM_INDICES)
 414
 415 #define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_U_ETH_RX_CQ_CONS
 416 #define U_SB_ETH_RX_BD_INDEX            HC_INDEX_U_ETH_RX_BD_CONS
 417 #define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_C_ETH_TX_CQ_CONS
 418
 419 #define BNX2X_RX_SB_INDEX \
 420         (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
 421
 422 #define BNX2X_RX_SB_BD_INDEX \
 423         (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
 424
 425 #define BNX2X_RX_SB_INDEX_NUM \
 426                 (((U_SB_ETH_RX_CQ_INDEX << \
 427                    USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
 428                   USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
 429                  ((U_SB_ETH_RX_BD_INDEX << \
 430                    USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
 431                   USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
 432
 433 #define BNX2X_TX_SB_INDEX \
 434         (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
 435
 436
 437 /* end of fast path */
 438
 439 /* common */
 440
 441 struct bnx2x_common {
 442
 443         u32                     chip_id;
 444 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 445 #define CHIP_ID(bp)                     (bp->common.chip_id & 0xfffffff0)
 446
 447 #define CHIP_NUM(bp)                    (bp->common.chip_id >> 16)
 448 #define CHIP_NUM_57710                  0x164e
 449 #define CHIP_NUM_57711                  0x164f
 450 #define CHIP_NUM_57711E                 0x1650
 451 #define CHIP_IS_E1(bp)                  (CHIP_NUM(bp) == CHIP_NUM_57710)
 452 #define CHIP_IS_57711(bp)               (CHIP_NUM(bp) == CHIP_NUM_57711)
 453 #define CHIP_IS_57711E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711E)
 454 #define CHIP_IS_E1H(bp)                 (CHIP_IS_57711(bp) || \
 455                                          CHIP_IS_57711E(bp))
 456 #define IS_E1H_OFFSET                   CHIP_IS_E1H(bp)
 457
 458 #define CHIP_REV(bp)                    (bp->common.chip_id & 0x0000f000)
 459 #define CHIP_REV_Ax                     0x00000000
 460 /* assume maximum 5 revisions */
 461 #define CHIP_REV_IS_SLOW(bp)            (CHIP_REV(bp) > 0x00005000)
 462 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
 463 #define CHIP_REV_IS_EMUL(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 464                                          !(CHIP_REV(bp) & 0x00001000))
 465 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
 466 #define CHIP_REV_IS_FPGA(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 467                                          (CHIP_REV(bp) & 0x00001000))
 468
 469 #define CHIP_TIME(bp)                   ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
 470                                         ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
 471
 472 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 473 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
 474
 475         int                     flash_size;
 476 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
 477 #define NVRAM_TIMEOUT_COUNT             30000
 478 #define NVRAM_PAGE_SIZE                 256
 479
 480         u32                     shmem_base;
 481
 482         u32                     hw_config;
 483         u32                     board;
 484
 485         u32                     bc_ver;
 486
 487         char                    *name;
 488 };
 489
 490
 491 /* end of common */
 492
 493 /* port */
 494
 495 struct nig_stats {
 496         u32 brb_discard;
 497         u32 brb_packet;
 498         u32 brb_truncate;
 499         u32 flow_ctrl_discard;
 500         u32 flow_ctrl_octets;
 501         u32 flow_ctrl_packet;
 502         u32 mng_discard;
 503         u32 mng_octet_inp;
 504         u32 mng_octet_out;
 505         u32 mng_packet_inp;
 506         u32 mng_packet_out;
 507         u32 pbf_octets;
 508         u32 pbf_packet;
 509         u32 safc_inp;
 510         u32 egress_mac_pkt0_lo;
 511         u32 egress_mac_pkt0_hi;
 512         u32 egress_mac_pkt1_lo;
 513         u32 egress_mac_pkt1_hi;
 514 };
 515
 516 struct bnx2x_port {
 517         u32                     pmf;
 518
 519         u32                     link_config;
 520
 521         u32                     supported;
 522 /* link settings - missing defines */
 523 #define SUPPORTED_2500baseX_Full        (1 << 15)
 524
 525         u32                     advertising;
 526 /* link settings - missing defines */
 527 #define ADVERTISED_2500baseX_Full       (1 << 15)
 528
 529         u32                     phy_addr;
 530
 531         /* used to synchronize phy accesses */
 532         struct mutex            phy_mutex;
 533
 534         u32                     port_stx;
 535
 536         struct nig_stats        old_nig_stats;
 537 };
 538
 539 /* end of port */
 540
 541
 542 enum bnx2x_stats_event {
 543         STATS_EVENT_PMF = 0,
 544         STATS_EVENT_LINK_UP,
 545         STATS_EVENT_UPDATE,
 546         STATS_EVENT_STOP,
 547         STATS_EVENT_MAX
 548 };
 549
 550 enum bnx2x_stats_state {
 551         STATS_STATE_DISABLED = 0,
 552         STATS_STATE_ENABLED,
 553         STATS_STATE_MAX
 554 };
 555
 556 struct bnx2x_eth_stats {
 557         u32 total_bytes_received_hi;
 558         u32 total_bytes_received_lo;
 559         u32 total_bytes_transmitted_hi;
 560         u32 total_bytes_transmitted_lo;
 561         u32 total_unicast_packets_received_hi;
 562         u32 total_unicast_packets_received_lo;
 563         u32 total_multicast_packets_received_hi;
 564         u32 total_multicast_packets_received_lo;
 565         u32 total_broadcast_packets_received_hi;
 566         u32 total_broadcast_packets_received_lo;
 567         u32 total_unicast_packets_transmitted_hi;
 568         u32 total_unicast_packets_transmitted_lo;
 569         u32 total_multicast_packets_transmitted_hi;
 570         u32 total_multicast_packets_transmitted_lo;
 571         u32 total_broadcast_packets_transmitted_hi;
 572         u32 total_broadcast_packets_transmitted_lo;
 573         u32 valid_bytes_received_hi;
 574         u32 valid_bytes_received_lo;
 575
 576         u32 error_bytes_received_hi;
 577         u32 error_bytes_received_lo;
 578
 579         u32 rx_stat_ifhcinbadoctets_hi;
 580         u32 rx_stat_ifhcinbadoctets_lo;
 581         u32 tx_stat_ifhcoutbadoctets_hi;
 582         u32 tx_stat_ifhcoutbadoctets_lo;
 583         u32 rx_stat_dot3statsfcserrors_hi;
 584         u32 rx_stat_dot3statsfcserrors_lo;
 585         u32 rx_stat_dot3statsalignmenterrors_hi;
 586         u32 rx_stat_dot3statsalignmenterrors_lo;
 587         u32 rx_stat_dot3statscarriersenseerrors_hi;
 588         u32 rx_stat_dot3statscarriersenseerrors_lo;
 589         u32 rx_stat_falsecarriererrors_hi;
 590         u32 rx_stat_falsecarriererrors_lo;
 591         u32 rx_stat_etherstatsundersizepkts_hi;
 592         u32 rx_stat_etherstatsundersizepkts_lo;
 593         u32 rx_stat_dot3statsframestoolong_hi;
 594         u32 rx_stat_dot3statsframestoolong_lo;
 595         u32 rx_stat_etherstatsfragments_hi;
 596         u32 rx_stat_etherstatsfragments_lo;
 597         u32 rx_stat_etherstatsjabbers_hi;
 598         u32 rx_stat_etherstatsjabbers_lo;
 599         u32 rx_stat_maccontrolframesreceived_hi;
 600         u32 rx_stat_maccontrolframesreceived_lo;
 601         u32 rx_stat_bmac_xpf_hi;
 602         u32 rx_stat_bmac_xpf_lo;
 603         u32 rx_stat_bmac_xcf_hi;
 604         u32 rx_stat_bmac_xcf_lo;
 605         u32 rx_stat_xoffstateentered_hi;
 606         u32 rx_stat_xoffstateentered_lo;
 607         u32 rx_stat_xonpauseframesreceived_hi;
 608         u32 rx_stat_xonpauseframesreceived_lo;
 609         u32 rx_stat_xoffpauseframesreceived_hi;
 610         u32 rx_stat_xoffpauseframesreceived_lo;
 611         u32 tx_stat_outxonsent_hi;
 612         u32 tx_stat_outxonsent_lo;
 613         u32 tx_stat_outxoffsent_hi;
 614         u32 tx_stat_outxoffsent_lo;
 615         u32 tx_stat_flowcontroldone_hi;
 616         u32 tx_stat_flowcontroldone_lo;
 617         u32 tx_stat_etherstatscollisions_hi;
 618         u32 tx_stat_etherstatscollisions_lo;
 619         u32 tx_stat_dot3statssinglecollisionframes_hi;
 620         u32 tx_stat_dot3statssinglecollisionframes_lo;
 621         u32 tx_stat_dot3statsmultiplecollisionframes_hi;
 622         u32 tx_stat_dot3statsmultiplecollisionframes_lo;
 623         u32 tx_stat_dot3statsdeferredtransmissions_hi;
 624         u32 tx_stat_dot3statsdeferredtransmissions_lo;
 625         u32 tx_stat_dot3statsexcessivecollisions_hi;
 626         u32 tx_stat_dot3statsexcessivecollisions_lo;
 627         u32 tx_stat_dot3statslatecollisions_hi;
 628         u32 tx_stat_dot3statslatecollisions_lo;
 629         u32 tx_stat_etherstatspkts64octets_hi;
 630         u32 tx_stat_etherstatspkts64octets_lo;
 631         u32 tx_stat_etherstatspkts65octetsto127octets_hi;
 632         u32 tx_stat_etherstatspkts65octetsto127octets_lo;
 633         u32 tx_stat_etherstatspkts128octetsto255octets_hi;
 634         u32 tx_stat_etherstatspkts128octetsto255octets_lo;
 635         u32 tx_stat_etherstatspkts256octetsto511octets_hi;
 636         u32 tx_stat_etherstatspkts256octetsto511octets_lo;
 637         u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
 638         u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
 639         u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
 640         u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
 641         u32 tx_stat_etherstatspktsover1522octets_hi;
 642         u32 tx_stat_etherstatspktsover1522octets_lo;
 643         u32 tx_stat_bmac_2047_hi;
 644         u32 tx_stat_bmac_2047_lo;
 645         u32 tx_stat_bmac_4095_hi;
 646         u32 tx_stat_bmac_4095_lo;
 647         u32 tx_stat_bmac_9216_hi;
 648         u32 tx_stat_bmac_9216_lo;
 649         u32 tx_stat_bmac_16383_hi;
 650         u32 tx_stat_bmac_16383_lo;
 651         u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
 652         u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
 653         u32 tx_stat_bmac_ufl_hi;
 654         u32 tx_stat_bmac_ufl_lo;
 655
 656         u32 brb_drop_hi;
 657         u32 brb_drop_lo;
 658         u32 brb_truncate_hi;
 659         u32 brb_truncate_lo;
 660
 661         u32 jabber_packets_received;
 662
 663         u32 etherstatspkts1024octetsto1522octets_hi;
 664         u32 etherstatspkts1024octetsto1522octets_lo;
 665         u32 etherstatspktsover1522octets_hi;
 666         u32 etherstatspktsover1522octets_lo;
 667
 668         u32 no_buff_discard;
 669
 670         u32 mac_filter_discard;
 671         u32 xxoverflow_discard;
 672         u32 brb_truncate_discard;
 673         u32 mac_discard;
 674
 675         u32 driver_xoff;
 676         u32 rx_err_discard_pkt;
 677         u32 rx_skb_alloc_failed;
 678         u32 hw_csum_err;
 679 };
 680
 681 #define STATS_OFFSET32(stat_name) \
 682                         (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
 683
 684
 685 #ifdef BNX2X_MULTI
 686 #define MAX_CONTEXT                     16
 687 #else
 688 #define MAX_CONTEXT                     1
 689 #endif
 690
 691 union cdu_context {
 692         struct eth_context eth;
 693         char pad[1024];
 694 };
 695
 696 #define MAX_DMAE_C                      8
 697
 698 /* DMA memory not used in fastpath */
 699 struct bnx2x_slowpath {
 700         union cdu_context               context[MAX_CONTEXT];
 701         struct eth_stats_query          fw_stats;
 702         struct mac_configuration_cmd    mac_config;
 703         struct mac_configuration_cmd    mcast_config;
 704
 705         /* used by dmae command executer */
 706         struct dmae_command             dmae[MAX_DMAE_C];
 707
 708         u32                             stats_comp;
 709         union mac_stats                 mac_stats;
 710         struct nig_stats                nig_stats;
 711         struct host_port_stats          port_stats;
 712         struct host_func_stats          func_stats;
 713
 714         u32                             wb_comp;
 715         u32                             wb_data[4];
 716 };
 717
 718 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
 719 #define bnx2x_sp_mapping(bp, var) \
 720                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
 721
 722
 723 /* attn group wiring */
 724 #define MAX_DYNAMIC_ATTN_GRPS           8
 725
 726 struct attn_route {
 727         u32     sig[4];
 728 };
 729
 730 struct bnx2x {
 731         /* Fields used in the tx and intr/napi performance paths
 732          * are grouped together in the beginning of the structure
 733          */
 734         struct bnx2x_fastpath   fp[MAX_CONTEXT];
 735         void __iomem            *regview;
 736         void __iomem            *doorbells;
 737 #define BNX2X_DB_SIZE           (16*2048)
 738
 739         struct net_device       *dev;
 740         struct pci_dev          *pdev;
 741
 742         atomic_t                intr_sem;
 743         struct msix_entry       msix_table[MAX_CONTEXT+1];
 744
 745         int                     tx_ring_size;
 746
 747 #ifdef BCM_VLAN
 748         struct vlan_group       *vlgrp;
 749 #endif
 750
 751         u32                     rx_csum;
 752         u32                     rx_offset;
 753         u32                     rx_buf_use_size;        /* useable size */
 754         u32                     rx_buf_size;            /* with alignment */
 755 #define ETH_OVREHEAD                    (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
 756 #define ETH_MIN_PACKET_SIZE             60
 757 #define ETH_MAX_PACKET_SIZE             1500
 758 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
 759
 760         struct host_def_status_block *def_status_blk;
 761 #define DEF_SB_ID                       16
 762         u16                     def_c_idx;
 763         u16                     def_u_idx;
 764         u16                     def_x_idx;
 765         u16                     def_t_idx;
 766         u16                     def_att_idx;
 767         u32                     attn_state;
 768         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
 769         u32                     nig_mask;
 770
 771         /* slow path ring */
 772         struct eth_spe          *spq;
 773         dma_addr_t              spq_mapping;
 774         u16                     spq_prod_idx;
 775         struct eth_spe          *spq_prod_bd;
 776         struct eth_spe          *spq_last_bd;
 777         u16                     *dsb_sp_prod;
 778         u16                     spq_left; /* serialize spq */
 779         /* used to synchronize spq accesses */
 780         spinlock_t              spq_lock;
 781
 782         /* Flags for marking that there is a STAT_QUERY or
 783            SET_MAC ramrod pending */
 784         u8                      stats_pending;
 785         u8                      set_mac_pending;
 786
 787         /* End of fields used in the performance code paths */
 788
 789         int                     panic;
 790         int                     msglevel;
 791
 792         u32                     flags;
 793 #define PCIX_FLAG                       1
 794 #define PCI_32BIT_FLAG                  2
 795 #define ONE_TDMA_FLAG                   4       /* no longer used */
 796 #define NO_WOL_FLAG                     8
 797 #define USING_DAC_FLAG                  0x10
 798 #define USING_MSIX_FLAG                 0x20
 799 #define ASF_ENABLE_FLAG                 0x40
 800 #define TPA_ENABLE_FLAG                 0x80
 801 #define NO_MCP_FLAG                     0x100
 802 #define BP_NOMCP(bp)                    (bp->flags & NO_MCP_FLAG)
 803
 804         int                     func;
 805 #define BP_PORT(bp)                     (bp->func % PORT_MAX)
 806 #define BP_FUNC(bp)                     (bp->func)
 807 #define BP_E1HVN(bp)                    (bp->func >> 1)
 808 #define BP_L_ID(bp)                     (BP_E1HVN(bp) << 2)
 809
 810         int                     pm_cap;
 811         int                     pcie_cap;
 812
 813         struct work_struct      sp_task;
 814         struct work_struct      reset_task;
 815
 816         struct timer_list       timer;
 817         int                     timer_interval;
 818         int                     current_interval;
 819
 820         u16                     fw_seq;
 821         u16                     fw_drv_pulse_wr_seq;
 822         u32                     func_stx;
 823
 824         struct link_params      link_params;
 825         struct link_vars        link_vars;
 826
 827         struct bnx2x_common     common;
 828         struct bnx2x_port       port;
 829
 830         u32                     mf_config;
 831         u16                     e1hov;
 832         u8                      e1hmf;
 833 #define IS_E1HMF(bp)                    (bp->e1hmf != 0)
 834
 835         u8                      wol;
 836
 837         int                     rx_ring_size;
 838
 839         u16                     tx_quick_cons_trip_int;
 840         u16                     tx_quick_cons_trip;
 841         u16                     tx_ticks_int;
 842         u16                     tx_ticks;
 843
 844         u16                     rx_quick_cons_trip_int;
 845         u16                     rx_quick_cons_trip;
 846         u16                     rx_ticks_int;
 847         u16                     rx_ticks;
 848
 849         u32                     lin_cnt;
 850
 851         int                     state;
 852 #define BNX2X_STATE_CLOSED              0x0
 853 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
 854 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
 855 #define BNX2X_STATE_OPEN                0x3000
 856 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
 857 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
 858 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
 859 #define BNX2X_STATE_DISABLED            0xd000
 860 #define BNX2X_STATE_DIAG                0xe000
 861 #define BNX2X_STATE_ERROR               0xf000
 862
 863         int                     num_queues;
 864 #define BP_MAX_QUEUES(bp)               (IS_E1HMF(bp) ? 4 : 16)
 865
 866         u32                     rx_mode;
 867 #define BNX2X_RX_MODE_NONE              0
 868 #define BNX2X_RX_MODE_NORMAL            1
 869 #define BNX2X_RX_MODE_ALLMULTI          2
 870 #define BNX2X_RX_MODE_PROMISC           3
 871 #define BNX2X_MAX_MULTICAST             64
 872 #define BNX2X_MAX_EMUL_MULTI            16
 873
 874         dma_addr_t              def_status_blk_mapping;
 875
 876         struct bnx2x_slowpath   *slowpath;
 877         dma_addr_t              slowpath_mapping;
 878
 879 #ifdef BCM_ISCSI
 880         void                    *t1;
 881         dma_addr_t              t1_mapping;
 882         void                    *t2;
 883         dma_addr_t              t2_mapping;
 884         void                    *timers;
 885         dma_addr_t              timers_mapping;
 886         void                    *qm;
 887         dma_addr_t              qm_mapping;
 888 #endif
 889
 890         int                     dmae_ready;
 891         /* used to synchronize dmae accesses */
 892         struct mutex            dmae_mutex;
 893         struct dmae_command     init_dmae;
 894
 895         /* used to synchronize stats collecting */
 896         int                     stats_state;
 897         /* used by dmae command loader */
 898         struct dmae_command     stats_dmae;
 899         int                     executer_idx;
 900
 901         u16                     stats_counter;
 902         struct tstorm_per_client_stats old_tclient;
 903         struct xstorm_per_client_stats old_xclient;
 904         struct bnx2x_eth_stats  eth_stats;
 905
 906         struct z_stream_s       *strm;
 907         void                    *gunzip_buf;
 908         dma_addr_t              gunzip_mapping;
 909         int                     gunzip_outlen;
 910 #define FW_BUF_SIZE                     0x8000
 911
 912 };
 913
 914
 915 #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
 916
 917 #define for_each_nondefault_queue(bp, var) \
 918                                 for (var = 1; var < bp->num_queues; var++)
 919 #define is_multi(bp)            (bp->num_queues > 1)
 920
 921
 922 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
 923 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 924                       u32 len32);
 925 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
 926
 927 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 928                            int wait)
 929 {
 930         u32 val;
 931
 932         do {
 933                 val = REG_RD(bp, reg);
 934                 if (val == expected)
 935                         break;
 936                 ms -= wait;
 937                 msleep(wait);
 938
 939         } while (ms > 0);
 940
 941         return val;
 942 }
 943
 944
 945 /* load/unload mode */
 946 #define LOAD_NORMAL                     0
 947 #define LOAD_OPEN                       1
 948 #define LOAD_DIAG                       2
 949 #define UNLOAD_NORMAL                   0
 950 #define UNLOAD_CLOSE                    1
 951
 952
 953 /* DMAE command defines */
 954 #define DMAE_CMD_SRC_PCI                0
 955 #define DMAE_CMD_SRC_GRC                DMAE_COMMAND_SRC
 956
 957 #define DMAE_CMD_DST_PCI                (1 << DMAE_COMMAND_DST_SHIFT)
 958 #define DMAE_CMD_DST_GRC                (2 << DMAE_COMMAND_DST_SHIFT)
 959
 960 #define DMAE_CMD_C_DST_PCI              0
 961 #define DMAE_CMD_C_DST_GRC              (1 << DMAE_COMMAND_C_DST_SHIFT)
 962
 963 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
 964
 965 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
 966 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
 967 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
 968 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
 969
 970 #define DMAE_CMD_PORT_0                 0
 971 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
 972
 973 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
 974 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
 975 #define DMAE_CMD_E1HVN_SHIFT            DMAE_COMMAND_E1HVN_SHIFT
 976
 977 #define DMAE_LEN32_RD_MAX               0x80
 978 #define DMAE_LEN32_WR_MAX               0x400
 979
 980 #define DMAE_COMP_VAL                   0xe0d0d0ae
 981
 982 #define MAX_DMAE_C_PER_PORT             8
 983 #define INIT_DMAE_C(bp)                 (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
 984                                          BP_E1HVN(bp))
 985 #define PMF_DMAE_C(bp)                  (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
 986                                          E1HVN_MAX)
 987
 988
 989 /* PCIE link and speed */
 990 #define PCICFG_LINK_WIDTH               0x1f00000
 991 #define PCICFG_LINK_WIDTH_SHIFT         20
 992 #define PCICFG_LINK_SPEED               0xf0000
 993 #define PCICFG_LINK_SPEED_SHIFT         16
 994
 995
 996 #define BNX2X_NUM_STATS                 42
 997 #define BNX2X_NUM_TESTS                 8
 998
 999 #define BNX2X_MAC_LOOPBACK              0
1000 #define BNX2X_PHY_LOOPBACK              1
1001 #define BNX2X_MAC_LOOPBACK_FAILED       1
1002 #define BNX2X_PHY_LOOPBACK_FAILED       2
1003 #define BNX2X_LOOPBACK_FAILED           (BNX2X_MAC_LOOPBACK_FAILED | \
1004                                          BNX2X_PHY_LOOPBACK_FAILED)
1005
1006
1007 #define STROM_ASSERT_ARRAY_SIZE         50
1008
1009
1010 /* must be used on a CID before placing it on a HW ring */
1011 #define HW_CID(bp, x)           ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1012
1013 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1014 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
1015
1016
1017 #define BNX2X_BTR                       3
1018 #define MAX_SPQ_PENDING                 8
1019
1020
1021 /* CMNG constants
1022    derived from lab experiments, and not from system spec calculations !!! */
1023 #define DEF_MIN_RATE                    100
1024 /* resolution of the rate shaping timer - 100 usec */
1025 #define RS_PERIODIC_TIMEOUT_USEC        100
1026 /* resolution of fairness algorithm in usecs -
1027    coefficient for calculating the actual t fair */
1028 #define T_FAIR_COEF                     10000000
1029 /* number of bytes in single QM arbitration cycle -
1030    coefficient for calculating the fairness timer */
1031 #define QM_ARB_BYTES                    40000
1032 #define FAIR_MEM                        2
1033
1034
1035 #define ATTN_NIG_FOR_FUNC               (1L << 8)
1036 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
1037 #define GPIO_2_FUNC                     (1L << 10)
1038 #define GPIO_3_FUNC                     (1L << 11)
1039 #define GPIO_4_FUNC                     (1L << 12)
1040 #define ATTN_GENERAL_ATTN_1             (1L << 13)
1041 #define ATTN_GENERAL_ATTN_2             (1L << 14)
1042 #define ATTN_GENERAL_ATTN_3             (1L << 15)
1043 #define ATTN_GENERAL_ATTN_4             (1L << 13)
1044 #define ATTN_GENERAL_ATTN_5             (1L << 14)
1045 #define ATTN_GENERAL_ATTN_6             (1L << 15)
1046
1047 #define ATTN_HARD_WIRED_MASK            0xff00
1048 #define ATTENTION_ID                    4
1049
1050
1051 /* stuff added to make the code fit 80Col */
1052
1053 #define BNX2X_PMF_LINK_ASSERT \
1054         GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1055
1056 #define BNX2X_MC_ASSERT_BITS \
1057         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1058          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1059          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1060          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1061
1062 #define BNX2X_MCP_ASSERT \
1063         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1064
1065 #define BNX2X_DOORQ_ASSERT \
1066         AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1067
1068 #define BNX2X_GRC_TIMEOUT       GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1069 #define BNX2X_GRC_RSV           (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1070                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1071                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1072                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1073                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1074                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1075
1076 #define HW_INTERRUT_ASSERT_SET_0 \
1077                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1078                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1079                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1080                                  AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1081 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1082                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1083                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1084                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1085                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1086 #define HW_INTERRUT_ASSERT_SET_1 \
1087                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1088                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1089                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1090                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1091                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1092                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1093                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1094                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1095                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1096                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1097                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1098 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1099                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1100                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1101                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1102                                 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1103                             AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1104                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1105                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1106                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1107                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1108                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1109 #define HW_INTERRUT_ASSERT_SET_2 \
1110                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1111                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1112                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1113                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1114                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1115 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1116                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1117                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1118                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1119                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1120                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1121                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1122
1123
1124 #define MULTI_FLAGS \
1125                 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1126                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1127                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1128                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1129                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1130
1131 #define MULTI_MASK                      0x7f
1132
1133
1134 #define DEF_USB_FUNC_OFF                (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1135 #define DEF_CSB_FUNC_OFF                (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1136 #define DEF_XSB_FUNC_OFF                (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1137 #define DEF_TSB_FUNC_OFF                (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1138
1139 #define C_DEF_SB_SP_INDEX               HC_INDEX_DEF_C_ETH_SLOW_PATH
1140
1141 #define BNX2X_SP_DSB_INDEX \
1142 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1143
1144
1145 #define CAM_IS_INVALID(x) \
1146 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1147
1148 #define CAM_INVALIDATE(x) \
1149         (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1150
1151
1152 /* Number of u32 elements in MC hash array */
1153 #define MC_HASH_SIZE                    8
1154 #define MC_HASH_OFFSET(bp, i)           (BAR_TSTRORM_INTMEM + \
1155         TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1156
1157
1158 #ifndef PXP2_REG_PXP2_INT_STS
1159 #define PXP2_REG_PXP2_INT_STS           PXP2_REG_PXP2_INT_STS_0
1160 #endif
1161
1162 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1163
1164 #endif /* bnx2x.h */