1 /* bnx2x_init.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
20 #define INIT_EMULATION 0x1
23 #define INIT_HARDWARE 0x7
25 #define STORM_INTMEM_SIZE_E1 (0x5800 / 4)
26 #define STORM_INTMEM_SIZE_E1H (0x10000 / 4)
27 #define TSTORM_INTMEM_ADDR 0x1a0000
28 #define CSTORM_INTMEM_ADDR 0x220000
29 #define XSTORM_INTMEM_ADDR 0x2a0000
30 #define USTORM_INTMEM_ADDR 0x320000
33 /* Init operation types and structures */
34 /* Common for both E1 and E1H */
35 #define OP_RD 0x1 /* read single register */
36 #define OP_WR 0x2 /* write single register */
37 #define OP_IW 0x3 /* write single register using mailbox */
38 #define OP_SW 0x4 /* copy a string to the device */
39 #define OP_SI 0x5 /* copy a string using mailbox */
40 #define OP_ZR 0x6 /* clear memory */
41 #define OP_ZP 0x7 /* unzip then copy with DMAE */
42 #define OP_WR_64 0x8 /* write 64 bit pattern */
43 #define OP_WB 0x9 /* copy a string using DMAE */
45 /* Operation specific for E1 */
46 #define OP_RD_E1 0xa /* read single register */
47 #define OP_WR_E1 0xb /* write single register */
48 #define OP_IW_E1 0xc /* write single register using mailbox */
49 #define OP_SW_E1 0xd /* copy a string to the device */
50 #define OP_SI_E1 0xe /* copy a string using mailbox */
51 #define OP_ZR_E1 0xf /* clear memory */
52 #define OP_ZP_E1 0x10 /* unzip then copy with DMAE */
53 #define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */
54 #define OP_WB_E1 0x12 /* copy a string using DMAE */
56 /* Operation specific for E1H */
57 #define OP_RD_E1H 0x13 /* read single register */
58 #define OP_WR_E1H 0x14 /* write single register */
59 #define OP_IW_E1H 0x15 /* write single register using mailbox */
60 #define OP_SW_E1H 0x16 /* copy a string to the device */
61 #define OP_SI_E1H 0x17 /* copy a string using mailbox */
62 #define OP_ZR_E1H 0x18 /* clear memory */
63 #define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */
64 #define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */
65 #define OP_WB_E1H 0x1b /* copy a string using DMAE */
67 /* FPGA and EMUL specific operations */
68 #define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */
69 #define OP_WR_EMUL 0x1d /* write single register on Emulation */
70 #define OP_WR_FPGA 0x1e /* write single register on FPGA */
71 #define OP_WR_ASIC 0x1f /* write single register on ASIC */
92 struct op_string_write
{
95 #ifdef __LITTLE_ENDIAN
98 #else /* __BIG_ENDIAN */
112 struct op_write write
;
113 struct op_string_write str_wr
;
118 #include "bnx2x_init_values.h"
120 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
);
121 static int bnx2x_gunzip(struct bnx2x
*bp
, u8
*zbuf
, int len
);
123 static void bnx2x_init_str_wr(struct bnx2x
*bp
, u32 addr
, const u32
*data
,
128 for (i
= 0; i
< len
; i
++) {
129 REG_WR(bp
, addr
+ i
*4, data
[i
]);
131 touch_softlockup_watchdog();
137 static void bnx2x_init_ind_wr(struct bnx2x
*bp
, u32 addr
, const u32
*data
,
142 for (i
= 0; i
< len
; i
++) {
143 REG_WR_IND(bp
, addr
+ i
*4, data
[i
]);
145 touch_softlockup_watchdog();
151 static void bnx2x_write_big_buf(struct bnx2x
*bp
, u32 addr
, u32 len
)
156 if (bp
->dmae_ready
) {
157 while (len
> DMAE_LEN32_WR_MAX
) {
158 bnx2x_write_dmae(bp
, bp
->gunzip_mapping
+ offset
,
159 addr
+ offset
, DMAE_LEN32_WR_MAX
);
160 offset
+= DMAE_LEN32_WR_MAX
* 4;
161 len
-= DMAE_LEN32_WR_MAX
;
163 bnx2x_write_dmae(bp
, bp
->gunzip_mapping
+ offset
,
166 bnx2x_init_str_wr(bp
, addr
, bp
->gunzip_buf
, len
);
168 bnx2x_init_str_wr(bp
, addr
, bp
->gunzip_buf
, len
);
172 static void bnx2x_init_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
174 if ((len
* 4) > FW_BUF_SIZE
) {
175 BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n",
179 memset(bp
->gunzip_buf
, fill
, len
* 4);
181 bnx2x_write_big_buf(bp
, addr
, len
);
184 static void bnx2x_init_wr_64(struct bnx2x
*bp
, u32 addr
, const u32
*data
,
187 u32 buf_len32
= FW_BUF_SIZE
/4;
192 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
193 data64
= HILO_U64((*(data
+ 1)), (*data
));
194 len64
= min((u32
)(FW_BUF_SIZE
/8), len64
);
195 for (i
= 0; i
< len64
; i
++) {
196 u64
*pdata
= ((u64
*)(bp
->gunzip_buf
)) + i
;
201 for (i
= 0; i
< len
; i
+= buf_len32
) {
202 u32 cur_len
= min(buf_len32
, len
- i
);
204 bnx2x_write_big_buf(bp
, addr
+ i
* 4, cur_len
);
208 /*********************************************************
209 There are different blobs for each PRAM section.
210 In addition, each blob write operation is divided into a few operations
211 in order to decrease the amount of phys. contiguous buffer needed.
212 Thus, when we select a blob the address may be with some offset
213 from the beginning of PRAM section.
214 The same holds for the INT_TABLE sections.
215 **********************************************************/
216 #define IF_IS_INT_TABLE_ADDR(base, addr) \
217 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
219 #define IF_IS_PRAM_ADDR(base, addr) \
220 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
222 static const u32
*bnx2x_sel_blob(u32 addr
, const u32
*data
, int is_e1
)
224 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE
, addr
)
225 data
= is_e1
? tsem_int_table_data_e1
:
226 tsem_int_table_data_e1h
;
228 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE
, addr
)
229 data
= is_e1
? csem_int_table_data_e1
:
230 csem_int_table_data_e1h
;
232 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE
, addr
)
233 data
= is_e1
? usem_int_table_data_e1
:
234 usem_int_table_data_e1h
;
236 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE
, addr
)
237 data
= is_e1
? xsem_int_table_data_e1
:
238 xsem_int_table_data_e1h
;
240 IF_IS_PRAM_ADDR(TSEM_REG_PRAM
, addr
)
241 data
= is_e1
? tsem_pram_data_e1
: tsem_pram_data_e1h
;
243 IF_IS_PRAM_ADDR(CSEM_REG_PRAM
, addr
)
244 data
= is_e1
? csem_pram_data_e1
: csem_pram_data_e1h
;
246 IF_IS_PRAM_ADDR(USEM_REG_PRAM
, addr
)
247 data
= is_e1
? usem_pram_data_e1
: usem_pram_data_e1h
;
249 IF_IS_PRAM_ADDR(XSEM_REG_PRAM
, addr
)
250 data
= is_e1
? xsem_pram_data_e1
: xsem_pram_data_e1h
;
255 static void bnx2x_init_wr_wb(struct bnx2x
*bp
, u32 addr
, const u32
*data
,
256 u32 len
, int gunzip
, int is_e1
, u32 blob_off
)
260 data
= bnx2x_sel_blob(addr
, data
, is_e1
) + blob_off
;
268 temp
= kmalloc(len
, GFP_KERNEL
);
269 size
= (len
/ 4) + ((len
% 4) ? 1 : 0);
270 for (i
= 0; i
< size
; i
++)
271 temp
[i
] = swab32(data
[i
]);
274 rc
= bnx2x_gunzip(bp
, (u8
*)data
, len
);
276 BNX2X_ERR("gunzip failed ! rc %d\n", rc
);
282 len
= bp
->gunzip_outlen
;
285 for (i
= 0; i
< len
; i
++)
286 ((u32
*)bp
->gunzip_buf
)[i
] =
287 swab32(((u32
*)bp
->gunzip_buf
)[i
]);
290 if ((len
* 4) > FW_BUF_SIZE
) {
291 BNX2X_ERR("LARGE DMAE OPERATION ! "
292 "addr 0x%x len 0x%x\n", addr
, len
*4);
295 memcpy(bp
->gunzip_buf
, data
, len
* 4);
298 if (bp
->dmae_ready
) {
299 while (len
> DMAE_LEN32_WR_MAX
) {
300 bnx2x_write_dmae(bp
, bp
->gunzip_mapping
+ offset
,
301 addr
+ offset
, DMAE_LEN32_WR_MAX
);
302 offset
+= DMAE_LEN32_WR_MAX
* 4;
303 len
-= DMAE_LEN32_WR_MAX
;
305 bnx2x_write_dmae(bp
, bp
->gunzip_mapping
+ offset
,
308 bnx2x_init_ind_wr(bp
, addr
, bp
->gunzip_buf
, len
);
311 static void bnx2x_init_block(struct bnx2x
*bp
, u32 op_start
, u32 op_end
)
313 int is_e1
= CHIP_IS_E1(bp
);
314 int is_e1h
= CHIP_IS_E1H(bp
);
315 int is_emul_e1h
= (CHIP_REV_IS_EMUL(bp
) && is_e1h
);
318 u32 op_type
, addr
, len
;
319 const u32
*data
, *data_base
;
321 if (CHIP_REV_IS_FPGA(bp
))
323 else if (CHIP_REV_IS_EMUL(bp
))
329 data_base
= init_data_e1
;
330 else /* CHIP_IS_E1H(bp) */
331 data_base
= init_data_e1h
;
333 for (i
= op_start
; i
< op_end
; i
++) {
335 op
= (union init_op
*)&(init_ops
[i
]);
337 op_type
= op
->str_wr
.op
;
338 addr
= op
->str_wr
.offset
;
339 len
= op
->str_wr
.data_len
;
340 data
= data_base
+ op
->str_wr
.data_off
;
342 /* careful! it must be in order */
343 if (unlikely(op_type
> OP_WB
)) {
346 if (op_type
<= OP_WB_E1
) {
348 op_type
-= (OP_RD_E1
- OP_RD
);
351 } else if (op_type
<= OP_WB_E1H
) {
353 op_type
-= (OP_RD_E1H
- OP_RD
);
356 /* HW/EMUL specific */
357 if (op_type
== hw_wr
)
360 /* EMUL on E1H is special */
361 if ((op_type
== OP_WR_EMUL_E1H
) && is_emul_e1h
)
370 REG_WR(bp
, addr
, op
->write
.val
);
373 bnx2x_init_str_wr(bp
, addr
, data
, len
);
376 bnx2x_init_wr_wb(bp
, addr
, data
, len
, 0, is_e1
, 0);
379 bnx2x_init_ind_wr(bp
, addr
, data
, len
);
382 bnx2x_init_fill(bp
, addr
, 0, op
->zero
.len
);
385 bnx2x_init_wr_wb(bp
, addr
, data
, len
, 1, is_e1
,
386 op
->str_wr
.data_off
);
389 bnx2x_init_wr_64(bp
, addr
, data
, len
);
392 /* happens whenever an op is of a diff HW */
394 DP(NETIF_MSG_HW
, "skipping init operation "
395 "index %d[%d:%d]: type %d addr 0x%x "
397 i
, op_start
, op_end
, op_type
, addr
, len
, len
);
405 /****************************************************************************
407 ****************************************************************************/
409 * This code configures the PCI read/write arbiter
410 * which implements a weighted round robin
411 * between the virtual queues in the chip.
413 * The values were derived for each PCI max payload and max request size.
414 * since max payload and max request size are only known at run time,
415 * this is done as a separate init stage.
423 /* configuration for one arbiter queue */
430 /* derived configuration for each read queue for each max request size */
431 static const struct arb_line read_arb_data
[NUM_RD_Q
][MAX_RD_ORD
+ 1] = {
432 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
433 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
434 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
435 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
436 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
437 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
438 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
439 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
440 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
441 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
442 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
443 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
444 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
445 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
446 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
447 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
448 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
449 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
450 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
451 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
452 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
453 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
454 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
455 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
456 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
457 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
458 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
459 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
460 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
463 /* derived configuration for each write queue for each max request size */
464 static const struct arb_line write_arb_data
[NUM_WR_Q
][MAX_WR_ORD
+ 1] = {
465 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
466 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
467 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
468 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
469 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
470 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
471 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
472 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
473 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
474 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
475 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
476 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
477 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
480 /* register addresses for read queues */
481 static const struct arb_line read_arb_addr
[NUM_RD_Q
-1] = {
482 /* 1 */ {PXP2_REG_RQ_BW_RD_L0
, PXP2_REG_RQ_BW_RD_ADD0
,
483 PXP2_REG_RQ_BW_RD_UBOUND0
},
484 {PXP2_REG_PSWRQ_BW_L1
, PXP2_REG_PSWRQ_BW_ADD1
,
485 PXP2_REG_PSWRQ_BW_UB1
},
486 {PXP2_REG_PSWRQ_BW_L2
, PXP2_REG_PSWRQ_BW_ADD2
,
487 PXP2_REG_PSWRQ_BW_UB2
},
488 {PXP2_REG_PSWRQ_BW_L3
, PXP2_REG_PSWRQ_BW_ADD3
,
489 PXP2_REG_PSWRQ_BW_UB3
},
490 {PXP2_REG_RQ_BW_RD_L4
, PXP2_REG_RQ_BW_RD_ADD4
,
491 PXP2_REG_RQ_BW_RD_UBOUND4
},
492 {PXP2_REG_RQ_BW_RD_L5
, PXP2_REG_RQ_BW_RD_ADD5
,
493 PXP2_REG_RQ_BW_RD_UBOUND5
},
494 {PXP2_REG_PSWRQ_BW_L6
, PXP2_REG_PSWRQ_BW_ADD6
,
495 PXP2_REG_PSWRQ_BW_UB6
},
496 {PXP2_REG_PSWRQ_BW_L7
, PXP2_REG_PSWRQ_BW_ADD7
,
497 PXP2_REG_PSWRQ_BW_UB7
},
498 {PXP2_REG_PSWRQ_BW_L8
, PXP2_REG_PSWRQ_BW_ADD8
,
499 PXP2_REG_PSWRQ_BW_UB8
},
500 /* 10 */{PXP2_REG_PSWRQ_BW_L9
, PXP2_REG_PSWRQ_BW_ADD9
,
501 PXP2_REG_PSWRQ_BW_UB9
},
502 {PXP2_REG_PSWRQ_BW_L10
, PXP2_REG_PSWRQ_BW_ADD10
,
503 PXP2_REG_PSWRQ_BW_UB10
},
504 {PXP2_REG_PSWRQ_BW_L11
, PXP2_REG_PSWRQ_BW_ADD11
,
505 PXP2_REG_PSWRQ_BW_UB11
},
506 {PXP2_REG_RQ_BW_RD_L12
, PXP2_REG_RQ_BW_RD_ADD12
,
507 PXP2_REG_RQ_BW_RD_UBOUND12
},
508 {PXP2_REG_RQ_BW_RD_L13
, PXP2_REG_RQ_BW_RD_ADD13
,
509 PXP2_REG_RQ_BW_RD_UBOUND13
},
510 {PXP2_REG_RQ_BW_RD_L14
, PXP2_REG_RQ_BW_RD_ADD14
,
511 PXP2_REG_RQ_BW_RD_UBOUND14
},
512 {PXP2_REG_RQ_BW_RD_L15
, PXP2_REG_RQ_BW_RD_ADD15
,
513 PXP2_REG_RQ_BW_RD_UBOUND15
},
514 {PXP2_REG_RQ_BW_RD_L16
, PXP2_REG_RQ_BW_RD_ADD16
,
515 PXP2_REG_RQ_BW_RD_UBOUND16
},
516 {PXP2_REG_RQ_BW_RD_L17
, PXP2_REG_RQ_BW_RD_ADD17
,
517 PXP2_REG_RQ_BW_RD_UBOUND17
},
518 {PXP2_REG_RQ_BW_RD_L18
, PXP2_REG_RQ_BW_RD_ADD18
,
519 PXP2_REG_RQ_BW_RD_UBOUND18
},
520 /* 20 */{PXP2_REG_RQ_BW_RD_L19
, PXP2_REG_RQ_BW_RD_ADD19
,
521 PXP2_REG_RQ_BW_RD_UBOUND19
},
522 {PXP2_REG_RQ_BW_RD_L20
, PXP2_REG_RQ_BW_RD_ADD20
,
523 PXP2_REG_RQ_BW_RD_UBOUND20
},
524 {PXP2_REG_RQ_BW_RD_L22
, PXP2_REG_RQ_BW_RD_ADD22
,
525 PXP2_REG_RQ_BW_RD_UBOUND22
},
526 {PXP2_REG_RQ_BW_RD_L23
, PXP2_REG_RQ_BW_RD_ADD23
,
527 PXP2_REG_RQ_BW_RD_UBOUND23
},
528 {PXP2_REG_RQ_BW_RD_L24
, PXP2_REG_RQ_BW_RD_ADD24
,
529 PXP2_REG_RQ_BW_RD_UBOUND24
},
530 {PXP2_REG_RQ_BW_RD_L25
, PXP2_REG_RQ_BW_RD_ADD25
,
531 PXP2_REG_RQ_BW_RD_UBOUND25
},
532 {PXP2_REG_RQ_BW_RD_L26
, PXP2_REG_RQ_BW_RD_ADD26
,
533 PXP2_REG_RQ_BW_RD_UBOUND26
},
534 {PXP2_REG_RQ_BW_RD_L27
, PXP2_REG_RQ_BW_RD_ADD27
,
535 PXP2_REG_RQ_BW_RD_UBOUND27
},
536 {PXP2_REG_PSWRQ_BW_L28
, PXP2_REG_PSWRQ_BW_ADD28
,
537 PXP2_REG_PSWRQ_BW_UB28
}
540 /* register addresses for write queues */
541 static const struct arb_line write_arb_addr
[NUM_WR_Q
-1] = {
542 /* 1 */ {PXP2_REG_PSWRQ_BW_L1
, PXP2_REG_PSWRQ_BW_ADD1
,
543 PXP2_REG_PSWRQ_BW_UB1
},
544 {PXP2_REG_PSWRQ_BW_L2
, PXP2_REG_PSWRQ_BW_ADD2
,
545 PXP2_REG_PSWRQ_BW_UB2
},
546 {PXP2_REG_PSWRQ_BW_L3
, PXP2_REG_PSWRQ_BW_ADD3
,
547 PXP2_REG_PSWRQ_BW_UB3
},
548 {PXP2_REG_PSWRQ_BW_L6
, PXP2_REG_PSWRQ_BW_ADD6
,
549 PXP2_REG_PSWRQ_BW_UB6
},
550 {PXP2_REG_PSWRQ_BW_L7
, PXP2_REG_PSWRQ_BW_ADD7
,
551 PXP2_REG_PSWRQ_BW_UB7
},
552 {PXP2_REG_PSWRQ_BW_L8
, PXP2_REG_PSWRQ_BW_ADD8
,
553 PXP2_REG_PSWRQ_BW_UB8
},
554 {PXP2_REG_PSWRQ_BW_L9
, PXP2_REG_PSWRQ_BW_ADD9
,
555 PXP2_REG_PSWRQ_BW_UB9
},
556 {PXP2_REG_PSWRQ_BW_L10
, PXP2_REG_PSWRQ_BW_ADD10
,
557 PXP2_REG_PSWRQ_BW_UB10
},
558 {PXP2_REG_PSWRQ_BW_L11
, PXP2_REG_PSWRQ_BW_ADD11
,
559 PXP2_REG_PSWRQ_BW_UB11
},
560 /* 10 */{PXP2_REG_PSWRQ_BW_L28
, PXP2_REG_PSWRQ_BW_ADD28
,
561 PXP2_REG_PSWRQ_BW_UB28
},
562 {PXP2_REG_RQ_BW_WR_L29
, PXP2_REG_RQ_BW_WR_ADD29
,
563 PXP2_REG_RQ_BW_WR_UBOUND29
},
564 {PXP2_REG_RQ_BW_WR_L30
, PXP2_REG_RQ_BW_WR_ADD30
,
565 PXP2_REG_RQ_BW_WR_UBOUND30
}
568 static void bnx2x_init_pxp(struct bnx2x
*bp
)
571 int r_order
, w_order
;
574 pci_read_config_word(bp
->pdev
,
575 bp
->pcie_cap
+ PCI_EXP_DEVCTL
, &devctl
);
576 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
577 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
579 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
581 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
585 if (r_order
> MAX_RD_ORD
) {
586 DP(NETIF_MSG_HW
, "read order of %d order adjusted to %d\n",
587 r_order
, MAX_RD_ORD
);
588 r_order
= MAX_RD_ORD
;
590 if (w_order
> MAX_WR_ORD
) {
591 DP(NETIF_MSG_HW
, "write order of %d order adjusted to %d\n",
592 w_order
, MAX_WR_ORD
);
593 w_order
= MAX_WR_ORD
;
595 if (CHIP_REV_IS_FPGA(bp
)) {
596 DP(NETIF_MSG_HW
, "write order adjusted to 1 for FPGA\n");
599 DP(NETIF_MSG_HW
, "read order %d write order %d\n", r_order
, w_order
);
601 for (i
= 0; i
< NUM_RD_Q
-1; i
++) {
602 REG_WR(bp
, read_arb_addr
[i
].l
, read_arb_data
[i
][r_order
].l
);
603 REG_WR(bp
, read_arb_addr
[i
].add
,
604 read_arb_data
[i
][r_order
].add
);
605 REG_WR(bp
, read_arb_addr
[i
].ubound
,
606 read_arb_data
[i
][r_order
].ubound
);
609 for (i
= 0; i
< NUM_WR_Q
-1; i
++) {
610 if ((write_arb_addr
[i
].l
== PXP2_REG_RQ_BW_WR_L29
) ||
611 (write_arb_addr
[i
].l
== PXP2_REG_RQ_BW_WR_L30
)) {
613 REG_WR(bp
, write_arb_addr
[i
].l
,
614 write_arb_data
[i
][w_order
].l
);
616 REG_WR(bp
, write_arb_addr
[i
].add
,
617 write_arb_data
[i
][w_order
].add
);
619 REG_WR(bp
, write_arb_addr
[i
].ubound
,
620 write_arb_data
[i
][w_order
].ubound
);
623 val
= REG_RD(bp
, write_arb_addr
[i
].l
);
624 REG_WR(bp
, write_arb_addr
[i
].l
,
625 val
| (write_arb_data
[i
][w_order
].l
<< 10));
627 val
= REG_RD(bp
, write_arb_addr
[i
].add
);
628 REG_WR(bp
, write_arb_addr
[i
].add
,
629 val
| (write_arb_data
[i
][w_order
].add
<< 10));
631 val
= REG_RD(bp
, write_arb_addr
[i
].ubound
);
632 REG_WR(bp
, write_arb_addr
[i
].ubound
,
633 val
| (write_arb_data
[i
][w_order
].ubound
<< 7));
637 val
= write_arb_data
[NUM_WR_Q
-1][w_order
].add
;
638 val
+= write_arb_data
[NUM_WR_Q
-1][w_order
].ubound
<< 10;
639 val
+= write_arb_data
[NUM_WR_Q
-1][w_order
].l
<< 17;
640 REG_WR(bp
, PXP2_REG_PSWRQ_BW_RD
, val
);
642 val
= read_arb_data
[NUM_RD_Q
-1][r_order
].add
;
643 val
+= read_arb_data
[NUM_RD_Q
-1][r_order
].ubound
<< 10;
644 val
+= read_arb_data
[NUM_RD_Q
-1][r_order
].l
<< 17;
645 REG_WR(bp
, PXP2_REG_PSWRQ_BW_WR
, val
);
647 REG_WR(bp
, PXP2_REG_RQ_WR_MBS0
, w_order
);
648 REG_WR(bp
, PXP2_REG_RQ_WR_MBS1
, w_order
);
649 REG_WR(bp
, PXP2_REG_RQ_RD_MBS0
, r_order
);
650 REG_WR(bp
, PXP2_REG_RQ_RD_MBS1
, r_order
);
652 if (r_order
== MAX_RD_ORD
)
653 REG_WR(bp
, PXP2_REG_RQ_PDR_LIMIT
, 0xe00);
655 REG_WR(bp
, PXP2_REG_WR_USDMDP_TH
, (0x18 << w_order
));
657 if (CHIP_IS_E1H(bp
)) {
658 val
= ((w_order
== 0) ? 2 : 3);
659 REG_WR(bp
, PXP2_REG_WR_HC_MPS
, val
);
660 REG_WR(bp
, PXP2_REG_WR_USDM_MPS
, val
);
661 REG_WR(bp
, PXP2_REG_WR_CSDM_MPS
, val
);
662 REG_WR(bp
, PXP2_REG_WR_TSDM_MPS
, val
);
663 REG_WR(bp
, PXP2_REG_WR_XSDM_MPS
, val
);
664 REG_WR(bp
, PXP2_REG_WR_QM_MPS
, val
);
665 REG_WR(bp
, PXP2_REG_WR_TM_MPS
, val
);
666 REG_WR(bp
, PXP2_REG_WR_SRC_MPS
, val
);
667 REG_WR(bp
, PXP2_REG_WR_DBG_MPS
, val
);
668 REG_WR(bp
, PXP2_REG_WR_DMAE_MPS
, 2); /* DMAE is special */
669 REG_WR(bp
, PXP2_REG_WR_CDU_MPS
, val
);
674 /****************************************************************************
676 ****************************************************************************/
678 #define CDU_REGION_NUMBER_XCM_AG 2
679 #define CDU_REGION_NUMBER_UCM_AG 4
682 * String-to-compress [31:8] = CID (all 24 bits)
683 * String-to-compress [7:4] = Region
684 * String-to-compress [3:0] = Type
686 #define CDU_VALID_DATA(_cid, _region, _type) \
687 (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
688 #define CDU_CRC8(_cid, _region, _type) \
689 calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
690 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
691 (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
692 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
693 (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
694 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
696 /*****************************************************************************
698 * Calculates crc 8 on a word value: polynomial 0-1-2-8
699 * Code was translated from Verilog.
700 ****************************************************************************/
701 static u8
calc_crc8(u32 data
, u8 crc
)
709 /* split the data into 31 bits */
710 for (i
= 0; i
< 32; i
++) {
715 /* split the crc into 8 bits */
716 for (i
= 0; i
< 8; i
++) {
721 NewCRC
[0] = D
[31] ^ D
[30] ^ D
[28] ^ D
[23] ^ D
[21] ^ D
[19] ^ D
[18] ^
722 D
[16] ^ D
[14] ^ D
[12] ^ D
[8] ^ D
[7] ^ D
[6] ^ D
[0] ^ C
[4] ^
724 NewCRC
[1] = D
[30] ^ D
[29] ^ D
[28] ^ D
[24] ^ D
[23] ^ D
[22] ^ D
[21] ^
725 D
[20] ^ D
[18] ^ D
[17] ^ D
[16] ^ D
[15] ^ D
[14] ^ D
[13] ^
726 D
[12] ^ D
[9] ^ D
[6] ^ D
[1] ^ D
[0] ^ C
[0] ^ C
[4] ^ C
[5] ^ C
[6];
727 NewCRC
[2] = D
[29] ^ D
[28] ^ D
[25] ^ D
[24] ^ D
[22] ^ D
[17] ^ D
[15] ^
728 D
[13] ^ D
[12] ^ D
[10] ^ D
[8] ^ D
[6] ^ D
[2] ^ D
[1] ^ D
[0] ^
729 C
[0] ^ C
[1] ^ C
[4] ^ C
[5];
730 NewCRC
[3] = D
[30] ^ D
[29] ^ D
[26] ^ D
[25] ^ D
[23] ^ D
[18] ^ D
[16] ^
731 D
[14] ^ D
[13] ^ D
[11] ^ D
[9] ^ D
[7] ^ D
[3] ^ D
[2] ^ D
[1] ^
732 C
[1] ^ C
[2] ^ C
[5] ^ C
[6];
733 NewCRC
[4] = D
[31] ^ D
[30] ^ D
[27] ^ D
[26] ^ D
[24] ^ D
[19] ^ D
[17] ^
734 D
[15] ^ D
[14] ^ D
[12] ^ D
[10] ^ D
[8] ^ D
[4] ^ D
[3] ^ D
[2] ^
735 C
[0] ^ C
[2] ^ C
[3] ^ C
[6] ^ C
[7];
736 NewCRC
[5] = D
[31] ^ D
[28] ^ D
[27] ^ D
[25] ^ D
[20] ^ D
[18] ^ D
[16] ^
737 D
[15] ^ D
[13] ^ D
[11] ^ D
[9] ^ D
[5] ^ D
[4] ^ D
[3] ^ C
[1] ^
739 NewCRC
[6] = D
[29] ^ D
[28] ^ D
[26] ^ D
[21] ^ D
[19] ^ D
[17] ^ D
[16] ^
740 D
[14] ^ D
[12] ^ D
[10] ^ D
[6] ^ D
[5] ^ D
[4] ^ C
[2] ^ C
[4] ^
742 NewCRC
[7] = D
[30] ^ D
[29] ^ D
[27] ^ D
[22] ^ D
[20] ^ D
[18] ^ D
[17] ^
743 D
[15] ^ D
[13] ^ D
[11] ^ D
[7] ^ D
[6] ^ D
[5] ^ C
[3] ^ C
[5] ^
747 for (i
= 0; i
< 8; i
++)
748 crc_res
|= (NewCRC
[i
] << i
);
753 /* registers addresses are not in order
754 so these arrays help simplify the code */
755 static const int cm_start
[E1H_FUNC_MAX
][9] = {
756 {MISC_FUNC0_START
, TCM_FUNC0_START
, UCM_FUNC0_START
, CCM_FUNC0_START
,
757 XCM_FUNC0_START
, TSEM_FUNC0_START
, USEM_FUNC0_START
, CSEM_FUNC0_START
,
759 {MISC_FUNC1_START
, TCM_FUNC1_START
, UCM_FUNC1_START
, CCM_FUNC1_START
,
760 XCM_FUNC1_START
, TSEM_FUNC1_START
, USEM_FUNC1_START
, CSEM_FUNC1_START
,
762 {MISC_FUNC2_START
, TCM_FUNC2_START
, UCM_FUNC2_START
, CCM_FUNC2_START
,
763 XCM_FUNC2_START
, TSEM_FUNC2_START
, USEM_FUNC2_START
, CSEM_FUNC2_START
,
765 {MISC_FUNC3_START
, TCM_FUNC3_START
, UCM_FUNC3_START
, CCM_FUNC3_START
,
766 XCM_FUNC3_START
, TSEM_FUNC3_START
, USEM_FUNC3_START
, CSEM_FUNC3_START
,
768 {MISC_FUNC4_START
, TCM_FUNC4_START
, UCM_FUNC4_START
, CCM_FUNC4_START
,
769 XCM_FUNC4_START
, TSEM_FUNC4_START
, USEM_FUNC4_START
, CSEM_FUNC4_START
,
771 {MISC_FUNC5_START
, TCM_FUNC5_START
, UCM_FUNC5_START
, CCM_FUNC5_START
,
772 XCM_FUNC5_START
, TSEM_FUNC5_START
, USEM_FUNC5_START
, CSEM_FUNC5_START
,
774 {MISC_FUNC6_START
, TCM_FUNC6_START
, UCM_FUNC6_START
, CCM_FUNC6_START
,
775 XCM_FUNC6_START
, TSEM_FUNC6_START
, USEM_FUNC6_START
, CSEM_FUNC6_START
,
777 {MISC_FUNC7_START
, TCM_FUNC7_START
, UCM_FUNC7_START
, CCM_FUNC7_START
,
778 XCM_FUNC7_START
, TSEM_FUNC7_START
, USEM_FUNC7_START
, CSEM_FUNC7_START
,
782 static const int cm_end
[E1H_FUNC_MAX
][9] = {
783 {MISC_FUNC0_END
, TCM_FUNC0_END
, UCM_FUNC0_END
, CCM_FUNC0_END
,
784 XCM_FUNC0_END
, TSEM_FUNC0_END
, USEM_FUNC0_END
, CSEM_FUNC0_END
,
786 {MISC_FUNC1_END
, TCM_FUNC1_END
, UCM_FUNC1_END
, CCM_FUNC1_END
,
787 XCM_FUNC1_END
, TSEM_FUNC1_END
, USEM_FUNC1_END
, CSEM_FUNC1_END
,
789 {MISC_FUNC2_END
, TCM_FUNC2_END
, UCM_FUNC2_END
, CCM_FUNC2_END
,
790 XCM_FUNC2_END
, TSEM_FUNC2_END
, USEM_FUNC2_END
, CSEM_FUNC2_END
,
792 {MISC_FUNC3_END
, TCM_FUNC3_END
, UCM_FUNC3_END
, CCM_FUNC3_END
,
793 XCM_FUNC3_END
, TSEM_FUNC3_END
, USEM_FUNC3_END
, CSEM_FUNC3_END
,
795 {MISC_FUNC4_END
, TCM_FUNC4_END
, UCM_FUNC4_END
, CCM_FUNC4_END
,
796 XCM_FUNC4_END
, TSEM_FUNC4_END
, USEM_FUNC4_END
, CSEM_FUNC4_END
,
798 {MISC_FUNC5_END
, TCM_FUNC5_END
, UCM_FUNC5_END
, CCM_FUNC5_END
,
799 XCM_FUNC5_END
, TSEM_FUNC5_END
, USEM_FUNC5_END
, CSEM_FUNC5_END
,
801 {MISC_FUNC6_END
, TCM_FUNC6_END
, UCM_FUNC6_END
, CCM_FUNC6_END
,
802 XCM_FUNC6_END
, TSEM_FUNC6_END
, USEM_FUNC6_END
, CSEM_FUNC6_END
,
804 {MISC_FUNC7_END
, TCM_FUNC7_END
, UCM_FUNC7_END
, CCM_FUNC7_END
,
805 XCM_FUNC7_END
, TSEM_FUNC7_END
, USEM_FUNC7_END
, CSEM_FUNC7_END
,
809 static const int hc_limits
[E1H_FUNC_MAX
][2] = {
810 {HC_FUNC0_START
, HC_FUNC0_END
},
811 {HC_FUNC1_START
, HC_FUNC1_END
},
812 {HC_FUNC2_START
, HC_FUNC2_END
},
813 {HC_FUNC3_START
, HC_FUNC3_END
},
814 {HC_FUNC4_START
, HC_FUNC4_END
},
815 {HC_FUNC5_START
, HC_FUNC5_END
},
816 {HC_FUNC6_START
, HC_FUNC6_END
},
817 {HC_FUNC7_START
, HC_FUNC7_END
}
820 #endif /* BNX2X_INIT_H */