1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #ifdef NETIF_F_HW_VLAN_TX
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
55 #include "bnx2x_reg.h"
56 #include "bnx2x_fw_defs.h"
57 #include "bnx2x_hsi.h"
58 #include "bnx2x_link.h"
60 #include "bnx2x_init.h"
62 #define DRV_MODULE_VERSION "1.45.23"
63 #define DRV_MODULE_RELDATE "2008/11/03"
64 #define BNX2X_BC_VER 0x040200
66 /* Time in jiffies before concluding the transmitter is hung */
67 #define TX_TIMEOUT (5*HZ)
69 static char version
[] __devinitdata
=
70 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
71 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
73 MODULE_AUTHOR("Eliezer Tamir");
74 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
75 MODULE_LICENSE("GPL");
76 MODULE_VERSION(DRV_MODULE_VERSION
);
78 static int disable_tpa
;
82 static int load_count
[3]; /* 0-common, 1-port0, 2-port1 */
85 module_param(disable_tpa
, int, 0);
86 module_param(use_inta
, int, 0);
87 module_param(poll
, int, 0);
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(disable_tpa
, "disable the TPA (LRO) feature");
90 MODULE_PARM_DESC(use_inta
, "use INT#A instead of MSI-X");
91 MODULE_PARM_DESC(poll
, "use polling (for debug)");
92 MODULE_PARM_DESC(debug
, "default debug msglevel");
95 module_param(use_multi
, int, 0);
96 MODULE_PARM_DESC(use_multi
, "use per-CPU queues");
98 static struct workqueue_struct
*bnx2x_wq
;
100 enum bnx2x_board_type
{
106 /* indexed by board_type, above */
109 } board_info
[] __devinitdata
= {
110 { "Broadcom NetXtreme II BCM57710 XGb" },
111 { "Broadcom NetXtreme II BCM57711 XGb" },
112 { "Broadcom NetXtreme II BCM57711E XGb" }
116 static const struct pci_device_id bnx2x_pci_tbl
[] = {
117 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_57710
,
118 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM57710
},
119 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_57711
,
120 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM57711
},
121 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_57711E
,
122 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM57711E
},
126 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
128 /****************************************************************************
129 * General service functions
130 ****************************************************************************/
133 * locking is done by mcp
135 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
137 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
138 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
139 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
140 PCICFG_VENDOR_ID_OFFSET
);
143 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
147 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
148 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
149 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
150 PCICFG_VENDOR_ID_OFFSET
);
155 static const u32 dmae_reg_go_c
[] = {
156 DMAE_REG_GO_C0
, DMAE_REG_GO_C1
, DMAE_REG_GO_C2
, DMAE_REG_GO_C3
,
157 DMAE_REG_GO_C4
, DMAE_REG_GO_C5
, DMAE_REG_GO_C6
, DMAE_REG_GO_C7
,
158 DMAE_REG_GO_C8
, DMAE_REG_GO_C9
, DMAE_REG_GO_C10
, DMAE_REG_GO_C11
,
159 DMAE_REG_GO_C12
, DMAE_REG_GO_C13
, DMAE_REG_GO_C14
, DMAE_REG_GO_C15
162 /* copy command into DMAE command memory and set DMAE command go */
163 static void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
,
169 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
170 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
171 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
173 DP(BNX2X_MSG_OFF
, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
174 idx
, i
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
176 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
179 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
182 struct dmae_command
*dmae
= &bp
->init_dmae
;
183 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
186 if (!bp
->dmae_ready
) {
187 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
189 DP(BNX2X_MSG_OFF
, "DMAE is not ready (dst_addr %08x len32 %d)"
190 " using indirect\n", dst_addr
, len32
);
191 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
195 mutex_lock(&bp
->dmae_mutex
);
197 memset(dmae
, 0, sizeof(struct dmae_command
));
199 dmae
->opcode
= (DMAE_CMD_SRC_PCI
| DMAE_CMD_DST_GRC
|
200 DMAE_CMD_C_DST_PCI
| DMAE_CMD_C_ENABLE
|
201 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
203 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
205 DMAE_CMD_ENDIANITY_DW_SWAP
|
207 (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
208 (BP_E1HVN(bp
) << DMAE_CMD_E1HVN_SHIFT
));
209 dmae
->src_addr_lo
= U64_LO(dma_addr
);
210 dmae
->src_addr_hi
= U64_HI(dma_addr
);
211 dmae
->dst_addr_lo
= dst_addr
>> 2;
212 dmae
->dst_addr_hi
= 0;
214 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
215 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
216 dmae
->comp_val
= DMAE_COMP_VAL
;
218 DP(BNX2X_MSG_OFF
, "dmae: opcode 0x%08x\n"
219 DP_LEVEL
"src_addr [%x:%08x] len [%d *4] "
220 "dst_addr [%x:%08x (%08x)]\n"
221 DP_LEVEL
"comp_addr [%x:%08x] comp_val 0x%08x\n",
222 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
223 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
, dst_addr
,
224 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
, dmae
->comp_val
);
225 DP(BNX2X_MSG_OFF
, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
226 bp
->slowpath
->wb_data
[0], bp
->slowpath
->wb_data
[1],
227 bp
->slowpath
->wb_data
[2], bp
->slowpath
->wb_data
[3]);
231 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
235 while (*wb_comp
!= DMAE_COMP_VAL
) {
236 DP(BNX2X_MSG_OFF
, "wb_comp 0x%08x\n", *wb_comp
);
239 BNX2X_ERR("dmae timeout!\n");
243 /* adjust delay for emulation/FPGA */
244 if (CHIP_REV_IS_SLOW(bp
))
250 mutex_unlock(&bp
->dmae_mutex
);
253 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
255 struct dmae_command
*dmae
= &bp
->init_dmae
;
256 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
259 if (!bp
->dmae_ready
) {
260 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
263 DP(BNX2X_MSG_OFF
, "DMAE is not ready (src_addr %08x len32 %d)"
264 " using indirect\n", src_addr
, len32
);
265 for (i
= 0; i
< len32
; i
++)
266 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
270 mutex_lock(&bp
->dmae_mutex
);
272 memset(bnx2x_sp(bp
, wb_data
[0]), 0, sizeof(u32
) * 4);
273 memset(dmae
, 0, sizeof(struct dmae_command
));
275 dmae
->opcode
= (DMAE_CMD_SRC_GRC
| DMAE_CMD_DST_PCI
|
276 DMAE_CMD_C_DST_PCI
| DMAE_CMD_C_ENABLE
|
277 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
279 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
281 DMAE_CMD_ENDIANITY_DW_SWAP
|
283 (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
284 (BP_E1HVN(bp
) << DMAE_CMD_E1HVN_SHIFT
));
285 dmae
->src_addr_lo
= src_addr
>> 2;
286 dmae
->src_addr_hi
= 0;
287 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
288 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
290 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
291 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
292 dmae
->comp_val
= DMAE_COMP_VAL
;
294 DP(BNX2X_MSG_OFF
, "dmae: opcode 0x%08x\n"
295 DP_LEVEL
"src_addr [%x:%08x] len [%d *4] "
296 "dst_addr [%x:%08x (%08x)]\n"
297 DP_LEVEL
"comp_addr [%x:%08x] comp_val 0x%08x\n",
298 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
299 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
, src_addr
,
300 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
, dmae
->comp_val
);
304 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
308 while (*wb_comp
!= DMAE_COMP_VAL
) {
311 BNX2X_ERR("dmae timeout!\n");
315 /* adjust delay for emulation/FPGA */
316 if (CHIP_REV_IS_SLOW(bp
))
321 DP(BNX2X_MSG_OFF
, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
322 bp
->slowpath
->wb_data
[0], bp
->slowpath
->wb_data
[1],
323 bp
->slowpath
->wb_data
[2], bp
->slowpath
->wb_data
[3]);
325 mutex_unlock(&bp
->dmae_mutex
);
328 /* used only for slowpath so not inlined */
329 static void bnx2x_wb_wr(struct bnx2x
*bp
, int reg
, u32 val_hi
, u32 val_lo
)
333 wb_write
[0] = val_hi
;
334 wb_write
[1] = val_lo
;
335 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
339 static u64
bnx2x_wb_rd(struct bnx2x
*bp
, int reg
)
343 REG_RD_DMAE(bp
, reg
, wb_data
, 2);
345 return HILO_U64(wb_data
[0], wb_data
[1]);
349 static int bnx2x_mc_assert(struct bnx2x
*bp
)
353 u32 row0
, row1
, row2
, row3
;
356 last_idx
= REG_RD8(bp
, BAR_XSTRORM_INTMEM
+
357 XSTORM_ASSERT_LIST_INDEX_OFFSET
);
359 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
361 /* print the asserts */
362 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
364 row0
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
365 XSTORM_ASSERT_LIST_OFFSET(i
));
366 row1
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
367 XSTORM_ASSERT_LIST_OFFSET(i
) + 4);
368 row2
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
369 XSTORM_ASSERT_LIST_OFFSET(i
) + 8);
370 row3
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
371 XSTORM_ASSERT_LIST_OFFSET(i
) + 12);
373 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
374 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
375 " 0x%08x 0x%08x 0x%08x\n",
376 i
, row3
, row2
, row1
, row0
);
384 last_idx
= REG_RD8(bp
, BAR_TSTRORM_INTMEM
+
385 TSTORM_ASSERT_LIST_INDEX_OFFSET
);
387 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
389 /* print the asserts */
390 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
392 row0
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
393 TSTORM_ASSERT_LIST_OFFSET(i
));
394 row1
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
395 TSTORM_ASSERT_LIST_OFFSET(i
) + 4);
396 row2
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
397 TSTORM_ASSERT_LIST_OFFSET(i
) + 8);
398 row3
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
399 TSTORM_ASSERT_LIST_OFFSET(i
) + 12);
401 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
402 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
403 " 0x%08x 0x%08x 0x%08x\n",
404 i
, row3
, row2
, row1
, row0
);
412 last_idx
= REG_RD8(bp
, BAR_CSTRORM_INTMEM
+
413 CSTORM_ASSERT_LIST_INDEX_OFFSET
);
415 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
417 /* print the asserts */
418 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
420 row0
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
421 CSTORM_ASSERT_LIST_OFFSET(i
));
422 row1
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
423 CSTORM_ASSERT_LIST_OFFSET(i
) + 4);
424 row2
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
425 CSTORM_ASSERT_LIST_OFFSET(i
) + 8);
426 row3
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
427 CSTORM_ASSERT_LIST_OFFSET(i
) + 12);
429 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
430 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
431 " 0x%08x 0x%08x 0x%08x\n",
432 i
, row3
, row2
, row1
, row0
);
440 last_idx
= REG_RD8(bp
, BAR_USTRORM_INTMEM
+
441 USTORM_ASSERT_LIST_INDEX_OFFSET
);
443 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
445 /* print the asserts */
446 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
448 row0
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
449 USTORM_ASSERT_LIST_OFFSET(i
));
450 row1
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
451 USTORM_ASSERT_LIST_OFFSET(i
) + 4);
452 row2
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
453 USTORM_ASSERT_LIST_OFFSET(i
) + 8);
454 row3
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
455 USTORM_ASSERT_LIST_OFFSET(i
) + 12);
457 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
458 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
459 " 0x%08x 0x%08x 0x%08x\n",
460 i
, row3
, row2
, row1
, row0
);
470 static void bnx2x_fw_dump(struct bnx2x
*bp
)
476 mark
= REG_RD(bp
, MCP_REG_MCPR_SCRATCH
+ 0xf104);
477 mark
= ((mark
+ 0x3) & ~0x3);
478 printk(KERN_ERR PFX
"begin fw dump (mark 0x%x)\n" KERN_ERR
, mark
);
480 for (offset
= mark
- 0x08000000; offset
<= 0xF900; offset
+= 0x8*4) {
481 for (word
= 0; word
< 8; word
++)
482 data
[word
] = htonl(REG_RD(bp
, MCP_REG_MCPR_SCRATCH
+
485 printk(KERN_CONT
"%s", (char *)data
);
487 for (offset
= 0xF108; offset
<= mark
- 0x08000000; offset
+= 0x8*4) {
488 for (word
= 0; word
< 8; word
++)
489 data
[word
] = htonl(REG_RD(bp
, MCP_REG_MCPR_SCRATCH
+
492 printk(KERN_CONT
"%s", (char *)data
);
494 printk("\n" KERN_ERR PFX
"end of fw dump\n");
497 static void bnx2x_panic_dump(struct bnx2x
*bp
)
502 bp
->stats_state
= STATS_STATE_DISABLED
;
503 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
505 BNX2X_ERR("begin crash dump -----------------\n");
507 for_each_queue(bp
, i
) {
508 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
509 struct eth_tx_db_data
*hw_prods
= fp
->hw_tx_prods
;
511 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
512 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
513 i
, fp
->tx_pkt_prod
, fp
->tx_pkt_cons
, fp
->tx_bd_prod
,
514 fp
->tx_bd_cons
, le16_to_cpu(*fp
->tx_cons_sb
));
515 BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)"
516 " *rx_bd_cons_sb(%x) rx_comp_prod(%x)"
517 " rx_comp_cons(%x) *rx_cons_sb(%x)\n",
518 fp
->rx_bd_prod
, fp
->rx_bd_cons
,
519 le16_to_cpu(*fp
->rx_bd_cons_sb
), fp
->rx_comp_prod
,
520 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
521 BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)"
522 " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)"
523 " *sb_u_idx(%x) bd data(%x,%x)\n",
524 fp
->rx_sge_prod
, fp
->last_max_sge
, fp
->fp_c_idx
,
525 fp
->status_blk
->c_status_block
.status_block_index
,
527 fp
->status_blk
->u_status_block
.status_block_index
,
528 hw_prods
->packets_prod
, hw_prods
->bds_prod
);
530 start
= TX_BD(le16_to_cpu(*fp
->tx_cons_sb
) - 10);
531 end
= TX_BD(le16_to_cpu(*fp
->tx_cons_sb
) + 245);
532 for (j
= start
; j
< end
; j
++) {
533 struct sw_tx_bd
*sw_bd
= &fp
->tx_buf_ring
[j
];
535 BNX2X_ERR("packet[%x]=[%p,%x]\n", j
,
536 sw_bd
->skb
, sw_bd
->first_bd
);
539 start
= TX_BD(fp
->tx_bd_cons
- 10);
540 end
= TX_BD(fp
->tx_bd_cons
+ 254);
541 for (j
= start
; j
< end
; j
++) {
542 u32
*tx_bd
= (u32
*)&fp
->tx_desc_ring
[j
];
544 BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
545 j
, tx_bd
[0], tx_bd
[1], tx_bd
[2], tx_bd
[3]);
548 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
549 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
550 for (j
= start
; j
< end
; j
++) {
551 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
552 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
554 BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
555 j
, rx_bd
[1], rx_bd
[0], sw_bd
->skb
);
558 start
= RX_SGE(fp
->rx_sge_prod
);
559 end
= RX_SGE(fp
->last_max_sge
);
560 for (j
= start
; j
< end
; j
++) {
561 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
562 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
564 BNX2X_ERR("rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
565 j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
568 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
569 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
570 for (j
= start
; j
< end
; j
++) {
571 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
573 BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
574 j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
578 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)"
579 " def_t_idx(%u) def_att_idx(%u) attn_state(%u)"
580 " spq_prod_idx(%u)\n",
581 bp
->def_c_idx
, bp
->def_u_idx
, bp
->def_x_idx
, bp
->def_t_idx
,
582 bp
->def_att_idx
, bp
->attn_state
, bp
->spq_prod_idx
);
586 BNX2X_ERR("end crash dump -----------------\n");
589 static void bnx2x_int_enable(struct bnx2x
*bp
)
591 int port
= BP_PORT(bp
);
592 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
593 u32 val
= REG_RD(bp
, addr
);
594 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
597 val
&= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0
;
598 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
599 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
601 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
602 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
603 HC_CONFIG_0_REG_INT_LINE_EN_0
|
604 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
606 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
607 val
, port
, addr
, msix
);
609 REG_WR(bp
, addr
, val
);
611 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
614 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
615 val
, port
, addr
, msix
);
617 REG_WR(bp
, addr
, val
);
619 if (CHIP_IS_E1H(bp
)) {
620 /* init leading/trailing edge */
622 val
= (0xfe0f | (1 << (BP_E1HVN(bp
) + 4)));
624 /* enable nig attention */
629 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
630 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
634 static void bnx2x_int_disable(struct bnx2x
*bp
)
636 int port
= BP_PORT(bp
);
637 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
638 u32 val
= REG_RD(bp
, addr
);
640 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
641 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
642 HC_CONFIG_0_REG_INT_LINE_EN_0
|
643 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
645 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x)\n",
648 REG_WR(bp
, addr
, val
);
649 if (REG_RD(bp
, addr
) != val
)
650 BNX2X_ERR("BUG! proper val not read from IGU!\n");
653 static void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
655 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
658 /* disable interrupt handling */
659 atomic_inc(&bp
->intr_sem
);
661 /* prevent the HW from sending interrupts */
662 bnx2x_int_disable(bp
);
664 /* make sure all ISRs are done */
666 for_each_queue(bp
, i
)
667 synchronize_irq(bp
->msix_table
[i
].vector
);
669 /* one more for the Slow Path IRQ */
670 synchronize_irq(bp
->msix_table
[i
].vector
);
672 synchronize_irq(bp
->pdev
->irq
);
674 /* make sure sp_task is not running */
675 cancel_delayed_work(&bp
->sp_task
);
676 flush_workqueue(bnx2x_wq
);
682 * General service functions
685 static inline void bnx2x_ack_sb(struct bnx2x
*bp
, u8 sb_id
,
686 u8 storm
, u16 index
, u8 op
, u8 update
)
688 u32 hc_addr
= (HC_REG_COMMAND_REG
+ BP_PORT(bp
)*32 +
689 COMMAND_REG_INT_ACK
);
690 struct igu_ack_register igu_ack
;
692 igu_ack
.status_block_index
= index
;
693 igu_ack
.sb_id_and_flags
=
694 ((sb_id
<< IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT
) |
695 (storm
<< IGU_ACK_REGISTER_STORM_ID_SHIFT
) |
696 (update
<< IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT
) |
697 (op
<< IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT
));
699 DP(BNX2X_MSG_OFF
, "write 0x%08x to HC addr 0x%x\n",
700 (*(u32
*)&igu_ack
), hc_addr
);
701 REG_WR(bp
, hc_addr
, (*(u32
*)&igu_ack
));
704 static inline u16
bnx2x_update_fpsb_idx(struct bnx2x_fastpath
*fp
)
706 struct host_status_block
*fpsb
= fp
->status_blk
;
709 barrier(); /* status block is written to by the chip */
710 if (fp
->fp_c_idx
!= fpsb
->c_status_block
.status_block_index
) {
711 fp
->fp_c_idx
= fpsb
->c_status_block
.status_block_index
;
714 if (fp
->fp_u_idx
!= fpsb
->u_status_block
.status_block_index
) {
715 fp
->fp_u_idx
= fpsb
->u_status_block
.status_block_index
;
721 static u16
bnx2x_ack_int(struct bnx2x
*bp
)
723 u32 hc_addr
= (HC_REG_COMMAND_REG
+ BP_PORT(bp
)*32 +
724 COMMAND_REG_SIMD_MASK
);
725 u32 result
= REG_RD(bp
, hc_addr
);
727 DP(BNX2X_MSG_OFF
, "read 0x%08x from HC addr 0x%x\n",
735 * fast path service functions
738 /* free skb in the packet ring at pos idx
739 * return idx of last bd freed
741 static u16
bnx2x_free_tx_pkt(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
744 struct sw_tx_bd
*tx_buf
= &fp
->tx_buf_ring
[idx
];
745 struct eth_tx_bd
*tx_bd
;
746 struct sk_buff
*skb
= tx_buf
->skb
;
747 u16 bd_idx
= TX_BD(tx_buf
->first_bd
), new_cons
;
750 DP(BNX2X_MSG_OFF
, "pkt_idx %d buff @(%p)->skb %p\n",
754 DP(BNX2X_MSG_OFF
, "free bd_idx %d\n", bd_idx
);
755 tx_bd
= &fp
->tx_desc_ring
[bd_idx
];
756 pci_unmap_single(bp
->pdev
, BD_UNMAP_ADDR(tx_bd
),
757 BD_UNMAP_LEN(tx_bd
), PCI_DMA_TODEVICE
);
759 nbd
= le16_to_cpu(tx_bd
->nbd
) - 1;
760 new_cons
= nbd
+ tx_buf
->first_bd
;
761 #ifdef BNX2X_STOP_ON_ERROR
762 if (nbd
> (MAX_SKB_FRAGS
+ 2)) {
763 BNX2X_ERR("BAD nbd!\n");
768 /* Skip a parse bd and the TSO split header bd
769 since they have no mapping */
771 bd_idx
= TX_BD(NEXT_TX_IDX(bd_idx
));
773 if (tx_bd
->bd_flags
.as_bitfield
& (ETH_TX_BD_FLAGS_IP_CSUM
|
774 ETH_TX_BD_FLAGS_TCP_CSUM
|
775 ETH_TX_BD_FLAGS_SW_LSO
)) {
777 bd_idx
= TX_BD(NEXT_TX_IDX(bd_idx
));
778 tx_bd
= &fp
->tx_desc_ring
[bd_idx
];
779 /* is this a TSO split header bd? */
780 if (tx_bd
->bd_flags
.as_bitfield
& ETH_TX_BD_FLAGS_SW_LSO
) {
782 bd_idx
= TX_BD(NEXT_TX_IDX(bd_idx
));
789 DP(BNX2X_MSG_OFF
, "free frag bd_idx %d\n", bd_idx
);
790 tx_bd
= &fp
->tx_desc_ring
[bd_idx
];
791 pci_unmap_page(bp
->pdev
, BD_UNMAP_ADDR(tx_bd
),
792 BD_UNMAP_LEN(tx_bd
), PCI_DMA_TODEVICE
);
794 bd_idx
= TX_BD(NEXT_TX_IDX(bd_idx
));
800 tx_buf
->first_bd
= 0;
806 static inline u16
bnx2x_tx_avail(struct bnx2x_fastpath
*fp
)
812 barrier(); /* Tell compiler that prod and cons can change */
813 prod
= fp
->tx_bd_prod
;
814 cons
= fp
->tx_bd_cons
;
816 /* NUM_TX_RINGS = number of "next-page" entries
817 It will be used as a threshold */
818 used
= SUB_S16(prod
, cons
) + (s16
)NUM_TX_RINGS
;
820 #ifdef BNX2X_STOP_ON_ERROR
822 WARN_ON(used
> fp
->bp
->tx_ring_size
);
823 WARN_ON((fp
->bp
->tx_ring_size
- used
) > MAX_TX_AVAIL
);
826 return (s16
)(fp
->bp
->tx_ring_size
) - used
;
829 static void bnx2x_tx_int(struct bnx2x_fastpath
*fp
, int work
)
831 struct bnx2x
*bp
= fp
->bp
;
832 u16 hw_cons
, sw_cons
, bd_cons
= fp
->tx_bd_cons
;
835 #ifdef BNX2X_STOP_ON_ERROR
836 if (unlikely(bp
->panic
))
840 hw_cons
= le16_to_cpu(*fp
->tx_cons_sb
);
841 sw_cons
= fp
->tx_pkt_cons
;
843 while (sw_cons
!= hw_cons
) {
846 pkt_cons
= TX_BD(sw_cons
);
848 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
850 DP(NETIF_MSG_TX_DONE
, "hw_cons %u sw_cons %u pkt_cons %u\n",
851 hw_cons
, sw_cons
, pkt_cons
);
853 /* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
855 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
858 bd_cons
= bnx2x_free_tx_pkt(bp
, fp
, pkt_cons
);
866 fp
->tx_pkt_cons
= sw_cons
;
867 fp
->tx_bd_cons
= bd_cons
;
869 /* Need to make the tx_cons update visible to start_xmit()
870 * before checking for netif_queue_stopped(). Without the
871 * memory barrier, there is a small possibility that start_xmit()
872 * will miss it and cause the queue to be stopped forever.
876 /* TBD need a thresh? */
877 if (unlikely(netif_queue_stopped(bp
->dev
))) {
879 netif_tx_lock(bp
->dev
);
881 if (netif_queue_stopped(bp
->dev
) &&
882 (bp
->state
== BNX2X_STATE_OPEN
) &&
883 (bnx2x_tx_avail(fp
) >= MAX_SKB_FRAGS
+ 3))
884 netif_wake_queue(bp
->dev
);
886 netif_tx_unlock(bp
->dev
);
891 static void bnx2x_sp_event(struct bnx2x_fastpath
*fp
,
892 union eth_rx_cqe
*rr_cqe
)
894 struct bnx2x
*bp
= fp
->bp
;
895 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
896 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
899 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
900 FP_IDX(fp
), cid
, command
, bp
->state
,
901 rr_cqe
->ramrod_cqe
.ramrod_type
);
906 switch (command
| fp
->state
) {
907 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
|
908 BNX2X_FP_STATE_OPENING
):
909 DP(NETIF_MSG_IFUP
, "got MULTI[%d] setup ramrod\n",
911 fp
->state
= BNX2X_FP_STATE_OPEN
;
914 case (RAMROD_CMD_ID_ETH_HALT
| BNX2X_FP_STATE_HALTING
):
915 DP(NETIF_MSG_IFDOWN
, "got MULTI[%d] halt ramrod\n",
917 fp
->state
= BNX2X_FP_STATE_HALTED
;
921 BNX2X_ERR("unexpected MC reply (%d) "
922 "fp->state is %x\n", command
, fp
->state
);
925 mb(); /* force bnx2x_wait_ramrod() to see the change */
929 switch (command
| bp
->state
) {
930 case (RAMROD_CMD_ID_ETH_PORT_SETUP
| BNX2X_STATE_OPENING_WAIT4_PORT
):
931 DP(NETIF_MSG_IFUP
, "got setup ramrod\n");
932 bp
->state
= BNX2X_STATE_OPEN
;
935 case (RAMROD_CMD_ID_ETH_HALT
| BNX2X_STATE_CLOSING_WAIT4_HALT
):
936 DP(NETIF_MSG_IFDOWN
, "got halt ramrod\n");
937 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_DELETE
;
938 fp
->state
= BNX2X_FP_STATE_HALTED
;
941 case (RAMROD_CMD_ID_ETH_CFC_DEL
| BNX2X_STATE_CLOSING_WAIT4_HALT
):
942 DP(NETIF_MSG_IFDOWN
, "got delete ramrod for MULTI[%d]\n", cid
);
943 bnx2x_fp(bp
, cid
, state
) = BNX2X_FP_STATE_CLOSED
;
947 case (RAMROD_CMD_ID_ETH_SET_MAC
| BNX2X_STATE_OPEN
):
948 case (RAMROD_CMD_ID_ETH_SET_MAC
| BNX2X_STATE_DIAG
):
949 DP(NETIF_MSG_IFUP
, "got set mac ramrod\n");
950 bp
->set_mac_pending
= 0;
953 case (RAMROD_CMD_ID_ETH_SET_MAC
| BNX2X_STATE_CLOSING_WAIT4_HALT
):
954 DP(NETIF_MSG_IFDOWN
, "got (un)set mac ramrod\n");
958 BNX2X_ERR("unexpected MC reply (%d) bp->state is %x\n",
962 mb(); /* force bnx2x_wait_ramrod() to see the change */
965 static inline void bnx2x_free_rx_sge(struct bnx2x
*bp
,
966 struct bnx2x_fastpath
*fp
, u16 index
)
968 struct sw_rx_page
*sw_buf
= &fp
->rx_page_ring
[index
];
969 struct page
*page
= sw_buf
->page
;
970 struct eth_rx_sge
*sge
= &fp
->rx_sge_ring
[index
];
972 /* Skip "next page" elements */
976 pci_unmap_page(bp
->pdev
, pci_unmap_addr(sw_buf
, mapping
),
977 BCM_PAGE_SIZE
*PAGES_PER_SGE
, PCI_DMA_FROMDEVICE
);
978 __free_pages(page
, PAGES_PER_SGE_SHIFT
);
985 static inline void bnx2x_free_rx_sge_range(struct bnx2x
*bp
,
986 struct bnx2x_fastpath
*fp
, int last
)
990 for (i
= 0; i
< last
; i
++)
991 bnx2x_free_rx_sge(bp
, fp
, i
);
994 static inline int bnx2x_alloc_rx_sge(struct bnx2x
*bp
,
995 struct bnx2x_fastpath
*fp
, u16 index
)
997 struct page
*page
= alloc_pages(GFP_ATOMIC
, PAGES_PER_SGE_SHIFT
);
998 struct sw_rx_page
*sw_buf
= &fp
->rx_page_ring
[index
];
999 struct eth_rx_sge
*sge
= &fp
->rx_sge_ring
[index
];
1002 if (unlikely(page
== NULL
))
1005 mapping
= pci_map_page(bp
->pdev
, page
, 0, BCM_PAGE_SIZE
*PAGES_PER_SGE
,
1006 PCI_DMA_FROMDEVICE
);
1007 if (unlikely(dma_mapping_error(&bp
->pdev
->dev
, mapping
))) {
1008 __free_pages(page
, PAGES_PER_SGE_SHIFT
);
1012 sw_buf
->page
= page
;
1013 pci_unmap_addr_set(sw_buf
, mapping
, mapping
);
1015 sge
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
1016 sge
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
1021 static inline int bnx2x_alloc_rx_skb(struct bnx2x
*bp
,
1022 struct bnx2x_fastpath
*fp
, u16 index
)
1024 struct sk_buff
*skb
;
1025 struct sw_rx_bd
*rx_buf
= &fp
->rx_buf_ring
[index
];
1026 struct eth_rx_bd
*rx_bd
= &fp
->rx_desc_ring
[index
];
1029 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buf_size
);
1030 if (unlikely(skb
== NULL
))
1033 mapping
= pci_map_single(bp
->pdev
, skb
->data
, bp
->rx_buf_size
,
1034 PCI_DMA_FROMDEVICE
);
1035 if (unlikely(dma_mapping_error(&bp
->pdev
->dev
, mapping
))) {
1041 pci_unmap_addr_set(rx_buf
, mapping
, mapping
);
1043 rx_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
1044 rx_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
1049 /* note that we are not allocating a new skb,
1050 * we are just moving one from cons to prod
1051 * we are not creating a new mapping,
1052 * so there is no need to check for dma_mapping_error().
1054 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath
*fp
,
1055 struct sk_buff
*skb
, u16 cons
, u16 prod
)
1057 struct bnx2x
*bp
= fp
->bp
;
1058 struct sw_rx_bd
*cons_rx_buf
= &fp
->rx_buf_ring
[cons
];
1059 struct sw_rx_bd
*prod_rx_buf
= &fp
->rx_buf_ring
[prod
];
1060 struct eth_rx_bd
*cons_bd
= &fp
->rx_desc_ring
[cons
];
1061 struct eth_rx_bd
*prod_bd
= &fp
->rx_desc_ring
[prod
];
1063 pci_dma_sync_single_for_device(bp
->pdev
,
1064 pci_unmap_addr(cons_rx_buf
, mapping
),
1065 bp
->rx_offset
+ RX_COPY_THRESH
,
1066 PCI_DMA_FROMDEVICE
);
1068 prod_rx_buf
->skb
= cons_rx_buf
->skb
;
1069 pci_unmap_addr_set(prod_rx_buf
, mapping
,
1070 pci_unmap_addr(cons_rx_buf
, mapping
));
1071 *prod_bd
= *cons_bd
;
1074 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath
*fp
,
1077 u16 last_max
= fp
->last_max_sge
;
1079 if (SUB_S16(idx
, last_max
) > 0)
1080 fp
->last_max_sge
= idx
;
1083 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath
*fp
)
1087 for (i
= 1; i
<= NUM_RX_SGE_PAGES
; i
++) {
1088 int idx
= RX_SGE_CNT
* i
- 1;
1090 for (j
= 0; j
< 2; j
++) {
1091 SGE_MASK_CLEAR_BIT(fp
, idx
);
1097 static void bnx2x_update_sge_prod(struct bnx2x_fastpath
*fp
,
1098 struct eth_fast_path_rx_cqe
*fp_cqe
)
1100 struct bnx2x
*bp
= fp
->bp
;
1101 u16 sge_len
= BCM_PAGE_ALIGN(le16_to_cpu(fp_cqe
->pkt_len
) -
1102 le16_to_cpu(fp_cqe
->len_on_bd
)) >>
1104 u16 last_max
, last_elem
, first_elem
;
1111 /* First mark all used pages */
1112 for (i
= 0; i
< sge_len
; i
++)
1113 SGE_MASK_CLEAR_BIT(fp
, RX_SGE(le16_to_cpu(fp_cqe
->sgl
[i
])));
1115 DP(NETIF_MSG_RX_STATUS
, "fp_cqe->sgl[%d] = %d\n",
1116 sge_len
- 1, le16_to_cpu(fp_cqe
->sgl
[sge_len
- 1]));
1118 /* Here we assume that the last SGE index is the biggest */
1119 prefetch((void *)(fp
->sge_mask
));
1120 bnx2x_update_last_max_sge(fp
, le16_to_cpu(fp_cqe
->sgl
[sge_len
- 1]));
1122 last_max
= RX_SGE(fp
->last_max_sge
);
1123 last_elem
= last_max
>> RX_SGE_MASK_ELEM_SHIFT
;
1124 first_elem
= RX_SGE(fp
->rx_sge_prod
) >> RX_SGE_MASK_ELEM_SHIFT
;
1126 /* If ring is not full */
1127 if (last_elem
+ 1 != first_elem
)
1130 /* Now update the prod */
1131 for (i
= first_elem
; i
!= last_elem
; i
= NEXT_SGE_MASK_ELEM(i
)) {
1132 if (likely(fp
->sge_mask
[i
]))
1135 fp
->sge_mask
[i
] = RX_SGE_MASK_ELEM_ONE_MASK
;
1136 delta
+= RX_SGE_MASK_ELEM_SZ
;
1140 fp
->rx_sge_prod
+= delta
;
1141 /* clear page-end entries */
1142 bnx2x_clear_sge_mask_next_elems(fp
);
1145 DP(NETIF_MSG_RX_STATUS
,
1146 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
1147 fp
->last_max_sge
, fp
->rx_sge_prod
);
1150 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath
*fp
)
1152 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1153 memset(fp
->sge_mask
, 0xff,
1154 (NUM_RX_SGE
>> RX_SGE_MASK_ELEM_SHIFT
)*sizeof(u64
));
1156 /* Clear the two last indices in the page to 1:
1157 these are the indices that correspond to the "next" element,
1158 hence will never be indicated and should be removed from
1159 the calculations. */
1160 bnx2x_clear_sge_mask_next_elems(fp
);
1163 static void bnx2x_tpa_start(struct bnx2x_fastpath
*fp
, u16 queue
,
1164 struct sk_buff
*skb
, u16 cons
, u16 prod
)
1166 struct bnx2x
*bp
= fp
->bp
;
1167 struct sw_rx_bd
*cons_rx_buf
= &fp
->rx_buf_ring
[cons
];
1168 struct sw_rx_bd
*prod_rx_buf
= &fp
->rx_buf_ring
[prod
];
1169 struct eth_rx_bd
*prod_bd
= &fp
->rx_desc_ring
[prod
];
1172 /* move empty skb from pool to prod and map it */
1173 prod_rx_buf
->skb
= fp
->tpa_pool
[queue
].skb
;
1174 mapping
= pci_map_single(bp
->pdev
, fp
->tpa_pool
[queue
].skb
->data
,
1175 bp
->rx_buf_size
, PCI_DMA_FROMDEVICE
);
1176 pci_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
1178 /* move partial skb from cons to pool (don't unmap yet) */
1179 fp
->tpa_pool
[queue
] = *cons_rx_buf
;
1181 /* mark bin state as start - print error if current state != stop */
1182 if (fp
->tpa_state
[queue
] != BNX2X_TPA_STOP
)
1183 BNX2X_ERR("start of bin not in stop [%d]\n", queue
);
1185 fp
->tpa_state
[queue
] = BNX2X_TPA_START
;
1187 /* point prod_bd to new skb */
1188 prod_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
1189 prod_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
1191 #ifdef BNX2X_STOP_ON_ERROR
1192 fp
->tpa_queue_used
|= (1 << queue
);
1193 #ifdef __powerpc64__
1194 DP(NETIF_MSG_RX_STATUS
, "fp->tpa_queue_used = 0x%lx\n",
1196 DP(NETIF_MSG_RX_STATUS
, "fp->tpa_queue_used = 0x%llx\n",
1198 fp
->tpa_queue_used
);
1202 static int bnx2x_fill_frag_skb(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
1203 struct sk_buff
*skb
,
1204 struct eth_fast_path_rx_cqe
*fp_cqe
,
1207 struct sw_rx_page
*rx_pg
, old_rx_pg
;
1209 u16 len_on_bd
= le16_to_cpu(fp_cqe
->len_on_bd
);
1210 u32 i
, frag_len
, frag_size
, pages
;
1214 frag_size
= le16_to_cpu(fp_cqe
->pkt_len
) - len_on_bd
;
1215 pages
= BCM_PAGE_ALIGN(frag_size
) >> BCM_PAGE_SHIFT
;
1217 /* This is needed in order to enable forwarding support */
1219 skb_shinfo(skb
)->gso_size
= min((u32
)BCM_PAGE_SIZE
,
1220 max(frag_size
, (u32
)len_on_bd
));
1222 #ifdef BNX2X_STOP_ON_ERROR
1223 if (pages
> 8*PAGES_PER_SGE
) {
1224 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1226 BNX2X_ERR("fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
1227 fp_cqe
->pkt_len
, len_on_bd
);
1233 /* Run through the SGL and compose the fragmented skb */
1234 for (i
= 0, j
= 0; i
< pages
; i
+= PAGES_PER_SGE
, j
++) {
1235 u16 sge_idx
= RX_SGE(le16_to_cpu(fp_cqe
->sgl
[j
]));
1237 /* FW gives the indices of the SGE as if the ring is an array
1238 (meaning that "next" element will consume 2 indices) */
1239 frag_len
= min(frag_size
, (u32
)(BCM_PAGE_SIZE
*PAGES_PER_SGE
));
1240 rx_pg
= &fp
->rx_page_ring
[sge_idx
];
1244 /* If we fail to allocate a substitute page, we simply stop
1245 where we are and drop the whole packet */
1246 err
= bnx2x_alloc_rx_sge(bp
, fp
, sge_idx
);
1247 if (unlikely(err
)) {
1248 bp
->eth_stats
.rx_skb_alloc_failed
++;
1252 /* Unmap the page as we r going to pass it to the stack */
1253 pci_unmap_page(bp
->pdev
, pci_unmap_addr(&old_rx_pg
, mapping
),
1254 BCM_PAGE_SIZE
*PAGES_PER_SGE
, PCI_DMA_FROMDEVICE
);
1256 /* Add one frag and update the appropriate fields in the skb */
1257 skb_fill_page_desc(skb
, j
, old_rx_pg
.page
, 0, frag_len
);
1259 skb
->data_len
+= frag_len
;
1260 skb
->truesize
+= frag_len
;
1261 skb
->len
+= frag_len
;
1263 frag_size
-= frag_len
;
1269 static void bnx2x_tpa_stop(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
1270 u16 queue
, int pad
, int len
, union eth_rx_cqe
*cqe
,
1273 struct sw_rx_bd
*rx_buf
= &fp
->tpa_pool
[queue
];
1274 struct sk_buff
*skb
= rx_buf
->skb
;
1276 struct sk_buff
*new_skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buf_size
);
1278 /* Unmap skb in the pool anyway, as we are going to change
1279 pool entry status to BNX2X_TPA_STOP even if new skb allocation
1281 pci_unmap_single(bp
->pdev
, pci_unmap_addr(rx_buf
, mapping
),
1282 bp
->rx_buf_size
, PCI_DMA_FROMDEVICE
);
1284 if (likely(new_skb
)) {
1285 /* fix ip xsum and give it to the stack */
1286 /* (no need to map the new skb) */
1289 prefetch(((char *)(skb
)) + 128);
1291 #ifdef BNX2X_STOP_ON_ERROR
1292 if (pad
+ len
> bp
->rx_buf_size
) {
1293 BNX2X_ERR("skb_put is about to fail... "
1294 "pad %d len %d rx_buf_size %d\n",
1295 pad
, len
, bp
->rx_buf_size
);
1301 skb_reserve(skb
, pad
);
1304 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1305 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1310 iph
= (struct iphdr
*)skb
->data
;
1312 iph
->check
= ip_fast_csum((u8
*)iph
, iph
->ihl
);
1315 if (!bnx2x_fill_frag_skb(bp
, fp
, skb
,
1316 &cqe
->fast_path_cqe
, cqe_idx
)) {
1318 if ((bp
->vlgrp
!= NULL
) &&
1319 (le16_to_cpu(cqe
->fast_path_cqe
.pars_flags
.flags
) &
1320 PARSING_FLAGS_VLAN
))
1321 vlan_hwaccel_receive_skb(skb
, bp
->vlgrp
,
1322 le16_to_cpu(cqe
->fast_path_cqe
.
1326 netif_receive_skb(skb
);
1328 DP(NETIF_MSG_RX_STATUS
, "Failed to allocate new pages"
1329 " - dropping packet!\n");
1334 /* put new skb in bin */
1335 fp
->tpa_pool
[queue
].skb
= new_skb
;
1338 /* else drop the packet and keep the buffer in the bin */
1339 DP(NETIF_MSG_RX_STATUS
,
1340 "Failed to allocate new skb - dropping packet!\n");
1341 bp
->eth_stats
.rx_skb_alloc_failed
++;
1344 fp
->tpa_state
[queue
] = BNX2X_TPA_STOP
;
1347 static inline void bnx2x_update_rx_prod(struct bnx2x
*bp
,
1348 struct bnx2x_fastpath
*fp
,
1349 u16 bd_prod
, u16 rx_comp_prod
,
1352 struct tstorm_eth_rx_producers rx_prods
= {0};
1355 /* Update producers */
1356 rx_prods
.bd_prod
= bd_prod
;
1357 rx_prods
.cqe_prod
= rx_comp_prod
;
1358 rx_prods
.sge_prod
= rx_sge_prod
;
1361 * Make sure that the BD and SGE data is updated before updating the
1362 * producers since FW might read the BD/SGE right after the producer
1364 * This is only applicable for weak-ordered memory model archs such
1365 * as IA-64. The following barrier is also mandatory since FW will
1366 * assumes BDs must have buffers.
1370 for (i
= 0; i
< sizeof(struct tstorm_eth_rx_producers
)/4; i
++)
1371 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
1372 TSTORM_RX_PRODS_OFFSET(BP_PORT(bp
), FP_CL_ID(fp
)) + i
*4,
1373 ((u32
*)&rx_prods
)[i
]);
1375 mmiowb(); /* keep prod updates ordered */
1377 DP(NETIF_MSG_RX_STATUS
,
1378 "Wrote: bd_prod %u cqe_prod %u sge_prod %u\n",
1379 bd_prod
, rx_comp_prod
, rx_sge_prod
);
1382 static int bnx2x_rx_int(struct bnx2x_fastpath
*fp
, int budget
)
1384 struct bnx2x
*bp
= fp
->bp
;
1385 u16 bd_cons
, bd_prod
, bd_prod_fw
, comp_ring_cons
;
1386 u16 hw_comp_cons
, sw_comp_cons
, sw_comp_prod
;
1389 #ifdef BNX2X_STOP_ON_ERROR
1390 if (unlikely(bp
->panic
))
1394 /* CQ "next element" is of the size of the regular element,
1395 that's why it's ok here */
1396 hw_comp_cons
= le16_to_cpu(*fp
->rx_cons_sb
);
1397 if ((hw_comp_cons
& MAX_RCQ_DESC_CNT
) == MAX_RCQ_DESC_CNT
)
1400 bd_cons
= fp
->rx_bd_cons
;
1401 bd_prod
= fp
->rx_bd_prod
;
1402 bd_prod_fw
= bd_prod
;
1403 sw_comp_cons
= fp
->rx_comp_cons
;
1404 sw_comp_prod
= fp
->rx_comp_prod
;
1406 /* Memory barrier necessary as speculative reads of the rx
1407 * buffer can be ahead of the index in the status block
1411 DP(NETIF_MSG_RX_STATUS
,
1412 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
1413 FP_IDX(fp
), hw_comp_cons
, sw_comp_cons
);
1415 while (sw_comp_cons
!= hw_comp_cons
) {
1416 struct sw_rx_bd
*rx_buf
= NULL
;
1417 struct sk_buff
*skb
;
1418 union eth_rx_cqe
*cqe
;
1422 comp_ring_cons
= RCQ_BD(sw_comp_cons
);
1423 bd_prod
= RX_BD(bd_prod
);
1424 bd_cons
= RX_BD(bd_cons
);
1426 cqe
= &fp
->rx_comp_ring
[comp_ring_cons
];
1427 cqe_fp_flags
= cqe
->fast_path_cqe
.type_error_flags
;
1429 DP(NETIF_MSG_RX_STATUS
, "CQE type %x err %x status %x"
1430 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags
),
1431 cqe_fp_flags
, cqe
->fast_path_cqe
.status_flags
,
1432 cqe
->fast_path_cqe
.rss_hash_result
,
1433 le16_to_cpu(cqe
->fast_path_cqe
.vlan_tag
),
1434 le16_to_cpu(cqe
->fast_path_cqe
.pkt_len
));
1436 /* is this a slowpath msg? */
1437 if (unlikely(CQE_TYPE(cqe_fp_flags
))) {
1438 bnx2x_sp_event(fp
, cqe
);
1441 /* this is an rx packet */
1443 rx_buf
= &fp
->rx_buf_ring
[bd_cons
];
1445 len
= le16_to_cpu(cqe
->fast_path_cqe
.pkt_len
);
1446 pad
= cqe
->fast_path_cqe
.placement_offset
;
1448 /* If CQE is marked both TPA_START and TPA_END
1449 it is a non-TPA CQE */
1450 if ((!fp
->disable_tpa
) &&
1451 (TPA_TYPE(cqe_fp_flags
) !=
1452 (TPA_TYPE_START
| TPA_TYPE_END
))) {
1453 u16 queue
= cqe
->fast_path_cqe
.queue_index
;
1455 if (TPA_TYPE(cqe_fp_flags
) == TPA_TYPE_START
) {
1456 DP(NETIF_MSG_RX_STATUS
,
1457 "calling tpa_start on queue %d\n",
1460 bnx2x_tpa_start(fp
, queue
, skb
,
1465 if (TPA_TYPE(cqe_fp_flags
) == TPA_TYPE_END
) {
1466 DP(NETIF_MSG_RX_STATUS
,
1467 "calling tpa_stop on queue %d\n",
1470 if (!BNX2X_RX_SUM_FIX(cqe
))
1471 BNX2X_ERR("STOP on none TCP "
1474 /* This is a size of the linear data
1476 len
= le16_to_cpu(cqe
->fast_path_cqe
.
1478 bnx2x_tpa_stop(bp
, fp
, queue
, pad
,
1479 len
, cqe
, comp_ring_cons
);
1480 #ifdef BNX2X_STOP_ON_ERROR
1485 bnx2x_update_sge_prod(fp
,
1486 &cqe
->fast_path_cqe
);
1491 pci_dma_sync_single_for_device(bp
->pdev
,
1492 pci_unmap_addr(rx_buf
, mapping
),
1493 pad
+ RX_COPY_THRESH
,
1494 PCI_DMA_FROMDEVICE
);
1496 prefetch(((char *)(skb
)) + 128);
1498 /* is this an error packet? */
1499 if (unlikely(cqe_fp_flags
& ETH_RX_ERROR_FALGS
)) {
1500 DP(NETIF_MSG_RX_ERR
,
1501 "ERROR flags %x rx packet %u\n",
1502 cqe_fp_flags
, sw_comp_cons
);
1503 bp
->eth_stats
.rx_err_discard_pkt
++;
1507 /* Since we don't have a jumbo ring
1508 * copy small packets if mtu > 1500
1510 if ((bp
->dev
->mtu
> ETH_MAX_PACKET_SIZE
) &&
1511 (len
<= RX_COPY_THRESH
)) {
1512 struct sk_buff
*new_skb
;
1514 new_skb
= netdev_alloc_skb(bp
->dev
,
1516 if (new_skb
== NULL
) {
1517 DP(NETIF_MSG_RX_ERR
,
1518 "ERROR packet dropped "
1519 "because of alloc failure\n");
1520 bp
->eth_stats
.rx_skb_alloc_failed
++;
1525 skb_copy_from_linear_data_offset(skb
, pad
,
1526 new_skb
->data
+ pad
, len
);
1527 skb_reserve(new_skb
, pad
);
1528 skb_put(new_skb
, len
);
1530 bnx2x_reuse_rx_skb(fp
, skb
, bd_cons
, bd_prod
);
1534 } else if (bnx2x_alloc_rx_skb(bp
, fp
, bd_prod
) == 0) {
1535 pci_unmap_single(bp
->pdev
,
1536 pci_unmap_addr(rx_buf
, mapping
),
1538 PCI_DMA_FROMDEVICE
);
1539 skb_reserve(skb
, pad
);
1543 DP(NETIF_MSG_RX_ERR
,
1544 "ERROR packet dropped because "
1545 "of alloc failure\n");
1546 bp
->eth_stats
.rx_skb_alloc_failed
++;
1548 bnx2x_reuse_rx_skb(fp
, skb
, bd_cons
, bd_prod
);
1552 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1554 skb
->ip_summed
= CHECKSUM_NONE
;
1556 if (likely(BNX2X_RX_CSUM_OK(cqe
)))
1557 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1559 bp
->eth_stats
.hw_csum_err
++;
1564 if ((bp
->vlgrp
!= NULL
) &&
1565 (le16_to_cpu(cqe
->fast_path_cqe
.pars_flags
.flags
) &
1566 PARSING_FLAGS_VLAN
))
1567 vlan_hwaccel_receive_skb(skb
, bp
->vlgrp
,
1568 le16_to_cpu(cqe
->fast_path_cqe
.vlan_tag
));
1571 netif_receive_skb(skb
);
1577 bd_cons
= NEXT_RX_IDX(bd_cons
);
1578 bd_prod
= NEXT_RX_IDX(bd_prod
);
1579 bd_prod_fw
= NEXT_RX_IDX(bd_prod_fw
);
1582 sw_comp_prod
= NEXT_RCQ_IDX(sw_comp_prod
);
1583 sw_comp_cons
= NEXT_RCQ_IDX(sw_comp_cons
);
1585 if (rx_pkt
== budget
)
1589 fp
->rx_bd_cons
= bd_cons
;
1590 fp
->rx_bd_prod
= bd_prod_fw
;
1591 fp
->rx_comp_cons
= sw_comp_cons
;
1592 fp
->rx_comp_prod
= sw_comp_prod
;
1594 /* Update producers */
1595 bnx2x_update_rx_prod(bp
, fp
, bd_prod_fw
, sw_comp_prod
,
1598 fp
->rx_pkt
+= rx_pkt
;
1604 static irqreturn_t
bnx2x_msix_fp_int(int irq
, void *fp_cookie
)
1606 struct bnx2x_fastpath
*fp
= fp_cookie
;
1607 struct bnx2x
*bp
= fp
->bp
;
1608 int index
= FP_IDX(fp
);
1610 /* Return here if interrupt is disabled */
1611 if (unlikely(atomic_read(&bp
->intr_sem
) != 0)) {
1612 DP(NETIF_MSG_INTR
, "called but intr_sem not 0, returning\n");
1616 DP(BNX2X_MSG_FP
, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1617 index
, FP_SB_ID(fp
));
1618 bnx2x_ack_sb(bp
, FP_SB_ID(fp
), USTORM_ID
, 0, IGU_INT_DISABLE
, 0);
1620 #ifdef BNX2X_STOP_ON_ERROR
1621 if (unlikely(bp
->panic
))
1625 prefetch(fp
->rx_cons_sb
);
1626 prefetch(fp
->tx_cons_sb
);
1627 prefetch(&fp
->status_blk
->c_status_block
.status_block_index
);
1628 prefetch(&fp
->status_blk
->u_status_block
.status_block_index
);
1630 netif_rx_schedule(&bnx2x_fp(bp
, index
, napi
));
1635 static irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1637 struct net_device
*dev
= dev_instance
;
1638 struct bnx2x
*bp
= netdev_priv(dev
);
1639 u16 status
= bnx2x_ack_int(bp
);
1642 /* Return here if interrupt is shared and it's not for us */
1643 if (unlikely(status
== 0)) {
1644 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1647 DP(NETIF_MSG_INTR
, "got an interrupt status %u\n", status
);
1649 /* Return here if interrupt is disabled */
1650 if (unlikely(atomic_read(&bp
->intr_sem
) != 0)) {
1651 DP(NETIF_MSG_INTR
, "called but intr_sem not 0, returning\n");
1655 #ifdef BNX2X_STOP_ON_ERROR
1656 if (unlikely(bp
->panic
))
1660 mask
= 0x2 << bp
->fp
[0].sb_id
;
1661 if (status
& mask
) {
1662 struct bnx2x_fastpath
*fp
= &bp
->fp
[0];
1664 prefetch(fp
->rx_cons_sb
);
1665 prefetch(fp
->tx_cons_sb
);
1666 prefetch(&fp
->status_blk
->c_status_block
.status_block_index
);
1667 prefetch(&fp
->status_blk
->u_status_block
.status_block_index
);
1669 netif_rx_schedule(&bnx2x_fp(bp
, 0, napi
));
1675 if (unlikely(status
& 0x1)) {
1676 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1684 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status %u)\n",
1690 /* end of fast path */
1692 static void bnx2x_stats_handle(struct bnx2x
*bp
, enum bnx2x_stats_event event
);
1697 * General service functions
1700 static int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1703 u32 resource_bit
= (1 << resource
);
1704 int func
= BP_FUNC(bp
);
1705 u32 hw_lock_control_reg
;
1708 /* Validating that the resource is within range */
1709 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1711 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1712 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1717 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1719 hw_lock_control_reg
=
1720 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1723 /* Validating that the resource is not already taken */
1724 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1725 if (lock_status
& resource_bit
) {
1726 DP(NETIF_MSG_HW
, "lock_status 0x%x resource_bit 0x%x\n",
1727 lock_status
, resource_bit
);
1731 /* Try for 5 second every 5ms */
1732 for (cnt
= 0; cnt
< 1000; cnt
++) {
1733 /* Try to acquire the lock */
1734 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1735 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1736 if (lock_status
& resource_bit
)
1741 DP(NETIF_MSG_HW
, "Timeout\n");
1745 static int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
1748 u32 resource_bit
= (1 << resource
);
1749 int func
= BP_FUNC(bp
);
1750 u32 hw_lock_control_reg
;
1752 /* Validating that the resource is within range */
1753 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1755 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1756 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1761 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1763 hw_lock_control_reg
=
1764 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1767 /* Validating that the resource is currently taken */
1768 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1769 if (!(lock_status
& resource_bit
)) {
1770 DP(NETIF_MSG_HW
, "lock_status 0x%x resource_bit 0x%x\n",
1771 lock_status
, resource_bit
);
1775 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
1779 /* HW Lock for shared dual port PHYs */
1780 static void bnx2x_acquire_phy_lock(struct bnx2x
*bp
)
1782 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(bp
->link_params
.ext_phy_config
);
1784 mutex_lock(&bp
->port
.phy_mutex
);
1786 if ((ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) ||
1787 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
))
1788 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_8072_MDIO
);
1791 static void bnx2x_release_phy_lock(struct bnx2x
*bp
)
1793 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(bp
->link_params
.ext_phy_config
);
1795 if ((ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) ||
1796 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
))
1797 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_8072_MDIO
);
1799 mutex_unlock(&bp
->port
.phy_mutex
);
1802 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
1804 /* The GPIO should be swapped if swap register is set and active */
1805 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1806 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1807 int gpio_shift
= gpio_num
+
1808 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1809 u32 gpio_mask
= (1 << gpio_shift
);
1812 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1813 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1817 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1818 /* read GPIO and mask except the float bits */
1819 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
1822 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
1823 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> output low\n",
1824 gpio_num
, gpio_shift
);
1825 /* clear FLOAT and set CLR */
1826 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1827 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
1830 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
1831 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> output high\n",
1832 gpio_num
, gpio_shift
);
1833 /* clear FLOAT and set SET */
1834 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1835 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
1838 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
1839 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> input\n",
1840 gpio_num
, gpio_shift
);
1842 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1849 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
1850 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1855 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio_num
, u32 mode
)
1857 u32 spio_mask
= (1 << spio_num
);
1860 if ((spio_num
< MISC_REGISTERS_SPIO_4
) ||
1861 (spio_num
> MISC_REGISTERS_SPIO_7
)) {
1862 BNX2X_ERR("Invalid SPIO %d\n", spio_num
);
1866 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
1867 /* read SPIO and mask except the float bits */
1868 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_REGISTERS_SPIO_FLOAT
);
1871 case MISC_REGISTERS_SPIO_OUTPUT_LOW
:
1872 DP(NETIF_MSG_LINK
, "Set SPIO %d -> output low\n", spio_num
);
1873 /* clear FLOAT and set CLR */
1874 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
1875 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_CLR_POS
);
1878 case MISC_REGISTERS_SPIO_OUTPUT_HIGH
:
1879 DP(NETIF_MSG_LINK
, "Set SPIO %d -> output high\n", spio_num
);
1880 /* clear FLOAT and set SET */
1881 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
1882 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_SET_POS
);
1885 case MISC_REGISTERS_SPIO_INPUT_HI_Z
:
1886 DP(NETIF_MSG_LINK
, "Set SPIO %d -> input\n", spio_num
);
1888 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
1895 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
1896 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
1901 static void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
1903 switch (bp
->link_vars
.ieee_fc
) {
1904 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
:
1905 bp
->port
.advertising
&= ~(ADVERTISED_Asym_Pause
|
1908 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
1909 bp
->port
.advertising
|= (ADVERTISED_Asym_Pause
|
1912 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
1913 bp
->port
.advertising
|= ADVERTISED_Asym_Pause
;
1916 bp
->port
.advertising
&= ~(ADVERTISED_Asym_Pause
|
1922 static void bnx2x_link_report(struct bnx2x
*bp
)
1924 if (bp
->link_vars
.link_up
) {
1925 if (bp
->state
== BNX2X_STATE_OPEN
)
1926 netif_carrier_on(bp
->dev
);
1927 printk(KERN_INFO PFX
"%s NIC Link is Up, ", bp
->dev
->name
);
1929 printk("%d Mbps ", bp
->link_vars
.line_speed
);
1931 if (bp
->link_vars
.duplex
== DUPLEX_FULL
)
1932 printk("full duplex");
1934 printk("half duplex");
1936 if (bp
->link_vars
.flow_ctrl
!= BNX2X_FLOW_CTRL_NONE
) {
1937 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_RX
) {
1938 printk(", receive ");
1939 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
1940 printk("& transmit ");
1942 printk(", transmit ");
1944 printk("flow control ON");
1948 } else { /* link_down */
1949 netif_carrier_off(bp
->dev
);
1950 printk(KERN_ERR PFX
"%s NIC Link is Down\n", bp
->dev
->name
);
1954 static u8
bnx2x_initial_phy_init(struct bnx2x
*bp
)
1956 if (!BP_NOMCP(bp
)) {
1959 /* Initialize link parameters structure variables */
1960 /* It is recommended to turn off RX FC for jumbo frames
1961 for better performance */
1963 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
1964 else if (bp
->dev
->mtu
> 5000)
1965 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
1967 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
1969 bnx2x_acquire_phy_lock(bp
);
1970 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
1971 bnx2x_release_phy_lock(bp
);
1973 if (bp
->link_vars
.link_up
)
1974 bnx2x_link_report(bp
);
1976 bnx2x_calc_fc_adv(bp
);
1980 BNX2X_ERR("Bootcode is missing -not initializing link\n");
1984 static void bnx2x_link_set(struct bnx2x
*bp
)
1986 if (!BP_NOMCP(bp
)) {
1987 bnx2x_acquire_phy_lock(bp
);
1988 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
1989 bnx2x_release_phy_lock(bp
);
1991 bnx2x_calc_fc_adv(bp
);
1993 BNX2X_ERR("Bootcode is missing -not setting link\n");
1996 static void bnx2x__link_reset(struct bnx2x
*bp
)
1998 if (!BP_NOMCP(bp
)) {
1999 bnx2x_acquire_phy_lock(bp
);
2000 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
);
2001 bnx2x_release_phy_lock(bp
);
2003 BNX2X_ERR("Bootcode is missing -not resetting link\n");
2006 static u8
bnx2x_link_test(struct bnx2x
*bp
)
2010 bnx2x_acquire_phy_lock(bp
);
2011 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
);
2012 bnx2x_release_phy_lock(bp
);
2017 /* Calculates the sum of vn_min_rates.
2018 It's needed for further normalizing of the min_rates.
2023 0 - if all the min_rates are 0.
2024 In the later case fairness algorithm should be deactivated.
2025 If not all min_rates are zero then those that are zeroes will
2028 static u32
bnx2x_calc_vn_wsum(struct bnx2x
*bp
)
2030 int i
, port
= BP_PORT(bp
);
2034 for (i
= 0; i
< E1HVN_MAX
; i
++) {
2036 SHMEM_RD(bp
, mf_cfg
.func_mf_config
[2*i
+ port
].config
);
2037 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2038 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2039 if (!(vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)) {
2040 /* If min rate is zero - set it to 1 */
2042 vn_min_rate
= DEF_MIN_RATE
;
2046 wsum
+= vn_min_rate
;
2050 /* ... only if all min rates are zeros - disable FAIRNESS */
2057 static void bnx2x_init_port_minmax(struct bnx2x
*bp
,
2060 struct cmng_struct_per_port
*m_cmng_port
)
2062 u32 r_param
= port_rate
/ 8;
2063 int port
= BP_PORT(bp
);
2066 memset(m_cmng_port
, 0, sizeof(struct cmng_struct_per_port
));
2068 /* Enable minmax only if we are in e1hmf mode */
2070 u32 fair_periodic_timeout_usec
;
2073 /* Enable rate shaping and fairness */
2074 m_cmng_port
->flags
.cmng_vn_enable
= 1;
2075 m_cmng_port
->flags
.fairness_enable
= en_fness
? 1 : 0;
2076 m_cmng_port
->flags
.rate_shaping_enable
= 1;
2079 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2080 " fairness will be disabled\n");
2082 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2083 m_cmng_port
->rs_vars
.rs_periodic_timeout
=
2084 RS_PERIODIC_TIMEOUT_USEC
/ 4;
2086 /* this is the threshold below which no timer arming will occur
2087 1.25 coefficient is for the threshold to be a little bigger
2088 than the real time, to compensate for timer in-accuracy */
2089 m_cmng_port
->rs_vars
.rs_threshold
=
2090 (RS_PERIODIC_TIMEOUT_USEC
* r_param
* 5) / 4;
2092 /* resolution of fairness timer */
2093 fair_periodic_timeout_usec
= QM_ARB_BYTES
/ r_param
;
2094 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2095 t_fair
= T_FAIR_COEF
/ port_rate
;
2097 /* this is the threshold below which we won't arm
2098 the timer anymore */
2099 m_cmng_port
->fair_vars
.fair_threshold
= QM_ARB_BYTES
;
2101 /* we multiply by 1e3/8 to get bytes/msec.
2102 We don't want the credits to pass a credit
2103 of the T_FAIR*FAIR_MEM (algorithm resolution) */
2104 m_cmng_port
->fair_vars
.upper_bound
=
2105 r_param
* t_fair
* FAIR_MEM
;
2106 /* since each tick is 4 usec */
2107 m_cmng_port
->fair_vars
.fairness_timeout
=
2108 fair_periodic_timeout_usec
/ 4;
2111 /* Disable rate shaping and fairness */
2112 m_cmng_port
->flags
.cmng_vn_enable
= 0;
2113 m_cmng_port
->flags
.fairness_enable
= 0;
2114 m_cmng_port
->flags
.rate_shaping_enable
= 0;
2117 "Single function mode minmax will be disabled\n");
2120 /* Store it to internal memory */
2121 for (i
= 0; i
< sizeof(struct cmng_struct_per_port
) / 4; i
++)
2122 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2123 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
) + i
* 4,
2124 ((u32
*)(m_cmng_port
))[i
]);
2127 static void bnx2x_init_vn_minmax(struct bnx2x
*bp
, int func
,
2128 u32 wsum
, u16 port_rate
,
2129 struct cmng_struct_per_port
*m_cmng_port
)
2131 struct rate_shaping_vars_per_vn m_rs_vn
;
2132 struct fairness_vars_per_vn m_fair_vn
;
2133 u32 vn_cfg
= SHMEM_RD(bp
, mf_cfg
.func_mf_config
[func
].config
);
2134 u16 vn_min_rate
, vn_max_rate
;
2137 /* If function is hidden - set min and max to zeroes */
2138 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
) {
2143 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2144 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2145 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2146 if current min rate is zero - set it to 1.
2147 This is a requirement of the algorithm. */
2148 if ((vn_min_rate
== 0) && wsum
)
2149 vn_min_rate
= DEF_MIN_RATE
;
2150 vn_max_rate
= ((vn_cfg
& FUNC_MF_CFG_MAX_BW_MASK
) >>
2151 FUNC_MF_CFG_MAX_BW_SHIFT
) * 100;
2154 DP(NETIF_MSG_IFUP
, "func %d: vn_min_rate=%d vn_max_rate=%d "
2155 "wsum=%d\n", func
, vn_min_rate
, vn_max_rate
, wsum
);
2157 memset(&m_rs_vn
, 0, sizeof(struct rate_shaping_vars_per_vn
));
2158 memset(&m_fair_vn
, 0, sizeof(struct fairness_vars_per_vn
));
2160 /* global vn counter - maximal Mbps for this vn */
2161 m_rs_vn
.vn_counter
.rate
= vn_max_rate
;
2163 /* quota - number of bytes transmitted in this period */
2164 m_rs_vn
.vn_counter
.quota
=
2165 (vn_max_rate
* RS_PERIODIC_TIMEOUT_USEC
) / 8;
2167 #ifdef BNX2X_PER_PROT_QOS
2168 /* per protocol counter */
2169 for (protocol
= 0; protocol
< NUM_OF_PROTOCOLS
; protocol
++) {
2170 /* maximal Mbps for this protocol */
2171 m_rs_vn
.protocol_counters
[protocol
].rate
=
2172 protocol_max_rate
[protocol
];
2173 /* the quota in each timer period -
2174 number of bytes transmitted in this period */
2175 m_rs_vn
.protocol_counters
[protocol
].quota
=
2176 (u32
)(rs_periodic_timeout_usec
*
2178 protocol_counters
[protocol
].rate
/8));
2183 /* credit for each period of the fairness algorithm:
2184 number of bytes in T_FAIR (the vn share the port rate).
2185 wsum should not be larger than 10000, thus
2186 T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2187 m_fair_vn
.vn_credit_delta
=
2188 max((u64
)(vn_min_rate
* (T_FAIR_COEF
/ (8 * wsum
))),
2189 (u64
)(m_cmng_port
->fair_vars
.fair_threshold
* 2));
2190 DP(NETIF_MSG_IFUP
, "m_fair_vn.vn_credit_delta=%d\n",
2191 m_fair_vn
.vn_credit_delta
);
2194 #ifdef BNX2X_PER_PROT_QOS
2196 u32 protocolWeightSum
= 0;
2198 for (protocol
= 0; protocol
< NUM_OF_PROTOCOLS
; protocol
++)
2199 protocolWeightSum
+=
2200 drvInit
.protocol_min_rate
[protocol
];
2201 /* per protocol counter -
2202 NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2203 if (protocolWeightSum
> 0) {
2205 protocol
< NUM_OF_PROTOCOLS
; protocol
++)
2206 /* credit for each period of the
2207 fairness algorithm - number of bytes in
2208 T_FAIR (the protocol share the vn rate) */
2209 m_fair_vn
.protocol_credit_delta
[protocol
] =
2210 (u32
)((vn_min_rate
/ 8) * t_fair
*
2211 protocol_min_rate
/ protocolWeightSum
);
2216 /* Store it to internal memory */
2217 for (i
= 0; i
< sizeof(struct rate_shaping_vars_per_vn
)/4; i
++)
2218 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2219 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
) + i
* 4,
2220 ((u32
*)(&m_rs_vn
))[i
]);
2222 for (i
= 0; i
< sizeof(struct fairness_vars_per_vn
)/4; i
++)
2223 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2224 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
) + i
* 4,
2225 ((u32
*)(&m_fair_vn
))[i
]);
2228 /* This function is called upon link interrupt */
2229 static void bnx2x_link_attn(struct bnx2x
*bp
)
2233 /* Make sure that we are synced with the current statistics */
2234 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2236 bnx2x_acquire_phy_lock(bp
);
2237 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2238 bnx2x_release_phy_lock(bp
);
2240 if (bp
->link_vars
.link_up
) {
2242 if (bp
->link_vars
.mac_type
== MAC_TYPE_BMAC
) {
2243 struct host_port_stats
*pstats
;
2245 pstats
= bnx2x_sp(bp
, port_stats
);
2246 /* reset old bmac stats */
2247 memset(&(pstats
->mac_stx
[0]), 0,
2248 sizeof(struct mac_stx
));
2250 if ((bp
->state
== BNX2X_STATE_OPEN
) ||
2251 (bp
->state
== BNX2X_STATE_DISABLED
))
2252 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2255 /* indicate link status */
2256 bnx2x_link_report(bp
);
2261 for (vn
= VN_0
; vn
< E1HVN_MAX
; vn
++) {
2262 if (vn
== BP_E1HVN(bp
))
2265 func
= ((vn
<< 1) | BP_PORT(bp
));
2267 /* Set the attention towards other drivers
2269 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_0
+
2270 (LINK_SYNC_ATTENTION_BIT_FUNC_0
+ func
)*4, 1);
2274 if (CHIP_IS_E1H(bp
) && (bp
->link_vars
.line_speed
> 0)) {
2275 struct cmng_struct_per_port m_cmng_port
;
2277 int port
= BP_PORT(bp
);
2279 /* Init RATE SHAPING and FAIRNESS contexts */
2280 wsum
= bnx2x_calc_vn_wsum(bp
);
2281 bnx2x_init_port_minmax(bp
, (int)wsum
,
2282 bp
->link_vars
.line_speed
,
2285 for (vn
= VN_0
; vn
< E1HVN_MAX
; vn
++)
2286 bnx2x_init_vn_minmax(bp
, 2*vn
+ port
,
2287 wsum
, bp
->link_vars
.line_speed
,
2292 static void bnx2x__link_status_update(struct bnx2x
*bp
)
2294 if (bp
->state
!= BNX2X_STATE_OPEN
)
2297 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2299 if (bp
->link_vars
.link_up
)
2300 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2302 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2304 /* indicate link status */
2305 bnx2x_link_report(bp
);
2308 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2310 int port
= BP_PORT(bp
);
2314 DP(NETIF_MSG_LINK
, "pmf %d\n", bp
->port
.pmf
);
2316 /* enable nig attention */
2317 val
= (0xff0f | (1 << (BP_E1HVN(bp
) + 4)));
2318 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2319 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2321 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
2329 * General service functions
2332 /* the slow path queue is odd since completions arrive on the fastpath ring */
2333 static int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
2334 u32 data_hi
, u32 data_lo
, int common
)
2336 int func
= BP_FUNC(bp
);
2338 DP(BNX2X_MSG_SP
/*NETIF_MSG_TIMER*/,
2339 "SPQE (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
2340 (u32
)U64_HI(bp
->spq_mapping
), (u32
)(U64_LO(bp
->spq_mapping
) +
2341 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
,
2342 HW_CID(bp
, cid
), data_hi
, data_lo
, bp
->spq_left
);
2344 #ifdef BNX2X_STOP_ON_ERROR
2345 if (unlikely(bp
->panic
))
2349 spin_lock_bh(&bp
->spq_lock
);
2351 if (!bp
->spq_left
) {
2352 BNX2X_ERR("BUG! SPQ ring full!\n");
2353 spin_unlock_bh(&bp
->spq_lock
);
2358 /* CID needs port number to be encoded int it */
2359 bp
->spq_prod_bd
->hdr
.conn_and_cmd_data
=
2360 cpu_to_le32(((command
<< SPE_HDR_CMD_ID_SHIFT
) |
2362 bp
->spq_prod_bd
->hdr
.type
= cpu_to_le16(ETH_CONNECTION_TYPE
);
2364 bp
->spq_prod_bd
->hdr
.type
|=
2365 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT
));
2367 bp
->spq_prod_bd
->data
.mac_config_addr
.hi
= cpu_to_le32(data_hi
);
2368 bp
->spq_prod_bd
->data
.mac_config_addr
.lo
= cpu_to_le32(data_lo
);
2372 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
2373 bp
->spq_prod_bd
= bp
->spq
;
2374 bp
->spq_prod_idx
= 0;
2375 DP(NETIF_MSG_TIMER
, "end of spq\n");
2382 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
2385 spin_unlock_bh(&bp
->spq_lock
);
2389 /* acquire split MCP access lock register */
2390 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
2397 for (j
= 0; j
< i
*10; j
++) {
2399 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
2400 val
= REG_RD(bp
, GRCBASE_MCP
+ 0x9c);
2401 if (val
& (1L << 31))
2406 if (!(val
& (1L << 31))) {
2407 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2414 /* release split MCP access lock register */
2415 static void bnx2x_release_alr(struct bnx2x
*bp
)
2419 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
2422 static inline u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
2424 struct host_def_status_block
*def_sb
= bp
->def_status_blk
;
2427 barrier(); /* status block is written to by the chip */
2428 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
2429 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
2432 if (bp
->def_c_idx
!= def_sb
->c_def_status_block
.status_block_index
) {
2433 bp
->def_c_idx
= def_sb
->c_def_status_block
.status_block_index
;
2436 if (bp
->def_u_idx
!= def_sb
->u_def_status_block
.status_block_index
) {
2437 bp
->def_u_idx
= def_sb
->u_def_status_block
.status_block_index
;
2440 if (bp
->def_x_idx
!= def_sb
->x_def_status_block
.status_block_index
) {
2441 bp
->def_x_idx
= def_sb
->x_def_status_block
.status_block_index
;
2444 if (bp
->def_t_idx
!= def_sb
->t_def_status_block
.status_block_index
) {
2445 bp
->def_t_idx
= def_sb
->t_def_status_block
.status_block_index
;
2452 * slow path service functions
2455 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
2457 int port
= BP_PORT(bp
);
2458 u32 hc_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
2459 COMMAND_REG_ATTN_BITS_SET
);
2460 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
2461 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
2462 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
2463 NIG_REG_MASK_INTERRUPT_PORT0
;
2466 if (bp
->attn_state
& asserted
)
2467 BNX2X_ERR("IGU ERROR\n");
2469 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
2470 aeu_mask
= REG_RD(bp
, aeu_addr
);
2472 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
2473 aeu_mask
, asserted
);
2474 aeu_mask
&= ~(asserted
& 0xff);
2475 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
2477 REG_WR(bp
, aeu_addr
, aeu_mask
);
2478 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
2480 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
2481 bp
->attn_state
|= asserted
;
2482 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
2484 if (asserted
& ATTN_HARD_WIRED_MASK
) {
2485 if (asserted
& ATTN_NIG_FOR_FUNC
) {
2487 /* save nig interrupt mask */
2488 bp
->nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
2489 REG_WR(bp
, nig_int_mask_addr
, 0);
2491 bnx2x_link_attn(bp
);
2493 /* handle unicore attn? */
2495 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
2496 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
2498 if (asserted
& GPIO_2_FUNC
)
2499 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
2501 if (asserted
& GPIO_3_FUNC
)
2502 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
2504 if (asserted
& GPIO_4_FUNC
)
2505 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
2508 if (asserted
& ATTN_GENERAL_ATTN_1
) {
2509 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
2510 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
2512 if (asserted
& ATTN_GENERAL_ATTN_2
) {
2513 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
2514 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
2516 if (asserted
& ATTN_GENERAL_ATTN_3
) {
2517 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
2518 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
2521 if (asserted
& ATTN_GENERAL_ATTN_4
) {
2522 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
2523 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
2525 if (asserted
& ATTN_GENERAL_ATTN_5
) {
2526 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
2527 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
2529 if (asserted
& ATTN_GENERAL_ATTN_6
) {
2530 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
2531 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
2535 } /* if hardwired */
2537 DP(NETIF_MSG_HW
, "about to mask 0x%08x at HC addr 0x%x\n",
2539 REG_WR(bp
, hc_addr
, asserted
);
2541 /* now set back the mask */
2542 if (asserted
& ATTN_NIG_FOR_FUNC
)
2543 REG_WR(bp
, nig_int_mask_addr
, bp
->nig_mask
);
2546 static inline void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
2548 int port
= BP_PORT(bp
);
2552 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
2553 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
2555 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
2557 val
= REG_RD(bp
, reg_offset
);
2558 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
2559 REG_WR(bp
, reg_offset
, val
);
2561 BNX2X_ERR("SPIO5 hw attention\n");
2563 switch (bp
->common
.board
& SHARED_HW_CFG_BOARD_TYPE_MASK
) {
2564 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G
:
2565 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G
:
2566 /* Fan failure attention */
2568 /* The PHY reset is controlled by GPIO 1 */
2569 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2570 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
2571 /* Low power mode is controlled by GPIO 2 */
2572 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2573 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
2574 /* mark the failure */
2575 bp
->link_params
.ext_phy_config
&=
2576 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
2577 bp
->link_params
.ext_phy_config
|=
2578 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
2580 dev_info
.port_hw_config
[port
].
2581 external_phy_config
,
2582 bp
->link_params
.ext_phy_config
);
2583 /* log the failure */
2584 printk(KERN_ERR PFX
"Fan Failure on Network"
2585 " Controller %s has caused the driver to"
2586 " shutdown the card to prevent permanent"
2587 " damage. Please contact Dell Support for"
2588 " assistance\n", bp
->dev
->name
);
2596 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
2598 val
= REG_RD(bp
, reg_offset
);
2599 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
2600 REG_WR(bp
, reg_offset
, val
);
2602 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2603 (attn
& HW_INTERRUT_ASSERT_SET_0
));
2608 static inline void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
2612 if (attn
& BNX2X_DOORQ_ASSERT
) {
2614 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
2615 BNX2X_ERR("DB hw attention 0x%x\n", val
);
2616 /* DORQ discard attention */
2618 BNX2X_ERR("FATAL error from DORQ\n");
2621 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
2623 int port
= BP_PORT(bp
);
2626 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
2627 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
2629 val
= REG_RD(bp
, reg_offset
);
2630 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
2631 REG_WR(bp
, reg_offset
, val
);
2633 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2634 (attn
& HW_INTERRUT_ASSERT_SET_1
));
2639 static inline void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
2643 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
2645 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
2646 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
2647 /* CFC error attention */
2649 BNX2X_ERR("FATAL error from CFC\n");
2652 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
2654 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
2655 BNX2X_ERR("PXP hw attention 0x%x\n", val
);
2656 /* RQ_USDMDP_FIFO_OVERFLOW */
2658 BNX2X_ERR("FATAL error from PXP\n");
2661 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
2663 int port
= BP_PORT(bp
);
2666 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
2667 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
2669 val
= REG_RD(bp
, reg_offset
);
2670 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
2671 REG_WR(bp
, reg_offset
, val
);
2673 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2674 (attn
& HW_INTERRUT_ASSERT_SET_2
));
2679 static inline void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
2683 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
2685 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
2686 int func
= BP_FUNC(bp
);
2688 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
2689 bnx2x__link_status_update(bp
);
2690 if (SHMEM_RD(bp
, func_mb
[func
].drv_status
) &
2692 bnx2x_pmf_update(bp
);
2694 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
2696 BNX2X_ERR("MC assert!\n");
2697 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
2698 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
2699 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
2700 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
2703 } else if (attn
& BNX2X_MCP_ASSERT
) {
2705 BNX2X_ERR("MCP assert!\n");
2706 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
2710 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
2713 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
2714 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
2715 if (attn
& BNX2X_GRC_TIMEOUT
) {
2716 val
= CHIP_IS_E1H(bp
) ?
2717 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
) : 0;
2718 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
2720 if (attn
& BNX2X_GRC_RSV
) {
2721 val
= CHIP_IS_E1H(bp
) ?
2722 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
) : 0;
2723 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
2725 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
2729 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
2731 struct attn_route attn
;
2732 struct attn_route group_mask
;
2733 int port
= BP_PORT(bp
);
2739 /* need to take HW lock because MCP or other port might also
2740 try to handle this event */
2741 bnx2x_acquire_alr(bp
);
2743 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
2744 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
2745 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
2746 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
2747 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x\n",
2748 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3]);
2750 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
2751 if (deasserted
& (1 << index
)) {
2752 group_mask
= bp
->attn_group
[index
];
2754 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x\n",
2755 index
, group_mask
.sig
[0], group_mask
.sig
[1],
2756 group_mask
.sig
[2], group_mask
.sig
[3]);
2758 bnx2x_attn_int_deasserted3(bp
,
2759 attn
.sig
[3] & group_mask
.sig
[3]);
2760 bnx2x_attn_int_deasserted1(bp
,
2761 attn
.sig
[1] & group_mask
.sig
[1]);
2762 bnx2x_attn_int_deasserted2(bp
,
2763 attn
.sig
[2] & group_mask
.sig
[2]);
2764 bnx2x_attn_int_deasserted0(bp
,
2765 attn
.sig
[0] & group_mask
.sig
[0]);
2767 if ((attn
.sig
[0] & group_mask
.sig
[0] &
2768 HW_PRTY_ASSERT_SET_0
) ||
2769 (attn
.sig
[1] & group_mask
.sig
[1] &
2770 HW_PRTY_ASSERT_SET_1
) ||
2771 (attn
.sig
[2] & group_mask
.sig
[2] &
2772 HW_PRTY_ASSERT_SET_2
))
2773 BNX2X_ERR("FATAL HW block parity attention\n");
2777 bnx2x_release_alr(bp
);
2779 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 + COMMAND_REG_ATTN_BITS_CLR
);
2782 DP(NETIF_MSG_HW
, "about to mask 0x%08x at HC addr 0x%x\n",
2784 REG_WR(bp
, reg_addr
, val
);
2786 if (~bp
->attn_state
& deasserted
)
2787 BNX2X_ERR("IGU ERROR\n");
2789 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
2790 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
2792 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
2793 aeu_mask
= REG_RD(bp
, reg_addr
);
2795 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
2796 aeu_mask
, deasserted
);
2797 aeu_mask
|= (deasserted
& 0xff);
2798 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
2800 REG_WR(bp
, reg_addr
, aeu_mask
);
2801 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
2803 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
2804 bp
->attn_state
&= ~deasserted
;
2805 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
2808 static void bnx2x_attn_int(struct bnx2x
*bp
)
2810 /* read local copy of bits */
2811 u32 attn_bits
= bp
->def_status_blk
->atten_status_block
.attn_bits
;
2812 u32 attn_ack
= bp
->def_status_blk
->atten_status_block
.attn_bits_ack
;
2813 u32 attn_state
= bp
->attn_state
;
2815 /* look for changed bits */
2816 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
2817 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
2820 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
2821 attn_bits
, attn_ack
, asserted
, deasserted
);
2823 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
2824 BNX2X_ERR("BAD attention state\n");
2826 /* handle bits that were raised */
2828 bnx2x_attn_int_asserted(bp
, asserted
);
2831 bnx2x_attn_int_deasserted(bp
, deasserted
);
2834 static void bnx2x_sp_task(struct work_struct
*work
)
2836 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
2840 /* Return here if interrupt is disabled */
2841 if (unlikely(atomic_read(&bp
->intr_sem
) != 0)) {
2842 DP(NETIF_MSG_INTR
, "called but intr_sem not 0, returning\n");
2846 status
= bnx2x_update_dsb_idx(bp
);
2847 /* if (status == 0) */
2848 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
2850 DP(NETIF_MSG_INTR
, "got a slowpath interrupt (updated %x)\n", status
);
2856 /* CStorm events: query_stats, port delete ramrod */
2858 bp
->stats_pending
= 0;
2860 bnx2x_ack_sb(bp
, DEF_SB_ID
, ATTENTION_ID
, bp
->def_att_idx
,
2862 bnx2x_ack_sb(bp
, DEF_SB_ID
, USTORM_ID
, le16_to_cpu(bp
->def_u_idx
),
2864 bnx2x_ack_sb(bp
, DEF_SB_ID
, CSTORM_ID
, le16_to_cpu(bp
->def_c_idx
),
2866 bnx2x_ack_sb(bp
, DEF_SB_ID
, XSTORM_ID
, le16_to_cpu(bp
->def_x_idx
),
2868 bnx2x_ack_sb(bp
, DEF_SB_ID
, TSTORM_ID
, le16_to_cpu(bp
->def_t_idx
),
2873 static irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
2875 struct net_device
*dev
= dev_instance
;
2876 struct bnx2x
*bp
= netdev_priv(dev
);
2878 /* Return here if interrupt is disabled */
2879 if (unlikely(atomic_read(&bp
->intr_sem
) != 0)) {
2880 DP(NETIF_MSG_INTR
, "called but intr_sem not 0, returning\n");
2884 bnx2x_ack_sb(bp
, DEF_SB_ID
, XSTORM_ID
, 0, IGU_INT_DISABLE
, 0);
2886 #ifdef BNX2X_STOP_ON_ERROR
2887 if (unlikely(bp
->panic
))
2891 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
2896 /* end of slow path */
2900 /****************************************************************************
2902 ****************************************************************************/
2904 /* sum[hi:lo] += add[hi:lo] */
2905 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2908 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
2911 /* difference = minuend - subtrahend */
2912 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2914 if (m_lo < s_lo) { \
2916 d_hi = m_hi - s_hi; \
2918 /* we can 'loan' 1 */ \
2920 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2922 /* m_hi <= s_hi */ \
2927 /* m_lo >= s_lo */ \
2928 if (m_hi < s_hi) { \
2932 /* m_hi >= s_hi */ \
2933 d_hi = m_hi - s_hi; \
2934 d_lo = m_lo - s_lo; \
2939 #define UPDATE_STAT64(s, t) \
2941 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2942 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2943 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2944 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2945 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2946 pstats->mac_stx[1].t##_lo, diff.lo); \
2949 #define UPDATE_STAT64_NIG(s, t) \
2951 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2952 diff.lo, new->s##_lo, old->s##_lo); \
2953 ADD_64(estats->t##_hi, diff.hi, \
2954 estats->t##_lo, diff.lo); \
2957 /* sum[hi:lo] += add */
2958 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2961 s_hi += (s_lo < a) ? 1 : 0; \
2964 #define UPDATE_EXTEND_STAT(s) \
2966 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
2967 pstats->mac_stx[1].s##_lo, \
2971 #define UPDATE_EXTEND_TSTAT(s, t) \
2973 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
2974 old_tclient->s = le32_to_cpu(tclient->s); \
2975 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2978 #define UPDATE_EXTEND_XSTAT(s, t) \
2980 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
2981 old_xclient->s = le32_to_cpu(xclient->s); \
2982 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2986 * General service functions
2989 static inline long bnx2x_hilo(u32
*hiref
)
2991 u32 lo
= *(hiref
+ 1);
2992 #if (BITS_PER_LONG == 64)
2995 return HILO_U64(hi
, lo
);
3002 * Init service functions
3005 static void bnx2x_storm_stats_post(struct bnx2x
*bp
)
3007 if (!bp
->stats_pending
) {
3008 struct eth_query_ramrod_data ramrod_data
= {0};
3011 ramrod_data
.drv_counter
= bp
->stats_counter
++;
3012 ramrod_data
.collect_port_1b
= bp
->port
.pmf
? 1 : 0;
3013 ramrod_data
.ctr_id_vector
= (1 << BP_CL_ID(bp
));
3015 rc
= bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_STAT_QUERY
, 0,
3016 ((u32
*)&ramrod_data
)[1],
3017 ((u32
*)&ramrod_data
)[0], 0);
3019 /* stats ramrod has it's own slot on the spq */
3021 bp
->stats_pending
= 1;
3026 static void bnx2x_stats_init(struct bnx2x
*bp
)
3028 int port
= BP_PORT(bp
);
3030 bp
->executer_idx
= 0;
3031 bp
->stats_counter
= 0;
3035 bp
->port
.port_stx
= SHMEM_RD(bp
, port_mb
[port
].port_stx
);
3037 bp
->port
.port_stx
= 0;
3038 DP(BNX2X_MSG_STATS
, "port_stx 0x%x\n", bp
->port
.port_stx
);
3040 memset(&(bp
->port
.old_nig_stats
), 0, sizeof(struct nig_stats
));
3041 bp
->port
.old_nig_stats
.brb_discard
=
3042 REG_RD(bp
, NIG_REG_STAT0_BRB_DISCARD
+ port
*0x38);
3043 bp
->port
.old_nig_stats
.brb_truncate
=
3044 REG_RD(bp
, NIG_REG_STAT0_BRB_TRUNCATE
+ port
*0x38);
3045 REG_RD_DMAE(bp
, NIG_REG_STAT0_EGRESS_MAC_PKT0
+ port
*0x50,
3046 &(bp
->port
.old_nig_stats
.egress_mac_pkt0_lo
), 2);
3047 REG_RD_DMAE(bp
, NIG_REG_STAT0_EGRESS_MAC_PKT1
+ port
*0x50,
3048 &(bp
->port
.old_nig_stats
.egress_mac_pkt1_lo
), 2);
3050 /* function stats */
3051 memset(&bp
->dev
->stats
, 0, sizeof(struct net_device_stats
));
3052 memset(&bp
->old_tclient
, 0, sizeof(struct tstorm_per_client_stats
));
3053 memset(&bp
->old_xclient
, 0, sizeof(struct xstorm_per_client_stats
));
3054 memset(&bp
->eth_stats
, 0, sizeof(struct bnx2x_eth_stats
));
3056 bp
->stats_state
= STATS_STATE_DISABLED
;
3057 if (IS_E1HMF(bp
) && bp
->port
.pmf
&& bp
->port
.port_stx
)
3058 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
3061 static void bnx2x_hw_stats_post(struct bnx2x
*bp
)
3063 struct dmae_command
*dmae
= &bp
->stats_dmae
;
3064 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3066 *stats_comp
= DMAE_COMP_VAL
;
3069 if (bp
->executer_idx
) {
3070 int loader_idx
= PMF_DMAE_C(bp
);
3072 memset(dmae
, 0, sizeof(struct dmae_command
));
3074 dmae
->opcode
= (DMAE_CMD_SRC_PCI
| DMAE_CMD_DST_GRC
|
3075 DMAE_CMD_C_DST_GRC
| DMAE_CMD_C_ENABLE
|
3076 DMAE_CMD_DST_RESET
|
3078 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3080 DMAE_CMD_ENDIANITY_DW_SWAP
|
3082 (BP_PORT(bp
) ? DMAE_CMD_PORT_1
:
3084 (BP_E1HVN(bp
) << DMAE_CMD_E1HVN_SHIFT
));
3085 dmae
->src_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, dmae
[0]));
3086 dmae
->src_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, dmae
[0]));
3087 dmae
->dst_addr_lo
= (DMAE_REG_CMD_MEM
+
3088 sizeof(struct dmae_command
) *
3089 (loader_idx
+ 1)) >> 2;
3090 dmae
->dst_addr_hi
= 0;
3091 dmae
->len
= sizeof(struct dmae_command
) >> 2;
3094 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
+ 1] >> 2;
3095 dmae
->comp_addr_hi
= 0;
3099 bnx2x_post_dmae(bp
, dmae
, loader_idx
);
3101 } else if (bp
->func_stx
) {
3103 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
3107 static int bnx2x_stats_comp(struct bnx2x
*bp
)
3109 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3113 while (*stats_comp
!= DMAE_COMP_VAL
) {
3115 BNX2X_ERR("timeout waiting for stats finished\n");
3125 * Statistics service functions
3128 static void bnx2x_stats_pmf_update(struct bnx2x
*bp
)
3130 struct dmae_command
*dmae
;
3132 int loader_idx
= PMF_DMAE_C(bp
);
3133 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3136 if (!IS_E1HMF(bp
) || !bp
->port
.pmf
|| !bp
->port
.port_stx
) {
3137 BNX2X_ERR("BUG!\n");
3141 bp
->executer_idx
= 0;
3143 opcode
= (DMAE_CMD_SRC_GRC
| DMAE_CMD_DST_PCI
|
3145 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
3147 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3149 DMAE_CMD_ENDIANITY_DW_SWAP
|
3151 (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
3152 (BP_E1HVN(bp
) << DMAE_CMD_E1HVN_SHIFT
));
3154 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3155 dmae
->opcode
= (opcode
| DMAE_CMD_C_DST_GRC
);
3156 dmae
->src_addr_lo
= bp
->port
.port_stx
>> 2;
3157 dmae
->src_addr_hi
= 0;
3158 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, port_stats
));
3159 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, port_stats
));
3160 dmae
->len
= DMAE_LEN32_RD_MAX
;
3161 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3162 dmae
->comp_addr_hi
= 0;
3165 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3166 dmae
->opcode
= (opcode
| DMAE_CMD_C_DST_PCI
);
3167 dmae
->src_addr_lo
= (bp
->port
.port_stx
>> 2) + DMAE_LEN32_RD_MAX
;
3168 dmae
->src_addr_hi
= 0;
3169 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, port_stats
) +
3170 DMAE_LEN32_RD_MAX
* 4);
3171 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, port_stats
) +
3172 DMAE_LEN32_RD_MAX
* 4);
3173 dmae
->len
= (sizeof(struct host_port_stats
) >> 2) - DMAE_LEN32_RD_MAX
;
3174 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, stats_comp
));
3175 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, stats_comp
));
3176 dmae
->comp_val
= DMAE_COMP_VAL
;
3179 bnx2x_hw_stats_post(bp
);
3180 bnx2x_stats_comp(bp
);
3183 static void bnx2x_port_stats_init(struct bnx2x
*bp
)
3185 struct dmae_command
*dmae
;
3186 int port
= BP_PORT(bp
);
3187 int vn
= BP_E1HVN(bp
);
3189 int loader_idx
= PMF_DMAE_C(bp
);
3191 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3194 if (!bp
->link_vars
.link_up
|| !bp
->port
.pmf
) {
3195 BNX2X_ERR("BUG!\n");
3199 bp
->executer_idx
= 0;
3202 opcode
= (DMAE_CMD_SRC_PCI
| DMAE_CMD_DST_GRC
|
3203 DMAE_CMD_C_DST_GRC
| DMAE_CMD_C_ENABLE
|
3204 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
3206 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3208 DMAE_CMD_ENDIANITY_DW_SWAP
|
3210 (port
? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
3211 (vn
<< DMAE_CMD_E1HVN_SHIFT
));
3213 if (bp
->port
.port_stx
) {
3215 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3216 dmae
->opcode
= opcode
;
3217 dmae
->src_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, port_stats
));
3218 dmae
->src_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, port_stats
));
3219 dmae
->dst_addr_lo
= bp
->port
.port_stx
>> 2;
3220 dmae
->dst_addr_hi
= 0;
3221 dmae
->len
= sizeof(struct host_port_stats
) >> 2;
3222 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3223 dmae
->comp_addr_hi
= 0;
3229 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3230 dmae
->opcode
= opcode
;
3231 dmae
->src_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, func_stats
));
3232 dmae
->src_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, func_stats
));
3233 dmae
->dst_addr_lo
= bp
->func_stx
>> 2;
3234 dmae
->dst_addr_hi
= 0;
3235 dmae
->len
= sizeof(struct host_func_stats
) >> 2;
3236 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3237 dmae
->comp_addr_hi
= 0;
3242 opcode
= (DMAE_CMD_SRC_GRC
| DMAE_CMD_DST_PCI
|
3243 DMAE_CMD_C_DST_GRC
| DMAE_CMD_C_ENABLE
|
3244 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
3246 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3248 DMAE_CMD_ENDIANITY_DW_SWAP
|
3250 (port
? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
3251 (vn
<< DMAE_CMD_E1HVN_SHIFT
));
3253 if (bp
->link_vars
.mac_type
== MAC_TYPE_BMAC
) {
3255 mac_addr
= (port
? NIG_REG_INGRESS_BMAC1_MEM
:
3256 NIG_REG_INGRESS_BMAC0_MEM
);
3258 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3259 BIGMAC_REGISTER_TX_STAT_GTBYT */
3260 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3261 dmae
->opcode
= opcode
;
3262 dmae
->src_addr_lo
= (mac_addr
+
3263 BIGMAC_REGISTER_TX_STAT_GTPKT
) >> 2;
3264 dmae
->src_addr_hi
= 0;
3265 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, mac_stats
));
3266 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, mac_stats
));
3267 dmae
->len
= (8 + BIGMAC_REGISTER_TX_STAT_GTBYT
-
3268 BIGMAC_REGISTER_TX_STAT_GTPKT
) >> 2;
3269 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3270 dmae
->comp_addr_hi
= 0;
3273 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3274 BIGMAC_REGISTER_RX_STAT_GRIPJ */
3275 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3276 dmae
->opcode
= opcode
;
3277 dmae
->src_addr_lo
= (mac_addr
+
3278 BIGMAC_REGISTER_RX_STAT_GR64
) >> 2;
3279 dmae
->src_addr_hi
= 0;
3280 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, mac_stats
) +
3281 offsetof(struct bmac_stats
, rx_stat_gr64_lo
));
3282 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, mac_stats
) +
3283 offsetof(struct bmac_stats
, rx_stat_gr64_lo
));
3284 dmae
->len
= (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ
-
3285 BIGMAC_REGISTER_RX_STAT_GR64
) >> 2;
3286 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3287 dmae
->comp_addr_hi
= 0;
3290 } else if (bp
->link_vars
.mac_type
== MAC_TYPE_EMAC
) {
3292 mac_addr
= (port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
);
3294 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3295 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3296 dmae
->opcode
= opcode
;
3297 dmae
->src_addr_lo
= (mac_addr
+
3298 EMAC_REG_EMAC_RX_STAT_AC
) >> 2;
3299 dmae
->src_addr_hi
= 0;
3300 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, mac_stats
));
3301 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, mac_stats
));
3302 dmae
->len
= EMAC_REG_EMAC_RX_STAT_AC_COUNT
;
3303 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3304 dmae
->comp_addr_hi
= 0;
3307 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3308 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3309 dmae
->opcode
= opcode
;
3310 dmae
->src_addr_lo
= (mac_addr
+
3311 EMAC_REG_EMAC_RX_STAT_AC_28
) >> 2;
3312 dmae
->src_addr_hi
= 0;
3313 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, mac_stats
) +
3314 offsetof(struct emac_stats
, rx_stat_falsecarriererrors
));
3315 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, mac_stats
) +
3316 offsetof(struct emac_stats
, rx_stat_falsecarriererrors
));
3318 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3319 dmae
->comp_addr_hi
= 0;
3322 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3323 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3324 dmae
->opcode
= opcode
;
3325 dmae
->src_addr_lo
= (mac_addr
+
3326 EMAC_REG_EMAC_TX_STAT_AC
) >> 2;
3327 dmae
->src_addr_hi
= 0;
3328 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, mac_stats
) +
3329 offsetof(struct emac_stats
, tx_stat_ifhcoutoctets
));
3330 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, mac_stats
) +
3331 offsetof(struct emac_stats
, tx_stat_ifhcoutoctets
));
3332 dmae
->len
= EMAC_REG_EMAC_TX_STAT_AC_COUNT
;
3333 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3334 dmae
->comp_addr_hi
= 0;
3339 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3340 dmae
->opcode
= opcode
;
3341 dmae
->src_addr_lo
= (port
? NIG_REG_STAT1_BRB_DISCARD
:
3342 NIG_REG_STAT0_BRB_DISCARD
) >> 2;
3343 dmae
->src_addr_hi
= 0;
3344 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, nig_stats
));
3345 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, nig_stats
));
3346 dmae
->len
= (sizeof(struct nig_stats
) - 4*sizeof(u32
)) >> 2;
3347 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3348 dmae
->comp_addr_hi
= 0;
3351 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3352 dmae
->opcode
= opcode
;
3353 dmae
->src_addr_lo
= (port
? NIG_REG_STAT1_EGRESS_MAC_PKT0
:
3354 NIG_REG_STAT0_EGRESS_MAC_PKT0
) >> 2;
3355 dmae
->src_addr_hi
= 0;
3356 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, nig_stats
) +
3357 offsetof(struct nig_stats
, egress_mac_pkt0_lo
));
3358 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, nig_stats
) +
3359 offsetof(struct nig_stats
, egress_mac_pkt0_lo
));
3360 dmae
->len
= (2*sizeof(u32
)) >> 2;
3361 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3362 dmae
->comp_addr_hi
= 0;
3365 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3366 dmae
->opcode
= (DMAE_CMD_SRC_GRC
| DMAE_CMD_DST_PCI
|
3367 DMAE_CMD_C_DST_PCI
| DMAE_CMD_C_ENABLE
|
3368 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
3370 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3372 DMAE_CMD_ENDIANITY_DW_SWAP
|
3374 (port
? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
3375 (vn
<< DMAE_CMD_E1HVN_SHIFT
));
3376 dmae
->src_addr_lo
= (port
? NIG_REG_STAT1_EGRESS_MAC_PKT1
:
3377 NIG_REG_STAT0_EGRESS_MAC_PKT1
) >> 2;
3378 dmae
->src_addr_hi
= 0;
3379 dmae
->dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, nig_stats
) +
3380 offsetof(struct nig_stats
, egress_mac_pkt1_lo
));
3381 dmae
->dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, nig_stats
) +
3382 offsetof(struct nig_stats
, egress_mac_pkt1_lo
));
3383 dmae
->len
= (2*sizeof(u32
)) >> 2;
3384 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, stats_comp
));
3385 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, stats_comp
));
3386 dmae
->comp_val
= DMAE_COMP_VAL
;
3391 static void bnx2x_func_stats_init(struct bnx2x
*bp
)
3393 struct dmae_command
*dmae
= &bp
->stats_dmae
;
3394 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3397 if (!bp
->func_stx
) {
3398 BNX2X_ERR("BUG!\n");
3402 bp
->executer_idx
= 0;
3403 memset(dmae
, 0, sizeof(struct dmae_command
));
3405 dmae
->opcode
= (DMAE_CMD_SRC_PCI
| DMAE_CMD_DST_GRC
|
3406 DMAE_CMD_C_DST_PCI
| DMAE_CMD_C_ENABLE
|
3407 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
3409 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3411 DMAE_CMD_ENDIANITY_DW_SWAP
|
3413 (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
3414 (BP_E1HVN(bp
) << DMAE_CMD_E1HVN_SHIFT
));
3415 dmae
->src_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, func_stats
));
3416 dmae
->src_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, func_stats
));
3417 dmae
->dst_addr_lo
= bp
->func_stx
>> 2;
3418 dmae
->dst_addr_hi
= 0;
3419 dmae
->len
= sizeof(struct host_func_stats
) >> 2;
3420 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, stats_comp
));
3421 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, stats_comp
));
3422 dmae
->comp_val
= DMAE_COMP_VAL
;
3427 static void bnx2x_stats_start(struct bnx2x
*bp
)
3430 bnx2x_port_stats_init(bp
);
3432 else if (bp
->func_stx
)
3433 bnx2x_func_stats_init(bp
);
3435 bnx2x_hw_stats_post(bp
);
3436 bnx2x_storm_stats_post(bp
);
3439 static void bnx2x_stats_pmf_start(struct bnx2x
*bp
)
3441 bnx2x_stats_comp(bp
);
3442 bnx2x_stats_pmf_update(bp
);
3443 bnx2x_stats_start(bp
);
3446 static void bnx2x_stats_restart(struct bnx2x
*bp
)
3448 bnx2x_stats_comp(bp
);
3449 bnx2x_stats_start(bp
);
3452 static void bnx2x_bmac_stats_update(struct bnx2x
*bp
)
3454 struct bmac_stats
*new = bnx2x_sp(bp
, mac_stats
.bmac_stats
);
3455 struct host_port_stats
*pstats
= bnx2x_sp(bp
, port_stats
);
3456 struct regpair diff
;
3458 UPDATE_STAT64(rx_stat_grerb
, rx_stat_ifhcinbadoctets
);
3459 UPDATE_STAT64(rx_stat_grfcs
, rx_stat_dot3statsfcserrors
);
3460 UPDATE_STAT64(rx_stat_grund
, rx_stat_etherstatsundersizepkts
);
3461 UPDATE_STAT64(rx_stat_grovr
, rx_stat_dot3statsframestoolong
);
3462 UPDATE_STAT64(rx_stat_grfrg
, rx_stat_etherstatsfragments
);
3463 UPDATE_STAT64(rx_stat_grjbr
, rx_stat_etherstatsjabbers
);
3464 UPDATE_STAT64(rx_stat_grxcf
, rx_stat_maccontrolframesreceived
);
3465 UPDATE_STAT64(rx_stat_grxpf
, rx_stat_xoffstateentered
);
3466 UPDATE_STAT64(rx_stat_grxpf
, rx_stat_xoffpauseframesreceived
);
3467 UPDATE_STAT64(tx_stat_gtxpf
, tx_stat_outxoffsent
);
3468 UPDATE_STAT64(tx_stat_gtxpf
, tx_stat_flowcontroldone
);
3469 UPDATE_STAT64(tx_stat_gt64
, tx_stat_etherstatspkts64octets
);
3470 UPDATE_STAT64(tx_stat_gt127
,
3471 tx_stat_etherstatspkts65octetsto127octets
);
3472 UPDATE_STAT64(tx_stat_gt255
,
3473 tx_stat_etherstatspkts128octetsto255octets
);
3474 UPDATE_STAT64(tx_stat_gt511
,
3475 tx_stat_etherstatspkts256octetsto511octets
);
3476 UPDATE_STAT64(tx_stat_gt1023
,
3477 tx_stat_etherstatspkts512octetsto1023octets
);
3478 UPDATE_STAT64(tx_stat_gt1518
,
3479 tx_stat_etherstatspkts1024octetsto1522octets
);
3480 UPDATE_STAT64(tx_stat_gt2047
, tx_stat_bmac_2047
);
3481 UPDATE_STAT64(tx_stat_gt4095
, tx_stat_bmac_4095
);
3482 UPDATE_STAT64(tx_stat_gt9216
, tx_stat_bmac_9216
);
3483 UPDATE_STAT64(tx_stat_gt16383
, tx_stat_bmac_16383
);
3484 UPDATE_STAT64(tx_stat_gterr
,
3485 tx_stat_dot3statsinternalmactransmiterrors
);
3486 UPDATE_STAT64(tx_stat_gtufl
, tx_stat_bmac_ufl
);
3489 static void bnx2x_emac_stats_update(struct bnx2x
*bp
)
3491 struct emac_stats
*new = bnx2x_sp(bp
, mac_stats
.emac_stats
);
3492 struct host_port_stats
*pstats
= bnx2x_sp(bp
, port_stats
);
3494 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets
);
3495 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets
);
3496 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors
);
3497 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors
);
3498 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors
);
3499 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors
);
3500 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts
);
3501 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong
);
3502 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments
);
3503 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers
);
3504 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived
);
3505 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered
);
3506 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived
);
3507 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived
);
3508 UPDATE_EXTEND_STAT(tx_stat_outxonsent
);
3509 UPDATE_EXTEND_STAT(tx_stat_outxoffsent
);
3510 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone
);
3511 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions
);
3512 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes
);
3513 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes
);
3514 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions
);
3515 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions
);
3516 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions
);
3517 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets
);
3518 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets
);
3519 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets
);
3520 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets
);
3521 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets
);
3522 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets
);
3523 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets
);
3524 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors
);
3527 static int bnx2x_hw_stats_update(struct bnx2x
*bp
)
3529 struct nig_stats
*new = bnx2x_sp(bp
, nig_stats
);
3530 struct nig_stats
*old
= &(bp
->port
.old_nig_stats
);
3531 struct host_port_stats
*pstats
= bnx2x_sp(bp
, port_stats
);
3532 struct bnx2x_eth_stats
*estats
= &bp
->eth_stats
;
3533 struct regpair diff
;
3535 if (bp
->link_vars
.mac_type
== MAC_TYPE_BMAC
)
3536 bnx2x_bmac_stats_update(bp
);
3538 else if (bp
->link_vars
.mac_type
== MAC_TYPE_EMAC
)
3539 bnx2x_emac_stats_update(bp
);
3541 else { /* unreached */
3542 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3546 ADD_EXTEND_64(pstats
->brb_drop_hi
, pstats
->brb_drop_lo
,
3547 new->brb_discard
- old
->brb_discard
);
3548 ADD_EXTEND_64(estats
->brb_truncate_hi
, estats
->brb_truncate_lo
,
3549 new->brb_truncate
- old
->brb_truncate
);
3551 UPDATE_STAT64_NIG(egress_mac_pkt0
,
3552 etherstatspkts1024octetsto1522octets
);
3553 UPDATE_STAT64_NIG(egress_mac_pkt1
, etherstatspktsover1522octets
);
3555 memcpy(old
, new, sizeof(struct nig_stats
));
3557 memcpy(&(estats
->rx_stat_ifhcinbadoctets_hi
), &(pstats
->mac_stx
[1]),
3558 sizeof(struct mac_stx
));
3559 estats
->brb_drop_hi
= pstats
->brb_drop_hi
;
3560 estats
->brb_drop_lo
= pstats
->brb_drop_lo
;
3562 pstats
->host_port_stats_start
= ++pstats
->host_port_stats_end
;
3567 static int bnx2x_storm_stats_update(struct bnx2x
*bp
)
3569 struct eth_stats_query
*stats
= bnx2x_sp(bp
, fw_stats
);
3570 int cl_id
= BP_CL_ID(bp
);
3571 struct tstorm_per_port_stats
*tport
=
3572 &stats
->tstorm_common
.port_statistics
;
3573 struct tstorm_per_client_stats
*tclient
=
3574 &stats
->tstorm_common
.client_statistics
[cl_id
];
3575 struct tstorm_per_client_stats
*old_tclient
= &bp
->old_tclient
;
3576 struct xstorm_per_client_stats
*xclient
=
3577 &stats
->xstorm_common
.client_statistics
[cl_id
];
3578 struct xstorm_per_client_stats
*old_xclient
= &bp
->old_xclient
;
3579 struct host_func_stats
*fstats
= bnx2x_sp(bp
, func_stats
);
3580 struct bnx2x_eth_stats
*estats
= &bp
->eth_stats
;
3583 /* are storm stats valid? */
3584 if ((u16
)(le16_to_cpu(tclient
->stats_counter
) + 1) !=
3585 bp
->stats_counter
) {
3586 DP(BNX2X_MSG_STATS
, "stats not updated by tstorm"
3587 " tstorm counter (%d) != stats_counter (%d)\n",
3588 tclient
->stats_counter
, bp
->stats_counter
);
3591 if ((u16
)(le16_to_cpu(xclient
->stats_counter
) + 1) !=
3592 bp
->stats_counter
) {
3593 DP(BNX2X_MSG_STATS
, "stats not updated by xstorm"
3594 " xstorm counter (%d) != stats_counter (%d)\n",
3595 xclient
->stats_counter
, bp
->stats_counter
);
3599 fstats
->total_bytes_received_hi
=
3600 fstats
->valid_bytes_received_hi
=
3601 le32_to_cpu(tclient
->total_rcv_bytes
.hi
);
3602 fstats
->total_bytes_received_lo
=
3603 fstats
->valid_bytes_received_lo
=
3604 le32_to_cpu(tclient
->total_rcv_bytes
.lo
);
3606 estats
->error_bytes_received_hi
=
3607 le32_to_cpu(tclient
->rcv_error_bytes
.hi
);
3608 estats
->error_bytes_received_lo
=
3609 le32_to_cpu(tclient
->rcv_error_bytes
.lo
);
3610 ADD_64(estats
->error_bytes_received_hi
,
3611 estats
->rx_stat_ifhcinbadoctets_hi
,
3612 estats
->error_bytes_received_lo
,
3613 estats
->rx_stat_ifhcinbadoctets_lo
);
3615 ADD_64(fstats
->total_bytes_received_hi
,
3616 estats
->error_bytes_received_hi
,
3617 fstats
->total_bytes_received_lo
,
3618 estats
->error_bytes_received_lo
);
3620 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts
, total_unicast_packets_received
);
3621 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts
,
3622 total_multicast_packets_received
);
3623 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts
,
3624 total_broadcast_packets_received
);
3626 fstats
->total_bytes_transmitted_hi
=
3627 le32_to_cpu(xclient
->total_sent_bytes
.hi
);
3628 fstats
->total_bytes_transmitted_lo
=
3629 le32_to_cpu(xclient
->total_sent_bytes
.lo
);
3631 UPDATE_EXTEND_XSTAT(unicast_pkts_sent
,
3632 total_unicast_packets_transmitted
);
3633 UPDATE_EXTEND_XSTAT(multicast_pkts_sent
,
3634 total_multicast_packets_transmitted
);
3635 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent
,
3636 total_broadcast_packets_transmitted
);
3638 memcpy(estats
, &(fstats
->total_bytes_received_hi
),
3639 sizeof(struct host_func_stats
) - 2*sizeof(u32
));
3641 estats
->mac_filter_discard
= le32_to_cpu(tport
->mac_filter_discard
);
3642 estats
->xxoverflow_discard
= le32_to_cpu(tport
->xxoverflow_discard
);
3643 estats
->brb_truncate_discard
=
3644 le32_to_cpu(tport
->brb_truncate_discard
);
3645 estats
->mac_discard
= le32_to_cpu(tport
->mac_discard
);
3647 old_tclient
->rcv_unicast_bytes
.hi
=
3648 le32_to_cpu(tclient
->rcv_unicast_bytes
.hi
);
3649 old_tclient
->rcv_unicast_bytes
.lo
=
3650 le32_to_cpu(tclient
->rcv_unicast_bytes
.lo
);
3651 old_tclient
->rcv_broadcast_bytes
.hi
=
3652 le32_to_cpu(tclient
->rcv_broadcast_bytes
.hi
);
3653 old_tclient
->rcv_broadcast_bytes
.lo
=
3654 le32_to_cpu(tclient
->rcv_broadcast_bytes
.lo
);
3655 old_tclient
->rcv_multicast_bytes
.hi
=
3656 le32_to_cpu(tclient
->rcv_multicast_bytes
.hi
);
3657 old_tclient
->rcv_multicast_bytes
.lo
=
3658 le32_to_cpu(tclient
->rcv_multicast_bytes
.lo
);
3659 old_tclient
->total_rcv_pkts
= le32_to_cpu(tclient
->total_rcv_pkts
);
3661 old_tclient
->checksum_discard
= le32_to_cpu(tclient
->checksum_discard
);
3662 old_tclient
->packets_too_big_discard
=
3663 le32_to_cpu(tclient
->packets_too_big_discard
);
3664 estats
->no_buff_discard
=
3665 old_tclient
->no_buff_discard
= le32_to_cpu(tclient
->no_buff_discard
);
3666 old_tclient
->ttl0_discard
= le32_to_cpu(tclient
->ttl0_discard
);
3668 old_xclient
->total_sent_pkts
= le32_to_cpu(xclient
->total_sent_pkts
);
3669 old_xclient
->unicast_bytes_sent
.hi
=
3670 le32_to_cpu(xclient
->unicast_bytes_sent
.hi
);
3671 old_xclient
->unicast_bytes_sent
.lo
=
3672 le32_to_cpu(xclient
->unicast_bytes_sent
.lo
);
3673 old_xclient
->multicast_bytes_sent
.hi
=
3674 le32_to_cpu(xclient
->multicast_bytes_sent
.hi
);
3675 old_xclient
->multicast_bytes_sent
.lo
=
3676 le32_to_cpu(xclient
->multicast_bytes_sent
.lo
);
3677 old_xclient
->broadcast_bytes_sent
.hi
=
3678 le32_to_cpu(xclient
->broadcast_bytes_sent
.hi
);
3679 old_xclient
->broadcast_bytes_sent
.lo
=
3680 le32_to_cpu(xclient
->broadcast_bytes_sent
.lo
);
3682 fstats
->host_func_stats_start
= ++fstats
->host_func_stats_end
;
3687 static void bnx2x_net_stats_update(struct bnx2x
*bp
)
3689 struct tstorm_per_client_stats
*old_tclient
= &bp
->old_tclient
;
3690 struct bnx2x_eth_stats
*estats
= &bp
->eth_stats
;
3691 struct net_device_stats
*nstats
= &bp
->dev
->stats
;
3693 nstats
->rx_packets
=
3694 bnx2x_hilo(&estats
->total_unicast_packets_received_hi
) +
3695 bnx2x_hilo(&estats
->total_multicast_packets_received_hi
) +
3696 bnx2x_hilo(&estats
->total_broadcast_packets_received_hi
);
3698 nstats
->tx_packets
=
3699 bnx2x_hilo(&estats
->total_unicast_packets_transmitted_hi
) +
3700 bnx2x_hilo(&estats
->total_multicast_packets_transmitted_hi
) +
3701 bnx2x_hilo(&estats
->total_broadcast_packets_transmitted_hi
);
3703 nstats
->rx_bytes
= bnx2x_hilo(&estats
->valid_bytes_received_hi
);
3705 nstats
->tx_bytes
= bnx2x_hilo(&estats
->total_bytes_transmitted_hi
);
3707 nstats
->rx_dropped
= old_tclient
->checksum_discard
+
3708 estats
->mac_discard
;
3709 nstats
->tx_dropped
= 0;
3712 bnx2x_hilo(&estats
->total_multicast_packets_transmitted_hi
);
3714 nstats
->collisions
=
3715 estats
->tx_stat_dot3statssinglecollisionframes_lo
+
3716 estats
->tx_stat_dot3statsmultiplecollisionframes_lo
+
3717 estats
->tx_stat_dot3statslatecollisions_lo
+
3718 estats
->tx_stat_dot3statsexcessivecollisions_lo
;
3720 estats
->jabber_packets_received
=
3721 old_tclient
->packets_too_big_discard
+
3722 estats
->rx_stat_dot3statsframestoolong_lo
;
3724 nstats
->rx_length_errors
=
3725 estats
->rx_stat_etherstatsundersizepkts_lo
+
3726 estats
->jabber_packets_received
;
3727 nstats
->rx_over_errors
= estats
->brb_drop_lo
+ estats
->brb_truncate_lo
;
3728 nstats
->rx_crc_errors
= estats
->rx_stat_dot3statsfcserrors_lo
;
3729 nstats
->rx_frame_errors
= estats
->rx_stat_dot3statsalignmenterrors_lo
;
3730 nstats
->rx_fifo_errors
= old_tclient
->no_buff_discard
;
3731 nstats
->rx_missed_errors
= estats
->xxoverflow_discard
;
3733 nstats
->rx_errors
= nstats
->rx_length_errors
+
3734 nstats
->rx_over_errors
+
3735 nstats
->rx_crc_errors
+
3736 nstats
->rx_frame_errors
+
3737 nstats
->rx_fifo_errors
+
3738 nstats
->rx_missed_errors
;
3740 nstats
->tx_aborted_errors
=
3741 estats
->tx_stat_dot3statslatecollisions_lo
+
3742 estats
->tx_stat_dot3statsexcessivecollisions_lo
;
3743 nstats
->tx_carrier_errors
= estats
->rx_stat_falsecarriererrors_lo
;
3744 nstats
->tx_fifo_errors
= 0;
3745 nstats
->tx_heartbeat_errors
= 0;
3746 nstats
->tx_window_errors
= 0;
3748 nstats
->tx_errors
= nstats
->tx_aborted_errors
+
3749 nstats
->tx_carrier_errors
;
3752 static void bnx2x_stats_update(struct bnx2x
*bp
)
3754 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3757 if (*stats_comp
!= DMAE_COMP_VAL
)
3761 update
= (bnx2x_hw_stats_update(bp
) == 0);
3763 update
|= (bnx2x_storm_stats_update(bp
) == 0);
3766 bnx2x_net_stats_update(bp
);
3769 if (bp
->stats_pending
) {
3770 bp
->stats_pending
++;
3771 if (bp
->stats_pending
== 3) {
3772 BNX2X_ERR("stats not updated for 3 times\n");
3779 if (bp
->msglevel
& NETIF_MSG_TIMER
) {
3780 struct tstorm_per_client_stats
*old_tclient
= &bp
->old_tclient
;
3781 struct bnx2x_eth_stats
*estats
= &bp
->eth_stats
;
3782 struct net_device_stats
*nstats
= &bp
->dev
->stats
;
3785 printk(KERN_DEBUG
"%s:\n", bp
->dev
->name
);
3786 printk(KERN_DEBUG
" tx avail (%4x) tx hc idx (%x)"
3788 bnx2x_tx_avail(bp
->fp
),
3789 le16_to_cpu(*bp
->fp
->tx_cons_sb
), nstats
->tx_packets
);
3790 printk(KERN_DEBUG
" rx usage (%4x) rx hc idx (%x)"
3792 (u16
)(le16_to_cpu(*bp
->fp
->rx_cons_sb
) -
3793 bp
->fp
->rx_comp_cons
),
3794 le16_to_cpu(*bp
->fp
->rx_cons_sb
), nstats
->rx_packets
);
3795 printk(KERN_DEBUG
" %s (Xoff events %u) brb drops %u\n",
3796 netif_queue_stopped(bp
->dev
) ? "Xoff" : "Xon",
3797 estats
->driver_xoff
, estats
->brb_drop_lo
);
3798 printk(KERN_DEBUG
"tstats: checksum_discard %u "
3799 "packets_too_big_discard %u no_buff_discard %u "
3800 "mac_discard %u mac_filter_discard %u "
3801 "xxovrflow_discard %u brb_truncate_discard %u "
3802 "ttl0_discard %u\n",
3803 old_tclient
->checksum_discard
,
3804 old_tclient
->packets_too_big_discard
,
3805 old_tclient
->no_buff_discard
, estats
->mac_discard
,
3806 estats
->mac_filter_discard
, estats
->xxoverflow_discard
,
3807 estats
->brb_truncate_discard
,
3808 old_tclient
->ttl0_discard
);
3810 for_each_queue(bp
, i
) {
3811 printk(KERN_DEBUG
"[%d]: %lu\t%lu\t%lu\n", i
,
3812 bnx2x_fp(bp
, i
, tx_pkt
),
3813 bnx2x_fp(bp
, i
, rx_pkt
),
3814 bnx2x_fp(bp
, i
, rx_calls
));
3818 bnx2x_hw_stats_post(bp
);
3819 bnx2x_storm_stats_post(bp
);
3822 static void bnx2x_port_stats_stop(struct bnx2x
*bp
)
3824 struct dmae_command
*dmae
;
3826 int loader_idx
= PMF_DMAE_C(bp
);
3827 u32
*stats_comp
= bnx2x_sp(bp
, stats_comp
);
3829 bp
->executer_idx
= 0;
3831 opcode
= (DMAE_CMD_SRC_PCI
| DMAE_CMD_DST_GRC
|
3833 DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
|
3835 DMAE_CMD_ENDIANITY_B_DW_SWAP
|
3837 DMAE_CMD_ENDIANITY_DW_SWAP
|
3839 (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
) |
3840 (BP_E1HVN(bp
) << DMAE_CMD_E1HVN_SHIFT
));
3842 if (bp
->port
.port_stx
) {
3844 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3846 dmae
->opcode
= (opcode
| DMAE_CMD_C_DST_GRC
);
3848 dmae
->opcode
= (opcode
| DMAE_CMD_C_DST_PCI
);
3849 dmae
->src_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, port_stats
));
3850 dmae
->src_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, port_stats
));
3851 dmae
->dst_addr_lo
= bp
->port
.port_stx
>> 2;
3852 dmae
->dst_addr_hi
= 0;
3853 dmae
->len
= sizeof(struct host_port_stats
) >> 2;
3855 dmae
->comp_addr_lo
= dmae_reg_go_c
[loader_idx
] >> 2;
3856 dmae
->comp_addr_hi
= 0;
3859 dmae
->comp_addr_lo
=
3860 U64_LO(bnx2x_sp_mapping(bp
, stats_comp
));
3861 dmae
->comp_addr_hi
=
3862 U64_HI(bnx2x_sp_mapping(bp
, stats_comp
));
3863 dmae
->comp_val
= DMAE_COMP_VAL
;
3871 dmae
= bnx2x_sp(bp
, dmae
[bp
->executer_idx
++]);
3872 dmae
->opcode
= (opcode
| DMAE_CMD_C_DST_PCI
);
3873 dmae
->src_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, func_stats
));
3874 dmae
->src_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, func_stats
));
3875 dmae
->dst_addr_lo
= bp
->func_stx
>> 2;
3876 dmae
->dst_addr_hi
= 0;
3877 dmae
->len
= sizeof(struct host_func_stats
) >> 2;
3878 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, stats_comp
));
3879 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, stats_comp
));
3880 dmae
->comp_val
= DMAE_COMP_VAL
;
3886 static void bnx2x_stats_stop(struct bnx2x
*bp
)
3890 bnx2x_stats_comp(bp
);
3893 update
= (bnx2x_hw_stats_update(bp
) == 0);
3895 update
|= (bnx2x_storm_stats_update(bp
) == 0);
3898 bnx2x_net_stats_update(bp
);
3901 bnx2x_port_stats_stop(bp
);
3903 bnx2x_hw_stats_post(bp
);
3904 bnx2x_stats_comp(bp
);
3908 static void bnx2x_stats_do_nothing(struct bnx2x
*bp
)
3912 static const struct {
3913 void (*action
)(struct bnx2x
*bp
);
3914 enum bnx2x_stats_state next_state
;
3915 } bnx2x_stats_stm
[STATS_STATE_MAX
][STATS_EVENT_MAX
] = {
3918 /* DISABLED PMF */ {bnx2x_stats_pmf_update
, STATS_STATE_DISABLED
},
3919 /* LINK_UP */ {bnx2x_stats_start
, STATS_STATE_ENABLED
},
3920 /* UPDATE */ {bnx2x_stats_do_nothing
, STATS_STATE_DISABLED
},
3921 /* STOP */ {bnx2x_stats_do_nothing
, STATS_STATE_DISABLED
}
3924 /* ENABLED PMF */ {bnx2x_stats_pmf_start
, STATS_STATE_ENABLED
},
3925 /* LINK_UP */ {bnx2x_stats_restart
, STATS_STATE_ENABLED
},
3926 /* UPDATE */ {bnx2x_stats_update
, STATS_STATE_ENABLED
},
3927 /* STOP */ {bnx2x_stats_stop
, STATS_STATE_DISABLED
}
3931 static void bnx2x_stats_handle(struct bnx2x
*bp
, enum bnx2x_stats_event event
)
3933 enum bnx2x_stats_state state
= bp
->stats_state
;
3935 bnx2x_stats_stm
[state
][event
].action(bp
);
3936 bp
->stats_state
= bnx2x_stats_stm
[state
][event
].next_state
;
3938 if ((event
!= STATS_EVENT_UPDATE
) || (bp
->msglevel
& NETIF_MSG_TIMER
))
3939 DP(BNX2X_MSG_STATS
, "state %d -> event %d -> state %d\n",
3940 state
, event
, bp
->stats_state
);
3943 static void bnx2x_timer(unsigned long data
)
3945 struct bnx2x
*bp
= (struct bnx2x
*) data
;
3947 if (!netif_running(bp
->dev
))
3950 if (atomic_read(&bp
->intr_sem
) != 0)
3954 struct bnx2x_fastpath
*fp
= &bp
->fp
[0];
3957 bnx2x_tx_int(fp
, 1000);
3958 rc
= bnx2x_rx_int(fp
, 1000);
3961 if (!BP_NOMCP(bp
)) {
3962 int func
= BP_FUNC(bp
);
3966 ++bp
->fw_drv_pulse_wr_seq
;
3967 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
3968 /* TBD - add SYSTEM_TIME */
3969 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
3970 SHMEM_WR(bp
, func_mb
[func
].drv_pulse_mb
, drv_pulse
);
3972 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[func
].mcp_pulse_mb
) &
3973 MCP_PULSE_SEQ_MASK
);
3974 /* The delta between driver pulse and mcp response
3975 * should be 1 (before mcp response) or 0 (after mcp response)
3977 if ((drv_pulse
!= mcp_pulse
) &&
3978 (drv_pulse
!= ((mcp_pulse
+ 1) & MCP_PULSE_SEQ_MASK
))) {
3979 /* someone lost a heartbeat... */
3980 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3981 drv_pulse
, mcp_pulse
);
3985 if ((bp
->state
== BNX2X_STATE_OPEN
) ||
3986 (bp
->state
== BNX2X_STATE_DISABLED
))
3987 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
3990 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
3993 /* end of Statistics */
3998 * nic init service functions
4001 static void bnx2x_zero_sb(struct bnx2x
*bp
, int sb_id
)
4003 int port
= BP_PORT(bp
);
4005 bnx2x_init_fill(bp
, BAR_USTRORM_INTMEM
+
4006 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port
, sb_id
), 0,
4007 sizeof(struct ustorm_status_block
)/4);
4008 bnx2x_init_fill(bp
, BAR_CSTRORM_INTMEM
+
4009 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port
, sb_id
), 0,
4010 sizeof(struct cstorm_status_block
)/4);
4013 static void bnx2x_init_sb(struct bnx2x
*bp
, struct host_status_block
*sb
,
4014 dma_addr_t mapping
, int sb_id
)
4016 int port
= BP_PORT(bp
);
4017 int func
= BP_FUNC(bp
);
4022 section
= ((u64
)mapping
) + offsetof(struct host_status_block
,
4024 sb
->u_status_block
.status_block_id
= sb_id
;
4026 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4027 USTORM_SB_HOST_SB_ADDR_OFFSET(port
, sb_id
), U64_LO(section
));
4028 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4029 ((USTORM_SB_HOST_SB_ADDR_OFFSET(port
, sb_id
)) + 4),
4031 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ FP_USB_FUNC_OFF
+
4032 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port
, sb_id
), func
);
4034 for (index
= 0; index
< HC_USTORM_SB_NUM_INDICES
; index
++)
4035 REG_WR16(bp
, BAR_USTRORM_INTMEM
+
4036 USTORM_SB_HC_DISABLE_OFFSET(port
, sb_id
, index
), 1);
4039 section
= ((u64
)mapping
) + offsetof(struct host_status_block
,
4041 sb
->c_status_block
.status_block_id
= sb_id
;
4043 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4044 CSTORM_SB_HOST_SB_ADDR_OFFSET(port
, sb_id
), U64_LO(section
));
4045 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4046 ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port
, sb_id
)) + 4),
4048 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ FP_CSB_FUNC_OFF
+
4049 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port
, sb_id
), func
);
4051 for (index
= 0; index
< HC_CSTORM_SB_NUM_INDICES
; index
++)
4052 REG_WR16(bp
, BAR_CSTRORM_INTMEM
+
4053 CSTORM_SB_HC_DISABLE_OFFSET(port
, sb_id
, index
), 1);
4055 bnx2x_ack_sb(bp
, sb_id
, CSTORM_ID
, 0, IGU_INT_ENABLE
, 0);
4058 static void bnx2x_zero_def_sb(struct bnx2x
*bp
)
4060 int func
= BP_FUNC(bp
);
4062 bnx2x_init_fill(bp
, BAR_USTRORM_INTMEM
+
4063 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), 0,
4064 sizeof(struct ustorm_def_status_block
)/4);
4065 bnx2x_init_fill(bp
, BAR_CSTRORM_INTMEM
+
4066 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), 0,
4067 sizeof(struct cstorm_def_status_block
)/4);
4068 bnx2x_init_fill(bp
, BAR_XSTRORM_INTMEM
+
4069 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), 0,
4070 sizeof(struct xstorm_def_status_block
)/4);
4071 bnx2x_init_fill(bp
, BAR_TSTRORM_INTMEM
+
4072 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), 0,
4073 sizeof(struct tstorm_def_status_block
)/4);
4076 static void bnx2x_init_def_sb(struct bnx2x
*bp
,
4077 struct host_def_status_block
*def_sb
,
4078 dma_addr_t mapping
, int sb_id
)
4080 int port
= BP_PORT(bp
);
4081 int func
= BP_FUNC(bp
);
4082 int index
, val
, reg_offset
;
4086 section
= ((u64
)mapping
) + offsetof(struct host_def_status_block
,
4087 atten_status_block
);
4088 def_sb
->atten_status_block
.status_block_id
= sb_id
;
4092 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
4093 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
4095 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4096 bp
->attn_group
[index
].sig
[0] = REG_RD(bp
,
4097 reg_offset
+ 0x10*index
);
4098 bp
->attn_group
[index
].sig
[1] = REG_RD(bp
,
4099 reg_offset
+ 0x4 + 0x10*index
);
4100 bp
->attn_group
[index
].sig
[2] = REG_RD(bp
,
4101 reg_offset
+ 0x8 + 0x10*index
);
4102 bp
->attn_group
[index
].sig
[3] = REG_RD(bp
,
4103 reg_offset
+ 0xc + 0x10*index
);
4106 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
4107 HC_REG_ATTN_MSG0_ADDR_L
);
4109 REG_WR(bp
, reg_offset
, U64_LO(section
));
4110 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
4112 reg_offset
= (port
? HC_REG_ATTN_NUM_P1
: HC_REG_ATTN_NUM_P0
);
4114 val
= REG_RD(bp
, reg_offset
);
4116 REG_WR(bp
, reg_offset
, val
);
4119 section
= ((u64
)mapping
) + offsetof(struct host_def_status_block
,
4120 u_def_status_block
);
4121 def_sb
->u_def_status_block
.status_block_id
= sb_id
;
4123 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4124 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
), U64_LO(section
));
4125 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4126 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
)) + 4),
4128 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ DEF_USB_FUNC_OFF
+
4129 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), func
);
4131 for (index
= 0; index
< HC_USTORM_DEF_SB_NUM_INDICES
; index
++)
4132 REG_WR16(bp
, BAR_USTRORM_INTMEM
+
4133 USTORM_DEF_SB_HC_DISABLE_OFFSET(func
, index
), 1);
4136 section
= ((u64
)mapping
) + offsetof(struct host_def_status_block
,
4137 c_def_status_block
);
4138 def_sb
->c_def_status_block
.status_block_id
= sb_id
;
4140 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4141 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
), U64_LO(section
));
4142 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4143 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
)) + 4),
4145 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ DEF_CSB_FUNC_OFF
+
4146 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), func
);
4148 for (index
= 0; index
< HC_CSTORM_DEF_SB_NUM_INDICES
; index
++)
4149 REG_WR16(bp
, BAR_CSTRORM_INTMEM
+
4150 CSTORM_DEF_SB_HC_DISABLE_OFFSET(func
, index
), 1);
4153 section
= ((u64
)mapping
) + offsetof(struct host_def_status_block
,
4154 t_def_status_block
);
4155 def_sb
->t_def_status_block
.status_block_id
= sb_id
;
4157 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4158 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
), U64_LO(section
));
4159 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4160 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
)) + 4),
4162 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ DEF_TSB_FUNC_OFF
+
4163 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), func
);
4165 for (index
= 0; index
< HC_TSTORM_DEF_SB_NUM_INDICES
; index
++)
4166 REG_WR16(bp
, BAR_TSTRORM_INTMEM
+
4167 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func
, index
), 1);
4170 section
= ((u64
)mapping
) + offsetof(struct host_def_status_block
,
4171 x_def_status_block
);
4172 def_sb
->x_def_status_block
.status_block_id
= sb_id
;
4174 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
4175 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
), U64_LO(section
));
4176 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
4177 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func
)) + 4),
4179 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ DEF_XSB_FUNC_OFF
+
4180 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func
), func
);
4182 for (index
= 0; index
< HC_XSTORM_DEF_SB_NUM_INDICES
; index
++)
4183 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+
4184 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func
, index
), 1);
4186 bp
->stats_pending
= 0;
4187 bp
->set_mac_pending
= 0;
4189 bnx2x_ack_sb(bp
, sb_id
, CSTORM_ID
, 0, IGU_INT_ENABLE
, 0);
4192 static void bnx2x_update_coalesce(struct bnx2x
*bp
)
4194 int port
= BP_PORT(bp
);
4197 for_each_queue(bp
, i
) {
4198 int sb_id
= bp
->fp
[i
].sb_id
;
4200 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4201 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
4202 USTORM_SB_HC_TIMEOUT_OFFSET(port
, sb_id
,
4203 U_SB_ETH_RX_CQ_INDEX
),
4205 REG_WR16(bp
, BAR_USTRORM_INTMEM
+
4206 USTORM_SB_HC_DISABLE_OFFSET(port
, sb_id
,
4207 U_SB_ETH_RX_CQ_INDEX
),
4208 bp
->rx_ticks
? 0 : 1);
4209 REG_WR16(bp
, BAR_USTRORM_INTMEM
+
4210 USTORM_SB_HC_DISABLE_OFFSET(port
, sb_id
,
4211 U_SB_ETH_RX_BD_INDEX
),
4212 bp
->rx_ticks
? 0 : 1);
4214 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4215 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
4216 CSTORM_SB_HC_TIMEOUT_OFFSET(port
, sb_id
,
4217 C_SB_ETH_TX_CQ_INDEX
),
4219 REG_WR16(bp
, BAR_CSTRORM_INTMEM
+
4220 CSTORM_SB_HC_DISABLE_OFFSET(port
, sb_id
,
4221 C_SB_ETH_TX_CQ_INDEX
),
4222 bp
->tx_ticks
? 0 : 1);
4226 static inline void bnx2x_free_tpa_pool(struct bnx2x
*bp
,
4227 struct bnx2x_fastpath
*fp
, int last
)
4231 for (i
= 0; i
< last
; i
++) {
4232 struct sw_rx_bd
*rx_buf
= &(fp
->tpa_pool
[i
]);
4233 struct sk_buff
*skb
= rx_buf
->skb
;
4236 DP(NETIF_MSG_IFDOWN
, "tpa bin %d empty on free\n", i
);
4240 if (fp
->tpa_state
[i
] == BNX2X_TPA_START
)
4241 pci_unmap_single(bp
->pdev
,
4242 pci_unmap_addr(rx_buf
, mapping
),
4244 PCI_DMA_FROMDEVICE
);
4251 static void bnx2x_init_rx_rings(struct bnx2x
*bp
)
4253 int func
= BP_FUNC(bp
);
4254 int max_agg_queues
= CHIP_IS_E1(bp
) ? ETH_MAX_AGGREGATION_QUEUES_E1
:
4255 ETH_MAX_AGGREGATION_QUEUES_E1H
;
4256 u16 ring_prod
, cqe_ring_prod
;
4259 bp
->rx_buf_size
= bp
->dev
->mtu
;
4260 bp
->rx_buf_size
+= bp
->rx_offset
+ ETH_OVREHEAD
+
4261 BCM_RX_ETH_PAYLOAD_ALIGN
;
4263 if (bp
->flags
& TPA_ENABLE_FLAG
) {
4265 "rx_buf_size %d effective_mtu %d\n",
4266 bp
->rx_buf_size
, bp
->dev
->mtu
+ ETH_OVREHEAD
);
4268 for_each_queue(bp
, j
) {
4269 struct bnx2x_fastpath
*fp
= &bp
->fp
[j
];
4271 for (i
= 0; i
< max_agg_queues
; i
++) {
4272 fp
->tpa_pool
[i
].skb
=
4273 netdev_alloc_skb(bp
->dev
, bp
->rx_buf_size
);
4274 if (!fp
->tpa_pool
[i
].skb
) {
4275 BNX2X_ERR("Failed to allocate TPA "
4276 "skb pool for queue[%d] - "
4277 "disabling TPA on this "
4279 bnx2x_free_tpa_pool(bp
, fp
, i
);
4280 fp
->disable_tpa
= 1;
4283 pci_unmap_addr_set((struct sw_rx_bd
*)
4284 &bp
->fp
->tpa_pool
[i
],
4286 fp
->tpa_state
[i
] = BNX2X_TPA_STOP
;
4291 for_each_queue(bp
, j
) {
4292 struct bnx2x_fastpath
*fp
= &bp
->fp
[j
];
4295 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
4296 fp
->rx_bd_cons_sb
= BNX2X_RX_SB_BD_INDEX
;
4298 /* "next page" elements initialization */
4300 for (i
= 1; i
<= NUM_RX_SGE_PAGES
; i
++) {
4301 struct eth_rx_sge
*sge
;
4303 sge
= &fp
->rx_sge_ring
[RX_SGE_CNT
* i
- 2];
4305 cpu_to_le32(U64_HI(fp
->rx_sge_mapping
+
4306 BCM_PAGE_SIZE
*(i
% NUM_RX_SGE_PAGES
)));
4308 cpu_to_le32(U64_LO(fp
->rx_sge_mapping
+
4309 BCM_PAGE_SIZE
*(i
% NUM_RX_SGE_PAGES
)));
4312 bnx2x_init_sge_ring_bit_mask(fp
);
4315 for (i
= 1; i
<= NUM_RX_RINGS
; i
++) {
4316 struct eth_rx_bd
*rx_bd
;
4318 rx_bd
= &fp
->rx_desc_ring
[RX_DESC_CNT
* i
- 2];
4320 cpu_to_le32(U64_HI(fp
->rx_desc_mapping
+
4321 BCM_PAGE_SIZE
*(i
% NUM_RX_RINGS
)));
4323 cpu_to_le32(U64_LO(fp
->rx_desc_mapping
+
4324 BCM_PAGE_SIZE
*(i
% NUM_RX_RINGS
)));
4328 for (i
= 1; i
<= NUM_RCQ_RINGS
; i
++) {
4329 struct eth_rx_cqe_next_page
*nextpg
;
4331 nextpg
= (struct eth_rx_cqe_next_page
*)
4332 &fp
->rx_comp_ring
[RCQ_DESC_CNT
* i
- 1];
4334 cpu_to_le32(U64_HI(fp
->rx_comp_mapping
+
4335 BCM_PAGE_SIZE
*(i
% NUM_RCQ_RINGS
)));
4337 cpu_to_le32(U64_LO(fp
->rx_comp_mapping
+
4338 BCM_PAGE_SIZE
*(i
% NUM_RCQ_RINGS
)));
4341 /* Allocate SGEs and initialize the ring elements */
4342 for (i
= 0, ring_prod
= 0;
4343 i
< MAX_RX_SGE_CNT
*NUM_RX_SGE_PAGES
; i
++) {
4345 if (bnx2x_alloc_rx_sge(bp
, fp
, ring_prod
) < 0) {
4346 BNX2X_ERR("was only able to allocate "
4348 BNX2X_ERR("disabling TPA for queue[%d]\n", j
);
4349 /* Cleanup already allocated elements */
4350 bnx2x_free_rx_sge_range(bp
, fp
, ring_prod
);
4351 bnx2x_free_tpa_pool(bp
, fp
, max_agg_queues
);
4352 fp
->disable_tpa
= 1;
4356 ring_prod
= NEXT_SGE_IDX(ring_prod
);
4358 fp
->rx_sge_prod
= ring_prod
;
4360 /* Allocate BDs and initialize BD ring */
4361 fp
->rx_comp_cons
= 0;
4362 cqe_ring_prod
= ring_prod
= 0;
4363 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
4364 if (bnx2x_alloc_rx_skb(bp
, fp
, ring_prod
) < 0) {
4365 BNX2X_ERR("was only able to allocate "
4367 bp
->eth_stats
.rx_skb_alloc_failed
++;
4370 ring_prod
= NEXT_RX_IDX(ring_prod
);
4371 cqe_ring_prod
= NEXT_RCQ_IDX(cqe_ring_prod
);
4372 WARN_ON(ring_prod
<= i
);
4375 fp
->rx_bd_prod
= ring_prod
;
4376 /* must not have more available CQEs than BDs */
4377 fp
->rx_comp_prod
= min((u16
)(NUM_RCQ_RINGS
*RCQ_DESC_CNT
),
4379 fp
->rx_pkt
= fp
->rx_calls
= 0;
4382 * this will generate an interrupt (to the TSTORM)
4383 * must only be done after chip is initialized
4385 bnx2x_update_rx_prod(bp
, fp
, ring_prod
, fp
->rx_comp_prod
,
4390 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4391 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func
),
4392 U64_LO(fp
->rx_comp_mapping
));
4393 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4394 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func
) + 4,
4395 U64_HI(fp
->rx_comp_mapping
));
4399 static void bnx2x_init_tx_ring(struct bnx2x
*bp
)
4403 for_each_queue(bp
, j
) {
4404 struct bnx2x_fastpath
*fp
= &bp
->fp
[j
];
4406 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
4407 struct eth_tx_bd
*tx_bd
=
4408 &fp
->tx_desc_ring
[TX_DESC_CNT
* i
- 1];
4411 cpu_to_le32(U64_HI(fp
->tx_desc_mapping
+
4412 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
4414 cpu_to_le32(U64_LO(fp
->tx_desc_mapping
+
4415 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
4418 fp
->tx_pkt_prod
= 0;
4419 fp
->tx_pkt_cons
= 0;
4422 fp
->tx_cons_sb
= BNX2X_TX_SB_INDEX
;
4427 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
4429 int func
= BP_FUNC(bp
);
4431 spin_lock_init(&bp
->spq_lock
);
4433 bp
->spq_left
= MAX_SPQ_PENDING
;
4434 bp
->spq_prod_idx
= 0;
4435 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
4436 bp
->spq_prod_bd
= bp
->spq
;
4437 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
4439 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ XSTORM_SPQ_PAGE_BASE_OFFSET(func
),
4440 U64_LO(bp
->spq_mapping
));
4442 XSEM_REG_FAST_MEMORY
+ XSTORM_SPQ_PAGE_BASE_OFFSET(func
) + 4,
4443 U64_HI(bp
->spq_mapping
));
4445 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ XSTORM_SPQ_PROD_OFFSET(func
),
4449 static void bnx2x_init_context(struct bnx2x
*bp
)
4453 for_each_queue(bp
, i
) {
4454 struct eth_context
*context
= bnx2x_sp(bp
, context
[i
].eth
);
4455 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
4456 u8 sb_id
= FP_SB_ID(fp
);
4458 context
->xstorm_st_context
.tx_bd_page_base_hi
=
4459 U64_HI(fp
->tx_desc_mapping
);
4460 context
->xstorm_st_context
.tx_bd_page_base_lo
=
4461 U64_LO(fp
->tx_desc_mapping
);
4462 context
->xstorm_st_context
.db_data_addr_hi
=
4463 U64_HI(fp
->tx_prods_mapping
);
4464 context
->xstorm_st_context
.db_data_addr_lo
=
4465 U64_LO(fp
->tx_prods_mapping
);
4466 context
->xstorm_st_context
.statistics_data
= (BP_CL_ID(bp
) |
4467 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE
);
4469 context
->ustorm_st_context
.common
.sb_index_numbers
=
4470 BNX2X_RX_SB_INDEX_NUM
;
4471 context
->ustorm_st_context
.common
.clientId
= FP_CL_ID(fp
);
4472 context
->ustorm_st_context
.common
.status_block_id
= sb_id
;
4473 context
->ustorm_st_context
.common
.flags
=
4474 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT
;
4475 context
->ustorm_st_context
.common
.mc_alignment_size
=
4476 BCM_RX_ETH_PAYLOAD_ALIGN
;
4477 context
->ustorm_st_context
.common
.bd_buff_size
=
4479 context
->ustorm_st_context
.common
.bd_page_base_hi
=
4480 U64_HI(fp
->rx_desc_mapping
);
4481 context
->ustorm_st_context
.common
.bd_page_base_lo
=
4482 U64_LO(fp
->rx_desc_mapping
);
4483 if (!fp
->disable_tpa
) {
4484 context
->ustorm_st_context
.common
.flags
|=
4485 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA
|
4486 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING
);
4487 context
->ustorm_st_context
.common
.sge_buff_size
=
4488 (u16
)(BCM_PAGE_SIZE
*PAGES_PER_SGE
);
4489 context
->ustorm_st_context
.common
.sge_page_base_hi
=
4490 U64_HI(fp
->rx_sge_mapping
);
4491 context
->ustorm_st_context
.common
.sge_page_base_lo
=
4492 U64_LO(fp
->rx_sge_mapping
);
4495 context
->cstorm_st_context
.sb_index_number
=
4496 C_SB_ETH_TX_CQ_INDEX
;
4497 context
->cstorm_st_context
.status_block_id
= sb_id
;
4499 context
->xstorm_ag_context
.cdu_reserved
=
4500 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp
, i
),
4501 CDU_REGION_NUMBER_XCM_AG
,
4502 ETH_CONNECTION_TYPE
);
4503 context
->ustorm_ag_context
.cdu_usage
=
4504 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp
, i
),
4505 CDU_REGION_NUMBER_UCM_AG
,
4506 ETH_CONNECTION_TYPE
);
4510 static void bnx2x_init_ind_table(struct bnx2x
*bp
)
4512 int port
= BP_PORT(bp
);
4518 DP(NETIF_MSG_IFUP
, "Initializing indirection table\n");
4519 for (i
= 0; i
< TSTORM_INDIRECTION_TABLE_SIZE
; i
++)
4520 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
4521 TSTORM_INDIRECTION_TABLE_OFFSET(port
) + i
,
4522 i
% bp
->num_queues
);
4524 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
4527 static void bnx2x_set_client_config(struct bnx2x
*bp
)
4529 struct tstorm_eth_client_config tstorm_client
= {0};
4530 int port
= BP_PORT(bp
);
4533 tstorm_client
.mtu
= bp
->dev
->mtu
+ ETH_OVREHEAD
;
4534 tstorm_client
.statistics_counter_id
= BP_CL_ID(bp
);
4535 tstorm_client
.config_flags
=
4536 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE
;
4538 if (bp
->rx_mode
&& bp
->vlgrp
) {
4539 tstorm_client
.config_flags
|=
4540 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE
;
4541 DP(NETIF_MSG_IFUP
, "vlan removal enabled\n");
4545 if (bp
->flags
& TPA_ENABLE_FLAG
) {
4546 tstorm_client
.max_sges_for_packet
=
4547 BCM_PAGE_ALIGN(tstorm_client
.mtu
) >> BCM_PAGE_SHIFT
;
4548 tstorm_client
.max_sges_for_packet
=
4549 ((tstorm_client
.max_sges_for_packet
+
4550 PAGES_PER_SGE
- 1) & (~(PAGES_PER_SGE
- 1))) >>
4551 PAGES_PER_SGE_SHIFT
;
4553 tstorm_client
.config_flags
|=
4554 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING
;
4557 for_each_queue(bp
, i
) {
4558 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4559 TSTORM_CLIENT_CONFIG_OFFSET(port
, bp
->fp
[i
].cl_id
),
4560 ((u32
*)&tstorm_client
)[0]);
4561 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4562 TSTORM_CLIENT_CONFIG_OFFSET(port
, bp
->fp
[i
].cl_id
) + 4,
4563 ((u32
*)&tstorm_client
)[1]);
4566 DP(BNX2X_MSG_OFF
, "tstorm_client: 0x%08x 0x%08x\n",
4567 ((u32
*)&tstorm_client
)[0], ((u32
*)&tstorm_client
)[1]);
4570 static void bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
4572 struct tstorm_eth_mac_filter_config tstorm_mac_filter
= {0};
4573 int mode
= bp
->rx_mode
;
4574 int mask
= (1 << BP_L_ID(bp
));
4575 int func
= BP_FUNC(bp
);
4578 DP(NETIF_MSG_IFUP
, "rx mode %d mask 0x%x\n", mode
, mask
);
4581 case BNX2X_RX_MODE_NONE
: /* no Rx */
4582 tstorm_mac_filter
.ucast_drop_all
= mask
;
4583 tstorm_mac_filter
.mcast_drop_all
= mask
;
4584 tstorm_mac_filter
.bcast_drop_all
= mask
;
4586 case BNX2X_RX_MODE_NORMAL
:
4587 tstorm_mac_filter
.bcast_accept_all
= mask
;
4589 case BNX2X_RX_MODE_ALLMULTI
:
4590 tstorm_mac_filter
.mcast_accept_all
= mask
;
4591 tstorm_mac_filter
.bcast_accept_all
= mask
;
4593 case BNX2X_RX_MODE_PROMISC
:
4594 tstorm_mac_filter
.ucast_accept_all
= mask
;
4595 tstorm_mac_filter
.mcast_accept_all
= mask
;
4596 tstorm_mac_filter
.bcast_accept_all
= mask
;
4599 BNX2X_ERR("BAD rx mode (%d)\n", mode
);
4603 for (i
= 0; i
< sizeof(struct tstorm_eth_mac_filter_config
)/4; i
++) {
4604 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4605 TSTORM_MAC_FILTER_CONFIG_OFFSET(func
) + i
* 4,
4606 ((u32
*)&tstorm_mac_filter
)[i
]);
4608 /* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4609 ((u32 *)&tstorm_mac_filter)[i]); */
4612 if (mode
!= BNX2X_RX_MODE_NONE
)
4613 bnx2x_set_client_config(bp
);
4616 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
4620 if (bp
->flags
& TPA_ENABLE_FLAG
) {
4621 struct tstorm_eth_tpa_exist tpa
= {0};
4625 REG_WR(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_TPA_EXIST_OFFSET
,
4627 REG_WR(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_TPA_EXIST_OFFSET
+ 4,
4631 /* Zero this manually as its initialization is
4632 currently missing in the initTool */
4633 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
4634 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4635 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
4638 static void bnx2x_init_internal_port(struct bnx2x
*bp
)
4640 int port
= BP_PORT(bp
);
4642 REG_WR(bp
, BAR_USTRORM_INTMEM
+ USTORM_HC_BTR_OFFSET(port
), BNX2X_BTR
);
4643 REG_WR(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_HC_BTR_OFFSET(port
), BNX2X_BTR
);
4644 REG_WR(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_HC_BTR_OFFSET(port
), BNX2X_BTR
);
4645 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_HC_BTR_OFFSET(port
), BNX2X_BTR
);
4648 static void bnx2x_init_internal_func(struct bnx2x
*bp
)
4650 struct tstorm_eth_function_common_config tstorm_config
= {0};
4651 struct stats_indication_flags stats_flags
= {0};
4652 int port
= BP_PORT(bp
);
4653 int func
= BP_FUNC(bp
);
4658 tstorm_config
.config_flags
= MULTI_FLAGS
;
4659 tstorm_config
.rss_result_mask
= MULTI_MASK
;
4662 tstorm_config
.leading_client_id
= BP_L_ID(bp
);
4664 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4665 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func
),
4666 (*(u32
*)&tstorm_config
));
4668 bp
->rx_mode
= BNX2X_RX_MODE_NONE
; /* no rx until link is up */
4669 bnx2x_set_storm_rx_mode(bp
);
4671 /* reset xstorm per client statistics */
4672 for (i
= 0; i
< sizeof(struct xstorm_per_client_stats
) / 4; i
++) {
4673 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
4674 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port
, BP_CL_ID(bp
)) +
4677 /* reset tstorm per client statistics */
4678 for (i
= 0; i
< sizeof(struct tstorm_per_client_stats
) / 4; i
++) {
4679 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4680 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port
, BP_CL_ID(bp
)) +
4684 /* Init statistics related context */
4685 stats_flags
.collect_eth
= 1;
4687 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_STATS_FLAGS_OFFSET(func
),
4688 ((u32
*)&stats_flags
)[0]);
4689 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_STATS_FLAGS_OFFSET(func
) + 4,
4690 ((u32
*)&stats_flags
)[1]);
4692 REG_WR(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_STATS_FLAGS_OFFSET(func
),
4693 ((u32
*)&stats_flags
)[0]);
4694 REG_WR(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_STATS_FLAGS_OFFSET(func
) + 4,
4695 ((u32
*)&stats_flags
)[1]);
4697 REG_WR(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_STATS_FLAGS_OFFSET(func
),
4698 ((u32
*)&stats_flags
)[0]);
4699 REG_WR(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_STATS_FLAGS_OFFSET(func
) + 4,
4700 ((u32
*)&stats_flags
)[1]);
4702 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
4703 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func
),
4704 U64_LO(bnx2x_sp_mapping(bp
, fw_stats
)));
4705 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
4706 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func
) + 4,
4707 U64_HI(bnx2x_sp_mapping(bp
, fw_stats
)));
4709 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4710 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func
),
4711 U64_LO(bnx2x_sp_mapping(bp
, fw_stats
)));
4712 REG_WR(bp
, BAR_TSTRORM_INTMEM
+
4713 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func
) + 4,
4714 U64_HI(bnx2x_sp_mapping(bp
, fw_stats
)));
4716 if (CHIP_IS_E1H(bp
)) {
4717 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNCTION_MODE_OFFSET
,
4719 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNCTION_MODE_OFFSET
,
4721 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNCTION_MODE_OFFSET
,
4723 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNCTION_MODE_OFFSET
,
4726 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_E1HOV_OFFSET(func
),
4730 /* Init CQ ring mapping and aggregation size */
4731 max_agg_size
= min((u32
)(bp
->rx_buf_size
+
4732 8*BCM_PAGE_SIZE
*PAGES_PER_SGE
),
4734 for_each_queue(bp
, i
) {
4735 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
4737 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4738 USTORM_CQE_PAGE_BASE_OFFSET(port
, FP_CL_ID(fp
)),
4739 U64_LO(fp
->rx_comp_mapping
));
4740 REG_WR(bp
, BAR_USTRORM_INTMEM
+
4741 USTORM_CQE_PAGE_BASE_OFFSET(port
, FP_CL_ID(fp
)) + 4,
4742 U64_HI(fp
->rx_comp_mapping
));
4744 REG_WR16(bp
, BAR_USTRORM_INTMEM
+
4745 USTORM_MAX_AGG_SIZE_OFFSET(port
, FP_CL_ID(fp
)),
4750 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
4752 switch (load_code
) {
4753 case FW_MSG_CODE_DRV_LOAD_COMMON
:
4754 bnx2x_init_internal_common(bp
);
4757 case FW_MSG_CODE_DRV_LOAD_PORT
:
4758 bnx2x_init_internal_port(bp
);
4761 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
4762 bnx2x_init_internal_func(bp
);
4766 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
4771 static void bnx2x_nic_init(struct bnx2x
*bp
, u32 load_code
)
4775 for_each_queue(bp
, i
) {
4776 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
4779 fp
->state
= BNX2X_FP_STATE_CLOSED
;
4781 fp
->cl_id
= BP_L_ID(bp
) + i
;
4782 fp
->sb_id
= fp
->cl_id
;
4784 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4785 bp
, fp
->status_blk
, i
, FP_CL_ID(fp
), FP_SB_ID(fp
));
4786 bnx2x_init_sb(bp
, fp
->status_blk
, fp
->status_blk_mapping
,
4788 bnx2x_update_fpsb_idx(fp
);
4791 bnx2x_init_def_sb(bp
, bp
->def_status_blk
, bp
->def_status_blk_mapping
,
4793 bnx2x_update_dsb_idx(bp
);
4794 bnx2x_update_coalesce(bp
);
4795 bnx2x_init_rx_rings(bp
);
4796 bnx2x_init_tx_ring(bp
);
4797 bnx2x_init_sp_ring(bp
);
4798 bnx2x_init_context(bp
);
4799 bnx2x_init_internal(bp
, load_code
);
4800 bnx2x_init_ind_table(bp
);
4801 bnx2x_int_enable(bp
);
4804 /* end of nic init */
4807 * gzip service functions
4810 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
4812 bp
->gunzip_buf
= pci_alloc_consistent(bp
->pdev
, FW_BUF_SIZE
,
4813 &bp
->gunzip_mapping
);
4814 if (bp
->gunzip_buf
== NULL
)
4817 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
4818 if (bp
->strm
== NULL
)
4821 bp
->strm
->workspace
= kmalloc(zlib_inflate_workspacesize(),
4823 if (bp
->strm
->workspace
== NULL
)
4833 pci_free_consistent(bp
->pdev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
4834 bp
->gunzip_mapping
);
4835 bp
->gunzip_buf
= NULL
;
4838 printk(KERN_ERR PFX
"%s: Cannot allocate firmware buffer for"
4839 " un-compression\n", bp
->dev
->name
);
4843 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
4845 kfree(bp
->strm
->workspace
);
4850 if (bp
->gunzip_buf
) {
4851 pci_free_consistent(bp
->pdev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
4852 bp
->gunzip_mapping
);
4853 bp
->gunzip_buf
= NULL
;
4857 static int bnx2x_gunzip(struct bnx2x
*bp
, u8
*zbuf
, int len
)
4861 /* check gzip header */
4862 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
))
4869 if (zbuf
[3] & FNAME
)
4870 while ((zbuf
[n
++] != 0) && (n
< len
));
4872 bp
->strm
->next_in
= zbuf
+ n
;
4873 bp
->strm
->avail_in
= len
- n
;
4874 bp
->strm
->next_out
= bp
->gunzip_buf
;
4875 bp
->strm
->avail_out
= FW_BUF_SIZE
;
4877 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
4881 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
4882 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
4883 printk(KERN_ERR PFX
"%s: Firmware decompression error: %s\n",
4884 bp
->dev
->name
, bp
->strm
->msg
);
4886 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
4887 if (bp
->gunzip_outlen
& 0x3)
4888 printk(KERN_ERR PFX
"%s: Firmware decompression error:"
4889 " gunzip_outlen (%d) not aligned\n",
4890 bp
->dev
->name
, bp
->gunzip_outlen
);
4891 bp
->gunzip_outlen
>>= 2;
4893 zlib_inflateEnd(bp
->strm
);
4895 if (rc
== Z_STREAM_END
)
4901 /* nic load/unload */
4904 * General service functions
4907 /* send a NIG loopback debug packet */
4908 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
4912 /* Ethernet source and destination addresses */
4913 wb_write
[0] = 0x55555555;
4914 wb_write
[1] = 0x55555555;
4915 wb_write
[2] = 0x20; /* SOP */
4916 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
4918 /* NON-IP protocol */
4919 wb_write
[0] = 0x09000000;
4920 wb_write
[1] = 0x55555555;
4921 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
4922 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
4925 /* some of the internal memories
4926 * are not directly readable from the driver
4927 * to test them we send debug packets
4929 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
4935 if (CHIP_REV_IS_FPGA(bp
))
4937 else if (CHIP_REV_IS_EMUL(bp
))
4942 DP(NETIF_MSG_HW
, "start part1\n");
4944 /* Disable inputs of parser neighbor blocks */
4945 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
4946 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
4947 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
4948 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
4950 /* Write 0 to parser credits for CFC search request */
4951 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
4953 /* send Ethernet packet */
4956 /* TODO do i reset NIG statistic? */
4957 /* Wait until NIG register shows 1 packet of size 0x10 */
4958 count
= 1000 * factor
;
4961 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
4962 val
= *bnx2x_sp(bp
, wb_data
[0]);
4970 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
4974 /* Wait until PRS register shows 1 packet */
4975 count
= 1000 * factor
;
4977 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
4985 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
4989 /* Reset and init BRB, PRS */
4990 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
4992 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
4994 bnx2x_init_block(bp
, BRB1_COMMON_START
, BRB1_COMMON_END
);
4995 bnx2x_init_block(bp
, PRS_COMMON_START
, PRS_COMMON_END
);
4997 DP(NETIF_MSG_HW
, "part2\n");
4999 /* Disable inputs of parser neighbor blocks */
5000 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5001 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5002 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5003 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5005 /* Write 0 to parser credits for CFC search request */
5006 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5008 /* send 10 Ethernet packets */
5009 for (i
= 0; i
< 10; i
++)
5012 /* Wait until NIG register shows 10 + 1
5013 packets of size 11*0x10 = 0xb0 */
5014 count
= 1000 * factor
;
5017 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5018 val
= *bnx2x_sp(bp
, wb_data
[0]);
5026 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5030 /* Wait until PRS register shows 2 packets */
5031 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5033 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5035 /* Write 1 to parser credits for CFC search request */
5036 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
5038 /* Wait until PRS register shows 3 packets */
5039 msleep(10 * factor
);
5040 /* Wait until NIG register shows 1 packet of size 0x10 */
5041 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5043 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5045 /* clear NIG EOP FIFO */
5046 for (i
= 0; i
< 11; i
++)
5047 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
5048 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
5050 BNX2X_ERR("clear of NIG failed\n");
5054 /* Reset and init BRB, PRS, NIG */
5055 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5057 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5059 bnx2x_init_block(bp
, BRB1_COMMON_START
, BRB1_COMMON_END
);
5060 bnx2x_init_block(bp
, PRS_COMMON_START
, PRS_COMMON_END
);
5063 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
5066 /* Enable inputs of parser neighbor blocks */
5067 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
5068 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
5069 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
5070 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
5072 DP(NETIF_MSG_HW
, "done\n");
5077 static void enable_blocks_attention(struct bnx2x
*bp
)
5079 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
5080 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
5081 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
5082 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
5083 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
5084 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
5085 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
5086 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
5087 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
5088 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5089 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5090 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
5091 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
5092 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
5093 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5094 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5095 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
5096 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
5097 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
5098 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
5099 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5100 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5101 if (CHIP_REV_IS_FPGA(bp
))
5102 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x580000);
5104 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x480000);
5105 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
5106 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
5107 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
5108 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5109 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5110 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
5111 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
5112 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5113 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0X18); /* bit 3,4 masked */
5117 static int bnx2x_init_common(struct bnx2x
*bp
)
5121 DP(BNX2X_MSG_MCP
, "starting common init func %d\n", BP_FUNC(bp
));
5123 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
5124 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, 0xfffc);
5126 bnx2x_init_block(bp
, MISC_COMMON_START
, MISC_COMMON_END
);
5127 if (CHIP_IS_E1H(bp
))
5128 REG_WR(bp
, MISC_REG_E1HMF_MODE
, IS_E1HMF(bp
));
5130 REG_WR(bp
, MISC_REG_LCPLL_CTRL_REG_2
, 0x100);
5132 REG_WR(bp
, MISC_REG_LCPLL_CTRL_REG_2
, 0x0);
5134 bnx2x_init_block(bp
, PXP_COMMON_START
, PXP_COMMON_END
);
5135 if (CHIP_IS_E1(bp
)) {
5136 /* enable HW interrupt from PXP on USDM overflow
5137 bit 16 on INT_MASK_0 */
5138 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
5141 bnx2x_init_block(bp
, PXP2_COMMON_START
, PXP2_COMMON_END
);
5145 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, 1);
5146 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, 1);
5147 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, 1);
5148 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, 1);
5149 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, 1);
5150 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 1);
5152 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5153 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, 1);
5154 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, 1);
5155 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, 1);
5156 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, 1);
5159 REG_WR(bp
, PXP2_REG_RQ_CDU_P_SIZE
, 2);
5161 REG_WR(bp
, PXP2_REG_RQ_TM_P_SIZE
, 5);
5162 REG_WR(bp
, PXP2_REG_RQ_QM_P_SIZE
, 5);
5163 REG_WR(bp
, PXP2_REG_RQ_SRC_P_SIZE
, 5);
5166 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
5167 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
5169 /* let the HW do it's magic ... */
5171 /* finish PXP init */
5172 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
5174 BNX2X_ERR("PXP2 CFG failed\n");
5177 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
5179 BNX2X_ERR("PXP2 RD_INIT failed\n");
5183 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
5184 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
5186 bnx2x_init_block(bp
, DMAE_COMMON_START
, DMAE_COMMON_END
);
5188 /* clean the DMAE memory */
5190 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8);
5192 bnx2x_init_block(bp
, TCM_COMMON_START
, TCM_COMMON_END
);
5193 bnx2x_init_block(bp
, UCM_COMMON_START
, UCM_COMMON_END
);
5194 bnx2x_init_block(bp
, CCM_COMMON_START
, CCM_COMMON_END
);
5195 bnx2x_init_block(bp
, XCM_COMMON_START
, XCM_COMMON_END
);
5197 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
5198 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
5199 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
5200 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
5202 bnx2x_init_block(bp
, QM_COMMON_START
, QM_COMMON_END
);
5203 /* soft reset pulse */
5204 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
5205 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
5208 bnx2x_init_block(bp
, TIMERS_COMMON_START
, TIMERS_COMMON_END
);
5211 bnx2x_init_block(bp
, DQ_COMMON_START
, DQ_COMMON_END
);
5212 REG_WR(bp
, DORQ_REG_DPM_CID_OFST
, BCM_PAGE_SHIFT
);
5213 if (!CHIP_REV_IS_SLOW(bp
)) {
5214 /* enable hw interrupt from doorbell Q */
5215 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
5218 bnx2x_init_block(bp
, BRB1_COMMON_START
, BRB1_COMMON_END
);
5219 if (CHIP_REV_IS_SLOW(bp
)) {
5220 /* fix for emulation and FPGA for no pause */
5221 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
, 513);
5222 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_1
, 513);
5223 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
, 0);
5224 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_1
, 0);
5227 bnx2x_init_block(bp
, PRS_COMMON_START
, PRS_COMMON_END
);
5229 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
5230 if (CHIP_IS_E1H(bp
))
5231 REG_WR(bp
, PRS_REG_E1HOV_MODE
, IS_E1HMF(bp
));
5233 bnx2x_init_block(bp
, TSDM_COMMON_START
, TSDM_COMMON_END
);
5234 bnx2x_init_block(bp
, CSDM_COMMON_START
, CSDM_COMMON_END
);
5235 bnx2x_init_block(bp
, USDM_COMMON_START
, USDM_COMMON_END
);
5236 bnx2x_init_block(bp
, XSDM_COMMON_START
, XSDM_COMMON_END
);
5238 if (CHIP_IS_E1H(bp
)) {
5239 bnx2x_init_fill(bp
, TSTORM_INTMEM_ADDR
, 0,
5240 STORM_INTMEM_SIZE_E1H
/2);
5242 TSTORM_INTMEM_ADDR
+ STORM_INTMEM_SIZE_E1H
/2,
5243 0, STORM_INTMEM_SIZE_E1H
/2);
5244 bnx2x_init_fill(bp
, CSTORM_INTMEM_ADDR
, 0,
5245 STORM_INTMEM_SIZE_E1H
/2);
5247 CSTORM_INTMEM_ADDR
+ STORM_INTMEM_SIZE_E1H
/2,
5248 0, STORM_INTMEM_SIZE_E1H
/2);
5249 bnx2x_init_fill(bp
, XSTORM_INTMEM_ADDR
, 0,
5250 STORM_INTMEM_SIZE_E1H
/2);
5252 XSTORM_INTMEM_ADDR
+ STORM_INTMEM_SIZE_E1H
/2,
5253 0, STORM_INTMEM_SIZE_E1H
/2);
5254 bnx2x_init_fill(bp
, USTORM_INTMEM_ADDR
, 0,
5255 STORM_INTMEM_SIZE_E1H
/2);
5257 USTORM_INTMEM_ADDR
+ STORM_INTMEM_SIZE_E1H
/2,
5258 0, STORM_INTMEM_SIZE_E1H
/2);
5260 bnx2x_init_fill(bp
, TSTORM_INTMEM_ADDR
, 0,
5261 STORM_INTMEM_SIZE_E1
);
5262 bnx2x_init_fill(bp
, CSTORM_INTMEM_ADDR
, 0,
5263 STORM_INTMEM_SIZE_E1
);
5264 bnx2x_init_fill(bp
, XSTORM_INTMEM_ADDR
, 0,
5265 STORM_INTMEM_SIZE_E1
);
5266 bnx2x_init_fill(bp
, USTORM_INTMEM_ADDR
, 0,
5267 STORM_INTMEM_SIZE_E1
);
5270 bnx2x_init_block(bp
, TSEM_COMMON_START
, TSEM_COMMON_END
);
5271 bnx2x_init_block(bp
, USEM_COMMON_START
, USEM_COMMON_END
);
5272 bnx2x_init_block(bp
, CSEM_COMMON_START
, CSEM_COMMON_END
);
5273 bnx2x_init_block(bp
, XSEM_COMMON_START
, XSEM_COMMON_END
);
5276 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
5278 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
5281 bnx2x_init_block(bp
, UPB_COMMON_START
, UPB_COMMON_END
);
5282 bnx2x_init_block(bp
, XPB_COMMON_START
, XPB_COMMON_END
);
5283 bnx2x_init_block(bp
, PBF_COMMON_START
, PBF_COMMON_END
);
5285 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
5286 for (i
= SRC_REG_KEYRSS0_0
; i
<= SRC_REG_KEYRSS1_9
; i
+= 4) {
5287 REG_WR(bp
, i
, 0xc0cac01a);
5288 /* TODO: replace with something meaningful */
5290 if (CHIP_IS_E1H(bp
))
5291 bnx2x_init_block(bp
, SRCH_COMMON_START
, SRCH_COMMON_END
);
5292 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
5294 if (sizeof(union cdu_context
) != 1024)
5295 /* we currently assume that a context is 1024 bytes */
5296 printk(KERN_ALERT PFX
"please adjust the size of"
5297 " cdu_context(%ld)\n", (long)sizeof(union cdu_context
));
5299 bnx2x_init_block(bp
, CDU_COMMON_START
, CDU_COMMON_END
);
5300 val
= (4 << 24) + (0 << 12) + 1024;
5301 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
5302 if (CHIP_IS_E1(bp
)) {
5303 /* !!! fix pxp client crdit until excel update */
5304 REG_WR(bp
, CDU_REG_CDU_DEBUG
, 0x264);
5305 REG_WR(bp
, CDU_REG_CDU_DEBUG
, 0);
5308 bnx2x_init_block(bp
, CFC_COMMON_START
, CFC_COMMON_END
);
5309 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
5311 bnx2x_init_block(bp
, HC_COMMON_START
, HC_COMMON_END
);
5312 bnx2x_init_block(bp
, MISC_AEU_COMMON_START
, MISC_AEU_COMMON_END
);
5314 /* PXPCS COMMON comes here */
5315 /* Reset PCIE errors for debug */
5316 REG_WR(bp
, 0x2814, 0xffffffff);
5317 REG_WR(bp
, 0x3820, 0xffffffff);
5319 /* EMAC0 COMMON comes here */
5320 /* EMAC1 COMMON comes here */
5321 /* DBU COMMON comes here */
5322 /* DBG COMMON comes here */
5324 bnx2x_init_block(bp
, NIG_COMMON_START
, NIG_COMMON_END
);
5325 if (CHIP_IS_E1H(bp
)) {
5326 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_E1HMF(bp
));
5327 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_E1HMF(bp
));
5330 if (CHIP_REV_IS_SLOW(bp
))
5333 /* finish CFC init */
5334 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
5336 BNX2X_ERR("CFC LL_INIT failed\n");
5339 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
5341 BNX2X_ERR("CFC AC_INIT failed\n");
5344 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
5346 BNX2X_ERR("CFC CAM_INIT failed\n");
5349 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
5351 /* read NIG statistic
5352 to see if this is our first up since powerup */
5353 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5354 val
= *bnx2x_sp(bp
, wb_data
[0]);
5356 /* do internal memory self test */
5357 if ((CHIP_IS_E1(bp
)) && (val
== 0) && bnx2x_int_mem_test(bp
)) {
5358 BNX2X_ERR("internal mem self test failed\n");
5362 switch (bp
->common
.board
& SHARED_HW_CFG_BOARD_TYPE_MASK
) {
5363 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G
:
5364 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G
:
5365 /* Fan failure is indicated by SPIO 5 */
5366 bnx2x_set_spio(bp
, MISC_REGISTERS_SPIO_5
,
5367 MISC_REGISTERS_SPIO_INPUT_HI_Z
);
5369 /* set to active low mode */
5370 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
5371 val
|= ((1 << MISC_REGISTERS_SPIO_5
) <<
5372 MISC_REGISTERS_SPIO_INT_OLD_SET_POS
);
5373 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
5375 /* enable interrupt to signal the IGU */
5376 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
5377 val
|= (1 << MISC_REGISTERS_SPIO_5
);
5378 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
5385 /* clear PXP2 attentions */
5386 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
5388 enable_blocks_attention(bp
);
5390 if (!BP_NOMCP(bp
)) {
5391 bnx2x_acquire_phy_lock(bp
);
5392 bnx2x_common_init_phy(bp
, bp
->common
.shmem_base
);
5393 bnx2x_release_phy_lock(bp
);
5395 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5400 static int bnx2x_init_port(struct bnx2x
*bp
)
5402 int port
= BP_PORT(bp
);
5405 DP(BNX2X_MSG_MCP
, "starting port init port %x\n", port
);
5407 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
5409 /* Port PXP comes here */
5410 /* Port PXP2 comes here */
5415 wb_write
[0] = ONCHIP_ADDR1(bp
->timers_mapping
);
5416 wb_write
[1] = ONCHIP_ADDR2(bp
->timers_mapping
);
5417 REG_WR_DMAE(bp
, PXP2_REG_RQ_ONCHIP_AT
+ i
*8, wb_write
, 2);
5418 REG_WR(bp
, PXP2_REG_PSWRQ_TM0_L2P
+ func
*4, PXP_ONE_ILT(i
));
5423 wb_write
[0] = ONCHIP_ADDR1(bp
->qm_mapping
);
5424 wb_write
[1] = ONCHIP_ADDR2(bp
->qm_mapping
);
5425 REG_WR_DMAE(bp
, PXP2_REG_RQ_ONCHIP_AT
+ i
*8, wb_write
, 2);
5426 REG_WR(bp
, PXP2_REG_PSWRQ_QM0_L2P
+ func
*4, PXP_ONE_ILT(i
));
5431 wb_write
[0] = ONCHIP_ADDR1(bp
->t1_mapping
);
5432 wb_write
[1] = ONCHIP_ADDR2(bp
->t1_mapping
);
5433 REG_WR_DMAE(bp
, PXP2_REG_RQ_ONCHIP_AT
+ i
*8, wb_write
, 2);
5434 REG_WR(bp
, PXP2_REG_PSWRQ_SRC0_L2P
+ func
*4, PXP_ONE_ILT(i
));
5436 /* Port CMs come here */
5438 /* Port QM comes here */
5440 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ func
*4, 1024/64*20);
5441 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ func
*4, 31);
5443 bnx2x_init_block(bp
, func
? TIMERS_PORT1_START
: TIMERS_PORT0_START
,
5444 func
? TIMERS_PORT1_END
: TIMERS_PORT0_END
);
5446 /* Port DQ comes here */
5447 /* Port BRB1 comes here */
5448 /* Port PRS comes here */
5449 /* Port TSDM comes here */
5450 /* Port CSDM comes here */
5451 /* Port USDM comes here */
5452 /* Port XSDM comes here */
5453 bnx2x_init_block(bp
, port
? TSEM_PORT1_START
: TSEM_PORT0_START
,
5454 port
? TSEM_PORT1_END
: TSEM_PORT0_END
);
5455 bnx2x_init_block(bp
, port
? USEM_PORT1_START
: USEM_PORT0_START
,
5456 port
? USEM_PORT1_END
: USEM_PORT0_END
);
5457 bnx2x_init_block(bp
, port
? CSEM_PORT1_START
: CSEM_PORT0_START
,
5458 port
? CSEM_PORT1_END
: CSEM_PORT0_END
);
5459 bnx2x_init_block(bp
, port
? XSEM_PORT1_START
: XSEM_PORT0_START
,
5460 port
? XSEM_PORT1_END
: XSEM_PORT0_END
);
5461 /* Port UPB comes here */
5462 /* Port XPB comes here */
5464 bnx2x_init_block(bp
, port
? PBF_PORT1_START
: PBF_PORT0_START
,
5465 port
? PBF_PORT1_END
: PBF_PORT0_END
);
5467 /* configure PBF to work without PAUSE mtu 9000 */
5468 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
5470 /* update threshold */
5471 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
5472 /* update init credit */
5473 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
5476 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
5478 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
5481 /* tell the searcher where the T2 table is */
5482 REG_WR(bp
, SRC_REG_COUNTFREE0
+ func
*4, 16*1024/64);
5484 wb_write
[0] = U64_LO(bp
->t2_mapping
);
5485 wb_write
[1] = U64_HI(bp
->t2_mapping
);
5486 REG_WR_DMAE(bp
, SRC_REG_FIRSTFREE0
+ func
*4, wb_write
, 2);
5487 wb_write
[0] = U64_LO((u64
)bp
->t2_mapping
+ 16*1024 - 64);
5488 wb_write
[1] = U64_HI((u64
)bp
->t2_mapping
+ 16*1024 - 64);
5489 REG_WR_DMAE(bp
, SRC_REG_LASTFREE0
+ func
*4, wb_write
, 2);
5491 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ func
*4, 10);
5492 /* Port SRCH comes here */
5494 /* Port CDU comes here */
5495 /* Port CFC comes here */
5497 if (CHIP_IS_E1(bp
)) {
5498 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
5499 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
5501 bnx2x_init_block(bp
, port
? HC_PORT1_START
: HC_PORT0_START
,
5502 port
? HC_PORT1_END
: HC_PORT0_END
);
5504 bnx2x_init_block(bp
, port
? MISC_AEU_PORT1_START
:
5505 MISC_AEU_PORT0_START
,
5506 port
? MISC_AEU_PORT1_END
: MISC_AEU_PORT0_END
);
5507 /* init aeu_mask_attn_func_0/1:
5508 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5509 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5510 * bits 4-7 are used for "per vn group attention" */
5511 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4,
5512 (IS_E1HMF(bp
) ? 0xF7 : 0x7));
5514 /* Port PXPCS comes here */
5515 /* Port EMAC0 comes here */
5516 /* Port EMAC1 comes here */
5517 /* Port DBU comes here */
5518 /* Port DBG comes here */
5519 bnx2x_init_block(bp
, port
? NIG_PORT1_START
: NIG_PORT0_START
,
5520 port
? NIG_PORT1_END
: NIG_PORT0_END
);
5522 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
5524 if (CHIP_IS_E1H(bp
)) {
5526 struct cmng_struct_per_port m_cmng_port
;
5529 /* 0x2 disable e1hov, 0x1 enable */
5530 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
5531 (IS_E1HMF(bp
) ? 0x1 : 0x2));
5533 /* Init RATE SHAPING and FAIRNESS contexts.
5534 Initialize as if there is 10G link. */
5535 wsum
= bnx2x_calc_vn_wsum(bp
);
5536 bnx2x_init_port_minmax(bp
, (int)wsum
, 10000, &m_cmng_port
);
5538 for (vn
= VN_0
; vn
< E1HVN_MAX
; vn
++)
5539 bnx2x_init_vn_minmax(bp
, 2*vn
+ port
,
5540 wsum
, 10000, &m_cmng_port
);
5543 /* Port MCP comes here */
5544 /* Port DMAE comes here */
5546 switch (bp
->common
.board
& SHARED_HW_CFG_BOARD_TYPE_MASK
) {
5547 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G
:
5548 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G
:
5549 /* add SPIO 5 to group 0 */
5550 val
= REG_RD(bp
, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
5551 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
5552 REG_WR(bp
, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
, val
);
5559 bnx2x__link_reset(bp
);
5564 #define ILT_PER_FUNC (768/2)
5565 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
5566 /* the phys address is shifted right 12 bits and has an added
5567 1=valid bit added to the 53rd bit
5568 then since this is a wide register(TM)
5569 we split it into two 32 bit writes
5571 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5572 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
5573 #define PXP_ONE_ILT(x) (((x) << 10) | x)
5574 #define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
5576 #define CNIC_ILT_LINES 0
5578 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
5582 if (CHIP_IS_E1H(bp
))
5583 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
5585 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
5587 bnx2x_wb_wr(bp
, reg
, ONCHIP_ADDR1(addr
), ONCHIP_ADDR2(addr
));
5590 static int bnx2x_init_func(struct bnx2x
*bp
)
5592 int port
= BP_PORT(bp
);
5593 int func
= BP_FUNC(bp
);
5596 DP(BNX2X_MSG_MCP
, "starting func init func %x\n", func
);
5598 i
= FUNC_ILT_BASE(func
);
5600 bnx2x_ilt_wr(bp
, i
, bnx2x_sp_mapping(bp
, context
));
5601 if (CHIP_IS_E1H(bp
)) {
5602 REG_WR(bp
, PXP2_REG_RQ_CDU_FIRST_ILT
, i
);
5603 REG_WR(bp
, PXP2_REG_RQ_CDU_LAST_ILT
, i
+ CNIC_ILT_LINES
);
5605 REG_WR(bp
, PXP2_REG_PSWRQ_CDU0_L2P
+ func
*4,
5606 PXP_ILT_RANGE(i
, i
+ CNIC_ILT_LINES
));
5609 if (CHIP_IS_E1H(bp
)) {
5610 for (i
= 0; i
< 9; i
++)
5611 bnx2x_init_block(bp
,
5612 cm_start
[func
][i
], cm_end
[func
][i
]);
5614 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
5615 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
*8, bp
->e1hov
);
5618 /* HC init per function */
5619 if (CHIP_IS_E1H(bp
)) {
5620 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
5622 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
5623 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
5625 bnx2x_init_block(bp
, hc_limits
[func
][0], hc_limits
[func
][1]);
5627 if (CHIP_IS_E1H(bp
))
5628 REG_WR(bp
, HC_REG_FUNC_NUM_P0
+ port
*4, func
);
5630 /* Reset PCIE errors for debug */
5631 REG_WR(bp
, 0x2114, 0xffffffff);
5632 REG_WR(bp
, 0x2120, 0xffffffff);
5637 static int bnx2x_init_hw(struct bnx2x
*bp
, u32 load_code
)
5641 DP(BNX2X_MSG_MCP
, "function %d load_code %x\n",
5642 BP_FUNC(bp
), load_code
);
5645 mutex_init(&bp
->dmae_mutex
);
5646 bnx2x_gunzip_init(bp
);
5648 switch (load_code
) {
5649 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5650 rc
= bnx2x_init_common(bp
);
5655 case FW_MSG_CODE_DRV_LOAD_PORT
:
5657 rc
= bnx2x_init_port(bp
);
5662 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5664 rc
= bnx2x_init_func(bp
);
5670 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5674 if (!BP_NOMCP(bp
)) {
5675 int func
= BP_FUNC(bp
);
5677 bp
->fw_drv_pulse_wr_seq
=
5678 (SHMEM_RD(bp
, func_mb
[func
].drv_pulse_mb
) &
5679 DRV_PULSE_SEQ_MASK
);
5680 bp
->func_stx
= SHMEM_RD(bp
, func_mb
[func
].fw_mb_param
);
5681 DP(BNX2X_MSG_MCP
, "drv_pulse 0x%x func_stx 0x%x\n",
5682 bp
->fw_drv_pulse_wr_seq
, bp
->func_stx
);
5686 /* this needs to be done before gunzip end */
5687 bnx2x_zero_def_sb(bp
);
5688 for_each_queue(bp
, i
)
5689 bnx2x_zero_sb(bp
, BP_L_ID(bp
) + i
);
5692 bnx2x_gunzip_end(bp
);
5697 /* send the MCP a request, block until there is a reply */
5698 static u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
)
5700 int func
= BP_FUNC(bp
);
5701 u32 seq
= ++bp
->fw_seq
;
5704 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
5706 SHMEM_WR(bp
, func_mb
[func
].drv_mb_header
, (command
| seq
));
5707 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB\n", (command
| seq
));
5710 /* let the FW do it's magic ... */
5713 rc
= SHMEM_RD(bp
, func_mb
[func
].fw_mb_header
);
5715 /* Give the FW up to 2 second (200*10ms) */
5716 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 200));
5718 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5719 cnt
*delay
, rc
, seq
);
5721 /* is this a reply to our command? */
5722 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
)) {
5723 rc
&= FW_MSG_CODE_MASK
;
5727 BNX2X_ERR("FW failed to respond!\n");
5735 static void bnx2x_free_mem(struct bnx2x
*bp
)
5738 #define BNX2X_PCI_FREE(x, y, size) \
5741 pci_free_consistent(bp->pdev, size, x, y); \
5747 #define BNX2X_FREE(x) \
5758 for_each_queue(bp
, i
) {
5761 BNX2X_PCI_FREE(bnx2x_fp(bp
, i
, status_blk
),
5762 bnx2x_fp(bp
, i
, status_blk_mapping
),
5763 sizeof(struct host_status_block
) +
5764 sizeof(struct eth_tx_db_data
));
5766 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5767 BNX2X_FREE(bnx2x_fp(bp
, i
, tx_buf_ring
));
5768 BNX2X_PCI_FREE(bnx2x_fp(bp
, i
, tx_desc_ring
),
5769 bnx2x_fp(bp
, i
, tx_desc_mapping
),
5770 sizeof(struct eth_tx_bd
) * NUM_TX_BD
);
5772 BNX2X_FREE(bnx2x_fp(bp
, i
, rx_buf_ring
));
5773 BNX2X_PCI_FREE(bnx2x_fp(bp
, i
, rx_desc_ring
),
5774 bnx2x_fp(bp
, i
, rx_desc_mapping
),
5775 sizeof(struct eth_rx_bd
) * NUM_RX_BD
);
5777 BNX2X_PCI_FREE(bnx2x_fp(bp
, i
, rx_comp_ring
),
5778 bnx2x_fp(bp
, i
, rx_comp_mapping
),
5779 sizeof(struct eth_fast_path_rx_cqe
) *
5783 BNX2X_FREE(bnx2x_fp(bp
, i
, rx_page_ring
));
5784 BNX2X_PCI_FREE(bnx2x_fp(bp
, i
, rx_sge_ring
),
5785 bnx2x_fp(bp
, i
, rx_sge_mapping
),
5786 BCM_PAGE_SIZE
* NUM_RX_SGE_PAGES
);
5788 /* end of fastpath */
5790 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
5791 sizeof(struct host_def_status_block
));
5793 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
5794 sizeof(struct bnx2x_slowpath
));
5797 BNX2X_PCI_FREE(bp
->t1
, bp
->t1_mapping
, 64*1024);
5798 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, 16*1024);
5799 BNX2X_PCI_FREE(bp
->timers
, bp
->timers_mapping
, 8*1024);
5800 BNX2X_PCI_FREE(bp
->qm
, bp
->qm_mapping
, 128*1024);
5802 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
5804 #undef BNX2X_PCI_FREE
5808 static int bnx2x_alloc_mem(struct bnx2x
*bp
)
5811 #define BNX2X_PCI_ALLOC(x, y, size) \
5813 x = pci_alloc_consistent(bp->pdev, size, y); \
5815 goto alloc_mem_err; \
5816 memset(x, 0, size); \
5819 #define BNX2X_ALLOC(x, size) \
5821 x = vmalloc(size); \
5823 goto alloc_mem_err; \
5824 memset(x, 0, size); \
5830 for_each_queue(bp
, i
) {
5831 bnx2x_fp(bp
, i
, bp
) = bp
;
5834 BNX2X_PCI_ALLOC(bnx2x_fp(bp
, i
, status_blk
),
5835 &bnx2x_fp(bp
, i
, status_blk_mapping
),
5836 sizeof(struct host_status_block
) +
5837 sizeof(struct eth_tx_db_data
));
5839 bnx2x_fp(bp
, i
, hw_tx_prods
) =
5840 (void *)(bnx2x_fp(bp
, i
, status_blk
) + 1);
5842 bnx2x_fp(bp
, i
, tx_prods_mapping
) =
5843 bnx2x_fp(bp
, i
, status_blk_mapping
) +
5844 sizeof(struct host_status_block
);
5846 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5847 BNX2X_ALLOC(bnx2x_fp(bp
, i
, tx_buf_ring
),
5848 sizeof(struct sw_tx_bd
) * NUM_TX_BD
);
5849 BNX2X_PCI_ALLOC(bnx2x_fp(bp
, i
, tx_desc_ring
),
5850 &bnx2x_fp(bp
, i
, tx_desc_mapping
),
5851 sizeof(struct eth_tx_bd
) * NUM_TX_BD
);
5853 BNX2X_ALLOC(bnx2x_fp(bp
, i
, rx_buf_ring
),
5854 sizeof(struct sw_rx_bd
) * NUM_RX_BD
);
5855 BNX2X_PCI_ALLOC(bnx2x_fp(bp
, i
, rx_desc_ring
),
5856 &bnx2x_fp(bp
, i
, rx_desc_mapping
),
5857 sizeof(struct eth_rx_bd
) * NUM_RX_BD
);
5859 BNX2X_PCI_ALLOC(bnx2x_fp(bp
, i
, rx_comp_ring
),
5860 &bnx2x_fp(bp
, i
, rx_comp_mapping
),
5861 sizeof(struct eth_fast_path_rx_cqe
) *
5865 BNX2X_ALLOC(bnx2x_fp(bp
, i
, rx_page_ring
),
5866 sizeof(struct sw_rx_page
) * NUM_RX_SGE
);
5867 BNX2X_PCI_ALLOC(bnx2x_fp(bp
, i
, rx_sge_ring
),
5868 &bnx2x_fp(bp
, i
, rx_sge_mapping
),
5869 BCM_PAGE_SIZE
* NUM_RX_SGE_PAGES
);
5871 /* end of fastpath */
5873 BNX2X_PCI_ALLOC(bp
->def_status_blk
, &bp
->def_status_blk_mapping
,
5874 sizeof(struct host_def_status_block
));
5876 BNX2X_PCI_ALLOC(bp
->slowpath
, &bp
->slowpath_mapping
,
5877 sizeof(struct bnx2x_slowpath
));
5880 BNX2X_PCI_ALLOC(bp
->t1
, &bp
->t1_mapping
, 64*1024);
5883 for (i
= 0; i
< 64*1024; i
+= 64) {
5884 *(u64
*)((char *)bp
->t1
+ i
+ 56) = 0x0UL
;
5885 *(u64
*)((char *)bp
->t1
+ i
+ 3) = 0x0UL
;
5888 /* allocate searcher T2 table
5889 we allocate 1/4 of alloc num for T2
5890 (which is not entered into the ILT) */
5891 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, 16*1024);
5894 for (i
= 0; i
< 16*1024; i
+= 64)
5895 * (u64
*)((char *)bp
->t2
+ i
+ 56) = bp
->t2_mapping
+ i
+ 64;
5897 /* now fixup the last line in the block to point to the next block */
5898 *(u64
*)((char *)bp
->t2
+ 1024*16-8) = bp
->t2_mapping
;
5900 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
5901 BNX2X_PCI_ALLOC(bp
->timers
, &bp
->timers_mapping
, 8*1024);
5903 /* QM queues (128*MAX_CONN) */
5904 BNX2X_PCI_ALLOC(bp
->qm
, &bp
->qm_mapping
, 128*1024);
5907 /* Slow path ring */
5908 BNX2X_PCI_ALLOC(bp
->spq
, &bp
->spq_mapping
, BCM_PAGE_SIZE
);
5916 #undef BNX2X_PCI_ALLOC
5920 static void bnx2x_free_tx_skbs(struct bnx2x
*bp
)
5924 for_each_queue(bp
, i
) {
5925 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
5927 u16 bd_cons
= fp
->tx_bd_cons
;
5928 u16 sw_prod
= fp
->tx_pkt_prod
;
5929 u16 sw_cons
= fp
->tx_pkt_cons
;
5931 while (sw_cons
!= sw_prod
) {
5932 bd_cons
= bnx2x_free_tx_pkt(bp
, fp
, TX_BD(sw_cons
));
5938 static void bnx2x_free_rx_skbs(struct bnx2x
*bp
)
5942 for_each_queue(bp
, j
) {
5943 struct bnx2x_fastpath
*fp
= &bp
->fp
[j
];
5945 for (i
= 0; i
< NUM_RX_BD
; i
++) {
5946 struct sw_rx_bd
*rx_buf
= &fp
->rx_buf_ring
[i
];
5947 struct sk_buff
*skb
= rx_buf
->skb
;
5952 pci_unmap_single(bp
->pdev
,
5953 pci_unmap_addr(rx_buf
, mapping
),
5955 PCI_DMA_FROMDEVICE
);
5960 if (!fp
->disable_tpa
)
5961 bnx2x_free_tpa_pool(bp
, fp
, CHIP_IS_E1(bp
) ?
5962 ETH_MAX_AGGREGATION_QUEUES_E1
:
5963 ETH_MAX_AGGREGATION_QUEUES_E1H
);
5967 static void bnx2x_free_skbs(struct bnx2x
*bp
)
5969 bnx2x_free_tx_skbs(bp
);
5970 bnx2x_free_rx_skbs(bp
);
5973 static void bnx2x_free_msix_irqs(struct bnx2x
*bp
)
5977 free_irq(bp
->msix_table
[0].vector
, bp
->dev
);
5978 DP(NETIF_MSG_IFDOWN
, "released sp irq (%d)\n",
5979 bp
->msix_table
[0].vector
);
5981 for_each_queue(bp
, i
) {
5982 DP(NETIF_MSG_IFDOWN
, "about to release fp #%d->%d irq "
5983 "state %x\n", i
, bp
->msix_table
[i
+ offset
].vector
,
5984 bnx2x_fp(bp
, i
, state
));
5986 if (bnx2x_fp(bp
, i
, state
) != BNX2X_FP_STATE_CLOSED
)
5987 BNX2X_ERR("IRQ of fp #%d being freed while "
5988 "state != closed\n", i
);
5990 free_irq(bp
->msix_table
[i
+ offset
].vector
, &bp
->fp
[i
]);
5994 static void bnx2x_free_irq(struct bnx2x
*bp
)
5996 if (bp
->flags
& USING_MSIX_FLAG
) {
5997 bnx2x_free_msix_irqs(bp
);
5998 pci_disable_msix(bp
->pdev
);
5999 bp
->flags
&= ~USING_MSIX_FLAG
;
6002 free_irq(bp
->pdev
->irq
, bp
->dev
);
6005 static int bnx2x_enable_msix(struct bnx2x
*bp
)
6009 bp
->msix_table
[0].entry
= 0;
6011 DP(NETIF_MSG_IFUP
, "msix_table[0].entry = 0 (slowpath)\n");
6013 for_each_queue(bp
, i
) {
6014 int igu_vec
= offset
+ i
+ BP_L_ID(bp
);
6016 bp
->msix_table
[i
+ offset
].entry
= igu_vec
;
6017 DP(NETIF_MSG_IFUP
, "msix_table[%d].entry = %d "
6018 "(fastpath #%u)\n", i
+ offset
, igu_vec
, i
);
6021 rc
= pci_enable_msix(bp
->pdev
, &bp
->msix_table
[0],
6022 bp
->num_queues
+ offset
);
6024 DP(NETIF_MSG_IFUP
, "MSI-X is not attainable\n");
6027 bp
->flags
|= USING_MSIX_FLAG
;
6032 static int bnx2x_req_msix_irqs(struct bnx2x
*bp
)
6034 int i
, rc
, offset
= 1;
6036 rc
= request_irq(bp
->msix_table
[0].vector
, bnx2x_msix_sp_int
, 0,
6037 bp
->dev
->name
, bp
->dev
);
6039 BNX2X_ERR("request sp irq failed\n");
6043 for_each_queue(bp
, i
) {
6044 rc
= request_irq(bp
->msix_table
[i
+ offset
].vector
,
6045 bnx2x_msix_fp_int
, 0,
6046 bp
->dev
->name
, &bp
->fp
[i
]);
6048 BNX2X_ERR("request fp #%d irq failed rc -%d\n",
6050 bnx2x_free_msix_irqs(bp
);
6054 bnx2x_fp(bp
, i
, state
) = BNX2X_FP_STATE_IRQ
;
6060 static int bnx2x_req_irq(struct bnx2x
*bp
)
6064 rc
= request_irq(bp
->pdev
->irq
, bnx2x_interrupt
, IRQF_SHARED
,
6065 bp
->dev
->name
, bp
->dev
);
6067 bnx2x_fp(bp
, 0, state
) = BNX2X_FP_STATE_IRQ
;
6072 static void bnx2x_napi_enable(struct bnx2x
*bp
)
6076 for_each_queue(bp
, i
)
6077 napi_enable(&bnx2x_fp(bp
, i
, napi
));
6080 static void bnx2x_napi_disable(struct bnx2x
*bp
)
6084 for_each_queue(bp
, i
)
6085 napi_disable(&bnx2x_fp(bp
, i
, napi
));
6088 static void bnx2x_netif_start(struct bnx2x
*bp
)
6090 if (atomic_dec_and_test(&bp
->intr_sem
)) {
6091 if (netif_running(bp
->dev
)) {
6092 if (bp
->state
== BNX2X_STATE_OPEN
)
6093 netif_wake_queue(bp
->dev
);
6094 bnx2x_napi_enable(bp
);
6095 bnx2x_int_enable(bp
);
6100 static void bnx2x_netif_stop(struct bnx2x
*bp
, int disable_hw
)
6102 bnx2x_int_disable_sync(bp
, disable_hw
);
6103 if (netif_running(bp
->dev
)) {
6104 bnx2x_napi_disable(bp
);
6105 netif_tx_disable(bp
->dev
);
6106 bp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
6111 * Init service functions
6114 static void bnx2x_set_mac_addr_e1(struct bnx2x
*bp
, int set
)
6116 struct mac_configuration_cmd
*config
= bnx2x_sp(bp
, mac_config
);
6117 int port
= BP_PORT(bp
);
6120 * unicasts 0-31:port0 32-63:port1
6121 * multicast 64-127:port0 128-191:port1
6123 config
->hdr
.length_6b
= 2;
6124 config
->hdr
.offset
= port
? 31 : 0;
6125 config
->hdr
.client_id
= BP_CL_ID(bp
);
6126 config
->hdr
.reserved1
= 0;
6129 config
->config_table
[0].cam_entry
.msb_mac_addr
=
6130 swab16(*(u16
*)&bp
->dev
->dev_addr
[0]);
6131 config
->config_table
[0].cam_entry
.middle_mac_addr
=
6132 swab16(*(u16
*)&bp
->dev
->dev_addr
[2]);
6133 config
->config_table
[0].cam_entry
.lsb_mac_addr
=
6134 swab16(*(u16
*)&bp
->dev
->dev_addr
[4]);
6135 config
->config_table
[0].cam_entry
.flags
= cpu_to_le16(port
);
6137 config
->config_table
[0].target_table_entry
.flags
= 0;
6139 CAM_INVALIDATE(config
->config_table
[0]);
6140 config
->config_table
[0].target_table_entry
.client_id
= 0;
6141 config
->config_table
[0].target_table_entry
.vlan_id
= 0;
6143 DP(NETIF_MSG_IFUP
, "%s MAC (%04x:%04x:%04x)\n",
6144 (set
? "setting" : "clearing"),
6145 config
->config_table
[0].cam_entry
.msb_mac_addr
,
6146 config
->config_table
[0].cam_entry
.middle_mac_addr
,
6147 config
->config_table
[0].cam_entry
.lsb_mac_addr
);
6150 config
->config_table
[1].cam_entry
.msb_mac_addr
= 0xffff;
6151 config
->config_table
[1].cam_entry
.middle_mac_addr
= 0xffff;
6152 config
->config_table
[1].cam_entry
.lsb_mac_addr
= 0xffff;
6153 config
->config_table
[1].cam_entry
.flags
= cpu_to_le16(port
);
6155 config
->config_table
[1].target_table_entry
.flags
=
6156 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST
;
6158 CAM_INVALIDATE(config
->config_table
[1]);
6159 config
->config_table
[1].target_table_entry
.client_id
= 0;
6160 config
->config_table
[1].target_table_entry
.vlan_id
= 0;
6162 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_SET_MAC
, 0,
6163 U64_HI(bnx2x_sp_mapping(bp
, mac_config
)),
6164 U64_LO(bnx2x_sp_mapping(bp
, mac_config
)), 0);
6167 static void bnx2x_set_mac_addr_e1h(struct bnx2x
*bp
, int set
)
6169 struct mac_configuration_cmd_e1h
*config
=
6170 (struct mac_configuration_cmd_e1h
*)bnx2x_sp(bp
, mac_config
);
6172 if (set
&& (bp
->state
!= BNX2X_STATE_OPEN
)) {
6173 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
6177 /* CAM allocation for E1H
6178 * unicasts: by func number
6179 * multicast: 20+FUNC*20, 20 each
6181 config
->hdr
.length_6b
= 1;
6182 config
->hdr
.offset
= BP_FUNC(bp
);
6183 config
->hdr
.client_id
= BP_CL_ID(bp
);
6184 config
->hdr
.reserved1
= 0;
6187 config
->config_table
[0].msb_mac_addr
=
6188 swab16(*(u16
*)&bp
->dev
->dev_addr
[0]);
6189 config
->config_table
[0].middle_mac_addr
=
6190 swab16(*(u16
*)&bp
->dev
->dev_addr
[2]);
6191 config
->config_table
[0].lsb_mac_addr
=
6192 swab16(*(u16
*)&bp
->dev
->dev_addr
[4]);
6193 config
->config_table
[0].client_id
= BP_L_ID(bp
);
6194 config
->config_table
[0].vlan_id
= 0;
6195 config
->config_table
[0].e1hov_id
= cpu_to_le16(bp
->e1hov
);
6197 config
->config_table
[0].flags
= BP_PORT(bp
);
6199 config
->config_table
[0].flags
=
6200 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE
;
6202 DP(NETIF_MSG_IFUP
, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n",
6203 (set
? "setting" : "clearing"),
6204 config
->config_table
[0].msb_mac_addr
,
6205 config
->config_table
[0].middle_mac_addr
,
6206 config
->config_table
[0].lsb_mac_addr
, bp
->e1hov
, BP_L_ID(bp
));
6208 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_SET_MAC
, 0,
6209 U64_HI(bnx2x_sp_mapping(bp
, mac_config
)),
6210 U64_LO(bnx2x_sp_mapping(bp
, mac_config
)), 0);
6213 static int bnx2x_wait_ramrod(struct bnx2x
*bp
, int state
, int idx
,
6214 int *state_p
, int poll
)
6216 /* can take a while if any port is running */
6219 DP(NETIF_MSG_IFUP
, "%s for state to become %x on IDX [%d]\n",
6220 poll
? "polling" : "waiting", state
, idx
);
6225 bnx2x_rx_int(bp
->fp
, 10);
6226 /* if index is different from 0
6227 * the reply for some commands will
6228 * be on the non default queue
6231 bnx2x_rx_int(&bp
->fp
[idx
], 10);
6234 mb(); /* state is changed by bnx2x_sp_event() */
6235 if (*state_p
== state
)
6242 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6243 poll
? "polling" : "waiting", state
, idx
);
6244 #ifdef BNX2X_STOP_ON_ERROR
6251 static int bnx2x_setup_leading(struct bnx2x
*bp
)
6255 /* reset IGU state */
6256 bnx2x_ack_sb(bp
, bp
->fp
[0].sb_id
, CSTORM_ID
, 0, IGU_INT_ENABLE
, 0);
6259 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_PORT_SETUP
, 0, 0, 0, 0);
6261 /* Wait for completion */
6262 rc
= bnx2x_wait_ramrod(bp
, BNX2X_STATE_OPEN
, 0, &(bp
->state
), 0);
6267 static int bnx2x_setup_multi(struct bnx2x
*bp
, int index
)
6269 /* reset IGU state */
6270 bnx2x_ack_sb(bp
, bp
->fp
[index
].sb_id
, CSTORM_ID
, 0, IGU_INT_ENABLE
, 0);
6273 bp
->fp
[index
].state
= BNX2X_FP_STATE_OPENING
;
6274 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_CLIENT_SETUP
, index
, 0, index
, 0);
6276 /* Wait for completion */
6277 return bnx2x_wait_ramrod(bp
, BNX2X_FP_STATE_OPEN
, index
,
6278 &(bp
->fp
[index
].state
), 0);
6281 static int bnx2x_poll(struct napi_struct
*napi
, int budget
);
6282 static void bnx2x_set_rx_mode(struct net_device
*dev
);
6284 /* must be called with rtnl_lock */
6285 static int bnx2x_nic_load(struct bnx2x
*bp
, int load_mode
)
6289 #ifdef BNX2X_STOP_ON_ERROR
6290 if (unlikely(bp
->panic
))
6294 bp
->state
= BNX2X_STATE_OPENING_WAIT4_LOAD
;
6296 /* Send LOAD_REQUEST command to MCP
6297 Returns the type of LOAD command:
6298 if it is the first port to be initialized
6299 common blocks should be initialized, otherwise - not
6301 if (!BP_NOMCP(bp
)) {
6302 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
);
6304 BNX2X_ERR("MCP response failure, aborting\n");
6307 if (load_code
== FW_MSG_CODE_DRV_LOAD_REFUSED
)
6308 return -EBUSY
; /* other port in diagnostic mode */
6311 int port
= BP_PORT(bp
);
6313 DP(NETIF_MSG_IFUP
, "NO MCP load counts before us %d, %d, %d\n",
6314 load_count
[0], load_count
[1], load_count
[2]);
6316 load_count
[1 + port
]++;
6317 DP(NETIF_MSG_IFUP
, "NO MCP new load counts %d, %d, %d\n",
6318 load_count
[0], load_count
[1], load_count
[2]);
6319 if (load_count
[0] == 1)
6320 load_code
= FW_MSG_CODE_DRV_LOAD_COMMON
;
6321 else if (load_count
[1 + port
] == 1)
6322 load_code
= FW_MSG_CODE_DRV_LOAD_PORT
;
6324 load_code
= FW_MSG_CODE_DRV_LOAD_FUNCTION
;
6327 if ((load_code
== FW_MSG_CODE_DRV_LOAD_COMMON
) ||
6328 (load_code
== FW_MSG_CODE_DRV_LOAD_PORT
))
6332 DP(NETIF_MSG_LINK
, "pmf %d\n", bp
->port
.pmf
);
6334 /* if we can't use MSI-X we only need one fp,
6335 * so try to enable MSI-X with the requested number of fp's
6336 * and fallback to inta with one fp
6342 if ((use_multi
> 1) && (use_multi
<= BP_MAX_QUEUES(bp
)))
6343 /* user requested number */
6344 bp
->num_queues
= use_multi
;
6347 bp
->num_queues
= min_t(u32
, num_online_cpus(),
6352 if (bnx2x_enable_msix(bp
)) {
6353 /* failed to enable MSI-X */
6356 BNX2X_ERR("Multi requested but failed"
6357 " to enable MSI-X\n");
6361 "set number of queues to %d\n", bp
->num_queues
);
6363 if (bnx2x_alloc_mem(bp
))
6366 for_each_queue(bp
, i
)
6367 bnx2x_fp(bp
, i
, disable_tpa
) =
6368 ((bp
->flags
& TPA_ENABLE_FLAG
) == 0);
6370 if (bp
->flags
& USING_MSIX_FLAG
) {
6371 rc
= bnx2x_req_msix_irqs(bp
);
6373 pci_disable_msix(bp
->pdev
);
6378 rc
= bnx2x_req_irq(bp
);
6380 BNX2X_ERR("IRQ request failed, aborting\n");
6385 for_each_queue(bp
, i
)
6386 netif_napi_add(bp
->dev
, &bnx2x_fp(bp
, i
, napi
),
6390 rc
= bnx2x_init_hw(bp
, load_code
);
6392 BNX2X_ERR("HW init failed, aborting\n");
6393 goto load_int_disable
;
6396 /* Setup NIC internals and enable interrupts */
6397 bnx2x_nic_init(bp
, load_code
);
6399 /* Send LOAD_DONE command to MCP */
6400 if (!BP_NOMCP(bp
)) {
6401 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
);
6403 BNX2X_ERR("MCP response failure, aborting\n");
6405 goto load_rings_free
;
6409 bnx2x_stats_init(bp
);
6411 bp
->state
= BNX2X_STATE_OPENING_WAIT4_PORT
;
6413 /* Enable Rx interrupt handling before sending the ramrod
6414 as it's completed on Rx FP queue */
6415 bnx2x_napi_enable(bp
);
6417 /* Enable interrupt handling */
6418 atomic_set(&bp
->intr_sem
, 0);
6420 rc
= bnx2x_setup_leading(bp
);
6422 BNX2X_ERR("Setup leading failed!\n");
6423 goto load_netif_stop
;
6426 if (CHIP_IS_E1H(bp
))
6427 if (bp
->mf_config
& FUNC_MF_CFG_FUNC_DISABLED
) {
6428 BNX2X_ERR("!!! mf_cfg function disabled\n");
6429 bp
->state
= BNX2X_STATE_DISABLED
;
6432 if (bp
->state
== BNX2X_STATE_OPEN
)
6433 for_each_nondefault_queue(bp
, i
) {
6434 rc
= bnx2x_setup_multi(bp
, i
);
6436 goto load_netif_stop
;
6440 bnx2x_set_mac_addr_e1(bp
, 1);
6442 bnx2x_set_mac_addr_e1h(bp
, 1);
6445 bnx2x_initial_phy_init(bp
);
6447 /* Start fast path */
6448 switch (load_mode
) {
6450 /* Tx queue should be only reenabled */
6451 netif_wake_queue(bp
->dev
);
6452 bnx2x_set_rx_mode(bp
->dev
);
6456 netif_start_queue(bp
->dev
);
6457 bnx2x_set_rx_mode(bp
->dev
);
6458 if (bp
->flags
& USING_MSIX_FLAG
)
6459 printk(KERN_INFO PFX
"%s: using MSI-X\n",
6464 bnx2x_set_rx_mode(bp
->dev
);
6465 bp
->state
= BNX2X_STATE_DIAG
;
6473 bnx2x__link_status_update(bp
);
6475 /* start the timer */
6476 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6482 bnx2x_napi_disable(bp
);
6484 /* Free SKBs, SGEs, TPA pool and driver internals */
6485 bnx2x_free_skbs(bp
);
6486 for_each_queue(bp
, i
)
6487 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
6489 bnx2x_int_disable_sync(bp
, 1);
6496 /* TBD we really need to reset the chip
6497 if we want to recover from this */
6501 static int bnx2x_stop_multi(struct bnx2x
*bp
, int index
)
6505 /* halt the connection */
6506 bp
->fp
[index
].state
= BNX2X_FP_STATE_HALTING
;
6507 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_HALT
, index
, 0, index
, 0);
6509 /* Wait for completion */
6510 rc
= bnx2x_wait_ramrod(bp
, BNX2X_FP_STATE_HALTED
, index
,
6511 &(bp
->fp
[index
].state
), 1);
6512 if (rc
) /* timeout */
6515 /* delete cfc entry */
6516 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_CFC_DEL
, index
, 0, 0, 1);
6518 /* Wait for completion */
6519 rc
= bnx2x_wait_ramrod(bp
, BNX2X_FP_STATE_CLOSED
, index
,
6520 &(bp
->fp
[index
].state
), 1);
6524 static int bnx2x_stop_leading(struct bnx2x
*bp
)
6526 u16 dsb_sp_prod_idx
;
6527 /* if the other port is handling traffic,
6528 this can take a lot of time */
6534 /* Send HALT ramrod */
6535 bp
->fp
[0].state
= BNX2X_FP_STATE_HALTING
;
6536 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_HALT
, 0, 0, BP_CL_ID(bp
), 0);
6538 /* Wait for completion */
6539 rc
= bnx2x_wait_ramrod(bp
, BNX2X_FP_STATE_HALTED
, 0,
6540 &(bp
->fp
[0].state
), 1);
6541 if (rc
) /* timeout */
6544 dsb_sp_prod_idx
= *bp
->dsb_sp_prod
;
6546 /* Send PORT_DELETE ramrod */
6547 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_PORT_DEL
, 0, 0, 0, 1);
6549 /* Wait for completion to arrive on default status block
6550 we are going to reset the chip anyway
6551 so there is not much to do if this times out
6553 while (dsb_sp_prod_idx
== *bp
->dsb_sp_prod
) {
6555 DP(NETIF_MSG_IFDOWN
, "timeout waiting for port del "
6556 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
6557 *bp
->dsb_sp_prod
, dsb_sp_prod_idx
);
6558 #ifdef BNX2X_STOP_ON_ERROR
6568 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_UNLOAD
;
6569 bp
->fp
[0].state
= BNX2X_FP_STATE_CLOSED
;
6574 static void bnx2x_reset_func(struct bnx2x
*bp
)
6576 int port
= BP_PORT(bp
);
6577 int func
= BP_FUNC(bp
);
6581 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6582 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6584 REG_WR(bp
, HC_REG_CONFIG_0
+ port
*4, 0x1000);
6587 base
= FUNC_ILT_BASE(func
);
6588 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
6589 bnx2x_ilt_wr(bp
, i
, 0);
6592 static void bnx2x_reset_port(struct bnx2x
*bp
)
6594 int port
= BP_PORT(bp
);
6597 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
6599 /* Do not rcv packets to BRB */
6600 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
6601 /* Do not direct rcv packets that are not for MCP to the BRB */
6602 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
6603 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
6606 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
6609 /* Check for BRB port occupancy */
6610 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
6612 DP(NETIF_MSG_IFDOWN
,
6613 "BRB1 is not empty %d blocks are occupied\n", val
);
6615 /* TODO: Close Doorbell port? */
6618 static void bnx2x_reset_common(struct bnx2x
*bp
)
6621 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6623 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, 0x1403);
6626 static void bnx2x_reset_chip(struct bnx2x
*bp
, u32 reset_code
)
6628 DP(BNX2X_MSG_MCP
, "function %d reset_code %x\n",
6629 BP_FUNC(bp
), reset_code
);
6631 switch (reset_code
) {
6632 case FW_MSG_CODE_DRV_UNLOAD_COMMON
:
6633 bnx2x_reset_port(bp
);
6634 bnx2x_reset_func(bp
);
6635 bnx2x_reset_common(bp
);
6638 case FW_MSG_CODE_DRV_UNLOAD_PORT
:
6639 bnx2x_reset_port(bp
);
6640 bnx2x_reset_func(bp
);
6643 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION
:
6644 bnx2x_reset_func(bp
);
6648 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code
);
6653 /* must be called with rtnl_lock */
6654 static int bnx2x_nic_unload(struct bnx2x
*bp
, int unload_mode
)
6656 int port
= BP_PORT(bp
);
6660 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_HALT
;
6662 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
6663 bnx2x_set_storm_rx_mode(bp
);
6665 bnx2x_netif_stop(bp
, 1);
6666 if (!netif_running(bp
->dev
))
6667 bnx2x_napi_disable(bp
);
6668 del_timer_sync(&bp
->timer
);
6669 SHMEM_WR(bp
, func_mb
[BP_FUNC(bp
)].drv_pulse_mb
,
6670 (DRV_PULSE_ALWAYS_ALIVE
| bp
->fw_drv_pulse_wr_seq
));
6671 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
6673 /* Wait until tx fast path tasks complete */
6674 for_each_queue(bp
, i
) {
6675 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
6679 while (BNX2X_HAS_TX_WORK(fp
)) {
6681 bnx2x_tx_int(fp
, 1000);
6683 BNX2X_ERR("timeout waiting for queue[%d]\n",
6685 #ifdef BNX2X_STOP_ON_ERROR
6697 /* Give HW time to discard old tx messages */
6703 if (CHIP_IS_E1(bp
)) {
6704 struct mac_configuration_cmd
*config
=
6705 bnx2x_sp(bp
, mcast_config
);
6707 bnx2x_set_mac_addr_e1(bp
, 0);
6709 for (i
= 0; i
< config
->hdr
.length_6b
; i
++)
6710 CAM_INVALIDATE(config
->config_table
[i
]);
6712 config
->hdr
.length_6b
= i
;
6713 if (CHIP_REV_IS_SLOW(bp
))
6714 config
->hdr
.offset
= BNX2X_MAX_EMUL_MULTI
*(1 + port
);
6716 config
->hdr
.offset
= BNX2X_MAX_MULTICAST
*(1 + port
);
6717 config
->hdr
.client_id
= BP_CL_ID(bp
);
6718 config
->hdr
.reserved1
= 0;
6720 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_SET_MAC
, 0,
6721 U64_HI(bnx2x_sp_mapping(bp
, mcast_config
)),
6722 U64_LO(bnx2x_sp_mapping(bp
, mcast_config
)), 0);
6725 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
6727 bnx2x_set_mac_addr_e1h(bp
, 0);
6729 for (i
= 0; i
< MC_HASH_SIZE
; i
++)
6730 REG_WR(bp
, MC_HASH_OFFSET(bp
, i
), 0);
6733 if (unload_mode
== UNLOAD_NORMAL
)
6734 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
6736 else if (bp
->flags
& NO_WOL_FLAG
) {
6737 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
6738 if (CHIP_IS_E1H(bp
))
6739 REG_WR(bp
, MISC_REG_E1HMF_MODE
, 0);
6741 } else if (bp
->wol
) {
6742 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
6743 u8
*mac_addr
= bp
->dev
->dev_addr
;
6745 /* The mac address is written to entries 1-4 to
6746 preserve entry 0 which is used by the PMF */
6747 u8 entry
= (BP_E1HVN(bp
) + 1)*8;
6749 val
= (mac_addr
[0] << 8) | mac_addr
[1];
6750 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
6752 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
6753 (mac_addr
[4] << 8) | mac_addr
[5];
6754 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
6756 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
6759 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
6761 /* Close multi and leading connections
6762 Completions for ramrods are collected in a synchronous way */
6763 for_each_nondefault_queue(bp
, i
)
6764 if (bnx2x_stop_multi(bp
, i
))
6767 rc
= bnx2x_stop_leading(bp
);
6769 BNX2X_ERR("Stop leading failed!\n");
6770 #ifdef BNX2X_STOP_ON_ERROR
6779 reset_code
= bnx2x_fw_command(bp
, reset_code
);
6781 DP(NETIF_MSG_IFDOWN
, "NO MCP load counts %d, %d, %d\n",
6782 load_count
[0], load_count
[1], load_count
[2]);
6784 load_count
[1 + port
]--;
6785 DP(NETIF_MSG_IFDOWN
, "NO MCP new load counts %d, %d, %d\n",
6786 load_count
[0], load_count
[1], load_count
[2]);
6787 if (load_count
[0] == 0)
6788 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
6789 else if (load_count
[1 + port
] == 0)
6790 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
6792 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
6795 if ((reset_code
== FW_MSG_CODE_DRV_UNLOAD_COMMON
) ||
6796 (reset_code
== FW_MSG_CODE_DRV_UNLOAD_PORT
))
6797 bnx2x__link_reset(bp
);
6799 /* Reset the chip */
6800 bnx2x_reset_chip(bp
, reset_code
);
6802 /* Report UNLOAD_DONE to MCP */
6804 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
);
6807 /* Free SKBs, SGEs, TPA pool and driver internals */
6808 bnx2x_free_skbs(bp
);
6809 for_each_queue(bp
, i
)
6810 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
6813 bp
->state
= BNX2X_STATE_CLOSED
;
6815 netif_carrier_off(bp
->dev
);
6820 static void bnx2x_reset_task(struct work_struct
*work
)
6822 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, reset_task
);
6824 #ifdef BNX2X_STOP_ON_ERROR
6825 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
6826 " so reset not done to allow debug dump,\n"
6827 KERN_ERR
" you will need to reboot when done\n");
6833 if (!netif_running(bp
->dev
))
6834 goto reset_task_exit
;
6836 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
6837 bnx2x_nic_load(bp
, LOAD_NORMAL
);
6843 /* end of nic load/unload */
6848 * Init service functions
6851 static void __devinit
bnx2x_undi_unload(struct bnx2x
*bp
)
6855 /* Check if there is any driver already loaded */
6856 val
= REG_RD(bp
, MISC_REG_UNPREPARED
);
6858 /* Check if it is the UNDI driver
6859 * UNDI driver initializes CID offset for normal bell to 0x7
6861 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_UNDI
);
6862 val
= REG_RD(bp
, DORQ_REG_NORM_CID_OFST
);
6864 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
6865 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_UNDI
);
6868 u32 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
6870 int func
= BP_FUNC(bp
);
6874 BNX2X_DEV_INFO("UNDI is active! reset device\n");
6876 /* try unload UNDI on port 0 */
6879 (SHMEM_RD(bp
, func_mb
[bp
->func
].drv_mb_header
) &
6880 DRV_MSG_SEQ_NUMBER_MASK
);
6881 reset_code
= bnx2x_fw_command(bp
, reset_code
);
6883 /* if UNDI is loaded on the other port */
6884 if (reset_code
!= FW_MSG_CODE_DRV_UNLOAD_COMMON
) {
6886 /* send "DONE" for previous unload */
6887 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
);
6889 /* unload UNDI on port 1 */
6892 (SHMEM_RD(bp
, func_mb
[bp
->func
].drv_mb_header
) &
6893 DRV_MSG_SEQ_NUMBER_MASK
);
6894 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
6896 bnx2x_fw_command(bp
, reset_code
);
6899 REG_WR(bp
, (BP_PORT(bp
) ? HC_REG_CONFIG_1
:
6900 HC_REG_CONFIG_0
), 0x1000);
6902 /* close input traffic and wait for it */
6903 /* Do not rcv packets to BRB */
6905 (BP_PORT(bp
) ? NIG_REG_LLH1_BRB1_DRV_MASK
:
6906 NIG_REG_LLH0_BRB1_DRV_MASK
), 0x0);
6907 /* Do not direct rcv packets that are not for MCP to
6910 (BP_PORT(bp
) ? NIG_REG_LLH1_BRB1_NOT_MCP
:
6911 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
6914 (BP_PORT(bp
) ? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
6915 MISC_REG_AEU_MASK_ATTN_FUNC_0
), 0);
6918 /* save NIG port swap info */
6919 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
6920 swap_en
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
6923 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6926 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
6928 /* take the NIG out of reset and restore swap values */
6930 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
6931 MISC_REGISTERS_RESET_REG_1_RST_NIG
);
6932 REG_WR(bp
, NIG_REG_PORT_SWAP
, swap_val
);
6933 REG_WR(bp
, NIG_REG_STRAP_OVERRIDE
, swap_en
);
6935 /* send unload done to the MCP */
6936 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
);
6938 /* restore our func and fw_seq */
6941 (SHMEM_RD(bp
, func_mb
[bp
->func
].drv_mb_header
) &
6942 DRV_MSG_SEQ_NUMBER_MASK
);
6947 static void __devinit
bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
6949 u32 val
, val2
, val3
, val4
, id
;
6952 /* Get the chip revision id and number. */
6953 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6954 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
6955 id
= ((val
& 0xffff) << 16);
6956 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
6957 id
|= ((val
& 0xf) << 12);
6958 val
= REG_RD(bp
, MISC_REG_CHIP_METAL
);
6959 id
|= ((val
& 0xff) << 4);
6960 REG_RD(bp
, MISC_REG_BOND_ID
);
6962 bp
->common
.chip_id
= id
;
6963 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
6964 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
6966 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
6967 bp
->common
.flash_size
= (NVRAM_1MB_SIZE
<<
6968 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
6969 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
6970 bp
->common
.flash_size
, bp
->common
.flash_size
);
6972 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
6973 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
6974 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp
->common
.shmem_base
);
6976 if (!bp
->common
.shmem_base
||
6977 (bp
->common
.shmem_base
< 0xA0000) ||
6978 (bp
->common
.shmem_base
>= 0xC0000)) {
6979 BNX2X_DEV_INFO("MCP not active\n");
6980 bp
->flags
|= NO_MCP_FLAG
;
6984 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
6985 if ((val
& (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
6986 != (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
6987 BNX2X_ERR("BAD MCP validity signature\n");
6989 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
6990 bp
->common
.board
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.board
);
6992 BNX2X_DEV_INFO("hw_config 0x%08x board 0x%08x\n",
6993 bp
->common
.hw_config
, bp
->common
.board
);
6995 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
6996 SHARED_HW_CFG_LED_MODE_MASK
) >>
6997 SHARED_HW_CFG_LED_MODE_SHIFT
);
6999 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
7000 bp
->common
.bc_ver
= val
;
7001 BNX2X_DEV_INFO("bc_ver %X\n", val
);
7002 if (val
< BNX2X_BC_VER
) {
7003 /* for now only warn
7004 * later we might need to enforce this */
7005 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
7006 " please upgrade BC\n", BNX2X_BC_VER
, val
);
7009 if (BP_E1HVN(bp
) == 0) {
7010 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_PMC
, &pmc
);
7011 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
7013 /* no WOL capability for E1HVN != 0 */
7014 bp
->flags
|= NO_WOL_FLAG
;
7016 BNX2X_DEV_INFO("%sWoL capable\n",
7017 (bp
->flags
& NO_WOL_FLAG
) ? "Not " : "");
7019 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
7020 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
7021 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
7022 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
7024 printk(KERN_INFO PFX
"part number %X-%X-%X-%X\n",
7025 val
, val2
, val3
, val4
);
7028 static void __devinit
bnx2x_link_settings_supported(struct bnx2x
*bp
,
7031 int port
= BP_PORT(bp
);
7034 switch (switch_cfg
) {
7036 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg
);
7039 SERDES_EXT_PHY_TYPE(bp
->link_params
.ext_phy_config
);
7040 switch (ext_phy_type
) {
7041 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
7042 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7045 bp
->port
.supported
|= (SUPPORTED_10baseT_Half
|
7046 SUPPORTED_10baseT_Full
|
7047 SUPPORTED_100baseT_Half
|
7048 SUPPORTED_100baseT_Full
|
7049 SUPPORTED_1000baseT_Full
|
7050 SUPPORTED_2500baseX_Full
|
7055 SUPPORTED_Asym_Pause
);
7058 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
7059 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
7062 bp
->port
.supported
|= (SUPPORTED_10baseT_Half
|
7063 SUPPORTED_10baseT_Full
|
7064 SUPPORTED_100baseT_Half
|
7065 SUPPORTED_100baseT_Full
|
7066 SUPPORTED_1000baseT_Full
|
7071 SUPPORTED_Asym_Pause
);
7075 BNX2X_ERR("NVRAM config error. "
7076 "BAD SerDes ext_phy_config 0x%x\n",
7077 bp
->link_params
.ext_phy_config
);
7081 bp
->port
.phy_addr
= REG_RD(bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+
7083 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
7086 case SWITCH_CFG_10G
:
7087 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg
);
7090 XGXS_EXT_PHY_TYPE(bp
->link_params
.ext_phy_config
);
7091 switch (ext_phy_type
) {
7092 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
7093 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7096 bp
->port
.supported
|= (SUPPORTED_10baseT_Half
|
7097 SUPPORTED_10baseT_Full
|
7098 SUPPORTED_100baseT_Half
|
7099 SUPPORTED_100baseT_Full
|
7100 SUPPORTED_1000baseT_Full
|
7101 SUPPORTED_2500baseX_Full
|
7102 SUPPORTED_10000baseT_Full
|
7107 SUPPORTED_Asym_Pause
);
7110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
7111 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
7114 bp
->port
.supported
|= (SUPPORTED_10000baseT_Full
|
7117 SUPPORTED_Asym_Pause
);
7120 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
7121 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
7124 bp
->port
.supported
|= (SUPPORTED_10000baseT_Full
|
7125 SUPPORTED_1000baseT_Full
|
7128 SUPPORTED_Asym_Pause
);
7131 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
7132 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
7135 bp
->port
.supported
|= (SUPPORTED_10000baseT_Full
|
7136 SUPPORTED_1000baseT_Full
|
7140 SUPPORTED_Asym_Pause
);
7143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
7144 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
7147 bp
->port
.supported
|= (SUPPORTED_10000baseT_Full
|
7148 SUPPORTED_2500baseX_Full
|
7149 SUPPORTED_1000baseT_Full
|
7153 SUPPORTED_Asym_Pause
);
7156 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
7157 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7160 bp
->port
.supported
|= (SUPPORTED_10000baseT_Full
|
7164 SUPPORTED_Asym_Pause
);
7167 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
7168 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7169 bp
->link_params
.ext_phy_config
);
7173 BNX2X_ERR("NVRAM config error. "
7174 "BAD XGXS ext_phy_config 0x%x\n",
7175 bp
->link_params
.ext_phy_config
);
7179 bp
->port
.phy_addr
= REG_RD(bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+
7181 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
7186 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7187 bp
->port
.link_config
);
7190 bp
->link_params
.phy_addr
= bp
->port
.phy_addr
;
7192 /* mask what we support according to speed_cap_mask */
7193 if (!(bp
->link_params
.speed_cap_mask
&
7194 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
7195 bp
->port
.supported
&= ~SUPPORTED_10baseT_Half
;
7197 if (!(bp
->link_params
.speed_cap_mask
&
7198 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
7199 bp
->port
.supported
&= ~SUPPORTED_10baseT_Full
;
7201 if (!(bp
->link_params
.speed_cap_mask
&
7202 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
7203 bp
->port
.supported
&= ~SUPPORTED_100baseT_Half
;
7205 if (!(bp
->link_params
.speed_cap_mask
&
7206 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
7207 bp
->port
.supported
&= ~SUPPORTED_100baseT_Full
;
7209 if (!(bp
->link_params
.speed_cap_mask
&
7210 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
7211 bp
->port
.supported
&= ~(SUPPORTED_1000baseT_Half
|
7212 SUPPORTED_1000baseT_Full
);
7214 if (!(bp
->link_params
.speed_cap_mask
&
7215 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
7216 bp
->port
.supported
&= ~SUPPORTED_2500baseX_Full
;
7218 if (!(bp
->link_params
.speed_cap_mask
&
7219 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
7220 bp
->port
.supported
&= ~SUPPORTED_10000baseT_Full
;
7222 BNX2X_DEV_INFO("supported 0x%x\n", bp
->port
.supported
);
7225 static void __devinit
bnx2x_link_settings_requested(struct bnx2x
*bp
)
7227 bp
->link_params
.req_duplex
= DUPLEX_FULL
;
7229 switch (bp
->port
.link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
7230 case PORT_FEATURE_LINK_SPEED_AUTO
:
7231 if (bp
->port
.supported
& SUPPORTED_Autoneg
) {
7232 bp
->link_params
.req_line_speed
= SPEED_AUTO_NEG
;
7233 bp
->port
.advertising
= bp
->port
.supported
;
7236 XGXS_EXT_PHY_TYPE(bp
->link_params
.ext_phy_config
);
7238 if ((ext_phy_type
==
7239 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) ||
7241 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
)) {
7242 /* force 10G, no AN */
7243 bp
->link_params
.req_line_speed
= SPEED_10000
;
7244 bp
->port
.advertising
=
7245 (ADVERTISED_10000baseT_Full
|
7249 BNX2X_ERR("NVRAM config error. "
7250 "Invalid link_config 0x%x"
7251 " Autoneg not supported\n",
7252 bp
->port
.link_config
);
7257 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
7258 if (bp
->port
.supported
& SUPPORTED_10baseT_Full
) {
7259 bp
->link_params
.req_line_speed
= SPEED_10
;
7260 bp
->port
.advertising
= (ADVERTISED_10baseT_Full
|
7263 BNX2X_ERR("NVRAM config error. "
7264 "Invalid link_config 0x%x"
7265 " speed_cap_mask 0x%x\n",
7266 bp
->port
.link_config
,
7267 bp
->link_params
.speed_cap_mask
);
7272 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
7273 if (bp
->port
.supported
& SUPPORTED_10baseT_Half
) {
7274 bp
->link_params
.req_line_speed
= SPEED_10
;
7275 bp
->link_params
.req_duplex
= DUPLEX_HALF
;
7276 bp
->port
.advertising
= (ADVERTISED_10baseT_Half
|
7279 BNX2X_ERR("NVRAM config error. "
7280 "Invalid link_config 0x%x"
7281 " speed_cap_mask 0x%x\n",
7282 bp
->port
.link_config
,
7283 bp
->link_params
.speed_cap_mask
);
7288 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
7289 if (bp
->port
.supported
& SUPPORTED_100baseT_Full
) {
7290 bp
->link_params
.req_line_speed
= SPEED_100
;
7291 bp
->port
.advertising
= (ADVERTISED_100baseT_Full
|
7294 BNX2X_ERR("NVRAM config error. "
7295 "Invalid link_config 0x%x"
7296 " speed_cap_mask 0x%x\n",
7297 bp
->port
.link_config
,
7298 bp
->link_params
.speed_cap_mask
);
7303 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
7304 if (bp
->port
.supported
& SUPPORTED_100baseT_Half
) {
7305 bp
->link_params
.req_line_speed
= SPEED_100
;
7306 bp
->link_params
.req_duplex
= DUPLEX_HALF
;
7307 bp
->port
.advertising
= (ADVERTISED_100baseT_Half
|
7310 BNX2X_ERR("NVRAM config error. "
7311 "Invalid link_config 0x%x"
7312 " speed_cap_mask 0x%x\n",
7313 bp
->port
.link_config
,
7314 bp
->link_params
.speed_cap_mask
);
7319 case PORT_FEATURE_LINK_SPEED_1G
:
7320 if (bp
->port
.supported
& SUPPORTED_1000baseT_Full
) {
7321 bp
->link_params
.req_line_speed
= SPEED_1000
;
7322 bp
->port
.advertising
= (ADVERTISED_1000baseT_Full
|
7325 BNX2X_ERR("NVRAM config error. "
7326 "Invalid link_config 0x%x"
7327 " speed_cap_mask 0x%x\n",
7328 bp
->port
.link_config
,
7329 bp
->link_params
.speed_cap_mask
);
7334 case PORT_FEATURE_LINK_SPEED_2_5G
:
7335 if (bp
->port
.supported
& SUPPORTED_2500baseX_Full
) {
7336 bp
->link_params
.req_line_speed
= SPEED_2500
;
7337 bp
->port
.advertising
= (ADVERTISED_2500baseX_Full
|
7340 BNX2X_ERR("NVRAM config error. "
7341 "Invalid link_config 0x%x"
7342 " speed_cap_mask 0x%x\n",
7343 bp
->port
.link_config
,
7344 bp
->link_params
.speed_cap_mask
);
7349 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
7350 case PORT_FEATURE_LINK_SPEED_10G_KX4
:
7351 case PORT_FEATURE_LINK_SPEED_10G_KR
:
7352 if (bp
->port
.supported
& SUPPORTED_10000baseT_Full
) {
7353 bp
->link_params
.req_line_speed
= SPEED_10000
;
7354 bp
->port
.advertising
= (ADVERTISED_10000baseT_Full
|
7357 BNX2X_ERR("NVRAM config error. "
7358 "Invalid link_config 0x%x"
7359 " speed_cap_mask 0x%x\n",
7360 bp
->port
.link_config
,
7361 bp
->link_params
.speed_cap_mask
);
7367 BNX2X_ERR("NVRAM config error. "
7368 "BAD link speed link_config 0x%x\n",
7369 bp
->port
.link_config
);
7370 bp
->link_params
.req_line_speed
= SPEED_AUTO_NEG
;
7371 bp
->port
.advertising
= bp
->port
.supported
;
7375 bp
->link_params
.req_flow_ctrl
= (bp
->port
.link_config
&
7376 PORT_FEATURE_FLOW_CONTROL_MASK
);
7377 if ((bp
->link_params
.req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
) &&
7378 !(bp
->port
.supported
& SUPPORTED_Autoneg
))
7379 bp
->link_params
.req_flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
7381 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
7382 " advertising 0x%x\n",
7383 bp
->link_params
.req_line_speed
,
7384 bp
->link_params
.req_duplex
,
7385 bp
->link_params
.req_flow_ctrl
, bp
->port
.advertising
);
7388 static void __devinit
bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
7390 int port
= BP_PORT(bp
);
7393 bp
->link_params
.bp
= bp
;
7394 bp
->link_params
.port
= port
;
7396 bp
->link_params
.serdes_config
=
7397 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].serdes_config
);
7398 bp
->link_params
.lane_config
=
7399 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
7400 bp
->link_params
.ext_phy_config
=
7402 dev_info
.port_hw_config
[port
].external_phy_config
);
7403 bp
->link_params
.speed_cap_mask
=
7405 dev_info
.port_hw_config
[port
].speed_capability_mask
);
7407 bp
->port
.link_config
=
7408 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
7410 BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
7411 KERN_INFO
" ext_phy_config 0x%08x speed_cap_mask 0x%08x"
7412 " link_config 0x%08x\n",
7413 bp
->link_params
.serdes_config
,
7414 bp
->link_params
.lane_config
,
7415 bp
->link_params
.ext_phy_config
,
7416 bp
->link_params
.speed_cap_mask
, bp
->port
.link_config
);
7418 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
&
7419 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
7420 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
7422 bnx2x_link_settings_requested(bp
);
7424 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
7425 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
7426 bp
->dev
->dev_addr
[0] = (u8
)(val2
>> 8 & 0xff);
7427 bp
->dev
->dev_addr
[1] = (u8
)(val2
& 0xff);
7428 bp
->dev
->dev_addr
[2] = (u8
)(val
>> 24 & 0xff);
7429 bp
->dev
->dev_addr
[3] = (u8
)(val
>> 16 & 0xff);
7430 bp
->dev
->dev_addr
[4] = (u8
)(val
>> 8 & 0xff);
7431 bp
->dev
->dev_addr
[5] = (u8
)(val
& 0xff);
7432 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
7433 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
7436 static int __devinit
bnx2x_get_hwinfo(struct bnx2x
*bp
)
7438 int func
= BP_FUNC(bp
);
7442 bnx2x_get_common_hwinfo(bp
);
7446 if (CHIP_IS_E1H(bp
)) {
7448 SHMEM_RD(bp
, mf_cfg
.func_mf_config
[func
].config
);
7450 val
= (SHMEM_RD(bp
, mf_cfg
.func_mf_config
[func
].e1hov_tag
) &
7451 FUNC_MF_CFG_E1HOV_TAG_MASK
);
7452 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
7456 BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d "
7458 func
, bp
->e1hov
, bp
->e1hov
);
7460 BNX2X_DEV_INFO("Single function mode\n");
7462 BNX2X_ERR("!!! No valid E1HOV for func %d,"
7463 " aborting\n", func
);
7469 if (!BP_NOMCP(bp
)) {
7470 bnx2x_get_port_hwinfo(bp
);
7472 bp
->fw_seq
= (SHMEM_RD(bp
, func_mb
[func
].drv_mb_header
) &
7473 DRV_MSG_SEQ_NUMBER_MASK
);
7474 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
7478 val2
= SHMEM_RD(bp
, mf_cfg
.func_mf_config
[func
].mac_upper
);
7479 val
= SHMEM_RD(bp
, mf_cfg
.func_mf_config
[func
].mac_lower
);
7480 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
7481 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
)) {
7482 bp
->dev
->dev_addr
[0] = (u8
)(val2
>> 8 & 0xff);
7483 bp
->dev
->dev_addr
[1] = (u8
)(val2
& 0xff);
7484 bp
->dev
->dev_addr
[2] = (u8
)(val
>> 24 & 0xff);
7485 bp
->dev
->dev_addr
[3] = (u8
)(val
>> 16 & 0xff);
7486 bp
->dev
->dev_addr
[4] = (u8
)(val
>> 8 & 0xff);
7487 bp
->dev
->dev_addr
[5] = (u8
)(val
& 0xff);
7488 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
,
7490 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
,
7498 /* only supposed to happen on emulation/FPGA */
7499 BNX2X_ERR("warning random MAC workaround active\n");
7500 random_ether_addr(bp
->dev
->dev_addr
);
7501 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
7507 static int __devinit
bnx2x_init_bp(struct bnx2x
*bp
)
7509 int func
= BP_FUNC(bp
);
7512 /* Disable interrupt handling until HW is initialized */
7513 atomic_set(&bp
->intr_sem
, 1);
7515 mutex_init(&bp
->port
.phy_mutex
);
7517 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
7518 INIT_WORK(&bp
->reset_task
, bnx2x_reset_task
);
7520 rc
= bnx2x_get_hwinfo(bp
);
7522 /* need to reset chip if undi was active */
7524 bnx2x_undi_unload(bp
);
7526 if (CHIP_REV_IS_FPGA(bp
))
7527 printk(KERN_ERR PFX
"FPGA detected\n");
7529 if (BP_NOMCP(bp
) && (func
== 0))
7531 "MCP disabled, must load devices in order!\n");
7535 bp
->flags
&= ~TPA_ENABLE_FLAG
;
7536 bp
->dev
->features
&= ~NETIF_F_LRO
;
7538 bp
->flags
|= TPA_ENABLE_FLAG
;
7539 bp
->dev
->features
|= NETIF_F_LRO
;
7543 bp
->tx_ring_size
= MAX_TX_AVAIL
;
7544 bp
->rx_ring_size
= MAX_RX_AVAIL
;
7552 bp
->timer_interval
= (CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
);
7553 bp
->current_interval
= (poll
? poll
: bp
->timer_interval
);
7555 init_timer(&bp
->timer
);
7556 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
7557 bp
->timer
.data
= (unsigned long) bp
;
7558 bp
->timer
.function
= bnx2x_timer
;
7564 * ethtool service functions
7567 /* All ethtool functions called with rtnl_lock */
7569 static int bnx2x_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
7571 struct bnx2x
*bp
= netdev_priv(dev
);
7573 cmd
->supported
= bp
->port
.supported
;
7574 cmd
->advertising
= bp
->port
.advertising
;
7576 if (netif_carrier_ok(dev
)) {
7577 cmd
->speed
= bp
->link_vars
.line_speed
;
7578 cmd
->duplex
= bp
->link_vars
.duplex
;
7580 cmd
->speed
= bp
->link_params
.req_line_speed
;
7581 cmd
->duplex
= bp
->link_params
.req_duplex
;
7586 vn_max_rate
= ((bp
->mf_config
& FUNC_MF_CFG_MAX_BW_MASK
) >>
7587 FUNC_MF_CFG_MAX_BW_SHIFT
) * 100;
7588 if (vn_max_rate
< cmd
->speed
)
7589 cmd
->speed
= vn_max_rate
;
7592 if (bp
->link_params
.switch_cfg
== SWITCH_CFG_10G
) {
7594 XGXS_EXT_PHY_TYPE(bp
->link_params
.ext_phy_config
);
7596 switch (ext_phy_type
) {
7597 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
7598 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
7599 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
7600 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
7601 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
7602 cmd
->port
= PORT_FIBRE
;
7605 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
7606 cmd
->port
= PORT_TP
;
7609 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
7610 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7611 bp
->link_params
.ext_phy_config
);
7615 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
7616 bp
->link_params
.ext_phy_config
);
7620 cmd
->port
= PORT_TP
;
7622 cmd
->phy_address
= bp
->port
.phy_addr
;
7623 cmd
->transceiver
= XCVR_INTERNAL
;
7625 if (bp
->link_params
.req_line_speed
== SPEED_AUTO_NEG
)
7626 cmd
->autoneg
= AUTONEG_ENABLE
;
7628 cmd
->autoneg
= AUTONEG_DISABLE
;
7633 DP(NETIF_MSG_LINK
, "ethtool_cmd: cmd %d\n"
7634 DP_LEVEL
" supported 0x%x advertising 0x%x speed %d\n"
7635 DP_LEVEL
" duplex %d port %d phy_address %d transceiver %d\n"
7636 DP_LEVEL
" autoneg %d maxtxpkt %d maxrxpkt %d\n",
7637 cmd
->cmd
, cmd
->supported
, cmd
->advertising
, cmd
->speed
,
7638 cmd
->duplex
, cmd
->port
, cmd
->phy_address
, cmd
->transceiver
,
7639 cmd
->autoneg
, cmd
->maxtxpkt
, cmd
->maxrxpkt
);
7644 static int bnx2x_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
7646 struct bnx2x
*bp
= netdev_priv(dev
);
7652 DP(NETIF_MSG_LINK
, "ethtool_cmd: cmd %d\n"
7653 DP_LEVEL
" supported 0x%x advertising 0x%x speed %d\n"
7654 DP_LEVEL
" duplex %d port %d phy_address %d transceiver %d\n"
7655 DP_LEVEL
" autoneg %d maxtxpkt %d maxrxpkt %d\n",
7656 cmd
->cmd
, cmd
->supported
, cmd
->advertising
, cmd
->speed
,
7657 cmd
->duplex
, cmd
->port
, cmd
->phy_address
, cmd
->transceiver
,
7658 cmd
->autoneg
, cmd
->maxtxpkt
, cmd
->maxrxpkt
);
7660 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
7661 if (!(bp
->port
.supported
& SUPPORTED_Autoneg
)) {
7662 DP(NETIF_MSG_LINK
, "Autoneg not supported\n");
7666 /* advertise the requested speed and duplex if supported */
7667 cmd
->advertising
&= bp
->port
.supported
;
7669 bp
->link_params
.req_line_speed
= SPEED_AUTO_NEG
;
7670 bp
->link_params
.req_duplex
= DUPLEX_FULL
;
7671 bp
->port
.advertising
|= (ADVERTISED_Autoneg
|
7674 } else { /* forced speed */
7675 /* advertise the requested speed and duplex if supported */
7676 switch (cmd
->speed
) {
7678 if (cmd
->duplex
== DUPLEX_FULL
) {
7679 if (!(bp
->port
.supported
&
7680 SUPPORTED_10baseT_Full
)) {
7682 "10M full not supported\n");
7686 advertising
= (ADVERTISED_10baseT_Full
|
7689 if (!(bp
->port
.supported
&
7690 SUPPORTED_10baseT_Half
)) {
7692 "10M half not supported\n");
7696 advertising
= (ADVERTISED_10baseT_Half
|
7702 if (cmd
->duplex
== DUPLEX_FULL
) {
7703 if (!(bp
->port
.supported
&
7704 SUPPORTED_100baseT_Full
)) {
7706 "100M full not supported\n");
7710 advertising
= (ADVERTISED_100baseT_Full
|
7713 if (!(bp
->port
.supported
&
7714 SUPPORTED_100baseT_Half
)) {
7716 "100M half not supported\n");
7720 advertising
= (ADVERTISED_100baseT_Half
|
7726 if (cmd
->duplex
!= DUPLEX_FULL
) {
7727 DP(NETIF_MSG_LINK
, "1G half not supported\n");
7731 if (!(bp
->port
.supported
& SUPPORTED_1000baseT_Full
)) {
7732 DP(NETIF_MSG_LINK
, "1G full not supported\n");
7736 advertising
= (ADVERTISED_1000baseT_Full
|
7741 if (cmd
->duplex
!= DUPLEX_FULL
) {
7743 "2.5G half not supported\n");
7747 if (!(bp
->port
.supported
& SUPPORTED_2500baseX_Full
)) {
7749 "2.5G full not supported\n");
7753 advertising
= (ADVERTISED_2500baseX_Full
|
7758 if (cmd
->duplex
!= DUPLEX_FULL
) {
7759 DP(NETIF_MSG_LINK
, "10G half not supported\n");
7763 if (!(bp
->port
.supported
& SUPPORTED_10000baseT_Full
)) {
7764 DP(NETIF_MSG_LINK
, "10G full not supported\n");
7768 advertising
= (ADVERTISED_10000baseT_Full
|
7773 DP(NETIF_MSG_LINK
, "Unsupported speed\n");
7777 bp
->link_params
.req_line_speed
= cmd
->speed
;
7778 bp
->link_params
.req_duplex
= cmd
->duplex
;
7779 bp
->port
.advertising
= advertising
;
7782 DP(NETIF_MSG_LINK
, "req_line_speed %d\n"
7783 DP_LEVEL
" req_duplex %d advertising 0x%x\n",
7784 bp
->link_params
.req_line_speed
, bp
->link_params
.req_duplex
,
7785 bp
->port
.advertising
);
7787 if (netif_running(dev
)) {
7788 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
7795 #define PHY_FW_VER_LEN 10
7797 static void bnx2x_get_drvinfo(struct net_device
*dev
,
7798 struct ethtool_drvinfo
*info
)
7800 struct bnx2x
*bp
= netdev_priv(dev
);
7801 u8 phy_fw_ver
[PHY_FW_VER_LEN
];
7803 strcpy(info
->driver
, DRV_MODULE_NAME
);
7804 strcpy(info
->version
, DRV_MODULE_VERSION
);
7806 phy_fw_ver
[0] = '\0';
7808 bnx2x_acquire_phy_lock(bp
);
7809 bnx2x_get_ext_phy_fw_version(&bp
->link_params
,
7810 (bp
->state
!= BNX2X_STATE_CLOSED
),
7811 phy_fw_ver
, PHY_FW_VER_LEN
);
7812 bnx2x_release_phy_lock(bp
);
7815 snprintf(info
->fw_version
, 32, "BC:%d.%d.%d%s%s",
7816 (bp
->common
.bc_ver
& 0xff0000) >> 16,
7817 (bp
->common
.bc_ver
& 0xff00) >> 8,
7818 (bp
->common
.bc_ver
& 0xff),
7819 ((phy_fw_ver
[0] != '\0') ? " PHY:" : ""), phy_fw_ver
);
7820 strcpy(info
->bus_info
, pci_name(bp
->pdev
));
7821 info
->n_stats
= BNX2X_NUM_STATS
;
7822 info
->testinfo_len
= BNX2X_NUM_TESTS
;
7823 info
->eedump_len
= bp
->common
.flash_size
;
7824 info
->regdump_len
= 0;
7827 static void bnx2x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
7829 struct bnx2x
*bp
= netdev_priv(dev
);
7831 if (bp
->flags
& NO_WOL_FLAG
) {
7835 wol
->supported
= WAKE_MAGIC
;
7837 wol
->wolopts
= WAKE_MAGIC
;
7841 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
7844 static int bnx2x_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
7846 struct bnx2x
*bp
= netdev_priv(dev
);
7848 if (wol
->wolopts
& ~WAKE_MAGIC
)
7851 if (wol
->wolopts
& WAKE_MAGIC
) {
7852 if (bp
->flags
& NO_WOL_FLAG
)
7862 static u32
bnx2x_get_msglevel(struct net_device
*dev
)
7864 struct bnx2x
*bp
= netdev_priv(dev
);
7866 return bp
->msglevel
;
7869 static void bnx2x_set_msglevel(struct net_device
*dev
, u32 level
)
7871 struct bnx2x
*bp
= netdev_priv(dev
);
7873 if (capable(CAP_NET_ADMIN
))
7874 bp
->msglevel
= level
;
7877 static int bnx2x_nway_reset(struct net_device
*dev
)
7879 struct bnx2x
*bp
= netdev_priv(dev
);
7884 if (netif_running(dev
)) {
7885 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
7892 static int bnx2x_get_eeprom_len(struct net_device
*dev
)
7894 struct bnx2x
*bp
= netdev_priv(dev
);
7896 return bp
->common
.flash_size
;
7899 static int bnx2x_acquire_nvram_lock(struct bnx2x
*bp
)
7901 int port
= BP_PORT(bp
);
7905 /* adjust timeout for emulation/FPGA */
7906 count
= NVRAM_TIMEOUT_COUNT
;
7907 if (CHIP_REV_IS_SLOW(bp
))
7910 /* request access to nvram interface */
7911 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
7912 (MCPR_NVM_SW_ARB_ARB_REQ_SET1
<< port
));
7914 for (i
= 0; i
< count
*10; i
++) {
7915 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_SW_ARB
);
7916 if (val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
))
7922 if (!(val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
))) {
7923 DP(BNX2X_MSG_NVM
, "cannot get access to nvram interface\n");
7930 static int bnx2x_release_nvram_lock(struct bnx2x
*bp
)
7932 int port
= BP_PORT(bp
);
7936 /* adjust timeout for emulation/FPGA */
7937 count
= NVRAM_TIMEOUT_COUNT
;
7938 if (CHIP_REV_IS_SLOW(bp
))
7941 /* relinquish nvram interface */
7942 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
7943 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< port
));
7945 for (i
= 0; i
< count
*10; i
++) {
7946 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_SW_ARB
);
7947 if (!(val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
)))
7953 if (val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
)) {
7954 DP(BNX2X_MSG_NVM
, "cannot free access to nvram interface\n");
7961 static void bnx2x_enable_nvram_access(struct bnx2x
*bp
)
7965 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
);
7967 /* enable both bits, even on read */
7968 REG_WR(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
,
7969 (val
| MCPR_NVM_ACCESS_ENABLE_EN
|
7970 MCPR_NVM_ACCESS_ENABLE_WR_EN
));
7973 static void bnx2x_disable_nvram_access(struct bnx2x
*bp
)
7977 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
);
7979 /* disable both bits, even after read */
7980 REG_WR(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
,
7981 (val
& ~(MCPR_NVM_ACCESS_ENABLE_EN
|
7982 MCPR_NVM_ACCESS_ENABLE_WR_EN
)));
7985 static int bnx2x_nvram_read_dword(struct bnx2x
*bp
, u32 offset
, u32
*ret_val
,
7991 /* build the command word */
7992 cmd_flags
|= MCPR_NVM_COMMAND_DOIT
;
7994 /* need to clear DONE bit separately */
7995 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, MCPR_NVM_COMMAND_DONE
);
7997 /* address of the NVRAM to read from */
7998 REG_WR(bp
, MCP_REG_MCPR_NVM_ADDR
,
7999 (offset
& MCPR_NVM_ADDR_NVM_ADDR_VALUE
));
8001 /* issue a read command */
8002 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, cmd_flags
);
8004 /* adjust timeout for emulation/FPGA */
8005 count
= NVRAM_TIMEOUT_COUNT
;
8006 if (CHIP_REV_IS_SLOW(bp
))
8009 /* wait for completion */
8012 for (i
= 0; i
< count
; i
++) {
8014 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_COMMAND
);
8016 if (val
& MCPR_NVM_COMMAND_DONE
) {
8017 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_READ
);
8018 /* we read nvram data in cpu order
8019 * but ethtool sees it as an array of bytes
8020 * converting to big-endian will do the work */
8021 val
= cpu_to_be32(val
);
8031 static int bnx2x_nvram_read(struct bnx2x
*bp
, u32 offset
, u8
*ret_buf
,
8038 if ((offset
& 0x03) || (buf_size
& 0x03) || (buf_size
== 0)) {
8040 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8045 if (offset
+ buf_size
> bp
->common
.flash_size
) {
8046 DP(BNX2X_MSG_NVM
, "Invalid parameter: offset (0x%x) +"
8047 " buf_size (0x%x) > flash_size (0x%x)\n",
8048 offset
, buf_size
, bp
->common
.flash_size
);
8052 /* request access to nvram interface */
8053 rc
= bnx2x_acquire_nvram_lock(bp
);
8057 /* enable access to nvram interface */
8058 bnx2x_enable_nvram_access(bp
);
8060 /* read the first word(s) */
8061 cmd_flags
= MCPR_NVM_COMMAND_FIRST
;
8062 while ((buf_size
> sizeof(u32
)) && (rc
== 0)) {
8063 rc
= bnx2x_nvram_read_dword(bp
, offset
, &val
, cmd_flags
);
8064 memcpy(ret_buf
, &val
, 4);
8066 /* advance to the next dword */
8067 offset
+= sizeof(u32
);
8068 ret_buf
+= sizeof(u32
);
8069 buf_size
-= sizeof(u32
);
8074 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
8075 rc
= bnx2x_nvram_read_dword(bp
, offset
, &val
, cmd_flags
);
8076 memcpy(ret_buf
, &val
, 4);
8079 /* disable access to nvram interface */
8080 bnx2x_disable_nvram_access(bp
);
8081 bnx2x_release_nvram_lock(bp
);
8086 static int bnx2x_get_eeprom(struct net_device
*dev
,
8087 struct ethtool_eeprom
*eeprom
, u8
*eebuf
)
8089 struct bnx2x
*bp
= netdev_priv(dev
);
8092 DP(BNX2X_MSG_NVM
, "ethtool_eeprom: cmd %d\n"
8093 DP_LEVEL
" magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8094 eeprom
->cmd
, eeprom
->magic
, eeprom
->offset
, eeprom
->offset
,
8095 eeprom
->len
, eeprom
->len
);
8097 /* parameters already validated in ethtool_get_eeprom */
8099 rc
= bnx2x_nvram_read(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
8104 static int bnx2x_nvram_write_dword(struct bnx2x
*bp
, u32 offset
, u32 val
,
8109 /* build the command word */
8110 cmd_flags
|= MCPR_NVM_COMMAND_DOIT
| MCPR_NVM_COMMAND_WR
;
8112 /* need to clear DONE bit separately */
8113 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, MCPR_NVM_COMMAND_DONE
);
8115 /* write the data */
8116 REG_WR(bp
, MCP_REG_MCPR_NVM_WRITE
, val
);
8118 /* address of the NVRAM to write to */
8119 REG_WR(bp
, MCP_REG_MCPR_NVM_ADDR
,
8120 (offset
& MCPR_NVM_ADDR_NVM_ADDR_VALUE
));
8122 /* issue the write command */
8123 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, cmd_flags
);
8125 /* adjust timeout for emulation/FPGA */
8126 count
= NVRAM_TIMEOUT_COUNT
;
8127 if (CHIP_REV_IS_SLOW(bp
))
8130 /* wait for completion */
8132 for (i
= 0; i
< count
; i
++) {
8134 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_COMMAND
);
8135 if (val
& MCPR_NVM_COMMAND_DONE
) {
8144 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
8146 static int bnx2x_nvram_write1(struct bnx2x
*bp
, u32 offset
, u8
*data_buf
,
8154 if (offset
+ buf_size
> bp
->common
.flash_size
) {
8155 DP(BNX2X_MSG_NVM
, "Invalid parameter: offset (0x%x) +"
8156 " buf_size (0x%x) > flash_size (0x%x)\n",
8157 offset
, buf_size
, bp
->common
.flash_size
);
8161 /* request access to nvram interface */
8162 rc
= bnx2x_acquire_nvram_lock(bp
);
8166 /* enable access to nvram interface */
8167 bnx2x_enable_nvram_access(bp
);
8169 cmd_flags
= (MCPR_NVM_COMMAND_FIRST
| MCPR_NVM_COMMAND_LAST
);
8170 align_offset
= (offset
& ~0x03);
8171 rc
= bnx2x_nvram_read_dword(bp
, align_offset
, &val
, cmd_flags
);
8174 val
&= ~(0xff << BYTE_OFFSET(offset
));
8175 val
|= (*data_buf
<< BYTE_OFFSET(offset
));
8177 /* nvram data is returned as an array of bytes
8178 * convert it back to cpu order */
8179 val
= be32_to_cpu(val
);
8181 rc
= bnx2x_nvram_write_dword(bp
, align_offset
, val
,
8185 /* disable access to nvram interface */
8186 bnx2x_disable_nvram_access(bp
);
8187 bnx2x_release_nvram_lock(bp
);
8192 static int bnx2x_nvram_write(struct bnx2x
*bp
, u32 offset
, u8
*data_buf
,
8200 if (buf_size
== 1) /* ethtool */
8201 return bnx2x_nvram_write1(bp
, offset
, data_buf
, buf_size
);
8203 if ((offset
& 0x03) || (buf_size
& 0x03) || (buf_size
== 0)) {
8205 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8210 if (offset
+ buf_size
> bp
->common
.flash_size
) {
8211 DP(BNX2X_MSG_NVM
, "Invalid parameter: offset (0x%x) +"
8212 " buf_size (0x%x) > flash_size (0x%x)\n",
8213 offset
, buf_size
, bp
->common
.flash_size
);
8217 /* request access to nvram interface */
8218 rc
= bnx2x_acquire_nvram_lock(bp
);
8222 /* enable access to nvram interface */
8223 bnx2x_enable_nvram_access(bp
);
8226 cmd_flags
= MCPR_NVM_COMMAND_FIRST
;
8227 while ((written_so_far
< buf_size
) && (rc
== 0)) {
8228 if (written_so_far
== (buf_size
- sizeof(u32
)))
8229 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
8230 else if (((offset
+ 4) % NVRAM_PAGE_SIZE
) == 0)
8231 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
8232 else if ((offset
% NVRAM_PAGE_SIZE
) == 0)
8233 cmd_flags
|= MCPR_NVM_COMMAND_FIRST
;
8235 memcpy(&val
, data_buf
, 4);
8237 rc
= bnx2x_nvram_write_dword(bp
, offset
, val
, cmd_flags
);
8239 /* advance to the next dword */
8240 offset
+= sizeof(u32
);
8241 data_buf
+= sizeof(u32
);
8242 written_so_far
+= sizeof(u32
);
8246 /* disable access to nvram interface */
8247 bnx2x_disable_nvram_access(bp
);
8248 bnx2x_release_nvram_lock(bp
);
8253 static int bnx2x_set_eeprom(struct net_device
*dev
,
8254 struct ethtool_eeprom
*eeprom
, u8
*eebuf
)
8256 struct bnx2x
*bp
= netdev_priv(dev
);
8259 if (!netif_running(dev
))
8262 DP(BNX2X_MSG_NVM
, "ethtool_eeprom: cmd %d\n"
8263 DP_LEVEL
" magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8264 eeprom
->cmd
, eeprom
->magic
, eeprom
->offset
, eeprom
->offset
,
8265 eeprom
->len
, eeprom
->len
);
8267 /* parameters already validated in ethtool_set_eeprom */
8269 /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
8270 if (eeprom
->magic
== 0x00504859)
8273 bnx2x_acquire_phy_lock(bp
);
8274 rc
= bnx2x_flash_download(bp
, BP_PORT(bp
),
8275 bp
->link_params
.ext_phy_config
,
8276 (bp
->state
!= BNX2X_STATE_CLOSED
),
8277 eebuf
, eeprom
->len
);
8278 if ((bp
->state
== BNX2X_STATE_OPEN
) ||
8279 (bp
->state
== BNX2X_STATE_DISABLED
)) {
8280 rc
|= bnx2x_link_reset(&bp
->link_params
,
8282 rc
|= bnx2x_phy_init(&bp
->link_params
,
8285 bnx2x_release_phy_lock(bp
);
8287 } else /* Only the PMF can access the PHY */
8290 rc
= bnx2x_nvram_write(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
8295 static int bnx2x_get_coalesce(struct net_device
*dev
,
8296 struct ethtool_coalesce
*coal
)
8298 struct bnx2x
*bp
= netdev_priv(dev
);
8300 memset(coal
, 0, sizeof(struct ethtool_coalesce
));
8302 coal
->rx_coalesce_usecs
= bp
->rx_ticks
;
8303 coal
->tx_coalesce_usecs
= bp
->tx_ticks
;
8308 static int bnx2x_set_coalesce(struct net_device
*dev
,
8309 struct ethtool_coalesce
*coal
)
8311 struct bnx2x
*bp
= netdev_priv(dev
);
8313 bp
->rx_ticks
= (u16
) coal
->rx_coalesce_usecs
;
8314 if (bp
->rx_ticks
> 3000)
8315 bp
->rx_ticks
= 3000;
8317 bp
->tx_ticks
= (u16
) coal
->tx_coalesce_usecs
;
8318 if (bp
->tx_ticks
> 0x3000)
8319 bp
->tx_ticks
= 0x3000;
8321 if (netif_running(dev
))
8322 bnx2x_update_coalesce(bp
);
8327 static void bnx2x_get_ringparam(struct net_device
*dev
,
8328 struct ethtool_ringparam
*ering
)
8330 struct bnx2x
*bp
= netdev_priv(dev
);
8332 ering
->rx_max_pending
= MAX_RX_AVAIL
;
8333 ering
->rx_mini_max_pending
= 0;
8334 ering
->rx_jumbo_max_pending
= 0;
8336 ering
->rx_pending
= bp
->rx_ring_size
;
8337 ering
->rx_mini_pending
= 0;
8338 ering
->rx_jumbo_pending
= 0;
8340 ering
->tx_max_pending
= MAX_TX_AVAIL
;
8341 ering
->tx_pending
= bp
->tx_ring_size
;
8344 static int bnx2x_set_ringparam(struct net_device
*dev
,
8345 struct ethtool_ringparam
*ering
)
8347 struct bnx2x
*bp
= netdev_priv(dev
);
8350 if ((ering
->rx_pending
> MAX_RX_AVAIL
) ||
8351 (ering
->tx_pending
> MAX_TX_AVAIL
) ||
8352 (ering
->tx_pending
<= MAX_SKB_FRAGS
+ 4))
8355 bp
->rx_ring_size
= ering
->rx_pending
;
8356 bp
->tx_ring_size
= ering
->tx_pending
;
8358 if (netif_running(dev
)) {
8359 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8360 rc
= bnx2x_nic_load(bp
, LOAD_NORMAL
);
8366 static void bnx2x_get_pauseparam(struct net_device
*dev
,
8367 struct ethtool_pauseparam
*epause
)
8369 struct bnx2x
*bp
= netdev_priv(dev
);
8371 epause
->autoneg
= (bp
->link_params
.req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
) &&
8372 (bp
->link_params
.req_line_speed
== SPEED_AUTO_NEG
);
8374 epause
->rx_pause
= ((bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_RX
) ==
8375 BNX2X_FLOW_CTRL_RX
);
8376 epause
->tx_pause
= ((bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
) ==
8377 BNX2X_FLOW_CTRL_TX
);
8379 DP(NETIF_MSG_LINK
, "ethtool_pauseparam: cmd %d\n"
8380 DP_LEVEL
" autoneg %d rx_pause %d tx_pause %d\n",
8381 epause
->cmd
, epause
->autoneg
, epause
->rx_pause
, epause
->tx_pause
);
8384 static int bnx2x_set_pauseparam(struct net_device
*dev
,
8385 struct ethtool_pauseparam
*epause
)
8387 struct bnx2x
*bp
= netdev_priv(dev
);
8392 DP(NETIF_MSG_LINK
, "ethtool_pauseparam: cmd %d\n"
8393 DP_LEVEL
" autoneg %d rx_pause %d tx_pause %d\n",
8394 epause
->cmd
, epause
->autoneg
, epause
->rx_pause
, epause
->tx_pause
);
8396 bp
->link_params
.req_flow_ctrl
= BNX2X_FLOW_CTRL_AUTO
;
8398 if (epause
->rx_pause
)
8399 bp
->link_params
.req_flow_ctrl
|= BNX2X_FLOW_CTRL_RX
;
8401 if (epause
->tx_pause
)
8402 bp
->link_params
.req_flow_ctrl
|= BNX2X_FLOW_CTRL_TX
;
8404 if (bp
->link_params
.req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
)
8405 bp
->link_params
.req_flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
8407 if (epause
->autoneg
) {
8408 if (!(bp
->port
.supported
& SUPPORTED_Autoneg
)) {
8409 DP(NETIF_MSG_LINK
, "autoneg not supported\n");
8413 if (bp
->link_params
.req_line_speed
== SPEED_AUTO_NEG
)
8414 bp
->link_params
.req_flow_ctrl
= BNX2X_FLOW_CTRL_AUTO
;
8418 "req_flow_ctrl 0x%x\n", bp
->link_params
.req_flow_ctrl
);
8420 if (netif_running(dev
)) {
8421 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
8428 static int bnx2x_set_flags(struct net_device
*dev
, u32 data
)
8430 struct bnx2x
*bp
= netdev_priv(dev
);
8434 /* TPA requires Rx CSUM offloading */
8435 if ((data
& ETH_FLAG_LRO
) && bp
->rx_csum
) {
8436 if (!(dev
->features
& NETIF_F_LRO
)) {
8437 dev
->features
|= NETIF_F_LRO
;
8438 bp
->flags
|= TPA_ENABLE_FLAG
;
8442 } else if (dev
->features
& NETIF_F_LRO
) {
8443 dev
->features
&= ~NETIF_F_LRO
;
8444 bp
->flags
&= ~TPA_ENABLE_FLAG
;
8448 if (changed
&& netif_running(dev
)) {
8449 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8450 rc
= bnx2x_nic_load(bp
, LOAD_NORMAL
);
8456 static u32
bnx2x_get_rx_csum(struct net_device
*dev
)
8458 struct bnx2x
*bp
= netdev_priv(dev
);
8463 static int bnx2x_set_rx_csum(struct net_device
*dev
, u32 data
)
8465 struct bnx2x
*bp
= netdev_priv(dev
);
8470 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
8471 TPA'ed packets will be discarded due to wrong TCP CSUM */
8473 u32 flags
= ethtool_op_get_flags(dev
);
8475 rc
= bnx2x_set_flags(dev
, (flags
& ~ETH_FLAG_LRO
));
8481 static int bnx2x_set_tso(struct net_device
*dev
, u32 data
)
8484 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO_ECN
);
8485 dev
->features
|= NETIF_F_TSO6
;
8487 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO_ECN
);
8488 dev
->features
&= ~NETIF_F_TSO6
;
8494 static const struct {
8495 char string
[ETH_GSTRING_LEN
];
8496 } bnx2x_tests_str_arr
[BNX2X_NUM_TESTS
] = {
8497 { "register_test (offline)" },
8498 { "memory_test (offline)" },
8499 { "loopback_test (offline)" },
8500 { "nvram_test (online)" },
8501 { "interrupt_test (online)" },
8502 { "link_test (online)" },
8503 { "idle check (online)" },
8504 { "MC errors (online)" }
8507 static int bnx2x_self_test_count(struct net_device
*dev
)
8509 return BNX2X_NUM_TESTS
;
8512 static int bnx2x_test_registers(struct bnx2x
*bp
)
8514 int idx
, i
, rc
= -ENODEV
;
8516 int port
= BP_PORT(bp
);
8517 static const struct {
8522 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0
, 4, 0x000003ff },
8523 { DORQ_REG_DB_ADDR0
, 4, 0xffffffff },
8524 { HC_REG_AGG_INT_0
, 4, 0x000003ff },
8525 { PBF_REG_MAC_IF0_ENABLE
, 4, 0x00000001 },
8526 { PBF_REG_P0_INIT_CRD
, 4, 0x000007ff },
8527 { PRS_REG_CID_PORT_0
, 4, 0x00ffffff },
8528 { PXP2_REG_PSWRQ_CDU0_L2P
, 4, 0x000fffff },
8529 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR
, 8, 0x0003ffff },
8530 { PXP2_REG_PSWRQ_TM0_L2P
, 4, 0x000fffff },
8531 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR
, 8, 0x0003ffff },
8532 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P
, 4, 0x000fffff },
8533 { QM_REG_CONNNUM_0
, 4, 0x000fffff },
8534 { TM_REG_LIN0_MAX_ACTIVE_CID
, 4, 0x0003ffff },
8535 { SRC_REG_KEYRSS0_0
, 40, 0xffffffff },
8536 { SRC_REG_KEYRSS0_7
, 40, 0xffffffff },
8537 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00
, 4, 0x00000001 },
8538 { XCM_REG_WU_DA_CNT_CMD00
, 4, 0x00000003 },
8539 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0
, 4, 0x000000ff },
8540 { NIG_REG_EGRESS_MNG0_FIFO
, 20, 0xffffffff },
8541 { NIG_REG_LLH0_T_BIT
, 4, 0x00000001 },
8542 /* 20 */ { NIG_REG_EMAC0_IN_EN
, 4, 0x00000001 },
8543 { NIG_REG_BMAC0_IN_EN
, 4, 0x00000001 },
8544 { NIG_REG_XCM0_OUT_EN
, 4, 0x00000001 },
8545 { NIG_REG_BRB0_OUT_EN
, 4, 0x00000001 },
8546 { NIG_REG_LLH0_XCM_MASK
, 4, 0x00000007 },
8547 { NIG_REG_LLH0_ACPI_PAT_6_LEN
, 68, 0x000000ff },
8548 { NIG_REG_LLH0_ACPI_PAT_0_CRC
, 68, 0xffffffff },
8549 { NIG_REG_LLH0_DEST_MAC_0_0
, 160, 0xffffffff },
8550 { NIG_REG_LLH0_DEST_IP_0_1
, 160, 0xffffffff },
8551 { NIG_REG_LLH0_IPV4_IPV6_0
, 160, 0x00000001 },
8552 /* 30 */ { NIG_REG_LLH0_DEST_UDP_0
, 160, 0x0000ffff },
8553 { NIG_REG_LLH0_DEST_TCP_0
, 160, 0x0000ffff },
8554 { NIG_REG_LLH0_VLAN_ID_0
, 160, 0x00000fff },
8555 { NIG_REG_XGXS_SERDES0_MODE_SEL
, 4, 0x00000001 },
8556 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
, 4, 0x00000001 },
8557 { NIG_REG_STATUS_INTERRUPT_PORT0
, 4, 0x07ffffff },
8558 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST
, 24, 0x00000001 },
8559 { NIG_REG_SERDES0_CTRL_PHY_ADDR
, 16, 0x0000001f },
8561 { 0xffffffff, 0, 0x00000000 }
8564 if (!netif_running(bp
->dev
))
8567 /* Repeat the test twice:
8568 First by writing 0x00000000, second by writing 0xffffffff */
8569 for (idx
= 0; idx
< 2; idx
++) {
8576 wr_val
= 0xffffffff;
8580 for (i
= 0; reg_tbl
[i
].offset0
!= 0xffffffff; i
++) {
8581 u32 offset
, mask
, save_val
, val
;
8583 offset
= reg_tbl
[i
].offset0
+ port
*reg_tbl
[i
].offset1
;
8584 mask
= reg_tbl
[i
].mask
;
8586 save_val
= REG_RD(bp
, offset
);
8588 REG_WR(bp
, offset
, wr_val
);
8589 val
= REG_RD(bp
, offset
);
8591 /* Restore the original register's value */
8592 REG_WR(bp
, offset
, save_val
);
8594 /* verify that value is as expected value */
8595 if ((val
& mask
) != (wr_val
& mask
))
8606 static int bnx2x_test_memory(struct bnx2x
*bp
)
8608 int i
, j
, rc
= -ENODEV
;
8610 static const struct {
8614 { CCM_REG_XX_DESCR_TABLE
, CCM_REG_XX_DESCR_TABLE_SIZE
},
8615 { CFC_REG_ACTIVITY_COUNTER
, CFC_REG_ACTIVITY_COUNTER_SIZE
},
8616 { CFC_REG_LINK_LIST
, CFC_REG_LINK_LIST_SIZE
},
8617 { DMAE_REG_CMD_MEM
, DMAE_REG_CMD_MEM_SIZE
},
8618 { TCM_REG_XX_DESCR_TABLE
, TCM_REG_XX_DESCR_TABLE_SIZE
},
8619 { UCM_REG_XX_DESCR_TABLE
, UCM_REG_XX_DESCR_TABLE_SIZE
},
8620 { XCM_REG_XX_DESCR_TABLE
, XCM_REG_XX_DESCR_TABLE_SIZE
},
8624 static const struct {
8630 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS
, 0x3ffc0, 0 },
8631 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS
, 0x2, 0x2 },
8632 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS
, 0, 0 },
8633 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS
, 0x3ffc0, 0 },
8634 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS
, 0x3ffc0, 0 },
8635 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS
, 0x3ffc1, 0 },
8637 { NULL
, 0xffffffff, 0, 0 }
8640 if (!netif_running(bp
->dev
))
8643 /* Go through all the memories */
8644 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++)
8645 for (j
= 0; j
< mem_tbl
[i
].size
; j
++)
8646 REG_RD(bp
, mem_tbl
[i
].offset
+ j
*4);
8648 /* Check the parity status */
8649 for (i
= 0; prty_tbl
[i
].offset
!= 0xffffffff; i
++) {
8650 val
= REG_RD(bp
, prty_tbl
[i
].offset
);
8651 if ((CHIP_IS_E1(bp
) && (val
& ~(prty_tbl
[i
].e1_mask
))) ||
8652 (CHIP_IS_E1H(bp
) && (val
& ~(prty_tbl
[i
].e1h_mask
)))) {
8654 "%s is 0x%x\n", prty_tbl
[i
].name
, val
);
8665 static void bnx2x_wait_for_link(struct bnx2x
*bp
, u8 link_up
)
8670 while (bnx2x_link_test(bp
) && cnt
--)
8674 static int bnx2x_run_loopback(struct bnx2x
*bp
, int loopback_mode
, u8 link_up
)
8676 unsigned int pkt_size
, num_pkts
, i
;
8677 struct sk_buff
*skb
;
8678 unsigned char *packet
;
8679 struct bnx2x_fastpath
*fp
= &bp
->fp
[0];
8680 u16 tx_start_idx
, tx_idx
;
8681 u16 rx_start_idx
, rx_idx
;
8683 struct sw_tx_bd
*tx_buf
;
8684 struct eth_tx_bd
*tx_bd
;
8686 union eth_rx_cqe
*cqe
;
8688 struct sw_rx_bd
*rx_buf
;
8692 if (loopback_mode
== BNX2X_MAC_LOOPBACK
) {
8693 bp
->link_params
.loopback_mode
= LOOPBACK_BMAC
;
8694 bnx2x_acquire_phy_lock(bp
);
8695 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
8696 bnx2x_release_phy_lock(bp
);
8698 } else if (loopback_mode
== BNX2X_PHY_LOOPBACK
) {
8699 bp
->link_params
.loopback_mode
= LOOPBACK_XGXS_10
;
8700 bnx2x_acquire_phy_lock(bp
);
8701 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
8702 bnx2x_release_phy_lock(bp
);
8703 /* wait until link state is restored */
8704 bnx2x_wait_for_link(bp
, link_up
);
8710 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buf_size
);
8713 goto test_loopback_exit
;
8715 packet
= skb_put(skb
, pkt_size
);
8716 memcpy(packet
, bp
->dev
->dev_addr
, ETH_ALEN
);
8717 memset(packet
+ ETH_ALEN
, 0, (ETH_HLEN
- ETH_ALEN
));
8718 for (i
= ETH_HLEN
; i
< pkt_size
; i
++)
8719 packet
[i
] = (unsigned char) (i
& 0xff);
8722 tx_start_idx
= le16_to_cpu(*fp
->tx_cons_sb
);
8723 rx_start_idx
= le16_to_cpu(*fp
->rx_cons_sb
);
8725 pkt_prod
= fp
->tx_pkt_prod
++;
8726 tx_buf
= &fp
->tx_buf_ring
[TX_BD(pkt_prod
)];
8727 tx_buf
->first_bd
= fp
->tx_bd_prod
;
8730 tx_bd
= &fp
->tx_desc_ring
[TX_BD(fp
->tx_bd_prod
)];
8731 mapping
= pci_map_single(bp
->pdev
, skb
->data
,
8732 skb_headlen(skb
), PCI_DMA_TODEVICE
);
8733 tx_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
8734 tx_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
8735 tx_bd
->nbd
= cpu_to_le16(1);
8736 tx_bd
->nbytes
= cpu_to_le16(skb_headlen(skb
));
8737 tx_bd
->vlan
= cpu_to_le16(pkt_prod
);
8738 tx_bd
->bd_flags
.as_bitfield
= (ETH_TX_BD_FLAGS_START_BD
|
8739 ETH_TX_BD_FLAGS_END_BD
);
8740 tx_bd
->general_data
= ((UNICAST_ADDRESS
<<
8741 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT
) | 1);
8745 fp
->hw_tx_prods
->bds_prod
=
8746 cpu_to_le16(le16_to_cpu(fp
->hw_tx_prods
->bds_prod
) + 1);
8747 mb(); /* FW restriction: must not reorder writing nbd and packets */
8748 fp
->hw_tx_prods
->packets_prod
=
8749 cpu_to_le32(le32_to_cpu(fp
->hw_tx_prods
->packets_prod
) + 1);
8750 DOORBELL(bp
, FP_IDX(fp
), 0);
8756 bp
->dev
->trans_start
= jiffies
;
8760 tx_idx
= le16_to_cpu(*fp
->tx_cons_sb
);
8761 if (tx_idx
!= tx_start_idx
+ num_pkts
)
8762 goto test_loopback_exit
;
8764 rx_idx
= le16_to_cpu(*fp
->rx_cons_sb
);
8765 if (rx_idx
!= rx_start_idx
+ num_pkts
)
8766 goto test_loopback_exit
;
8768 cqe
= &fp
->rx_comp_ring
[RCQ_BD(fp
->rx_comp_cons
)];
8769 cqe_fp_flags
= cqe
->fast_path_cqe
.type_error_flags
;
8770 if (CQE_TYPE(cqe_fp_flags
) || (cqe_fp_flags
& ETH_RX_ERROR_FALGS
))
8771 goto test_loopback_rx_exit
;
8773 len
= le16_to_cpu(cqe
->fast_path_cqe
.pkt_len
);
8774 if (len
!= pkt_size
)
8775 goto test_loopback_rx_exit
;
8777 rx_buf
= &fp
->rx_buf_ring
[RX_BD(fp
->rx_bd_cons
)];
8779 skb_reserve(skb
, cqe
->fast_path_cqe
.placement_offset
);
8780 for (i
= ETH_HLEN
; i
< pkt_size
; i
++)
8781 if (*(skb
->data
+ i
) != (unsigned char) (i
& 0xff))
8782 goto test_loopback_rx_exit
;
8786 test_loopback_rx_exit
:
8788 fp
->rx_bd_cons
= NEXT_RX_IDX(fp
->rx_bd_cons
);
8789 fp
->rx_bd_prod
= NEXT_RX_IDX(fp
->rx_bd_prod
);
8790 fp
->rx_comp_cons
= NEXT_RCQ_IDX(fp
->rx_comp_cons
);
8791 fp
->rx_comp_prod
= NEXT_RCQ_IDX(fp
->rx_comp_prod
);
8793 /* Update producers */
8794 bnx2x_update_rx_prod(bp
, fp
, fp
->rx_bd_prod
, fp
->rx_comp_prod
,
8798 bp
->link_params
.loopback_mode
= LOOPBACK_NONE
;
8803 static int bnx2x_test_loopback(struct bnx2x
*bp
, u8 link_up
)
8807 if (!netif_running(bp
->dev
))
8808 return BNX2X_LOOPBACK_FAILED
;
8810 bnx2x_netif_stop(bp
, 1);
8812 if (bnx2x_run_loopback(bp
, BNX2X_MAC_LOOPBACK
, link_up
)) {
8813 DP(NETIF_MSG_PROBE
, "MAC loopback failed\n");
8814 rc
|= BNX2X_MAC_LOOPBACK_FAILED
;
8817 if (bnx2x_run_loopback(bp
, BNX2X_PHY_LOOPBACK
, link_up
)) {
8818 DP(NETIF_MSG_PROBE
, "PHY loopback failed\n");
8819 rc
|= BNX2X_PHY_LOOPBACK_FAILED
;
8822 bnx2x_netif_start(bp
);
8827 #define CRC32_RESIDUAL 0xdebb20e3
8829 static int bnx2x_test_nvram(struct bnx2x
*bp
)
8831 static const struct {
8835 { 0, 0x14 }, /* bootstrap */
8836 { 0x14, 0xec }, /* dir */
8837 { 0x100, 0x350 }, /* manuf_info */
8838 { 0x450, 0xf0 }, /* feature_info */
8839 { 0x640, 0x64 }, /* upgrade_key_info */
8841 { 0x708, 0x70 }, /* manuf_key_info */
8846 u8
*data
= (u8
*)buf
;
8850 rc
= bnx2x_nvram_read(bp
, 0, data
, 4);
8852 DP(NETIF_MSG_PROBE
, "magic value read (rc -%d)\n", -rc
);
8853 goto test_nvram_exit
;
8856 magic
= be32_to_cpu(buf
[0]);
8857 if (magic
!= 0x669955aa) {
8858 DP(NETIF_MSG_PROBE
, "magic value (0x%08x)\n", magic
);
8860 goto test_nvram_exit
;
8863 for (i
= 0; nvram_tbl
[i
].size
; i
++) {
8865 rc
= bnx2x_nvram_read(bp
, nvram_tbl
[i
].offset
, data
,
8869 "nvram_tbl[%d] read data (rc -%d)\n", i
, -rc
);
8870 goto test_nvram_exit
;
8873 csum
= ether_crc_le(nvram_tbl
[i
].size
, data
);
8874 if (csum
!= CRC32_RESIDUAL
) {
8876 "nvram_tbl[%d] csum value (0x%08x)\n", i
, csum
);
8878 goto test_nvram_exit
;
8886 static int bnx2x_test_intr(struct bnx2x
*bp
)
8888 struct mac_configuration_cmd
*config
= bnx2x_sp(bp
, mac_config
);
8891 if (!netif_running(bp
->dev
))
8894 config
->hdr
.length_6b
= 0;
8895 config
->hdr
.offset
= 0;
8896 config
->hdr
.client_id
= BP_CL_ID(bp
);
8897 config
->hdr
.reserved1
= 0;
8899 rc
= bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_SET_MAC
, 0,
8900 U64_HI(bnx2x_sp_mapping(bp
, mac_config
)),
8901 U64_LO(bnx2x_sp_mapping(bp
, mac_config
)), 0);
8903 bp
->set_mac_pending
++;
8904 for (i
= 0; i
< 10; i
++) {
8905 if (!bp
->set_mac_pending
)
8907 msleep_interruptible(10);
8916 static void bnx2x_self_test(struct net_device
*dev
,
8917 struct ethtool_test
*etest
, u64
*buf
)
8919 struct bnx2x
*bp
= netdev_priv(dev
);
8921 memset(buf
, 0, sizeof(u64
) * BNX2X_NUM_TESTS
);
8923 if (!netif_running(dev
))
8926 /* offline tests are not supported in MF mode */
8928 etest
->flags
&= ~ETH_TEST_FL_OFFLINE
;
8930 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
8933 link_up
= bp
->link_vars
.link_up
;
8934 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8935 bnx2x_nic_load(bp
, LOAD_DIAG
);
8936 /* wait until link state is restored */
8937 bnx2x_wait_for_link(bp
, link_up
);
8939 if (bnx2x_test_registers(bp
) != 0) {
8941 etest
->flags
|= ETH_TEST_FL_FAILED
;
8943 if (bnx2x_test_memory(bp
) != 0) {
8945 etest
->flags
|= ETH_TEST_FL_FAILED
;
8947 buf
[2] = bnx2x_test_loopback(bp
, link_up
);
8949 etest
->flags
|= ETH_TEST_FL_FAILED
;
8951 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8952 bnx2x_nic_load(bp
, LOAD_NORMAL
);
8953 /* wait until link state is restored */
8954 bnx2x_wait_for_link(bp
, link_up
);
8956 if (bnx2x_test_nvram(bp
) != 0) {
8958 etest
->flags
|= ETH_TEST_FL_FAILED
;
8960 if (bnx2x_test_intr(bp
) != 0) {
8962 etest
->flags
|= ETH_TEST_FL_FAILED
;
8965 if (bnx2x_link_test(bp
) != 0) {
8967 etest
->flags
|= ETH_TEST_FL_FAILED
;
8969 buf
[7] = bnx2x_mc_assert(bp
);
8971 etest
->flags
|= ETH_TEST_FL_FAILED
;
8973 #ifdef BNX2X_EXTRA_DEBUG
8974 bnx2x_panic_dump(bp
);
8978 static const struct {
8982 #define STATS_FLAGS_PORT 1
8983 #define STATS_FLAGS_FUNC 2
8984 u8 string
[ETH_GSTRING_LEN
];
8985 } bnx2x_stats_arr
[BNX2X_NUM_STATS
] = {
8986 /* 1 */ { STATS_OFFSET32(valid_bytes_received_hi
),
8987 8, STATS_FLAGS_FUNC
, "rx_bytes" },
8988 { STATS_OFFSET32(error_bytes_received_hi
),
8989 8, STATS_FLAGS_FUNC
, "rx_error_bytes" },
8990 { STATS_OFFSET32(total_bytes_transmitted_hi
),
8991 8, STATS_FLAGS_FUNC
, "tx_bytes" },
8992 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi
),
8993 8, STATS_FLAGS_PORT
, "tx_error_bytes" },
8994 { STATS_OFFSET32(total_unicast_packets_received_hi
),
8995 8, STATS_FLAGS_FUNC
, "rx_ucast_packets" },
8996 { STATS_OFFSET32(total_multicast_packets_received_hi
),
8997 8, STATS_FLAGS_FUNC
, "rx_mcast_packets" },
8998 { STATS_OFFSET32(total_broadcast_packets_received_hi
),
8999 8, STATS_FLAGS_FUNC
, "rx_bcast_packets" },
9000 { STATS_OFFSET32(total_unicast_packets_transmitted_hi
),
9001 8, STATS_FLAGS_FUNC
, "tx_packets" },
9002 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi
),
9003 8, STATS_FLAGS_PORT
, "tx_mac_errors" },
9004 /* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi
),
9005 8, STATS_FLAGS_PORT
, "tx_carrier_errors" },
9006 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi
),
9007 8, STATS_FLAGS_PORT
, "rx_crc_errors" },
9008 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi
),
9009 8, STATS_FLAGS_PORT
, "rx_align_errors" },
9010 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi
),
9011 8, STATS_FLAGS_PORT
, "tx_single_collisions" },
9012 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi
),
9013 8, STATS_FLAGS_PORT
, "tx_multi_collisions" },
9014 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi
),
9015 8, STATS_FLAGS_PORT
, "tx_deferred" },
9016 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi
),
9017 8, STATS_FLAGS_PORT
, "tx_excess_collisions" },
9018 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi
),
9019 8, STATS_FLAGS_PORT
, "tx_late_collisions" },
9020 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi
),
9021 8, STATS_FLAGS_PORT
, "tx_total_collisions" },
9022 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi
),
9023 8, STATS_FLAGS_PORT
, "rx_fragments" },
9024 /* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi
),
9025 8, STATS_FLAGS_PORT
, "rx_jabbers" },
9026 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi
),
9027 8, STATS_FLAGS_PORT
, "rx_undersize_packets" },
9028 { STATS_OFFSET32(jabber_packets_received
),
9029 4, STATS_FLAGS_FUNC
, "rx_oversize_packets" },
9030 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi
),
9031 8, STATS_FLAGS_PORT
, "tx_64_byte_packets" },
9032 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi
),
9033 8, STATS_FLAGS_PORT
, "tx_65_to_127_byte_packets" },
9034 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi
),
9035 8, STATS_FLAGS_PORT
, "tx_128_to_255_byte_packets" },
9036 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi
),
9037 8, STATS_FLAGS_PORT
, "tx_256_to_511_byte_packets" },
9038 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi
),
9039 8, STATS_FLAGS_PORT
, "tx_512_to_1023_byte_packets" },
9040 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi
),
9041 8, STATS_FLAGS_PORT
, "tx_1024_to_1522_byte_packets" },
9042 { STATS_OFFSET32(etherstatspktsover1522octets_hi
),
9043 8, STATS_FLAGS_PORT
, "tx_1523_to_9022_byte_packets" },
9044 /* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi
),
9045 8, STATS_FLAGS_PORT
, "rx_xon_frames" },
9046 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi
),
9047 8, STATS_FLAGS_PORT
, "rx_xoff_frames" },
9048 { STATS_OFFSET32(tx_stat_outxonsent_hi
),
9049 8, STATS_FLAGS_PORT
, "tx_xon_frames" },
9050 { STATS_OFFSET32(tx_stat_outxoffsent_hi
),
9051 8, STATS_FLAGS_PORT
, "tx_xoff_frames" },
9052 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi
),
9053 8, STATS_FLAGS_PORT
, "rx_mac_ctrl_frames" },
9054 { STATS_OFFSET32(mac_filter_discard
),
9055 4, STATS_FLAGS_PORT
, "rx_filtered_packets" },
9056 { STATS_OFFSET32(no_buff_discard
),
9057 4, STATS_FLAGS_FUNC
, "rx_discards" },
9058 { STATS_OFFSET32(xxoverflow_discard
),
9059 4, STATS_FLAGS_PORT
, "rx_fw_discards" },
9060 { STATS_OFFSET32(brb_drop_hi
),
9061 8, STATS_FLAGS_PORT
, "brb_discard" },
9062 { STATS_OFFSET32(brb_truncate_hi
),
9063 8, STATS_FLAGS_PORT
, "brb_truncate" },
9064 /* 40 */{ STATS_OFFSET32(rx_err_discard_pkt
),
9065 4, STATS_FLAGS_FUNC
, "rx_phy_ip_err_discards"},
9066 { STATS_OFFSET32(rx_skb_alloc_failed
),
9067 4, STATS_FLAGS_FUNC
, "rx_skb_alloc_discard" },
9068 /* 42 */{ STATS_OFFSET32(hw_csum_err
),
9069 4, STATS_FLAGS_FUNC
, "rx_csum_offload_errors" }
9072 #define IS_NOT_E1HMF_STAT(bp, i) \
9073 (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT))
9075 static void bnx2x_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
9077 struct bnx2x
*bp
= netdev_priv(dev
);
9080 switch (stringset
) {
9082 for (i
= 0, j
= 0; i
< BNX2X_NUM_STATS
; i
++) {
9083 if (IS_NOT_E1HMF_STAT(bp
, i
))
9085 strcpy(buf
+ j
*ETH_GSTRING_LEN
,
9086 bnx2x_stats_arr
[i
].string
);
9092 memcpy(buf
, bnx2x_tests_str_arr
, sizeof(bnx2x_tests_str_arr
));
9097 static int bnx2x_get_stats_count(struct net_device
*dev
)
9099 struct bnx2x
*bp
= netdev_priv(dev
);
9100 int i
, num_stats
= 0;
9102 for (i
= 0; i
< BNX2X_NUM_STATS
; i
++) {
9103 if (IS_NOT_E1HMF_STAT(bp
, i
))
9110 static void bnx2x_get_ethtool_stats(struct net_device
*dev
,
9111 struct ethtool_stats
*stats
, u64
*buf
)
9113 struct bnx2x
*bp
= netdev_priv(dev
);
9114 u32
*hw_stats
= (u32
*)&bp
->eth_stats
;
9117 for (i
= 0, j
= 0; i
< BNX2X_NUM_STATS
; i
++) {
9118 if (IS_NOT_E1HMF_STAT(bp
, i
))
9121 if (bnx2x_stats_arr
[i
].size
== 0) {
9122 /* skip this counter */
9127 if (bnx2x_stats_arr
[i
].size
== 4) {
9128 /* 4-byte counter */
9129 buf
[j
] = (u64
) *(hw_stats
+ bnx2x_stats_arr
[i
].offset
);
9133 /* 8-byte counter */
9134 buf
[j
] = HILO_U64(*(hw_stats
+ bnx2x_stats_arr
[i
].offset
),
9135 *(hw_stats
+ bnx2x_stats_arr
[i
].offset
+ 1));
9140 static int bnx2x_phys_id(struct net_device
*dev
, u32 data
)
9142 struct bnx2x
*bp
= netdev_priv(dev
);
9143 int port
= BP_PORT(bp
);
9146 if (!netif_running(dev
))
9155 for (i
= 0; i
< (data
* 2); i
++) {
9157 bnx2x_set_led(bp
, port
, LED_MODE_OPER
, SPEED_1000
,
9158 bp
->link_params
.hw_led_mode
,
9159 bp
->link_params
.chip_id
);
9161 bnx2x_set_led(bp
, port
, LED_MODE_OFF
, 0,
9162 bp
->link_params
.hw_led_mode
,
9163 bp
->link_params
.chip_id
);
9165 msleep_interruptible(500);
9166 if (signal_pending(current
))
9170 if (bp
->link_vars
.link_up
)
9171 bnx2x_set_led(bp
, port
, LED_MODE_OPER
,
9172 bp
->link_vars
.line_speed
,
9173 bp
->link_params
.hw_led_mode
,
9174 bp
->link_params
.chip_id
);
9179 static struct ethtool_ops bnx2x_ethtool_ops
= {
9180 .get_settings
= bnx2x_get_settings
,
9181 .set_settings
= bnx2x_set_settings
,
9182 .get_drvinfo
= bnx2x_get_drvinfo
,
9183 .get_wol
= bnx2x_get_wol
,
9184 .set_wol
= bnx2x_set_wol
,
9185 .get_msglevel
= bnx2x_get_msglevel
,
9186 .set_msglevel
= bnx2x_set_msglevel
,
9187 .nway_reset
= bnx2x_nway_reset
,
9188 .get_link
= ethtool_op_get_link
,
9189 .get_eeprom_len
= bnx2x_get_eeprom_len
,
9190 .get_eeprom
= bnx2x_get_eeprom
,
9191 .set_eeprom
= bnx2x_set_eeprom
,
9192 .get_coalesce
= bnx2x_get_coalesce
,
9193 .set_coalesce
= bnx2x_set_coalesce
,
9194 .get_ringparam
= bnx2x_get_ringparam
,
9195 .set_ringparam
= bnx2x_set_ringparam
,
9196 .get_pauseparam
= bnx2x_get_pauseparam
,
9197 .set_pauseparam
= bnx2x_set_pauseparam
,
9198 .get_rx_csum
= bnx2x_get_rx_csum
,
9199 .set_rx_csum
= bnx2x_set_rx_csum
,
9200 .get_tx_csum
= ethtool_op_get_tx_csum
,
9201 .set_tx_csum
= ethtool_op_set_tx_hw_csum
,
9202 .set_flags
= bnx2x_set_flags
,
9203 .get_flags
= ethtool_op_get_flags
,
9204 .get_sg
= ethtool_op_get_sg
,
9205 .set_sg
= ethtool_op_set_sg
,
9206 .get_tso
= ethtool_op_get_tso
,
9207 .set_tso
= bnx2x_set_tso
,
9208 .self_test_count
= bnx2x_self_test_count
,
9209 .self_test
= bnx2x_self_test
,
9210 .get_strings
= bnx2x_get_strings
,
9211 .phys_id
= bnx2x_phys_id
,
9212 .get_stats_count
= bnx2x_get_stats_count
,
9213 .get_ethtool_stats
= bnx2x_get_ethtool_stats
,
9216 /* end of ethtool_ops */
9218 /****************************************************************************
9219 * General service functions
9220 ****************************************************************************/
9222 static int bnx2x_set_power_state(struct bnx2x
*bp
, pci_power_t state
)
9226 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
9230 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
,
9231 ((pmcsr
& ~PCI_PM_CTRL_STATE_MASK
) |
9232 PCI_PM_CTRL_PME_STATUS
));
9234 if (pmcsr
& PCI_PM_CTRL_STATE_MASK
)
9235 /* delay required during transition out of D3hot */
9240 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
9244 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
9246 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
,
9249 /* No more memory access after this point until
9250 * device is brought back to D0.
9261 * net_device service functions
9264 static int bnx2x_poll(struct napi_struct
*napi
, int budget
)
9266 struct bnx2x_fastpath
*fp
= container_of(napi
, struct bnx2x_fastpath
,
9268 struct bnx2x
*bp
= fp
->bp
;
9272 #ifdef BNX2X_STOP_ON_ERROR
9273 if (unlikely(bp
->panic
))
9277 prefetch(fp
->tx_buf_ring
[TX_BD(fp
->tx_pkt_cons
)].skb
);
9278 prefetch(fp
->rx_buf_ring
[RX_BD(fp
->rx_bd_cons
)].skb
);
9279 prefetch((char *)(fp
->rx_buf_ring
[RX_BD(fp
->rx_bd_cons
)].skb
) + 256);
9281 bnx2x_update_fpsb_idx(fp
);
9283 if (BNX2X_HAS_TX_WORK(fp
))
9284 bnx2x_tx_int(fp
, budget
);
9286 rx_cons_sb
= le16_to_cpu(*fp
->rx_cons_sb
);
9287 if ((rx_cons_sb
& MAX_RCQ_DESC_CNT
) == MAX_RCQ_DESC_CNT
)
9289 if (BNX2X_HAS_RX_WORK(fp
))
9290 work_done
= bnx2x_rx_int(fp
, budget
);
9292 rmb(); /* BNX2X_HAS_WORK() reads the status block */
9293 rx_cons_sb
= le16_to_cpu(*fp
->rx_cons_sb
);
9294 if ((rx_cons_sb
& MAX_RCQ_DESC_CNT
) == MAX_RCQ_DESC_CNT
)
9297 /* must not complete if we consumed full budget */
9298 if ((work_done
< budget
) && !BNX2X_HAS_WORK(fp
)) {
9300 #ifdef BNX2X_STOP_ON_ERROR
9303 netif_rx_complete(napi
);
9305 bnx2x_ack_sb(bp
, FP_SB_ID(fp
), USTORM_ID
,
9306 le16_to_cpu(fp
->fp_u_idx
), IGU_INT_NOP
, 1);
9307 bnx2x_ack_sb(bp
, FP_SB_ID(fp
), CSTORM_ID
,
9308 le16_to_cpu(fp
->fp_c_idx
), IGU_INT_ENABLE
, 1);
9314 /* we split the first BD into headers and data BDs
9315 * to ease the pain of our fellow microcode engineers
9316 * we use one mapping for both BDs
9317 * So far this has only been observed to happen
9318 * in Other Operating Systems(TM)
9320 static noinline u16
bnx2x_tx_split(struct bnx2x
*bp
,
9321 struct bnx2x_fastpath
*fp
,
9322 struct eth_tx_bd
**tx_bd
, u16 hlen
,
9323 u16 bd_prod
, int nbd
)
9325 struct eth_tx_bd
*h_tx_bd
= *tx_bd
;
9326 struct eth_tx_bd
*d_tx_bd
;
9328 int old_len
= le16_to_cpu(h_tx_bd
->nbytes
);
9330 /* first fix first BD */
9331 h_tx_bd
->nbd
= cpu_to_le16(nbd
);
9332 h_tx_bd
->nbytes
= cpu_to_le16(hlen
);
9334 DP(NETIF_MSG_TX_QUEUED
, "TSO split header size is %d "
9335 "(%x:%x) nbd %d\n", h_tx_bd
->nbytes
, h_tx_bd
->addr_hi
,
9336 h_tx_bd
->addr_lo
, h_tx_bd
->nbd
);
9338 /* now get a new data BD
9339 * (after the pbd) and fill it */
9340 bd_prod
= TX_BD(NEXT_TX_IDX(bd_prod
));
9341 d_tx_bd
= &fp
->tx_desc_ring
[bd_prod
];
9343 mapping
= HILO_U64(le32_to_cpu(h_tx_bd
->addr_hi
),
9344 le32_to_cpu(h_tx_bd
->addr_lo
)) + hlen
;
9346 d_tx_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
9347 d_tx_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
9348 d_tx_bd
->nbytes
= cpu_to_le16(old_len
- hlen
);
9350 /* this marks the BD as one that has no individual mapping
9351 * the FW ignores this flag in a BD not marked start
9353 d_tx_bd
->bd_flags
.as_bitfield
= ETH_TX_BD_FLAGS_SW_LSO
;
9354 DP(NETIF_MSG_TX_QUEUED
,
9355 "TSO split data size is %d (%x:%x)\n",
9356 d_tx_bd
->nbytes
, d_tx_bd
->addr_hi
, d_tx_bd
->addr_lo
);
9358 /* update tx_bd for marking the last BD flag */
9364 static inline u16
bnx2x_csum_fix(unsigned char *t_header
, u16 csum
, s8 fix
)
9367 csum
= (u16
) ~csum_fold(csum_sub(csum
,
9368 csum_partial(t_header
- fix
, fix
, 0)));
9371 csum
= (u16
) ~csum_fold(csum_add(csum
,
9372 csum_partial(t_header
, -fix
, 0)));
9374 return swab16(csum
);
9377 static inline u32
bnx2x_xmit_type(struct bnx2x
*bp
, struct sk_buff
*skb
)
9381 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
)
9385 if (skb
->protocol
== ntohs(ETH_P_IPV6
)) {
9387 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
9388 rc
|= XMIT_CSUM_TCP
;
9392 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
9393 rc
|= XMIT_CSUM_TCP
;
9397 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV4
)
9400 else if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
9406 /* check if packet requires linearization (packet is too fragmented) */
9407 static int bnx2x_pkt_req_lin(struct bnx2x
*bp
, struct sk_buff
*skb
,
9412 int first_bd_sz
= 0;
9414 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
9415 if (skb_shinfo(skb
)->nr_frags
>= (MAX_FETCH_BD
- 3)) {
9417 if (xmit_type
& XMIT_GSO
) {
9418 unsigned short lso_mss
= skb_shinfo(skb
)->gso_size
;
9419 /* Check if LSO packet needs to be copied:
9420 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
9421 int wnd_size
= MAX_FETCH_BD
- 3;
9422 /* Number of windows to check */
9423 int num_wnds
= skb_shinfo(skb
)->nr_frags
- wnd_size
;
9428 /* Headers length */
9429 hlen
= (int)(skb_transport_header(skb
) - skb
->data
) +
9432 /* Amount of data (w/o headers) on linear part of SKB*/
9433 first_bd_sz
= skb_headlen(skb
) - hlen
;
9435 wnd_sum
= first_bd_sz
;
9437 /* Calculate the first sum - it's special */
9438 for (frag_idx
= 0; frag_idx
< wnd_size
- 1; frag_idx
++)
9440 skb_shinfo(skb
)->frags
[frag_idx
].size
;
9442 /* If there was data on linear skb data - check it */
9443 if (first_bd_sz
> 0) {
9444 if (unlikely(wnd_sum
< lso_mss
)) {
9449 wnd_sum
-= first_bd_sz
;
9452 /* Others are easier: run through the frag list and
9453 check all windows */
9454 for (wnd_idx
= 0; wnd_idx
<= num_wnds
; wnd_idx
++) {
9456 skb_shinfo(skb
)->frags
[wnd_idx
+ wnd_size
- 1].size
;
9458 if (unlikely(wnd_sum
< lso_mss
)) {
9463 skb_shinfo(skb
)->frags
[wnd_idx
].size
;
9467 /* in non-LSO too fragmented packet should always
9474 if (unlikely(to_copy
))
9475 DP(NETIF_MSG_TX_QUEUED
,
9476 "Linearization IS REQUIRED for %s packet. "
9477 "num_frags %d hlen %d first_bd_sz %d\n",
9478 (xmit_type
& XMIT_GSO
) ? "LSO" : "non-LSO",
9479 skb_shinfo(skb
)->nr_frags
, hlen
, first_bd_sz
);
9484 /* called with netif_tx_lock
9485 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
9486 * netif_wake_queue()
9488 static int bnx2x_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
9490 struct bnx2x
*bp
= netdev_priv(dev
);
9491 struct bnx2x_fastpath
*fp
;
9492 struct sw_tx_bd
*tx_buf
;
9493 struct eth_tx_bd
*tx_bd
;
9494 struct eth_tx_parse_bd
*pbd
= NULL
;
9495 u16 pkt_prod
, bd_prod
;
9498 u32 xmit_type
= bnx2x_xmit_type(bp
, skb
);
9499 int vlan_off
= (bp
->e1hov
? 4 : 0);
9503 #ifdef BNX2X_STOP_ON_ERROR
9504 if (unlikely(bp
->panic
))
9505 return NETDEV_TX_BUSY
;
9508 fp_index
= (smp_processor_id() % bp
->num_queues
);
9509 fp
= &bp
->fp
[fp_index
];
9511 if (unlikely(bnx2x_tx_avail(fp
) < (skb_shinfo(skb
)->nr_frags
+ 3))) {
9512 bp
->eth_stats
.driver_xoff
++,
9513 netif_stop_queue(dev
);
9514 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
9515 return NETDEV_TX_BUSY
;
9518 DP(NETIF_MSG_TX_QUEUED
, "SKB: summed %x protocol %x protocol(%x,%x)"
9519 " gso type %x xmit_type %x\n",
9520 skb
->ip_summed
, skb
->protocol
, ipv6_hdr(skb
)->nexthdr
,
9521 ip_hdr(skb
)->protocol
, skb_shinfo(skb
)->gso_type
, xmit_type
);
9523 /* First, check if we need to linearize the skb
9524 (due to FW restrictions) */
9525 if (bnx2x_pkt_req_lin(bp
, skb
, xmit_type
)) {
9526 /* Statistics of linearization */
9528 if (skb_linearize(skb
) != 0) {
9529 DP(NETIF_MSG_TX_QUEUED
, "SKB linearization failed - "
9530 "silently dropping this SKB\n");
9531 dev_kfree_skb_any(skb
);
9532 return NETDEV_TX_OK
;
9537 Please read carefully. First we use one BD which we mark as start,
9538 then for TSO or xsum we have a parsing info BD,
9539 and only then we have the rest of the TSO BDs.
9540 (don't forget to mark the last one as last,
9541 and to unmap only AFTER you write to the BD ...)
9542 And above all, all pdb sizes are in words - NOT DWORDS!
9545 pkt_prod
= fp
->tx_pkt_prod
++;
9546 bd_prod
= TX_BD(fp
->tx_bd_prod
);
9548 /* get a tx_buf and first BD */
9549 tx_buf
= &fp
->tx_buf_ring
[TX_BD(pkt_prod
)];
9550 tx_bd
= &fp
->tx_desc_ring
[bd_prod
];
9552 tx_bd
->bd_flags
.as_bitfield
= ETH_TX_BD_FLAGS_START_BD
;
9553 tx_bd
->general_data
= (UNICAST_ADDRESS
<<
9554 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT
);
9556 tx_bd
->general_data
|= (1 << ETH_TX_BD_HDR_NBDS_SHIFT
);
9558 /* remember the first BD of the packet */
9559 tx_buf
->first_bd
= fp
->tx_bd_prod
;
9562 DP(NETIF_MSG_TX_QUEUED
,
9563 "sending pkt %u @%p next_idx %u bd %u @%p\n",
9564 pkt_prod
, tx_buf
, fp
->tx_pkt_prod
, bd_prod
, tx_bd
);
9566 if ((bp
->vlgrp
!= NULL
) && vlan_tx_tag_present(skb
)) {
9567 tx_bd
->vlan
= cpu_to_le16(vlan_tx_tag_get(skb
));
9568 tx_bd
->bd_flags
.as_bitfield
|= ETH_TX_BD_FLAGS_VLAN_TAG
;
9571 tx_bd
->vlan
= cpu_to_le16(pkt_prod
);
9574 /* turn on parsing and get a BD */
9575 bd_prod
= TX_BD(NEXT_TX_IDX(bd_prod
));
9576 pbd
= (void *)&fp
->tx_desc_ring
[bd_prod
];
9578 memset(pbd
, 0, sizeof(struct eth_tx_parse_bd
));
9581 if (xmit_type
& XMIT_CSUM
) {
9582 hlen
= (skb_network_header(skb
) - skb
->data
+ vlan_off
) / 2;
9584 /* for now NS flag is not used in Linux */
9585 pbd
->global_data
= (hlen
|
9586 ((skb
->protocol
== ntohs(ETH_P_8021Q
)) <<
9587 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT
));
9589 pbd
->ip_hlen
= (skb_transport_header(skb
) -
9590 skb_network_header(skb
)) / 2;
9592 hlen
+= pbd
->ip_hlen
+ tcp_hdrlen(skb
) / 2;
9594 pbd
->total_hlen
= cpu_to_le16(hlen
);
9595 hlen
= hlen
*2 - vlan_off
;
9597 tx_bd
->bd_flags
.as_bitfield
|= ETH_TX_BD_FLAGS_TCP_CSUM
;
9599 if (xmit_type
& XMIT_CSUM_V4
)
9600 tx_bd
->bd_flags
.as_bitfield
|=
9601 ETH_TX_BD_FLAGS_IP_CSUM
;
9603 tx_bd
->bd_flags
.as_bitfield
|= ETH_TX_BD_FLAGS_IPV6
;
9605 if (xmit_type
& XMIT_CSUM_TCP
) {
9606 pbd
->tcp_pseudo_csum
= swab16(tcp_hdr(skb
)->check
);
9609 s8 fix
= SKB_CS_OFF(skb
); /* signed! */
9611 pbd
->global_data
|= ETH_TX_PARSE_BD_CS_ANY_FLG
;
9612 pbd
->cs_offset
= fix
/ 2;
9614 DP(NETIF_MSG_TX_QUEUED
,
9615 "hlen %d offset %d fix %d csum before fix %x\n",
9616 le16_to_cpu(pbd
->total_hlen
), pbd
->cs_offset
, fix
,
9619 /* HW bug: fixup the CSUM */
9620 pbd
->tcp_pseudo_csum
=
9621 bnx2x_csum_fix(skb_transport_header(skb
),
9624 DP(NETIF_MSG_TX_QUEUED
, "csum after fix %x\n",
9625 pbd
->tcp_pseudo_csum
);
9629 mapping
= pci_map_single(bp
->pdev
, skb
->data
,
9630 skb_headlen(skb
), PCI_DMA_TODEVICE
);
9632 tx_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
9633 tx_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
9634 nbd
= skb_shinfo(skb
)->nr_frags
+ ((pbd
== NULL
) ? 1 : 2);
9635 tx_bd
->nbd
= cpu_to_le16(nbd
);
9636 tx_bd
->nbytes
= cpu_to_le16(skb_headlen(skb
));
9638 DP(NETIF_MSG_TX_QUEUED
, "first bd @%p addr (%x:%x) nbd %d"
9639 " nbytes %d flags %x vlan %x\n",
9640 tx_bd
, tx_bd
->addr_hi
, tx_bd
->addr_lo
, le16_to_cpu(tx_bd
->nbd
),
9641 le16_to_cpu(tx_bd
->nbytes
), tx_bd
->bd_flags
.as_bitfield
,
9642 le16_to_cpu(tx_bd
->vlan
));
9644 if (xmit_type
& XMIT_GSO
) {
9646 DP(NETIF_MSG_TX_QUEUED
,
9647 "TSO packet len %d hlen %d total len %d tso size %d\n",
9648 skb
->len
, hlen
, skb_headlen(skb
),
9649 skb_shinfo(skb
)->gso_size
);
9651 tx_bd
->bd_flags
.as_bitfield
|= ETH_TX_BD_FLAGS_SW_LSO
;
9653 if (unlikely(skb_headlen(skb
) > hlen
))
9654 bd_prod
= bnx2x_tx_split(bp
, fp
, &tx_bd
, hlen
,
9657 pbd
->lso_mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
);
9658 pbd
->tcp_send_seq
= swab32(tcp_hdr(skb
)->seq
);
9659 pbd
->tcp_flags
= pbd_tcp_flags(skb
);
9661 if (xmit_type
& XMIT_GSO_V4
) {
9662 pbd
->ip_id
= swab16(ip_hdr(skb
)->id
);
9663 pbd
->tcp_pseudo_csum
=
9664 swab16(~csum_tcpudp_magic(ip_hdr(skb
)->saddr
,
9666 0, IPPROTO_TCP
, 0));
9669 pbd
->tcp_pseudo_csum
=
9670 swab16(~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
9671 &ipv6_hdr(skb
)->daddr
,
9672 0, IPPROTO_TCP
, 0));
9674 pbd
->global_data
|= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN
;
9677 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
9678 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
9680 bd_prod
= TX_BD(NEXT_TX_IDX(bd_prod
));
9681 tx_bd
= &fp
->tx_desc_ring
[bd_prod
];
9683 mapping
= pci_map_page(bp
->pdev
, frag
->page
, frag
->page_offset
,
9684 frag
->size
, PCI_DMA_TODEVICE
);
9686 tx_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
9687 tx_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
9688 tx_bd
->nbytes
= cpu_to_le16(frag
->size
);
9689 tx_bd
->vlan
= cpu_to_le16(pkt_prod
);
9690 tx_bd
->bd_flags
.as_bitfield
= 0;
9692 DP(NETIF_MSG_TX_QUEUED
,
9693 "frag %d bd @%p addr (%x:%x) nbytes %d flags %x\n",
9694 i
, tx_bd
, tx_bd
->addr_hi
, tx_bd
->addr_lo
,
9695 le16_to_cpu(tx_bd
->nbytes
), tx_bd
->bd_flags
.as_bitfield
);
9698 /* now at last mark the BD as the last BD */
9699 tx_bd
->bd_flags
.as_bitfield
|= ETH_TX_BD_FLAGS_END_BD
;
9701 DP(NETIF_MSG_TX_QUEUED
, "last bd @%p flags %x\n",
9702 tx_bd
, tx_bd
->bd_flags
.as_bitfield
);
9704 bd_prod
= TX_BD(NEXT_TX_IDX(bd_prod
));
9706 /* now send a tx doorbell, counting the next BD
9707 * if the packet contains or ends with it
9709 if (TX_BD_POFF(bd_prod
) < nbd
)
9713 DP(NETIF_MSG_TX_QUEUED
,
9714 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
9715 " tcp_flags %x xsum %x seq %u hlen %u\n",
9716 pbd
, pbd
->global_data
, pbd
->ip_hlen
, pbd
->ip_id
,
9717 pbd
->lso_mss
, pbd
->tcp_flags
, pbd
->tcp_pseudo_csum
,
9718 pbd
->tcp_send_seq
, le16_to_cpu(pbd
->total_hlen
));
9720 DP(NETIF_MSG_TX_QUEUED
, "doorbell: nbd %d bd %u\n", nbd
, bd_prod
);
9723 * Make sure that the BD data is updated before updating the producer
9724 * since FW might read the BD right after the producer is updated.
9725 * This is only applicable for weak-ordered memory model archs such
9726 * as IA-64. The following barrier is also mandatory since FW will
9727 * assumes packets must have BDs.
9731 fp
->hw_tx_prods
->bds_prod
=
9732 cpu_to_le16(le16_to_cpu(fp
->hw_tx_prods
->bds_prod
) + nbd
);
9733 mb(); /* FW restriction: must not reorder writing nbd and packets */
9734 fp
->hw_tx_prods
->packets_prod
=
9735 cpu_to_le32(le32_to_cpu(fp
->hw_tx_prods
->packets_prod
) + 1);
9736 DOORBELL(bp
, FP_IDX(fp
), 0);
9740 fp
->tx_bd_prod
+= nbd
;
9741 dev
->trans_start
= jiffies
;
9743 if (unlikely(bnx2x_tx_avail(fp
) < MAX_SKB_FRAGS
+ 3)) {
9744 /* We want bnx2x_tx_int to "see" the updated tx_bd_prod
9745 if we put Tx into XOFF state. */
9747 netif_stop_queue(dev
);
9748 bp
->eth_stats
.driver_xoff
++;
9749 if (bnx2x_tx_avail(fp
) >= MAX_SKB_FRAGS
+ 3)
9750 netif_wake_queue(dev
);
9754 return NETDEV_TX_OK
;
9757 /* called with rtnl_lock */
9758 static int bnx2x_open(struct net_device
*dev
)
9760 struct bnx2x
*bp
= netdev_priv(dev
);
9762 bnx2x_set_power_state(bp
, PCI_D0
);
9764 return bnx2x_nic_load(bp
, LOAD_OPEN
);
9767 /* called with rtnl_lock */
9768 static int bnx2x_close(struct net_device
*dev
)
9770 struct bnx2x
*bp
= netdev_priv(dev
);
9772 /* Unload the driver, release IRQs */
9773 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
);
9774 if (atomic_read(&bp
->pdev
->enable_cnt
) == 1)
9775 if (!CHIP_REV_IS_SLOW(bp
))
9776 bnx2x_set_power_state(bp
, PCI_D3hot
);
9781 /* called with netif_tx_lock from set_multicast */
9782 static void bnx2x_set_rx_mode(struct net_device
*dev
)
9784 struct bnx2x
*bp
= netdev_priv(dev
);
9785 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
9786 int port
= BP_PORT(bp
);
9788 if (bp
->state
!= BNX2X_STATE_OPEN
) {
9789 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
9793 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", dev
->flags
);
9795 if (dev
->flags
& IFF_PROMISC
)
9796 rx_mode
= BNX2X_RX_MODE_PROMISC
;
9798 else if ((dev
->flags
& IFF_ALLMULTI
) ||
9799 ((dev
->mc_count
> BNX2X_MAX_MULTICAST
) && CHIP_IS_E1(bp
)))
9800 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
9802 else { /* some multicasts */
9803 if (CHIP_IS_E1(bp
)) {
9805 struct dev_mc_list
*mclist
;
9806 struct mac_configuration_cmd
*config
=
9807 bnx2x_sp(bp
, mcast_config
);
9809 for (i
= 0, mclist
= dev
->mc_list
;
9810 mclist
&& (i
< dev
->mc_count
);
9811 i
++, mclist
= mclist
->next
) {
9813 config
->config_table
[i
].
9814 cam_entry
.msb_mac_addr
=
9815 swab16(*(u16
*)&mclist
->dmi_addr
[0]);
9816 config
->config_table
[i
].
9817 cam_entry
.middle_mac_addr
=
9818 swab16(*(u16
*)&mclist
->dmi_addr
[2]);
9819 config
->config_table
[i
].
9820 cam_entry
.lsb_mac_addr
=
9821 swab16(*(u16
*)&mclist
->dmi_addr
[4]);
9822 config
->config_table
[i
].cam_entry
.flags
=
9824 config
->config_table
[i
].
9825 target_table_entry
.flags
= 0;
9826 config
->config_table
[i
].
9827 target_table_entry
.client_id
= 0;
9828 config
->config_table
[i
].
9829 target_table_entry
.vlan_id
= 0;
9832 "setting MCAST[%d] (%04x:%04x:%04x)\n", i
,
9833 config
->config_table
[i
].
9834 cam_entry
.msb_mac_addr
,
9835 config
->config_table
[i
].
9836 cam_entry
.middle_mac_addr
,
9837 config
->config_table
[i
].
9838 cam_entry
.lsb_mac_addr
);
9840 old
= config
->hdr
.length_6b
;
9842 for (; i
< old
; i
++) {
9843 if (CAM_IS_INVALID(config
->
9845 i
--; /* already invalidated */
9849 CAM_INVALIDATE(config
->
9854 if (CHIP_REV_IS_SLOW(bp
))
9855 offset
= BNX2X_MAX_EMUL_MULTI
*(1 + port
);
9857 offset
= BNX2X_MAX_MULTICAST
*(1 + port
);
9859 config
->hdr
.length_6b
= i
;
9860 config
->hdr
.offset
= offset
;
9861 config
->hdr
.client_id
= BP_CL_ID(bp
);
9862 config
->hdr
.reserved1
= 0;
9864 bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_SET_MAC
, 0,
9865 U64_HI(bnx2x_sp_mapping(bp
, mcast_config
)),
9866 U64_LO(bnx2x_sp_mapping(bp
, mcast_config
)),
9869 /* Accept one or more multicasts */
9870 struct dev_mc_list
*mclist
;
9871 u32 mc_filter
[MC_HASH_SIZE
];
9872 u32 crc
, bit
, regidx
;
9875 memset(mc_filter
, 0, 4 * MC_HASH_SIZE
);
9877 for (i
= 0, mclist
= dev
->mc_list
;
9878 mclist
&& (i
< dev
->mc_count
);
9879 i
++, mclist
= mclist
->next
) {
9881 DP(NETIF_MSG_IFUP
, "Adding mcast MAC: %pM\n",
9884 crc
= crc32c_le(0, mclist
->dmi_addr
, ETH_ALEN
);
9885 bit
= (crc
>> 24) & 0xff;
9888 mc_filter
[regidx
] |= (1 << bit
);
9891 for (i
= 0; i
< MC_HASH_SIZE
; i
++)
9892 REG_WR(bp
, MC_HASH_OFFSET(bp
, i
),
9897 bp
->rx_mode
= rx_mode
;
9898 bnx2x_set_storm_rx_mode(bp
);
9901 /* called with rtnl_lock */
9902 static int bnx2x_change_mac_addr(struct net_device
*dev
, void *p
)
9904 struct sockaddr
*addr
= p
;
9905 struct bnx2x
*bp
= netdev_priv(dev
);
9907 if (!is_valid_ether_addr((u8
*)(addr
->sa_data
)))
9910 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
9911 if (netif_running(dev
)) {
9913 bnx2x_set_mac_addr_e1(bp
, 1);
9915 bnx2x_set_mac_addr_e1h(bp
, 1);
9921 /* called with rtnl_lock */
9922 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
9924 struct mii_ioctl_data
*data
= if_mii(ifr
);
9925 struct bnx2x
*bp
= netdev_priv(dev
);
9926 int port
= BP_PORT(bp
);
9931 data
->phy_id
= bp
->port
.phy_addr
;
9938 if (!netif_running(dev
))
9941 mutex_lock(&bp
->port
.phy_mutex
);
9942 err
= bnx2x_cl45_read(bp
, port
, 0, bp
->port
.phy_addr
,
9943 DEFAULT_PHY_DEV_ADDR
,
9944 (data
->reg_num
& 0x1f), &mii_regval
);
9945 data
->val_out
= mii_regval
;
9946 mutex_unlock(&bp
->port
.phy_mutex
);
9951 if (!capable(CAP_NET_ADMIN
))
9954 if (!netif_running(dev
))
9957 mutex_lock(&bp
->port
.phy_mutex
);
9958 err
= bnx2x_cl45_write(bp
, port
, 0, bp
->port
.phy_addr
,
9959 DEFAULT_PHY_DEV_ADDR
,
9960 (data
->reg_num
& 0x1f), data
->val_in
);
9961 mutex_unlock(&bp
->port
.phy_mutex
);
9972 /* called with rtnl_lock */
9973 static int bnx2x_change_mtu(struct net_device
*dev
, int new_mtu
)
9975 struct bnx2x
*bp
= netdev_priv(dev
);
9978 if ((new_mtu
> ETH_MAX_JUMBO_PACKET_SIZE
) ||
9979 ((new_mtu
+ ETH_HLEN
) < ETH_MIN_PACKET_SIZE
))
9982 /* This does not race with packet allocation
9983 * because the actual alloc size is
9984 * only updated as part of load
9988 if (netif_running(dev
)) {
9989 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
9990 rc
= bnx2x_nic_load(bp
, LOAD_NORMAL
);
9996 static void bnx2x_tx_timeout(struct net_device
*dev
)
9998 struct bnx2x
*bp
= netdev_priv(dev
);
10000 #ifdef BNX2X_STOP_ON_ERROR
10004 /* This allows the netif to be shutdown gracefully before resetting */
10005 schedule_work(&bp
->reset_task
);
10009 /* called with rtnl_lock */
10010 static void bnx2x_vlan_rx_register(struct net_device
*dev
,
10011 struct vlan_group
*vlgrp
)
10013 struct bnx2x
*bp
= netdev_priv(dev
);
10016 if (netif_running(dev
))
10017 bnx2x_set_client_config(bp
);
10022 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
10023 static void poll_bnx2x(struct net_device
*dev
)
10025 struct bnx2x
*bp
= netdev_priv(dev
);
10027 disable_irq(bp
->pdev
->irq
);
10028 bnx2x_interrupt(bp
->pdev
->irq
, dev
);
10029 enable_irq(bp
->pdev
->irq
);
10033 static const struct net_device_ops bnx2x_netdev_ops
= {
10034 .ndo_open
= bnx2x_open
,
10035 .ndo_stop
= bnx2x_close
,
10036 .ndo_start_xmit
= bnx2x_start_xmit
,
10037 .ndo_set_multicast_list
= bnx2x_set_rx_mode
,
10038 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
10039 .ndo_validate_addr
= eth_validate_addr
,
10040 .ndo_do_ioctl
= bnx2x_ioctl
,
10041 .ndo_change_mtu
= bnx2x_change_mtu
,
10042 .ndo_tx_timeout
= bnx2x_tx_timeout
,
10044 .ndo_vlan_rx_register
= bnx2x_vlan_rx_register
,
10046 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
10047 .ndo_poll_controller
= poll_bnx2x
,
10052 static int __devinit
bnx2x_init_dev(struct pci_dev
*pdev
,
10053 struct net_device
*dev
)
10058 SET_NETDEV_DEV(dev
, &pdev
->dev
);
10059 bp
= netdev_priv(dev
);
10064 bp
->func
= PCI_FUNC(pdev
->devfn
);
10066 rc
= pci_enable_device(pdev
);
10068 printk(KERN_ERR PFX
"Cannot enable PCI device, aborting\n");
10072 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
10073 printk(KERN_ERR PFX
"Cannot find PCI device base address,"
10076 goto err_out_disable
;
10079 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
10080 printk(KERN_ERR PFX
"Cannot find second PCI device"
10081 " base address, aborting\n");
10083 goto err_out_disable
;
10086 if (atomic_read(&pdev
->enable_cnt
) == 1) {
10087 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
10089 printk(KERN_ERR PFX
"Cannot obtain PCI resources,"
10091 goto err_out_disable
;
10094 pci_set_master(pdev
);
10095 pci_save_state(pdev
);
10098 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
10099 if (bp
->pm_cap
== 0) {
10100 printk(KERN_ERR PFX
"Cannot find power management"
10101 " capability, aborting\n");
10103 goto err_out_release
;
10106 bp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
10107 if (bp
->pcie_cap
== 0) {
10108 printk(KERN_ERR PFX
"Cannot find PCI Express capability,"
10111 goto err_out_release
;
10114 if (pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) == 0) {
10115 bp
->flags
|= USING_DAC_FLAG
;
10116 if (pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
) != 0) {
10117 printk(KERN_ERR PFX
"pci_set_consistent_dma_mask"
10118 " failed, aborting\n");
10120 goto err_out_release
;
10123 } else if (pci_set_dma_mask(pdev
, DMA_32BIT_MASK
) != 0) {
10124 printk(KERN_ERR PFX
"System does not support DMA,"
10127 goto err_out_release
;
10130 dev
->mem_start
= pci_resource_start(pdev
, 0);
10131 dev
->base_addr
= dev
->mem_start
;
10132 dev
->mem_end
= pci_resource_end(pdev
, 0);
10134 dev
->irq
= pdev
->irq
;
10136 bp
->regview
= pci_ioremap_bar(pdev
, 0);
10137 if (!bp
->regview
) {
10138 printk(KERN_ERR PFX
"Cannot map register space, aborting\n");
10140 goto err_out_release
;
10143 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
10144 min_t(u64
, BNX2X_DB_SIZE
,
10145 pci_resource_len(pdev
, 2)));
10146 if (!bp
->doorbells
) {
10147 printk(KERN_ERR PFX
"Cannot map doorbell space, aborting\n");
10149 goto err_out_unmap
;
10152 bnx2x_set_power_state(bp
, PCI_D0
);
10154 /* clean indirect addresses */
10155 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
10156 PCICFG_VENDOR_ID_OFFSET
);
10157 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
+ BP_PORT(bp
)*16, 0);
10158 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
+ BP_PORT(bp
)*16, 0);
10159 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
+ BP_PORT(bp
)*16, 0);
10160 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
+ BP_PORT(bp
)*16, 0);
10162 dev
->watchdog_timeo
= TX_TIMEOUT
;
10164 dev
->netdev_ops
= &bnx2x_netdev_ops
;
10165 dev
->ethtool_ops
= &bnx2x_ethtool_ops
;
10166 dev
->features
|= NETIF_F_SG
;
10167 dev
->features
|= NETIF_F_HW_CSUM
;
10168 if (bp
->flags
& USING_DAC_FLAG
)
10169 dev
->features
|= NETIF_F_HIGHDMA
;
10171 dev
->features
|= (NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
);
10173 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO_ECN
);
10174 dev
->features
|= NETIF_F_TSO6
;
10180 iounmap(bp
->regview
);
10181 bp
->regview
= NULL
;
10183 if (bp
->doorbells
) {
10184 iounmap(bp
->doorbells
);
10185 bp
->doorbells
= NULL
;
10189 if (atomic_read(&pdev
->enable_cnt
) == 1)
10190 pci_release_regions(pdev
);
10193 pci_disable_device(pdev
);
10194 pci_set_drvdata(pdev
, NULL
);
10200 static int __devinit
bnx2x_get_pcie_width(struct bnx2x
*bp
)
10202 u32 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCICFG_LINK_CONTROL
);
10204 val
= (val
& PCICFG_LINK_WIDTH
) >> PCICFG_LINK_WIDTH_SHIFT
;
10208 /* return value of 1=2.5GHz 2=5GHz */
10209 static int __devinit
bnx2x_get_pcie_speed(struct bnx2x
*bp
)
10211 u32 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCICFG_LINK_CONTROL
);
10213 val
= (val
& PCICFG_LINK_SPEED
) >> PCICFG_LINK_SPEED_SHIFT
;
10217 static int __devinit
bnx2x_init_one(struct pci_dev
*pdev
,
10218 const struct pci_device_id
*ent
)
10220 static int version_printed
;
10221 struct net_device
*dev
= NULL
;
10225 if (version_printed
++ == 0)
10226 printk(KERN_INFO
"%s", version
);
10228 /* dev zeroed in init_etherdev */
10229 dev
= alloc_etherdev(sizeof(*bp
));
10231 printk(KERN_ERR PFX
"Cannot allocate net device\n");
10235 bp
= netdev_priv(dev
);
10236 bp
->msglevel
= debug
;
10238 rc
= bnx2x_init_dev(pdev
, dev
);
10244 rc
= register_netdev(dev
);
10246 dev_err(&pdev
->dev
, "Cannot register net device\n");
10247 goto init_one_exit
;
10250 pci_set_drvdata(pdev
, dev
);
10252 rc
= bnx2x_init_bp(bp
);
10254 unregister_netdev(dev
);
10255 goto init_one_exit
;
10258 netif_carrier_off(dev
);
10260 bp
->common
.name
= board_info
[ent
->driver_data
].name
;
10261 printk(KERN_INFO
"%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
10262 " IRQ %d, ", dev
->name
, bp
->common
.name
,
10263 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
10264 bnx2x_get_pcie_width(bp
),
10265 (bnx2x_get_pcie_speed(bp
) == 2) ? "5GHz (Gen2)" : "2.5GHz",
10266 dev
->base_addr
, bp
->pdev
->irq
);
10267 printk(KERN_CONT
"node addr %pM\n", dev
->dev_addr
);
10272 iounmap(bp
->regview
);
10275 iounmap(bp
->doorbells
);
10279 if (atomic_read(&pdev
->enable_cnt
) == 1)
10280 pci_release_regions(pdev
);
10282 pci_disable_device(pdev
);
10283 pci_set_drvdata(pdev
, NULL
);
10288 static void __devexit
bnx2x_remove_one(struct pci_dev
*pdev
)
10290 struct net_device
*dev
= pci_get_drvdata(pdev
);
10294 printk(KERN_ERR PFX
"BAD net device from bnx2x_init_one\n");
10297 bp
= netdev_priv(dev
);
10299 unregister_netdev(dev
);
10302 iounmap(bp
->regview
);
10305 iounmap(bp
->doorbells
);
10309 if (atomic_read(&pdev
->enable_cnt
) == 1)
10310 pci_release_regions(pdev
);
10312 pci_disable_device(pdev
);
10313 pci_set_drvdata(pdev
, NULL
);
10316 static int bnx2x_suspend(struct pci_dev
*pdev
, pm_message_t state
)
10318 struct net_device
*dev
= pci_get_drvdata(pdev
);
10322 printk(KERN_ERR PFX
"BAD net device from bnx2x_init_one\n");
10325 bp
= netdev_priv(dev
);
10329 pci_save_state(pdev
);
10331 if (!netif_running(dev
)) {
10336 netif_device_detach(dev
);
10338 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
);
10340 bnx2x_set_power_state(bp
, pci_choose_state(pdev
, state
));
10347 static int bnx2x_resume(struct pci_dev
*pdev
)
10349 struct net_device
*dev
= pci_get_drvdata(pdev
);
10354 printk(KERN_ERR PFX
"BAD net device from bnx2x_init_one\n");
10357 bp
= netdev_priv(dev
);
10361 pci_restore_state(pdev
);
10363 if (!netif_running(dev
)) {
10368 bnx2x_set_power_state(bp
, PCI_D0
);
10369 netif_device_attach(dev
);
10371 rc
= bnx2x_nic_load(bp
, LOAD_OPEN
);
10378 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
10382 bp
->state
= BNX2X_STATE_ERROR
;
10384 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
10386 bnx2x_netif_stop(bp
, 0);
10388 del_timer_sync(&bp
->timer
);
10389 bp
->stats_state
= STATS_STATE_DISABLED
;
10390 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
10393 bnx2x_free_irq(bp
);
10395 if (CHIP_IS_E1(bp
)) {
10396 struct mac_configuration_cmd
*config
=
10397 bnx2x_sp(bp
, mcast_config
);
10399 for (i
= 0; i
< config
->hdr
.length_6b
; i
++)
10400 CAM_INVALIDATE(config
->config_table
[i
]);
10403 /* Free SKBs, SGEs, TPA pool and driver internals */
10404 bnx2x_free_skbs(bp
);
10405 for_each_queue(bp
, i
)
10406 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
10407 bnx2x_free_mem(bp
);
10409 bp
->state
= BNX2X_STATE_CLOSED
;
10411 netif_carrier_off(bp
->dev
);
10416 static void bnx2x_eeh_recover(struct bnx2x
*bp
)
10420 mutex_init(&bp
->port
.phy_mutex
);
10422 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
10423 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
10424 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp
->common
.shmem_base
);
10426 if (!bp
->common
.shmem_base
||
10427 (bp
->common
.shmem_base
< 0xA0000) ||
10428 (bp
->common
.shmem_base
>= 0xC0000)) {
10429 BNX2X_DEV_INFO("MCP not active\n");
10430 bp
->flags
|= NO_MCP_FLAG
;
10434 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
10435 if ((val
& (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
10436 != (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
10437 BNX2X_ERR("BAD MCP validity signature\n");
10439 if (!BP_NOMCP(bp
)) {
10440 bp
->fw_seq
= (SHMEM_RD(bp
, func_mb
[BP_FUNC(bp
)].drv_mb_header
)
10441 & DRV_MSG_SEQ_NUMBER_MASK
);
10442 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
10447 * bnx2x_io_error_detected - called when PCI error is detected
10448 * @pdev: Pointer to PCI device
10449 * @state: The current pci connection state
10451 * This function is called after a PCI bus error affecting
10452 * this device has been detected.
10454 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
10455 pci_channel_state_t state
)
10457 struct net_device
*dev
= pci_get_drvdata(pdev
);
10458 struct bnx2x
*bp
= netdev_priv(dev
);
10462 netif_device_detach(dev
);
10464 if (netif_running(dev
))
10465 bnx2x_eeh_nic_unload(bp
);
10467 pci_disable_device(pdev
);
10471 /* Request a slot reset */
10472 return PCI_ERS_RESULT_NEED_RESET
;
10476 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10477 * @pdev: Pointer to PCI device
10479 * Restart the card from scratch, as if from a cold-boot.
10481 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
10483 struct net_device
*dev
= pci_get_drvdata(pdev
);
10484 struct bnx2x
*bp
= netdev_priv(dev
);
10488 if (pci_enable_device(pdev
)) {
10489 dev_err(&pdev
->dev
,
10490 "Cannot re-enable PCI device after reset\n");
10492 return PCI_ERS_RESULT_DISCONNECT
;
10495 pci_set_master(pdev
);
10496 pci_restore_state(pdev
);
10498 if (netif_running(dev
))
10499 bnx2x_set_power_state(bp
, PCI_D0
);
10503 return PCI_ERS_RESULT_RECOVERED
;
10507 * bnx2x_io_resume - called when traffic can start flowing again
10508 * @pdev: Pointer to PCI device
10510 * This callback is called when the error recovery driver tells us that
10511 * its OK to resume normal operation.
10513 static void bnx2x_io_resume(struct pci_dev
*pdev
)
10515 struct net_device
*dev
= pci_get_drvdata(pdev
);
10516 struct bnx2x
*bp
= netdev_priv(dev
);
10520 bnx2x_eeh_recover(bp
);
10522 if (netif_running(dev
))
10523 bnx2x_nic_load(bp
, LOAD_NORMAL
);
10525 netif_device_attach(dev
);
10530 static struct pci_error_handlers bnx2x_err_handler
= {
10531 .error_detected
= bnx2x_io_error_detected
,
10532 .slot_reset
= bnx2x_io_slot_reset
,
10533 .resume
= bnx2x_io_resume
,
10536 static struct pci_driver bnx2x_pci_driver
= {
10537 .name
= DRV_MODULE_NAME
,
10538 .id_table
= bnx2x_pci_tbl
,
10539 .probe
= bnx2x_init_one
,
10540 .remove
= __devexit_p(bnx2x_remove_one
),
10541 .suspend
= bnx2x_suspend
,
10542 .resume
= bnx2x_resume
,
10543 .err_handler
= &bnx2x_err_handler
,
10546 static int __init
bnx2x_init(void)
10548 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
10549 if (bnx2x_wq
== NULL
) {
10550 printk(KERN_ERR PFX
"Cannot create workqueue\n");
10554 return pci_register_driver(&bnx2x_pci_driver
);
10557 static void __exit
bnx2x_cleanup(void)
10559 pci_unregister_driver(&bnx2x_pci_driver
);
10561 destroy_workqueue(bnx2x_wq
);
10564 module_init(bnx2x_init
);
10565 module_exit(bnx2x_cleanup
);