2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5 * (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
11 * Send feedback to <socketcan-users@lists.berlios.de>
14 * Your platform definition file should specify something like:
16 * static struct at91_can_data ek_can_data = {
17 * transceiver_switch = sam9263ek_transceiver_switch,
20 * at91_add_device_can(&ek_can_data);
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
38 #include <linux/can/dev.h>
39 #include <linux/can/error.h>
41 #include <mach/board.h>
43 #define AT91_NAPI_WEIGHT 12
49 #define AT91_MB_RX_NUM 12
50 #define AT91_MB_TX_SHIFT 2
52 #define AT91_MB_RX_FIRST 0
53 #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
55 #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
56 #define AT91_MB_RX_SPLIT 8
57 #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
58 #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
60 #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
61 #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
62 #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
64 #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
65 #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
66 #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
67 #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
69 /* Common registers */
84 /* Mailbox registers (0 <= i <= 15) */
85 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
86 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
87 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
88 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
89 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
90 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
91 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
92 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
95 #define AT91_MR_CANEN BIT(0)
96 #define AT91_MR_LPM BIT(1)
97 #define AT91_MR_ABM BIT(2)
98 #define AT91_MR_OVL BIT(3)
99 #define AT91_MR_TEOF BIT(4)
100 #define AT91_MR_TTM BIT(5)
101 #define AT91_MR_TIMFRZ BIT(6)
102 #define AT91_MR_DRPT BIT(7)
104 #define AT91_SR_RBSY BIT(29)
106 #define AT91_MMR_PRIO_SHIFT (16)
108 #define AT91_MID_MIDE BIT(29)
110 #define AT91_MSR_MRTR BIT(20)
111 #define AT91_MSR_MABT BIT(22)
112 #define AT91_MSR_MRDY BIT(23)
113 #define AT91_MSR_MMI BIT(24)
115 #define AT91_MCR_MRTR BIT(20)
116 #define AT91_MCR_MTCR BIT(23)
120 AT91_MB_MODE_DISABLED
= 0,
122 AT91_MB_MODE_RX_OVRWR
= 2,
124 AT91_MB_MODE_CONSUMER
= 4,
125 AT91_MB_MODE_PRODUCER
= 5,
128 /* Interrupt mask bits */
129 #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
130 - (1 << AT91_MB_RX_FIRST))
131 #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
132 - (1 << AT91_MB_TX_FIRST))
133 #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
135 #define AT91_IRQ_ERRA (1 << 16)
136 #define AT91_IRQ_WARN (1 << 17)
137 #define AT91_IRQ_ERRP (1 << 18)
138 #define AT91_IRQ_BOFF (1 << 19)
139 #define AT91_IRQ_SLEEP (1 << 20)
140 #define AT91_IRQ_WAKEUP (1 << 21)
141 #define AT91_IRQ_TOVF (1 << 22)
142 #define AT91_IRQ_TSTP (1 << 23)
143 #define AT91_IRQ_CERR (1 << 24)
144 #define AT91_IRQ_SERR (1 << 25)
145 #define AT91_IRQ_AERR (1 << 26)
146 #define AT91_IRQ_FERR (1 << 27)
147 #define AT91_IRQ_BERR (1 << 28)
149 #define AT91_IRQ_ERR_ALL (0x1fff0000)
150 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
151 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
152 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
153 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
155 #define AT91_IRQ_ALL (0x1fffffff)
158 struct can_priv can
; /* must be the first member! */
159 struct net_device
*dev
;
160 struct napi_struct napi
;
162 void __iomem
*reg_base
;
165 unsigned int tx_next
;
166 unsigned int tx_echo
;
167 unsigned int rx_next
;
170 struct at91_can_data
*pdata
;
173 static struct can_bittiming_const at91_bittiming_const
= {
174 .name
= KBUILD_MODNAME
,
185 static inline int get_tx_next_mb(const struct at91_priv
*priv
)
187 return (priv
->tx_next
& AT91_NEXT_MB_MASK
) + AT91_MB_TX_FIRST
;
190 static inline int get_tx_next_prio(const struct at91_priv
*priv
)
192 return (priv
->tx_next
>> AT91_NEXT_PRIO_SHIFT
) & 0xf;
195 static inline int get_tx_echo_mb(const struct at91_priv
*priv
)
197 return (priv
->tx_echo
& AT91_NEXT_MB_MASK
) + AT91_MB_TX_FIRST
;
200 static inline u32
at91_read(const struct at91_priv
*priv
, enum at91_reg reg
)
202 return __raw_readl(priv
->reg_base
+ reg
);
205 static inline void at91_write(const struct at91_priv
*priv
, enum at91_reg reg
,
208 __raw_writel(value
, priv
->reg_base
+ reg
);
211 static inline void set_mb_mode_prio(const struct at91_priv
*priv
,
212 unsigned int mb
, enum at91_mb_mode mode
, int prio
)
214 at91_write(priv
, AT91_MMR(mb
), (mode
<< 24) | (prio
<< 16));
217 static inline void set_mb_mode(const struct at91_priv
*priv
, unsigned int mb
,
218 enum at91_mb_mode mode
)
220 set_mb_mode_prio(priv
, mb
, mode
, 0);
224 * Swtich transceiver on or off
226 static void at91_transceiver_switch(const struct at91_priv
*priv
, int on
)
228 if (priv
->pdata
&& priv
->pdata
->transceiver_switch
)
229 priv
->pdata
->transceiver_switch(on
);
232 static void at91_setup_mailboxes(struct net_device
*dev
)
234 struct at91_priv
*priv
= netdev_priv(dev
);
238 * The first 12 mailboxes are used as a reception FIFO. The
239 * last mailbox is configured with overwrite option. The
240 * overwrite flag indicates a FIFO overflow.
242 for (i
= AT91_MB_RX_FIRST
; i
< AT91_MB_RX_LAST
; i
++)
243 set_mb_mode(priv
, i
, AT91_MB_MODE_RX
);
244 set_mb_mode(priv
, AT91_MB_RX_LAST
, AT91_MB_MODE_RX_OVRWR
);
246 /* reset acceptance mask and id register */
247 for (i
= AT91_MB_RX_FIRST
; i
<= AT91_MB_RX_LAST
; i
++) {
248 at91_write(priv
, AT91_MAM(i
), 0x0 );
249 at91_write(priv
, AT91_MID(i
), AT91_MID_MIDE
);
252 /* The last 4 mailboxes are used for transmitting. */
253 for (i
= AT91_MB_TX_FIRST
; i
<= AT91_MB_TX_LAST
; i
++)
254 set_mb_mode_prio(priv
, i
, AT91_MB_MODE_TX
, 0);
256 /* Reset tx and rx helper pointers */
257 priv
->tx_next
= priv
->tx_echo
= priv
->rx_next
= 0;
260 static int at91_set_bittiming(struct net_device
*dev
)
262 const struct at91_priv
*priv
= netdev_priv(dev
);
263 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
266 reg_br
= ((priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
) ? 1 << 24 : 0) |
267 ((bt
->brp
- 1) << 16) | ((bt
->sjw
- 1) << 12) |
268 ((bt
->prop_seg
- 1) << 8) | ((bt
->phase_seg1
- 1) << 4) |
269 ((bt
->phase_seg2
- 1) << 0);
271 netdev_info(dev
, "writing AT91_BR: 0x%08x\n", reg_br
);
273 at91_write(priv
, AT91_BR
, reg_br
);
278 static int at91_get_berr_counter(const struct net_device
*dev
,
279 struct can_berr_counter
*bec
)
281 const struct at91_priv
*priv
= netdev_priv(dev
);
282 u32 reg_ecr
= at91_read(priv
, AT91_ECR
);
284 bec
->rxerr
= reg_ecr
& 0xff;
285 bec
->txerr
= reg_ecr
>> 16;
290 static void at91_chip_start(struct net_device
*dev
)
292 struct at91_priv
*priv
= netdev_priv(dev
);
295 /* disable interrupts */
296 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
299 reg_mr
= at91_read(priv
, AT91_MR
);
300 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
302 at91_set_bittiming(dev
);
303 at91_setup_mailboxes(dev
);
304 at91_transceiver_switch(priv
, 1);
307 at91_write(priv
, AT91_MR
, AT91_MR_CANEN
);
309 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
311 /* Enable interrupts */
312 reg_ier
= AT91_IRQ_MB_RX
| AT91_IRQ_ERRP
| AT91_IRQ_ERR_FRAME
;
313 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
314 at91_write(priv
, AT91_IER
, reg_ier
);
317 static void at91_chip_stop(struct net_device
*dev
, enum can_state state
)
319 struct at91_priv
*priv
= netdev_priv(dev
);
322 /* disable interrupts */
323 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
325 reg_mr
= at91_read(priv
, AT91_MR
);
326 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
328 at91_transceiver_switch(priv
, 0);
329 priv
->can
.state
= state
;
333 * theory of operation:
335 * According to the datasheet priority 0 is the highest priority, 15
336 * is the lowest. If two mailboxes have the same priority level the
337 * message of the mailbox with the lowest number is sent first.
339 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
340 * the next mailbox with prio 0, and so on, until all mailboxes are
341 * used. Then we start from the beginning with mailbox
342 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
343 * prio 1. When we reach the last mailbox with prio 15, we have to
344 * stop sending, waiting for all messages to be delivered, then start
345 * again with mailbox AT91_MB_TX_FIRST prio 0.
347 * We use the priv->tx_next as counter for the next transmission
348 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
349 * encode the mailbox number, the upper 4 bits the mailbox priority:
351 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
352 * (mb - AT91_MB_TX_FIRST);
355 static netdev_tx_t
at91_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
357 struct at91_priv
*priv
= netdev_priv(dev
);
358 struct net_device_stats
*stats
= &dev
->stats
;
359 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
360 unsigned int mb
, prio
;
361 u32 reg_mid
, reg_mcr
;
363 if (can_dropped_invalid_skb(dev
, skb
))
366 mb
= get_tx_next_mb(priv
);
367 prio
= get_tx_next_prio(priv
);
369 if (unlikely(!(at91_read(priv
, AT91_MSR(mb
)) & AT91_MSR_MRDY
))) {
370 netif_stop_queue(dev
);
372 netdev_err(dev
, "BUG! TX buffer full when queue awake!\n");
373 return NETDEV_TX_BUSY
;
376 if (cf
->can_id
& CAN_EFF_FLAG
)
377 reg_mid
= (cf
->can_id
& CAN_EFF_MASK
) | AT91_MID_MIDE
;
379 reg_mid
= (cf
->can_id
& CAN_SFF_MASK
) << 18;
381 reg_mcr
= ((cf
->can_id
& CAN_RTR_FLAG
) ? AT91_MCR_MRTR
: 0) |
382 (cf
->can_dlc
<< 16) | AT91_MCR_MTCR
;
384 /* disable MB while writing ID (see datasheet) */
385 set_mb_mode(priv
, mb
, AT91_MB_MODE_DISABLED
);
386 at91_write(priv
, AT91_MID(mb
), reg_mid
);
387 set_mb_mode_prio(priv
, mb
, AT91_MB_MODE_TX
, prio
);
389 at91_write(priv
, AT91_MDL(mb
), *(u32
*)(cf
->data
+ 0));
390 at91_write(priv
, AT91_MDH(mb
), *(u32
*)(cf
->data
+ 4));
392 /* This triggers transmission */
393 at91_write(priv
, AT91_MCR(mb
), reg_mcr
);
395 stats
->tx_bytes
+= cf
->can_dlc
;
397 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
398 can_put_echo_skb(skb
, dev
, mb
- AT91_MB_TX_FIRST
);
401 * we have to stop the queue and deliver all messages in case
402 * of a prio+mb counter wrap around. This is the case if
403 * tx_next buffer prio and mailbox equals 0.
405 * also stop the queue if next buffer is still in use
409 if (!(at91_read(priv
, AT91_MSR(get_tx_next_mb(priv
))) &
411 (priv
->tx_next
& AT91_NEXT_MASK
) == 0)
412 netif_stop_queue(dev
);
414 /* Enable interrupt for this mailbox */
415 at91_write(priv
, AT91_IER
, 1 << mb
);
421 * at91_activate_rx_low - activate lower rx mailboxes
424 * Reenables the lower mailboxes for reception of new CAN messages
426 static inline void at91_activate_rx_low(const struct at91_priv
*priv
)
428 u32 mask
= AT91_MB_RX_LOW_MASK
;
429 at91_write(priv
, AT91_TCR
, mask
);
433 * at91_activate_rx_mb - reactive single rx mailbox
435 * @mb: mailbox to reactivate
437 * Reenables given mailbox for reception of new CAN messages
439 static inline void at91_activate_rx_mb(const struct at91_priv
*priv
,
443 at91_write(priv
, AT91_TCR
, mask
);
447 * at91_rx_overflow_err - send error frame due to rx overflow
450 static void at91_rx_overflow_err(struct net_device
*dev
)
452 struct net_device_stats
*stats
= &dev
->stats
;
454 struct can_frame
*cf
;
456 netdev_dbg(dev
, "RX buffer overflow\n");
457 stats
->rx_over_errors
++;
460 skb
= alloc_can_err_skb(dev
, &cf
);
464 cf
->can_id
|= CAN_ERR_CRTL
;
465 cf
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
466 netif_receive_skb(skb
);
469 stats
->rx_bytes
+= cf
->can_dlc
;
473 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
475 * @mb: mailbox number to read from
476 * @cf: can frame where to store message
478 * Reads a CAN message from the given mailbox and stores data into
479 * given can frame. "mb" and "cf" must be valid.
481 static void at91_read_mb(struct net_device
*dev
, unsigned int mb
,
482 struct can_frame
*cf
)
484 const struct at91_priv
*priv
= netdev_priv(dev
);
485 u32 reg_msr
, reg_mid
;
487 reg_mid
= at91_read(priv
, AT91_MID(mb
));
488 if (reg_mid
& AT91_MID_MIDE
)
489 cf
->can_id
= ((reg_mid
>> 0) & CAN_EFF_MASK
) | CAN_EFF_FLAG
;
491 cf
->can_id
= (reg_mid
>> 18) & CAN_SFF_MASK
;
493 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
494 if (reg_msr
& AT91_MSR_MRTR
)
495 cf
->can_id
|= CAN_RTR_FLAG
;
496 cf
->can_dlc
= get_can_dlc((reg_msr
>> 16) & 0xf);
498 *(u32
*)(cf
->data
+ 0) = at91_read(priv
, AT91_MDL(mb
));
499 *(u32
*)(cf
->data
+ 4) = at91_read(priv
, AT91_MDH(mb
));
501 /* allow RX of extended frames */
502 at91_write(priv
, AT91_MID(mb
), AT91_MID_MIDE
);
504 if (unlikely(mb
== AT91_MB_RX_LAST
&& reg_msr
& AT91_MSR_MMI
))
505 at91_rx_overflow_err(dev
);
509 * at91_read_msg - read CAN message from mailbox
511 * @mb: mail box to read from
513 * Reads a CAN message from given mailbox, and put into linux network
514 * RX queue, does all housekeeping chores (stats, ...)
516 static void at91_read_msg(struct net_device
*dev
, unsigned int mb
)
518 struct net_device_stats
*stats
= &dev
->stats
;
519 struct can_frame
*cf
;
522 skb
= alloc_can_skb(dev
, &cf
);
523 if (unlikely(!skb
)) {
528 at91_read_mb(dev
, mb
, cf
);
529 netif_receive_skb(skb
);
532 stats
->rx_bytes
+= cf
->can_dlc
;
536 * at91_poll_rx - read multiple CAN messages from mailboxes
538 * @quota: max number of pkgs we're allowed to receive
540 * Theory of Operation:
542 * 12 of the 16 mailboxes on the chip are reserved for RX. we split
543 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
545 * Like it or not, but the chip always saves a received CAN message
546 * into the first free mailbox it finds (starting with the
547 * lowest). This makes it very difficult to read the messages in the
548 * right order from the chip. This is how we work around that problem:
550 * The first message goes into mb nr. 0 and issues an interrupt. All
551 * rx ints are disabled in the interrupt handler and a napi poll is
552 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
553 * receive another message).
556 * ______^______ __^__
558 * +-+-+-+-+-+-+-+-++-+-+-+-+
559 * |x|x|x|x|x|x|x|x|| | | | |
560 * +-+-+-+-+-+-+-+-++-+-+-+-+
561 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
562 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
564 * The variable priv->rx_next points to the next mailbox to read a
565 * message from. As long we're in the lower mailboxes we just read the
566 * mailbox but not reenable it.
568 * With completion of the last of the lower mailboxes, we reenable the
569 * whole first group, but continue to look for filled mailboxes in the
570 * upper mailboxes. Imagine the second group like overflow mailboxes,
571 * which takes CAN messages if the lower goup is full. While in the
572 * upper group we reenable the mailbox right after reading it. Giving
573 * the chip more room to store messages.
575 * After finishing we look again in the lower group if we've still
579 static int at91_poll_rx(struct net_device
*dev
, int quota
)
581 struct at91_priv
*priv
= netdev_priv(dev
);
582 u32 reg_sr
= at91_read(priv
, AT91_SR
);
583 const unsigned long *addr
= (unsigned long *)®_sr
;
587 if (priv
->rx_next
> AT91_MB_RX_LOW_LAST
&&
588 reg_sr
& AT91_MB_RX_LOW_MASK
)
590 "order of incoming frames cannot be guaranteed\n");
593 for (mb
= find_next_bit(addr
, AT91_MB_RX_NUM
, priv
->rx_next
);
594 mb
< AT91_MB_RX_NUM
&& quota
> 0;
595 reg_sr
= at91_read(priv
, AT91_SR
),
596 mb
= find_next_bit(addr
, AT91_MB_RX_NUM
, ++priv
->rx_next
)) {
597 at91_read_msg(dev
, mb
);
599 /* reactivate mailboxes */
600 if (mb
== AT91_MB_RX_LOW_LAST
)
601 /* all lower mailboxed, if just finished it */
602 at91_activate_rx_low(priv
);
603 else if (mb
> AT91_MB_RX_LOW_LAST
)
604 /* only the mailbox we read */
605 at91_activate_rx_mb(priv
, mb
);
611 /* upper group completed, look again in lower */
612 if (priv
->rx_next
> AT91_MB_RX_LOW_LAST
&&
613 quota
> 0 && mb
>= AT91_MB_RX_NUM
) {
621 static void at91_poll_err_frame(struct net_device
*dev
,
622 struct can_frame
*cf
, u32 reg_sr
)
624 struct at91_priv
*priv
= netdev_priv(dev
);
627 if (reg_sr
& AT91_IRQ_CERR
) {
628 netdev_dbg(dev
, "CERR irq\n");
629 dev
->stats
.rx_errors
++;
630 priv
->can
.can_stats
.bus_error
++;
631 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
635 if (reg_sr
& AT91_IRQ_SERR
) {
636 netdev_dbg(dev
, "SERR irq\n");
637 dev
->stats
.rx_errors
++;
638 priv
->can
.can_stats
.bus_error
++;
639 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
640 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
643 /* Acknowledgement Error */
644 if (reg_sr
& AT91_IRQ_AERR
) {
645 netdev_dbg(dev
, "AERR irq\n");
646 dev
->stats
.tx_errors
++;
647 cf
->can_id
|= CAN_ERR_ACK
;
651 if (reg_sr
& AT91_IRQ_FERR
) {
652 netdev_dbg(dev
, "FERR irq\n");
653 dev
->stats
.rx_errors
++;
654 priv
->can
.can_stats
.bus_error
++;
655 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
656 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
660 if (reg_sr
& AT91_IRQ_BERR
) {
661 netdev_dbg(dev
, "BERR irq\n");
662 dev
->stats
.tx_errors
++;
663 priv
->can
.can_stats
.bus_error
++;
664 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
665 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
669 static int at91_poll_err(struct net_device
*dev
, int quota
, u32 reg_sr
)
672 struct can_frame
*cf
;
677 skb
= alloc_can_err_skb(dev
, &cf
);
681 at91_poll_err_frame(dev
, cf
, reg_sr
);
682 netif_receive_skb(skb
);
684 dev
->stats
.rx_packets
++;
685 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
690 static int at91_poll(struct napi_struct
*napi
, int quota
)
692 struct net_device
*dev
= napi
->dev
;
693 const struct at91_priv
*priv
= netdev_priv(dev
);
694 u32 reg_sr
= at91_read(priv
, AT91_SR
);
697 if (reg_sr
& AT91_IRQ_MB_RX
)
698 work_done
+= at91_poll_rx(dev
, quota
- work_done
);
701 * The error bits are clear on read,
702 * so use saved value from irq handler.
704 reg_sr
|= priv
->reg_sr
;
705 if (reg_sr
& AT91_IRQ_ERR_FRAME
)
706 work_done
+= at91_poll_err(dev
, quota
- work_done
, reg_sr
);
708 if (work_done
< quota
) {
709 /* enable IRQs for frame errors and all mailboxes >= rx_next */
710 u32 reg_ier
= AT91_IRQ_ERR_FRAME
;
711 reg_ier
|= AT91_IRQ_MB_RX
& ~AT91_MB_RX_MASK(priv
->rx_next
);
714 at91_write(priv
, AT91_IER
, reg_ier
);
721 * theory of operation:
723 * priv->tx_echo holds the number of the oldest can_frame put for
724 * transmission into the hardware, but not yet ACKed by the CAN tx
727 * We iterate from priv->tx_echo to priv->tx_next and check if the
728 * packet has been transmitted, echo it back to the CAN framework. If
729 * we discover a not yet transmitted package, stop looking for more.
732 static void at91_irq_tx(struct net_device
*dev
, u32 reg_sr
)
734 struct at91_priv
*priv
= netdev_priv(dev
);
738 /* masking of reg_sr not needed, already done by at91_irq */
740 for (/* nix */; (priv
->tx_next
- priv
->tx_echo
) > 0; priv
->tx_echo
++) {
741 mb
= get_tx_echo_mb(priv
);
743 /* no event in mailbox? */
744 if (!(reg_sr
& (1 << mb
)))
747 /* Disable irq for this TX mailbox */
748 at91_write(priv
, AT91_IDR
, 1 << mb
);
751 * only echo if mailbox signals us a transfer
752 * complete (MSR_MRDY). Otherwise it's a tansfer
753 * abort. "can_bus_off()" takes care about the skbs
754 * parked in the echo queue.
756 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
757 if (likely(reg_msr
& AT91_MSR_MRDY
&&
758 ~reg_msr
& AT91_MSR_MABT
)) {
759 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
760 can_get_echo_skb(dev
, mb
- AT91_MB_TX_FIRST
);
761 dev
->stats
.tx_packets
++;
766 * restart queue if we don't have a wrap around but restart if
767 * we get a TX int for the last can frame directly before a
770 if ((priv
->tx_next
& AT91_NEXT_MASK
) != 0 ||
771 (priv
->tx_echo
& AT91_NEXT_MASK
) == 0)
772 netif_wake_queue(dev
);
775 static void at91_irq_err_state(struct net_device
*dev
,
776 struct can_frame
*cf
, enum can_state new_state
)
778 struct at91_priv
*priv
= netdev_priv(dev
);
779 u32 reg_idr
= 0, reg_ier
= 0;
780 struct can_berr_counter bec
;
782 at91_get_berr_counter(dev
, &bec
);
784 switch (priv
->can
.state
) {
785 case CAN_STATE_ERROR_ACTIVE
:
788 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
789 * => : there was a warning int
791 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
792 new_state
<= CAN_STATE_BUS_OFF
) {
793 netdev_dbg(dev
, "Error Warning IRQ\n");
794 priv
->can
.can_stats
.error_warning
++;
796 cf
->can_id
|= CAN_ERR_CRTL
;
797 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
798 CAN_ERR_CRTL_TX_WARNING
:
799 CAN_ERR_CRTL_RX_WARNING
;
801 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
803 * from: ERROR_ACTIVE, ERROR_WARNING
804 * to : ERROR_PASSIVE, BUS_OFF
805 * => : error passive int
807 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
808 new_state
<= CAN_STATE_BUS_OFF
) {
809 netdev_dbg(dev
, "Error Passive IRQ\n");
810 priv
->can
.can_stats
.error_passive
++;
812 cf
->can_id
|= CAN_ERR_CRTL
;
813 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
814 CAN_ERR_CRTL_TX_PASSIVE
:
815 CAN_ERR_CRTL_RX_PASSIVE
;
818 case CAN_STATE_BUS_OFF
:
821 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
823 if (new_state
<= CAN_STATE_ERROR_PASSIVE
) {
824 cf
->can_id
|= CAN_ERR_RESTARTED
;
826 netdev_dbg(dev
, "restarted\n");
827 priv
->can
.can_stats
.restarts
++;
829 netif_carrier_on(dev
);
830 netif_wake_queue(dev
);
838 /* process state changes depending on the new state */
840 case CAN_STATE_ERROR_ACTIVE
:
842 * actually we want to enable AT91_IRQ_WARN here, but
843 * it screws up the system under certain
844 * circumstances. so just enable AT91_IRQ_ERRP, thus
847 netdev_dbg(dev
, "Error Active\n");
848 cf
->can_id
|= CAN_ERR_PROT
;
849 cf
->data
[2] = CAN_ERR_PROT_ACTIVE
;
850 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
851 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
852 reg_ier
= AT91_IRQ_ERRP
;
854 case CAN_STATE_ERROR_PASSIVE
:
855 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_ERRP
;
856 reg_ier
= AT91_IRQ_BOFF
;
858 case CAN_STATE_BUS_OFF
:
859 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_ERRP
|
860 AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
863 cf
->can_id
|= CAN_ERR_BUSOFF
;
865 netdev_dbg(dev
, "bus-off\n");
866 netif_carrier_off(dev
);
867 priv
->can
.can_stats
.bus_off
++;
869 /* turn off chip, if restart is disabled */
870 if (!priv
->can
.restart_ms
) {
871 at91_chip_stop(dev
, CAN_STATE_BUS_OFF
);
879 at91_write(priv
, AT91_IDR
, reg_idr
);
880 at91_write(priv
, AT91_IER
, reg_ier
);
883 static void at91_irq_err(struct net_device
*dev
)
885 struct at91_priv
*priv
= netdev_priv(dev
);
887 struct can_frame
*cf
;
888 enum can_state new_state
;
891 reg_sr
= at91_read(priv
, AT91_SR
);
893 /* we need to look at the unmasked reg_sr */
894 if (unlikely(reg_sr
& AT91_IRQ_BOFF
))
895 new_state
= CAN_STATE_BUS_OFF
;
896 else if (unlikely(reg_sr
& AT91_IRQ_ERRP
))
897 new_state
= CAN_STATE_ERROR_PASSIVE
;
898 else if (unlikely(reg_sr
& AT91_IRQ_WARN
))
899 new_state
= CAN_STATE_ERROR_WARNING
;
900 else if (likely(reg_sr
& AT91_IRQ_ERRA
))
901 new_state
= CAN_STATE_ERROR_ACTIVE
;
903 netdev_err(dev
, "BUG! hardware in undefined state\n");
907 /* state hasn't changed */
908 if (likely(new_state
== priv
->can
.state
))
911 skb
= alloc_can_err_skb(dev
, &cf
);
915 at91_irq_err_state(dev
, cf
, new_state
);
918 dev
->stats
.rx_packets
++;
919 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
921 priv
->can
.state
= new_state
;
927 static irqreturn_t
at91_irq(int irq
, void *dev_id
)
929 struct net_device
*dev
= dev_id
;
930 struct at91_priv
*priv
= netdev_priv(dev
);
931 irqreturn_t handled
= IRQ_NONE
;
934 reg_sr
= at91_read(priv
, AT91_SR
);
935 reg_imr
= at91_read(priv
, AT91_IMR
);
937 /* Ignore masked interrupts */
942 handled
= IRQ_HANDLED
;
944 /* Receive or error interrupt? -> napi */
945 if (reg_sr
& (AT91_IRQ_MB_RX
| AT91_IRQ_ERR_FRAME
)) {
947 * The error bits are clear on read,
948 * save for later use.
950 priv
->reg_sr
= reg_sr
;
951 at91_write(priv
, AT91_IDR
,
952 AT91_IRQ_MB_RX
| AT91_IRQ_ERR_FRAME
);
953 napi_schedule(&priv
->napi
);
956 /* Transmission complete interrupt */
957 if (reg_sr
& AT91_IRQ_MB_TX
)
958 at91_irq_tx(dev
, reg_sr
);
966 static int at91_open(struct net_device
*dev
)
968 struct at91_priv
*priv
= netdev_priv(dev
);
971 clk_enable(priv
->clk
);
973 /* check or determine and set bittime */
974 err
= open_candev(dev
);
978 /* register interrupt handler */
979 if (request_irq(dev
->irq
, at91_irq
, IRQF_SHARED
,
985 /* start chip and queuing */
986 at91_chip_start(dev
);
987 napi_enable(&priv
->napi
);
988 netif_start_queue(dev
);
995 clk_disable(priv
->clk
);
1001 * stop CAN bus activity
1003 static int at91_close(struct net_device
*dev
)
1005 struct at91_priv
*priv
= netdev_priv(dev
);
1007 netif_stop_queue(dev
);
1008 napi_disable(&priv
->napi
);
1009 at91_chip_stop(dev
, CAN_STATE_STOPPED
);
1011 free_irq(dev
->irq
, dev
);
1012 clk_disable(priv
->clk
);
1019 static int at91_set_mode(struct net_device
*dev
, enum can_mode mode
)
1022 case CAN_MODE_START
:
1023 at91_chip_start(dev
);
1024 netif_wake_queue(dev
);
1034 static const struct net_device_ops at91_netdev_ops
= {
1035 .ndo_open
= at91_open
,
1036 .ndo_stop
= at91_close
,
1037 .ndo_start_xmit
= at91_start_xmit
,
1040 static int __devinit
at91_can_probe(struct platform_device
*pdev
)
1042 struct net_device
*dev
;
1043 struct at91_priv
*priv
;
1044 struct resource
*res
;
1049 clk
= clk_get(&pdev
->dev
, "can_clk");
1051 dev_err(&pdev
->dev
, "no clock defined\n");
1056 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1057 irq
= platform_get_irq(pdev
, 0);
1058 if (!res
|| irq
<= 0) {
1063 if (!request_mem_region(res
->start
,
1070 addr
= ioremap_nocache(res
->start
, resource_size(res
));
1076 dev
= alloc_candev(sizeof(struct at91_priv
), AT91_MB_TX_NUM
);
1082 dev
->netdev_ops
= &at91_netdev_ops
;
1084 dev
->flags
|= IFF_ECHO
;
1086 priv
= netdev_priv(dev
);
1087 priv
->can
.clock
.freq
= clk_get_rate(clk
);
1088 priv
->can
.bittiming_const
= &at91_bittiming_const
;
1089 priv
->can
.do_set_mode
= at91_set_mode
;
1090 priv
->can
.do_get_berr_counter
= at91_get_berr_counter
;
1091 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
;
1092 priv
->reg_base
= addr
;
1095 priv
->pdata
= pdev
->dev
.platform_data
;
1097 netif_napi_add(dev
, &priv
->napi
, at91_poll
, AT91_NAPI_WEIGHT
);
1099 dev_set_drvdata(&pdev
->dev
, dev
);
1100 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1102 err
= register_candev(dev
);
1104 dev_err(&pdev
->dev
, "registering netdev failed\n");
1108 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%d)\n",
1109 priv
->reg_base
, dev
->irq
);
1118 release_mem_region(res
->start
, resource_size(res
));
1125 static int __devexit
at91_can_remove(struct platform_device
*pdev
)
1127 struct net_device
*dev
= platform_get_drvdata(pdev
);
1128 struct at91_priv
*priv
= netdev_priv(dev
);
1129 struct resource
*res
;
1131 unregister_netdev(dev
);
1133 platform_set_drvdata(pdev
, NULL
);
1135 iounmap(priv
->reg_base
);
1137 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1138 release_mem_region(res
->start
, resource_size(res
));
1147 static struct platform_driver at91_can_driver
= {
1148 .probe
= at91_can_probe
,
1149 .remove
= __devexit_p(at91_can_remove
),
1151 .name
= KBUILD_MODNAME
,
1152 .owner
= THIS_MODULE
,
1156 static int __init
at91_can_module_init(void)
1158 return platform_driver_register(&at91_can_driver
);
1161 static void __exit
at91_can_module_exit(void)
1163 platform_driver_unregister(&at91_can_driver
);
1166 module_init(at91_can_module_init
);
1167 module_exit(at91_can_module_exit
);
1169 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1170 MODULE_LICENSE("GPL v2");
1171 MODULE_DESCRIPTION(KBUILD_MODNAME
" CAN netdevice driver");