2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/platform/flexcan.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/pinctrl/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN error and status register (ESR) bits */
96 #define FLEXCAN_ESR_TWRN_INT BIT(17)
97 #define FLEXCAN_ESR_RWRN_INT BIT(16)
98 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
99 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
100 #define FLEXCAN_ESR_ACK_ERR BIT(13)
101 #define FLEXCAN_ESR_CRC_ERR BIT(12)
102 #define FLEXCAN_ESR_FRM_ERR BIT(11)
103 #define FLEXCAN_ESR_STF_ERR BIT(10)
104 #define FLEXCAN_ESR_TX_WRN BIT(9)
105 #define FLEXCAN_ESR_RX_WRN BIT(8)
106 #define FLEXCAN_ESR_IDLE BIT(7)
107 #define FLEXCAN_ESR_TXRX BIT(6)
108 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112 #define FLEXCAN_ESR_BOFF_INT BIT(2)
113 #define FLEXCAN_ESR_ERR_INT BIT(1)
114 #define FLEXCAN_ESR_WAK_INT BIT(0)
115 #define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119 #define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121 #define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
123 #define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
127 /* FLEXCAN interrupt flag register (IFLAG) bits */
128 #define FLEXCAN_TX_BUF_ID 8
129 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
130 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133 #define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
137 /* FLEXCAN message buffers */
138 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139 #define FLEXCAN_MB_CNT_SRR BIT(22)
140 #define FLEXCAN_MB_CNT_IDE BIT(21)
141 #define FLEXCAN_MB_CNT_RTR BIT(20)
142 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
145 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
147 /* Structure of the message buffer */
154 /* Structure of the hardware registers */
155 struct flexcan_regs
{
158 u32 timer
; /* 0x08 */
159 u32 _reserved1
; /* 0x0c */
160 u32 rxgmask
; /* 0x10 */
161 u32 rx14mask
; /* 0x14 */
162 u32 rx15mask
; /* 0x18 */
165 u32 imask2
; /* 0x24 */
166 u32 imask1
; /* 0x28 */
167 u32 iflag2
; /* 0x2c */
168 u32 iflag1
; /* 0x30 */
171 u32 imeur
; /* 0x3c */
174 u32 rxfgmask
; /* 0x48 */
175 u32 rxfir
; /* 0x4c */
177 struct flexcan_mb cantxfg
[64];
180 struct flexcan_devtype_data
{
181 u32 hw_ver
; /* hardware controller version */
184 struct flexcan_priv
{
186 struct net_device
*dev
;
187 struct napi_struct napi
;
191 u32 reg_ctrl_default
;
195 struct flexcan_platform_data
*pdata
;
196 const struct flexcan_devtype_data
*devtype_data
;
199 static struct flexcan_devtype_data fsl_p1010_devtype_data
= {
203 static struct flexcan_devtype_data fsl_imx6q_devtype_data
= {
207 static const struct can_bittiming_const flexcan_bittiming_const
= {
220 * Abstract off the read/write for arm versus ppc.
222 #if defined(__BIG_ENDIAN)
223 static inline u32
flexcan_read(void __iomem
*addr
)
225 return in_be32(addr
);
228 static inline void flexcan_write(u32 val
, void __iomem
*addr
)
233 static inline u32
flexcan_read(void __iomem
*addr
)
238 static inline void flexcan_write(u32 val
, void __iomem
*addr
)
245 * Swtich transceiver on or off
247 static void flexcan_transceiver_switch(const struct flexcan_priv
*priv
, int on
)
249 if (priv
->pdata
&& priv
->pdata
->transceiver_switch
)
250 priv
->pdata
->transceiver_switch(on
);
253 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv
*priv
,
256 return (priv
->can
.ctrlmode
& CAN_CTRLMODE_BERR_REPORTING
) &&
257 (reg_esr
& FLEXCAN_ESR_ERR_BUS
);
260 static inline void flexcan_chip_enable(struct flexcan_priv
*priv
)
262 struct flexcan_regs __iomem
*regs
= priv
->base
;
265 reg
= flexcan_read(®s
->mcr
);
266 reg
&= ~FLEXCAN_MCR_MDIS
;
267 flexcan_write(reg
, ®s
->mcr
);
272 static inline void flexcan_chip_disable(struct flexcan_priv
*priv
)
274 struct flexcan_regs __iomem
*regs
= priv
->base
;
277 reg
= flexcan_read(®s
->mcr
);
278 reg
|= FLEXCAN_MCR_MDIS
;
279 flexcan_write(reg
, ®s
->mcr
);
282 static int flexcan_get_berr_counter(const struct net_device
*dev
,
283 struct can_berr_counter
*bec
)
285 const struct flexcan_priv
*priv
= netdev_priv(dev
);
286 struct flexcan_regs __iomem
*regs
= priv
->base
;
287 u32 reg
= flexcan_read(®s
->ecr
);
289 bec
->txerr
= (reg
>> 0) & 0xff;
290 bec
->rxerr
= (reg
>> 8) & 0xff;
295 static int flexcan_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
297 const struct flexcan_priv
*priv
= netdev_priv(dev
);
298 struct flexcan_regs __iomem
*regs
= priv
->base
;
299 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
301 u32 ctrl
= FLEXCAN_MB_CNT_CODE(0xc) | (cf
->can_dlc
<< 16);
303 if (can_dropped_invalid_skb(dev
, skb
))
306 netif_stop_queue(dev
);
308 if (cf
->can_id
& CAN_EFF_FLAG
) {
309 can_id
= cf
->can_id
& CAN_EFF_MASK
;
310 ctrl
|= FLEXCAN_MB_CNT_IDE
| FLEXCAN_MB_CNT_SRR
;
312 can_id
= (cf
->can_id
& CAN_SFF_MASK
) << 18;
315 if (cf
->can_id
& CAN_RTR_FLAG
)
316 ctrl
|= FLEXCAN_MB_CNT_RTR
;
318 if (cf
->can_dlc
> 0) {
319 u32 data
= be32_to_cpup((__be32
*)&cf
->data
[0]);
320 flexcan_write(data
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].data
[0]);
322 if (cf
->can_dlc
> 3) {
323 u32 data
= be32_to_cpup((__be32
*)&cf
->data
[4]);
324 flexcan_write(data
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].data
[1]);
327 can_put_echo_skb(skb
, dev
, 0);
329 flexcan_write(can_id
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].can_id
);
330 flexcan_write(ctrl
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].can_ctrl
);
335 static void do_bus_err(struct net_device
*dev
,
336 struct can_frame
*cf
, u32 reg_esr
)
338 struct flexcan_priv
*priv
= netdev_priv(dev
);
339 int rx_errors
= 0, tx_errors
= 0;
341 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
343 if (reg_esr
& FLEXCAN_ESR_BIT1_ERR
) {
344 netdev_dbg(dev
, "BIT1_ERR irq\n");
345 cf
->data
[2] |= CAN_ERR_PROT_BIT1
;
348 if (reg_esr
& FLEXCAN_ESR_BIT0_ERR
) {
349 netdev_dbg(dev
, "BIT0_ERR irq\n");
350 cf
->data
[2] |= CAN_ERR_PROT_BIT0
;
353 if (reg_esr
& FLEXCAN_ESR_ACK_ERR
) {
354 netdev_dbg(dev
, "ACK_ERR irq\n");
355 cf
->can_id
|= CAN_ERR_ACK
;
356 cf
->data
[3] |= CAN_ERR_PROT_LOC_ACK
;
359 if (reg_esr
& FLEXCAN_ESR_CRC_ERR
) {
360 netdev_dbg(dev
, "CRC_ERR irq\n");
361 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
362 cf
->data
[3] |= CAN_ERR_PROT_LOC_CRC_SEQ
;
365 if (reg_esr
& FLEXCAN_ESR_FRM_ERR
) {
366 netdev_dbg(dev
, "FRM_ERR irq\n");
367 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
370 if (reg_esr
& FLEXCAN_ESR_STF_ERR
) {
371 netdev_dbg(dev
, "STF_ERR irq\n");
372 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
376 priv
->can
.can_stats
.bus_error
++;
378 dev
->stats
.rx_errors
++;
380 dev
->stats
.tx_errors
++;
383 static int flexcan_poll_bus_err(struct net_device
*dev
, u32 reg_esr
)
386 struct can_frame
*cf
;
388 skb
= alloc_can_err_skb(dev
, &cf
);
392 do_bus_err(dev
, cf
, reg_esr
);
393 netif_receive_skb(skb
);
395 dev
->stats
.rx_packets
++;
396 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
401 static void do_state(struct net_device
*dev
,
402 struct can_frame
*cf
, enum can_state new_state
)
404 struct flexcan_priv
*priv
= netdev_priv(dev
);
405 struct can_berr_counter bec
;
407 flexcan_get_berr_counter(dev
, &bec
);
409 switch (priv
->can
.state
) {
410 case CAN_STATE_ERROR_ACTIVE
:
413 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
414 * => : there was a warning int
416 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
417 new_state
<= CAN_STATE_BUS_OFF
) {
418 netdev_dbg(dev
, "Error Warning IRQ\n");
419 priv
->can
.can_stats
.error_warning
++;
421 cf
->can_id
|= CAN_ERR_CRTL
;
422 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
423 CAN_ERR_CRTL_TX_WARNING
:
424 CAN_ERR_CRTL_RX_WARNING
;
426 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
428 * from: ERROR_ACTIVE, ERROR_WARNING
429 * to : ERROR_PASSIVE, BUS_OFF
430 * => : error passive int
432 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
433 new_state
<= CAN_STATE_BUS_OFF
) {
434 netdev_dbg(dev
, "Error Passive IRQ\n");
435 priv
->can
.can_stats
.error_passive
++;
437 cf
->can_id
|= CAN_ERR_CRTL
;
438 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
439 CAN_ERR_CRTL_TX_PASSIVE
:
440 CAN_ERR_CRTL_RX_PASSIVE
;
443 case CAN_STATE_BUS_OFF
:
444 netdev_err(dev
, "BUG! "
445 "hardware recovered automatically from BUS_OFF\n");
451 /* process state changes depending on the new state */
453 case CAN_STATE_ERROR_ACTIVE
:
454 netdev_dbg(dev
, "Error Active\n");
455 cf
->can_id
|= CAN_ERR_PROT
;
456 cf
->data
[2] = CAN_ERR_PROT_ACTIVE
;
458 case CAN_STATE_BUS_OFF
:
459 cf
->can_id
|= CAN_ERR_BUSOFF
;
467 static int flexcan_poll_state(struct net_device
*dev
, u32 reg_esr
)
469 struct flexcan_priv
*priv
= netdev_priv(dev
);
471 struct can_frame
*cf
;
472 enum can_state new_state
;
475 flt
= reg_esr
& FLEXCAN_ESR_FLT_CONF_MASK
;
476 if (likely(flt
== FLEXCAN_ESR_FLT_CONF_ACTIVE
)) {
477 if (likely(!(reg_esr
& (FLEXCAN_ESR_TX_WRN
|
478 FLEXCAN_ESR_RX_WRN
))))
479 new_state
= CAN_STATE_ERROR_ACTIVE
;
481 new_state
= CAN_STATE_ERROR_WARNING
;
482 } else if (unlikely(flt
== FLEXCAN_ESR_FLT_CONF_PASSIVE
))
483 new_state
= CAN_STATE_ERROR_PASSIVE
;
485 new_state
= CAN_STATE_BUS_OFF
;
487 /* state hasn't changed */
488 if (likely(new_state
== priv
->can
.state
))
491 skb
= alloc_can_err_skb(dev
, &cf
);
495 do_state(dev
, cf
, new_state
);
496 priv
->can
.state
= new_state
;
497 netif_receive_skb(skb
);
499 dev
->stats
.rx_packets
++;
500 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
505 static void flexcan_read_fifo(const struct net_device
*dev
,
506 struct can_frame
*cf
)
508 const struct flexcan_priv
*priv
= netdev_priv(dev
);
509 struct flexcan_regs __iomem
*regs
= priv
->base
;
510 struct flexcan_mb __iomem
*mb
= ®s
->cantxfg
[0];
511 u32 reg_ctrl
, reg_id
;
513 reg_ctrl
= flexcan_read(&mb
->can_ctrl
);
514 reg_id
= flexcan_read(&mb
->can_id
);
515 if (reg_ctrl
& FLEXCAN_MB_CNT_IDE
)
516 cf
->can_id
= ((reg_id
>> 0) & CAN_EFF_MASK
) | CAN_EFF_FLAG
;
518 cf
->can_id
= (reg_id
>> 18) & CAN_SFF_MASK
;
520 if (reg_ctrl
& FLEXCAN_MB_CNT_RTR
)
521 cf
->can_id
|= CAN_RTR_FLAG
;
522 cf
->can_dlc
= get_can_dlc((reg_ctrl
>> 16) & 0xf);
524 *(__be32
*)(cf
->data
+ 0) = cpu_to_be32(flexcan_read(&mb
->data
[0]));
525 *(__be32
*)(cf
->data
+ 4) = cpu_to_be32(flexcan_read(&mb
->data
[1]));
528 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
, ®s
->iflag1
);
529 flexcan_read(®s
->timer
);
532 static int flexcan_read_frame(struct net_device
*dev
)
534 struct net_device_stats
*stats
= &dev
->stats
;
535 struct can_frame
*cf
;
538 skb
= alloc_can_skb(dev
, &cf
);
539 if (unlikely(!skb
)) {
544 flexcan_read_fifo(dev
, cf
);
545 netif_receive_skb(skb
);
548 stats
->rx_bytes
+= cf
->can_dlc
;
553 static int flexcan_poll(struct napi_struct
*napi
, int quota
)
555 struct net_device
*dev
= napi
->dev
;
556 const struct flexcan_priv
*priv
= netdev_priv(dev
);
557 struct flexcan_regs __iomem
*regs
= priv
->base
;
558 u32 reg_iflag1
, reg_esr
;
562 * The error bits are cleared on read,
563 * use saved value from irq handler.
565 reg_esr
= flexcan_read(®s
->esr
) | priv
->reg_esr
;
567 /* handle state changes */
568 work_done
+= flexcan_poll_state(dev
, reg_esr
);
571 reg_iflag1
= flexcan_read(®s
->iflag1
);
572 while (reg_iflag1
& FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
&&
574 work_done
+= flexcan_read_frame(dev
);
575 reg_iflag1
= flexcan_read(®s
->iflag1
);
578 /* report bus errors */
579 if (flexcan_has_and_handle_berr(priv
, reg_esr
) && work_done
< quota
)
580 work_done
+= flexcan_poll_bus_err(dev
, reg_esr
);
582 if (work_done
< quota
) {
585 flexcan_write(FLEXCAN_IFLAG_DEFAULT
, ®s
->imask1
);
586 flexcan_write(priv
->reg_ctrl_default
, ®s
->ctrl
);
592 static irqreturn_t
flexcan_irq(int irq
, void *dev_id
)
594 struct net_device
*dev
= dev_id
;
595 struct net_device_stats
*stats
= &dev
->stats
;
596 struct flexcan_priv
*priv
= netdev_priv(dev
);
597 struct flexcan_regs __iomem
*regs
= priv
->base
;
598 u32 reg_iflag1
, reg_esr
;
600 reg_iflag1
= flexcan_read(®s
->iflag1
);
601 reg_esr
= flexcan_read(®s
->esr
);
602 /* ACK all bus error and state change IRQ sources */
603 if (reg_esr
& FLEXCAN_ESR_ALL_INT
)
604 flexcan_write(reg_esr
& FLEXCAN_ESR_ALL_INT
, ®s
->esr
);
607 * schedule NAPI in case of:
610 * - bus error IRQ and bus error reporting is activated
612 if ((reg_iflag1
& FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
) ||
613 (reg_esr
& FLEXCAN_ESR_ERR_STATE
) ||
614 flexcan_has_and_handle_berr(priv
, reg_esr
)) {
616 * The error bits are cleared on read,
617 * save them for later use.
619 priv
->reg_esr
= reg_esr
& FLEXCAN_ESR_ERR_BUS
;
620 flexcan_write(FLEXCAN_IFLAG_DEFAULT
&
621 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
, ®s
->imask1
);
622 flexcan_write(priv
->reg_ctrl_default
& ~FLEXCAN_CTRL_ERR_ALL
,
624 napi_schedule(&priv
->napi
);
628 if (reg_iflag1
& FLEXCAN_IFLAG_RX_FIFO_OVERFLOW
) {
629 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW
, ®s
->iflag1
);
630 dev
->stats
.rx_over_errors
++;
631 dev
->stats
.rx_errors
++;
634 /* transmission complete interrupt */
635 if (reg_iflag1
& (1 << FLEXCAN_TX_BUF_ID
)) {
636 stats
->tx_bytes
+= can_get_echo_skb(dev
, 0);
638 flexcan_write((1 << FLEXCAN_TX_BUF_ID
), ®s
->iflag1
);
639 netif_wake_queue(dev
);
645 static void flexcan_set_bittiming(struct net_device
*dev
)
647 const struct flexcan_priv
*priv
= netdev_priv(dev
);
648 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
649 struct flexcan_regs __iomem
*regs
= priv
->base
;
652 reg
= flexcan_read(®s
->ctrl
);
653 reg
&= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
654 FLEXCAN_CTRL_RJW(0x3) |
655 FLEXCAN_CTRL_PSEG1(0x7) |
656 FLEXCAN_CTRL_PSEG2(0x7) |
657 FLEXCAN_CTRL_PROPSEG(0x7) |
662 reg
|= FLEXCAN_CTRL_PRESDIV(bt
->brp
- 1) |
663 FLEXCAN_CTRL_PSEG1(bt
->phase_seg1
- 1) |
664 FLEXCAN_CTRL_PSEG2(bt
->phase_seg2
- 1) |
665 FLEXCAN_CTRL_RJW(bt
->sjw
- 1) |
666 FLEXCAN_CTRL_PROPSEG(bt
->prop_seg
- 1);
668 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
)
669 reg
|= FLEXCAN_CTRL_LPB
;
670 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
)
671 reg
|= FLEXCAN_CTRL_LOM
;
672 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
)
673 reg
|= FLEXCAN_CTRL_SMP
;
675 netdev_info(dev
, "writing ctrl=0x%08x\n", reg
);
676 flexcan_write(reg
, ®s
->ctrl
);
678 /* print chip status */
679 netdev_dbg(dev
, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__
,
680 flexcan_read(®s
->mcr
), flexcan_read(®s
->ctrl
));
686 * this functions is entered with clocks enabled
689 static int flexcan_chip_start(struct net_device
*dev
)
691 struct flexcan_priv
*priv
= netdev_priv(dev
);
692 struct flexcan_regs __iomem
*regs
= priv
->base
;
695 u32 reg_mcr
, reg_ctrl
;
698 flexcan_chip_enable(priv
);
701 flexcan_write(FLEXCAN_MCR_SOFTRST
, ®s
->mcr
);
704 reg_mcr
= flexcan_read(®s
->mcr
);
705 if (reg_mcr
& FLEXCAN_MCR_SOFTRST
) {
706 netdev_err(dev
, "Failed to softreset can module (mcr=0x%08x)\n",
712 flexcan_set_bittiming(dev
);
720 * only supervisor access
726 reg_mcr
= flexcan_read(®s
->mcr
);
727 reg_mcr
|= FLEXCAN_MCR_FRZ
| FLEXCAN_MCR_FEN
| FLEXCAN_MCR_HALT
|
728 FLEXCAN_MCR_SUPV
| FLEXCAN_MCR_WRN_EN
|
729 FLEXCAN_MCR_IDAM_C
| FLEXCAN_MCR_SRX_DIS
;
730 netdev_dbg(dev
, "%s: writing mcr=0x%08x", __func__
, reg_mcr
);
731 flexcan_write(reg_mcr
, ®s
->mcr
);
736 * disable timer sync feature
738 * disable auto busoff recovery
739 * transmit lowest buffer first
741 * enable tx and rx warning interrupt
742 * enable bus off interrupt
743 * (== FLEXCAN_CTRL_ERR_STATE)
745 * _note_: we enable the "error interrupt"
746 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
747 * warning or bus passive interrupts.
749 reg_ctrl
= flexcan_read(®s
->ctrl
);
750 reg_ctrl
&= ~FLEXCAN_CTRL_TSYN
;
751 reg_ctrl
|= FLEXCAN_CTRL_BOFF_REC
| FLEXCAN_CTRL_LBUF
|
752 FLEXCAN_CTRL_ERR_STATE
| FLEXCAN_CTRL_ERR_MSK
;
754 /* save for later use */
755 priv
->reg_ctrl_default
= reg_ctrl
;
756 netdev_dbg(dev
, "%s: writing ctrl=0x%08x", __func__
, reg_ctrl
);
757 flexcan_write(reg_ctrl
, ®s
->ctrl
);
759 for (i
= 0; i
< ARRAY_SIZE(regs
->cantxfg
); i
++) {
760 flexcan_write(0, ®s
->cantxfg
[i
].can_ctrl
);
761 flexcan_write(0, ®s
->cantxfg
[i
].can_id
);
762 flexcan_write(0, ®s
->cantxfg
[i
].data
[0]);
763 flexcan_write(0, ®s
->cantxfg
[i
].data
[1]);
765 /* put MB into rx queue */
766 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
767 ®s
->cantxfg
[i
].can_ctrl
);
770 /* acceptance mask/acceptance code (accept everything) */
771 flexcan_write(0x0, ®s
->rxgmask
);
772 flexcan_write(0x0, ®s
->rx14mask
);
773 flexcan_write(0x0, ®s
->rx15mask
);
775 if (priv
->devtype_data
->hw_ver
>= 10)
776 flexcan_write(0x0, ®s
->rxfgmask
);
778 flexcan_transceiver_switch(priv
, 1);
780 /* synchronize with the can bus */
781 reg_mcr
= flexcan_read(®s
->mcr
);
782 reg_mcr
&= ~FLEXCAN_MCR_HALT
;
783 flexcan_write(reg_mcr
, ®s
->mcr
);
785 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
787 /* enable FIFO interrupts */
788 flexcan_write(FLEXCAN_IFLAG_DEFAULT
, ®s
->imask1
);
790 /* print chip status */
791 netdev_dbg(dev
, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__
,
792 flexcan_read(®s
->mcr
), flexcan_read(®s
->ctrl
));
797 flexcan_chip_disable(priv
);
804 * this functions is entered with clocks enabled
807 static void flexcan_chip_stop(struct net_device
*dev
)
809 struct flexcan_priv
*priv
= netdev_priv(dev
);
810 struct flexcan_regs __iomem
*regs
= priv
->base
;
813 /* Disable all interrupts */
814 flexcan_write(0, ®s
->imask1
);
816 /* Disable + halt module */
817 reg
= flexcan_read(®s
->mcr
);
818 reg
|= FLEXCAN_MCR_MDIS
| FLEXCAN_MCR_HALT
;
819 flexcan_write(reg
, ®s
->mcr
);
821 flexcan_transceiver_switch(priv
, 0);
822 priv
->can
.state
= CAN_STATE_STOPPED
;
827 static int flexcan_open(struct net_device
*dev
)
829 struct flexcan_priv
*priv
= netdev_priv(dev
);
832 clk_prepare_enable(priv
->clk_ipg
);
833 clk_prepare_enable(priv
->clk_per
);
835 err
= open_candev(dev
);
839 err
= request_irq(dev
->irq
, flexcan_irq
, IRQF_SHARED
, dev
->name
, dev
);
843 /* start chip and queuing */
844 err
= flexcan_chip_start(dev
);
847 napi_enable(&priv
->napi
);
848 netif_start_queue(dev
);
855 clk_disable_unprepare(priv
->clk_per
);
856 clk_disable_unprepare(priv
->clk_ipg
);
861 static int flexcan_close(struct net_device
*dev
)
863 struct flexcan_priv
*priv
= netdev_priv(dev
);
865 netif_stop_queue(dev
);
866 napi_disable(&priv
->napi
);
867 flexcan_chip_stop(dev
);
869 free_irq(dev
->irq
, dev
);
870 clk_disable_unprepare(priv
->clk_per
);
871 clk_disable_unprepare(priv
->clk_ipg
);
878 static int flexcan_set_mode(struct net_device
*dev
, enum can_mode mode
)
884 err
= flexcan_chip_start(dev
);
888 netif_wake_queue(dev
);
898 static const struct net_device_ops flexcan_netdev_ops
= {
899 .ndo_open
= flexcan_open
,
900 .ndo_stop
= flexcan_close
,
901 .ndo_start_xmit
= flexcan_start_xmit
,
904 static int __devinit
register_flexcandev(struct net_device
*dev
)
906 struct flexcan_priv
*priv
= netdev_priv(dev
);
907 struct flexcan_regs __iomem
*regs
= priv
->base
;
910 clk_prepare_enable(priv
->clk_ipg
);
911 clk_prepare_enable(priv
->clk_per
);
913 /* select "bus clock", chip must be disabled */
914 flexcan_chip_disable(priv
);
915 reg
= flexcan_read(®s
->ctrl
);
916 reg
|= FLEXCAN_CTRL_CLK_SRC
;
917 flexcan_write(reg
, ®s
->ctrl
);
919 flexcan_chip_enable(priv
);
921 /* set freeze, halt and activate FIFO, restrict register access */
922 reg
= flexcan_read(®s
->mcr
);
923 reg
|= FLEXCAN_MCR_FRZ
| FLEXCAN_MCR_HALT
|
924 FLEXCAN_MCR_FEN
| FLEXCAN_MCR_SUPV
;
925 flexcan_write(reg
, ®s
->mcr
);
928 * Currently we only support newer versions of this core
929 * featuring a RX FIFO. Older cores found on some Coldfire
930 * derivates are not yet supported.
932 reg
= flexcan_read(®s
->mcr
);
933 if (!(reg
& FLEXCAN_MCR_FEN
)) {
934 netdev_err(dev
, "Could not enable RX FIFO, unsupported core\n");
939 err
= register_candev(dev
);
942 /* disable core and turn off clocks */
943 flexcan_chip_disable(priv
);
944 clk_disable_unprepare(priv
->clk_per
);
945 clk_disable_unprepare(priv
->clk_ipg
);
950 static void __devexit
unregister_flexcandev(struct net_device
*dev
)
952 unregister_candev(dev
);
955 static const struct of_device_id flexcan_of_match
[] = {
956 { .compatible
= "fsl,p1010-flexcan", .data
= &fsl_p1010_devtype_data
, },
957 { .compatible
= "fsl,imx6q-flexcan", .data
= &fsl_imx6q_devtype_data
, },
961 static const struct platform_device_id flexcan_id_table
[] = {
962 { .name
= "flexcan", .driver_data
= (kernel_ulong_t
)&fsl_p1010_devtype_data
, },
966 static int __devinit
flexcan_probe(struct platform_device
*pdev
)
968 const struct of_device_id
*of_id
;
969 const struct flexcan_devtype_data
*devtype_data
;
970 struct net_device
*dev
;
971 struct flexcan_priv
*priv
;
972 struct resource
*mem
;
973 struct clk
*clk_ipg
= NULL
, *clk_per
= NULL
;
974 struct pinctrl
*pinctrl
;
976 resource_size_t mem_size
;
980 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
982 return PTR_ERR(pinctrl
);
984 if (pdev
->dev
.of_node
)
985 of_property_read_u32(pdev
->dev
.of_node
,
986 "clock-frequency", &clock_freq
);
989 clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
990 if (IS_ERR(clk_ipg
)) {
991 dev_err(&pdev
->dev
, "no ipg clock defined\n");
992 err
= PTR_ERR(clk_ipg
);
995 clock_freq
= clk_get_rate(clk_ipg
);
997 clk_per
= devm_clk_get(&pdev
->dev
, "per");
998 if (IS_ERR(clk_per
)) {
999 dev_err(&pdev
->dev
, "no per clock defined\n");
1000 err
= PTR_ERR(clk_per
);
1005 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1006 irq
= platform_get_irq(pdev
, 0);
1007 if (!mem
|| irq
<= 0) {
1012 mem_size
= resource_size(mem
);
1013 if (!request_mem_region(mem
->start
, mem_size
, pdev
->name
)) {
1018 base
= ioremap(mem
->start
, mem_size
);
1024 dev
= alloc_candev(sizeof(struct flexcan_priv
), 1);
1030 of_id
= of_match_device(flexcan_of_match
, &pdev
->dev
);
1032 devtype_data
= of_id
->data
;
1033 } else if (pdev
->id_entry
->driver_data
) {
1034 devtype_data
= (struct flexcan_devtype_data
*)
1035 pdev
->id_entry
->driver_data
;
1038 goto failed_devtype
;
1041 dev
->netdev_ops
= &flexcan_netdev_ops
;
1043 dev
->flags
|= IFF_ECHO
;
1045 priv
= netdev_priv(dev
);
1046 priv
->can
.clock
.freq
= clock_freq
;
1047 priv
->can
.bittiming_const
= &flexcan_bittiming_const
;
1048 priv
->can
.do_set_mode
= flexcan_set_mode
;
1049 priv
->can
.do_get_berr_counter
= flexcan_get_berr_counter
;
1050 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_LOOPBACK
|
1051 CAN_CTRLMODE_LISTENONLY
| CAN_CTRLMODE_3_SAMPLES
|
1052 CAN_CTRLMODE_BERR_REPORTING
;
1055 priv
->clk_ipg
= clk_ipg
;
1056 priv
->clk_per
= clk_per
;
1057 priv
->pdata
= pdev
->dev
.platform_data
;
1058 priv
->devtype_data
= devtype_data
;
1060 netif_napi_add(dev
, &priv
->napi
, flexcan_poll
, FLEXCAN_NAPI_WEIGHT
);
1062 dev_set_drvdata(&pdev
->dev
, dev
);
1063 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1065 err
= register_flexcandev(dev
);
1067 dev_err(&pdev
->dev
, "registering netdev failed\n");
1068 goto failed_register
;
1071 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%d)\n",
1072 priv
->base
, dev
->irq
);
1082 release_mem_region(mem
->start
, mem_size
);
1088 static int __devexit
flexcan_remove(struct platform_device
*pdev
)
1090 struct net_device
*dev
= platform_get_drvdata(pdev
);
1091 struct flexcan_priv
*priv
= netdev_priv(dev
);
1092 struct resource
*mem
;
1094 unregister_flexcandev(dev
);
1095 platform_set_drvdata(pdev
, NULL
);
1096 iounmap(priv
->base
);
1098 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1099 release_mem_region(mem
->start
, resource_size(mem
));
1107 static int flexcan_suspend(struct platform_device
*pdev
, pm_message_t state
)
1109 struct net_device
*dev
= platform_get_drvdata(pdev
);
1110 struct flexcan_priv
*priv
= netdev_priv(dev
);
1112 flexcan_chip_disable(priv
);
1114 if (netif_running(dev
)) {
1115 netif_stop_queue(dev
);
1116 netif_device_detach(dev
);
1118 priv
->can
.state
= CAN_STATE_SLEEPING
;
1123 static int flexcan_resume(struct platform_device
*pdev
)
1125 struct net_device
*dev
= platform_get_drvdata(pdev
);
1126 struct flexcan_priv
*priv
= netdev_priv(dev
);
1128 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
1129 if (netif_running(dev
)) {
1130 netif_device_attach(dev
);
1131 netif_start_queue(dev
);
1133 flexcan_chip_enable(priv
);
1138 #define flexcan_suspend NULL
1139 #define flexcan_resume NULL
1142 static struct platform_driver flexcan_driver
= {
1145 .owner
= THIS_MODULE
,
1146 .of_match_table
= flexcan_of_match
,
1148 .probe
= flexcan_probe
,
1149 .remove
= __devexit_p(flexcan_remove
),
1150 .suspend
= flexcan_suspend
,
1151 .resume
= flexcan_resume
,
1152 .id_table
= flexcan_id_table
,
1155 module_platform_driver(flexcan_driver
);
1157 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1158 "Marc Kleine-Budde <kernel@pengutronix.de>");
1159 MODULE_LICENSE("GPL v2");
1160 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");