projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: x86: zero apic_arb_prio on reset
[deliverable/linux.git] / drivers / net / can / flexcan.c
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
40
41 #define DRV_NAME "flexcan"
42
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95 /* FLEXCAN control register 2 (CTRL2) bits */
96 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
97 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
98 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
99 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
100 #define FLEXCAN_CTRL2_MRP BIT(18)
101 #define FLEXCAN_CTRL2_RRS BIT(17)
102 #define FLEXCAN_CTRL2_EACEN BIT(16)
103
104 /* FLEXCAN memory error control register (MECR) bits */
105 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
106 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
107 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
108 #define FLEXCAN_MECR_CEI_MSK BIT(16)
109 #define FLEXCAN_MECR_HAERRIE BIT(15)
110 #define FLEXCAN_MECR_FAERRIE BIT(14)
111 #define FLEXCAN_MECR_EXTERRIE BIT(13)
112 #define FLEXCAN_MECR_RERRDIS BIT(9)
113 #define FLEXCAN_MECR_ECCDIS BIT(8)
114 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
115
116 /* FLEXCAN error and status register (ESR) bits */
117 #define FLEXCAN_ESR_TWRN_INT BIT(17)
118 #define FLEXCAN_ESR_RWRN_INT BIT(16)
119 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
120 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
121 #define FLEXCAN_ESR_ACK_ERR BIT(13)
122 #define FLEXCAN_ESR_CRC_ERR BIT(12)
123 #define FLEXCAN_ESR_FRM_ERR BIT(11)
124 #define FLEXCAN_ESR_STF_ERR BIT(10)
125 #define FLEXCAN_ESR_TX_WRN BIT(9)
126 #define FLEXCAN_ESR_RX_WRN BIT(8)
127 #define FLEXCAN_ESR_IDLE BIT(7)
128 #define FLEXCAN_ESR_TXRX BIT(6)
129 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
130 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_BOFF_INT BIT(2)
134 #define FLEXCAN_ESR_ERR_INT BIT(1)
135 #define FLEXCAN_ESR_WAK_INT BIT(0)
136 #define FLEXCAN_ESR_ERR_BUS \
137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
140 #define FLEXCAN_ESR_ERR_STATE \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
142 #define FLEXCAN_ESR_ERR_ALL \
143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
144 #define FLEXCAN_ESR_ALL_INT \
145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
147
148 /* FLEXCAN interrupt flag register (IFLAG) bits */
149 /* Errata ERR005829 step7: Reserve first valid MB */
150 #define FLEXCAN_TX_BUF_RESERVED 8
151 #define FLEXCAN_TX_BUF_ID 9
152 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
153 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
154 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
155 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
156 #define FLEXCAN_IFLAG_DEFAULT \
157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
159
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
162 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
163 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
164 #define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
165 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
166
167 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
168 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
169 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
170 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
171
172 #define FLEXCAN_MB_CNT_SRR BIT(22)
173 #define FLEXCAN_MB_CNT_IDE BIT(21)
174 #define FLEXCAN_MB_CNT_RTR BIT(20)
175 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
176 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
177
178 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
179
180 #define FLEXCAN_TIMEOUT_US (50)
181
182 /*
183 * FLEXCAN hardware feature flags
184 *
185 * Below is some version info we got:
186 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
187 * Filter? connected? detection ception in MB
188 * MX25 FlexCAN2 03.00.00.00 no no no no
189 * MX28 FlexCAN2 03.00.04.00 yes yes no no
190 * MX35 FlexCAN2 03.00.00.00 no no no no
191 * MX53 FlexCAN2 03.00.00.00 yes no no no
192 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
193 * VF610 FlexCAN3 ? no yes yes yes?
194 *
195 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
196 */
197 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
198 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
199 #define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
200
201 /* Structure of the message buffer */
202 struct flexcan_mb {
203 u32 can_ctrl;
204 u32 can_id;
205 u32 data[2];
206 };
207
208 /* Structure of the hardware registers */
209 struct flexcan_regs {
210 u32 mcr; /* 0x00 */
211 u32 ctrl; /* 0x04 */
212 u32 timer; /* 0x08 */
213 u32 _reserved1; /* 0x0c */
214 u32 rxgmask; /* 0x10 */
215 u32 rx14mask; /* 0x14 */
216 u32 rx15mask; /* 0x18 */
217 u32 ecr; /* 0x1c */
218 u32 esr; /* 0x20 */
219 u32 imask2; /* 0x24 */
220 u32 imask1; /* 0x28 */
221 u32 iflag2; /* 0x2c */
222 u32 iflag1; /* 0x30 */
223 u32 ctrl2; /* 0x34 */
224 u32 esr2; /* 0x38 */
225 u32 imeur; /* 0x3c */
226 u32 lrfr; /* 0x40 */
227 u32 crcr; /* 0x44 */
228 u32 rxfgmask; /* 0x48 */
229 u32 rxfir; /* 0x4c */
230 u32 _reserved3[12]; /* 0x50 */
231 struct flexcan_mb cantxfg[64]; /* 0x80 */
232 /* FIFO-mode:
233 * MB
234 * 0x080...0x08f 0 RX message buffer
235 * 0x090...0x0df 1-5 reserverd
236 * 0x0e0...0x0ff 6-7 8 entry ID table
237 * (mx25, mx28, mx35, mx53)
238 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
239 * size conf'ed via ctrl2::RFFN
240 * (mx6, vf610)
241 */
242 u32 _reserved4[408];
243 u32 mecr; /* 0xae0 */
244 u32 erriar; /* 0xae4 */
245 u32 erridpr; /* 0xae8 */
246 u32 errippr; /* 0xaec */
247 u32 rerrar; /* 0xaf0 */
248 u32 rerrdr; /* 0xaf4 */
249 u32 rerrsynr; /* 0xaf8 */
250 u32 errsr; /* 0xafc */
251 };
252
253 struct flexcan_devtype_data {
254 u32 features; /* hardware controller features */
255 };
256
257 struct flexcan_priv {
258 struct can_priv can;
259 struct napi_struct napi;
260
261 void __iomem *base;
262 u32 reg_esr;
263 u32 reg_ctrl_default;
264
265 struct clk *clk_ipg;
266 struct clk *clk_per;
267 struct flexcan_platform_data *pdata;
268 const struct flexcan_devtype_data *devtype_data;
269 struct regulator *reg_xceiver;
270 };
271
272 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
273 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
274 };
275 static struct flexcan_devtype_data fsl_imx28_devtype_data;
276 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
277 .features = FLEXCAN_HAS_V10_FEATURES,
278 };
279 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
280 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
281 };
282
283 static const struct can_bittiming_const flexcan_bittiming_const = {
284 .name = DRV_NAME,
285 .tseg1_min = 4,
286 .tseg1_max = 16,
287 .tseg2_min = 2,
288 .tseg2_max = 8,
289 .sjw_max = 4,
290 .brp_min = 1,
291 .brp_max = 256,
292 .brp_inc = 1,
293 };
294
295 /*
296 * Abstract off the read/write for arm versus ppc. This
297 * assumes that PPC uses big-endian registers and everything
298 * else uses little-endian registers, independent of CPU
299 * endianess.
300 */
301 #if defined(CONFIG_PPC)
302 static inline u32 flexcan_read(void __iomem *addr)
303 {
304 return in_be32(addr);
305 }
306
307 static inline void flexcan_write(u32 val, void __iomem *addr)
308 {
309 out_be32(addr, val);
310 }
311 #else
312 static inline u32 flexcan_read(void __iomem *addr)
313 {
314 return readl(addr);
315 }
316
317 static inline void flexcan_write(u32 val, void __iomem *addr)
318 {
319 writel(val, addr);
320 }
321 #endif
322
323 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
324 {
325 if (!priv->reg_xceiver)
326 return 0;
327
328 return regulator_enable(priv->reg_xceiver);
329 }
330
331 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
332 {
333 if (!priv->reg_xceiver)
334 return 0;
335
336 return regulator_disable(priv->reg_xceiver);
337 }
338
339 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
340 u32 reg_esr)
341 {
342 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
343 (reg_esr & FLEXCAN_ESR_ERR_BUS);
344 }
345
346 static int flexcan_chip_enable(struct flexcan_priv *priv)
347 {
348 struct flexcan_regs __iomem *regs = priv->base;
349 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
350 u32 reg;
351
352 reg = flexcan_read(&regs->mcr);
353 reg &= ~FLEXCAN_MCR_MDIS;
354 flexcan_write(reg, &regs->mcr);
355
356 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
357 udelay(10);
358
359 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
360 return -ETIMEDOUT;
361
362 return 0;
363 }
364
365 static int flexcan_chip_disable(struct flexcan_priv *priv)
366 {
367 struct flexcan_regs __iomem *regs = priv->base;
368 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
369 u32 reg;
370
371 reg = flexcan_read(&regs->mcr);
372 reg |= FLEXCAN_MCR_MDIS;
373 flexcan_write(reg, &regs->mcr);
374
375 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
376 udelay(10);
377
378 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
379 return -ETIMEDOUT;
380
381 return 0;
382 }
383
384 static int flexcan_chip_freeze(struct flexcan_priv *priv)
385 {
386 struct flexcan_regs __iomem *regs = priv->base;
387 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
388 u32 reg;
389
390 reg = flexcan_read(&regs->mcr);
391 reg |= FLEXCAN_MCR_HALT;
392 flexcan_write(reg, &regs->mcr);
393
394 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
395 udelay(100);
396
397 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
398 return -ETIMEDOUT;
399
400 return 0;
401 }
402
403 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
404 {
405 struct flexcan_regs __iomem *regs = priv->base;
406 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
407 u32 reg;
408
409 reg = flexcan_read(&regs->mcr);
410 reg &= ~FLEXCAN_MCR_HALT;
411 flexcan_write(reg, &regs->mcr);
412
413 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
414 udelay(10);
415
416 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
417 return -ETIMEDOUT;
418
419 return 0;
420 }
421
422 static int flexcan_chip_softreset(struct flexcan_priv *priv)
423 {
424 struct flexcan_regs __iomem *regs = priv->base;
425 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
426
427 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
428 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
429 udelay(10);
430
431 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
432 return -ETIMEDOUT;
433
434 return 0;
435 }
436
437
438 static int __flexcan_get_berr_counter(const struct net_device *dev,
439 struct can_berr_counter *bec)
440 {
441 const struct flexcan_priv *priv = netdev_priv(dev);
442 struct flexcan_regs __iomem *regs = priv->base;
443 u32 reg = flexcan_read(&regs->ecr);
444
445 bec->txerr = (reg >> 0) & 0xff;
446 bec->rxerr = (reg >> 8) & 0xff;
447
448 return 0;
449 }
450
451 static int flexcan_get_berr_counter(const struct net_device *dev,
452 struct can_berr_counter *bec)
453 {
454 const struct flexcan_priv *priv = netdev_priv(dev);
455 int err;
456
457 err = clk_prepare_enable(priv->clk_ipg);
458 if (err)
459 return err;
460
461 err = clk_prepare_enable(priv->clk_per);
462 if (err)
463 goto out_disable_ipg;
464
465 err = __flexcan_get_berr_counter(dev, bec);
466
467 clk_disable_unprepare(priv->clk_per);
468 out_disable_ipg:
469 clk_disable_unprepare(priv->clk_ipg);
470
471 return err;
472 }
473
474 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
475 {
476 const struct flexcan_priv *priv = netdev_priv(dev);
477 struct flexcan_regs __iomem *regs = priv->base;
478 struct can_frame *cf = (struct can_frame *)skb->data;
479 u32 can_id;
480 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
481
482 if (can_dropped_invalid_skb(dev, skb))
483 return NETDEV_TX_OK;
484
485 netif_stop_queue(dev);
486
487 if (cf->can_id & CAN_EFF_FLAG) {
488 can_id = cf->can_id & CAN_EFF_MASK;
489 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
490 } else {
491 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
492 }
493
494 if (cf->can_id & CAN_RTR_FLAG)
495 ctrl |= FLEXCAN_MB_CNT_RTR;
496
497 if (cf->can_dlc > 0) {
498 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
499 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
500 }
501 if (cf->can_dlc > 3) {
502 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
503 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
504 }
505
506 can_put_echo_skb(skb, dev, 0);
507
508 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
509 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
510
511 /* Errata ERR005829 step8:
512 * Write twice INACTIVE(0x8) code to first MB.
513 */
514 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
515 &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
516 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
517 &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
518
519 return NETDEV_TX_OK;
520 }
521
522 static void do_bus_err(struct net_device *dev,
523 struct can_frame *cf, u32 reg_esr)
524 {
525 struct flexcan_priv *priv = netdev_priv(dev);
526 int rx_errors = 0, tx_errors = 0;
527
528 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
529
530 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
531 netdev_dbg(dev, "BIT1_ERR irq\n");
532 cf->data[2] |= CAN_ERR_PROT_BIT1;
533 tx_errors = 1;
534 }
535 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
536 netdev_dbg(dev, "BIT0_ERR irq\n");
537 cf->data[2] |= CAN_ERR_PROT_BIT0;
538 tx_errors = 1;
539 }
540 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
541 netdev_dbg(dev, "ACK_ERR irq\n");
542 cf->can_id |= CAN_ERR_ACK;
543 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
544 tx_errors = 1;
545 }
546 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
547 netdev_dbg(dev, "CRC_ERR irq\n");
548 cf->data[2] |= CAN_ERR_PROT_BIT;
549 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
550 rx_errors = 1;
551 }
552 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
553 netdev_dbg(dev, "FRM_ERR irq\n");
554 cf->data[2] |= CAN_ERR_PROT_FORM;
555 rx_errors = 1;
556 }
557 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
558 netdev_dbg(dev, "STF_ERR irq\n");
559 cf->data[2] |= CAN_ERR_PROT_STUFF;
560 rx_errors = 1;
561 }
562
563 priv->can.can_stats.bus_error++;
564 if (rx_errors)
565 dev->stats.rx_errors++;
566 if (tx_errors)
567 dev->stats.tx_errors++;
568 }
569
570 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
571 {
572 struct sk_buff *skb;
573 struct can_frame *cf;
574
575 skb = alloc_can_err_skb(dev, &cf);
576 if (unlikely(!skb))
577 return 0;
578
579 do_bus_err(dev, cf, reg_esr);
580
581 dev->stats.rx_packets++;
582 dev->stats.rx_bytes += cf->can_dlc;
583 netif_receive_skb(skb);
584
585 return 1;
586 }
587
588 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
589 {
590 struct flexcan_priv *priv = netdev_priv(dev);
591 struct sk_buff *skb;
592 struct can_frame *cf;
593 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
594 int flt;
595 struct can_berr_counter bec;
596
597 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
598 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
599 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
600 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
601 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
602 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
603 new_state = max(tx_state, rx_state);
604 } else {
605 __flexcan_get_berr_counter(dev, &bec);
606 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
607 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
608 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
609 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
610 }
611
612 /* state hasn't changed */
613 if (likely(new_state == priv->can.state))
614 return 0;
615
616 skb = alloc_can_err_skb(dev, &cf);
617 if (unlikely(!skb))
618 return 0;
619
620 can_change_state(dev, cf, tx_state, rx_state);
621
622 if (unlikely(new_state == CAN_STATE_BUS_OFF))
623 can_bus_off(dev);
624
625 dev->stats.rx_packets++;
626 dev->stats.rx_bytes += cf->can_dlc;
627 netif_receive_skb(skb);
628
629 return 1;
630 }
631
632 static void flexcan_read_fifo(const struct net_device *dev,
633 struct can_frame *cf)
634 {
635 const struct flexcan_priv *priv = netdev_priv(dev);
636 struct flexcan_regs __iomem *regs = priv->base;
637 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
638 u32 reg_ctrl, reg_id;
639
640 reg_ctrl = flexcan_read(&mb->can_ctrl);
641 reg_id = flexcan_read(&mb->can_id);
642 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
643 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
644 else
645 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
646
647 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
648 cf->can_id |= CAN_RTR_FLAG;
649 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
650
651 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
652 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
653
654 /* mark as read */
655 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
656 flexcan_read(&regs->timer);
657 }
658
659 static int flexcan_read_frame(struct net_device *dev)
660 {
661 struct net_device_stats *stats = &dev->stats;
662 struct can_frame *cf;
663 struct sk_buff *skb;
664
665 skb = alloc_can_skb(dev, &cf);
666 if (unlikely(!skb)) {
667 stats->rx_dropped++;
668 return 0;
669 }
670
671 flexcan_read_fifo(dev, cf);
672
673 stats->rx_packets++;
674 stats->rx_bytes += cf->can_dlc;
675 netif_receive_skb(skb);
676
677 can_led_event(dev, CAN_LED_EVENT_RX);
678
679 return 1;
680 }
681
682 static int flexcan_poll(struct napi_struct *napi, int quota)
683 {
684 struct net_device *dev = napi->dev;
685 const struct flexcan_priv *priv = netdev_priv(dev);
686 struct flexcan_regs __iomem *regs = priv->base;
687 u32 reg_iflag1, reg_esr;
688 int work_done = 0;
689
690 /*
691 * The error bits are cleared on read,
692 * use saved value from irq handler.
693 */
694 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
695
696 /* handle state changes */
697 work_done += flexcan_poll_state(dev, reg_esr);
698
699 /* handle RX-FIFO */
700 reg_iflag1 = flexcan_read(&regs->iflag1);
701 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
702 work_done < quota) {
703 work_done += flexcan_read_frame(dev);
704 reg_iflag1 = flexcan_read(&regs->iflag1);
705 }
706
707 /* report bus errors */
708 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
709 work_done += flexcan_poll_bus_err(dev, reg_esr);
710
711 if (work_done < quota) {
712 napi_complete(napi);
713 /* enable IRQs */
714 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
715 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
716 }
717
718 return work_done;
719 }
720
721 static irqreturn_t flexcan_irq(int irq, void *dev_id)
722 {
723 struct net_device *dev = dev_id;
724 struct net_device_stats *stats = &dev->stats;
725 struct flexcan_priv *priv = netdev_priv(dev);
726 struct flexcan_regs __iomem *regs = priv->base;
727 u32 reg_iflag1, reg_esr;
728
729 reg_iflag1 = flexcan_read(&regs->iflag1);
730 reg_esr = flexcan_read(&regs->esr);
731 /* ACK all bus error and state change IRQ sources */
732 if (reg_esr & FLEXCAN_ESR_ALL_INT)
733 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
734
735 /*
736 * schedule NAPI in case of:
737 * - rx IRQ
738 * - state change IRQ
739 * - bus error IRQ and bus error reporting is activated
740 */
741 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
742 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
743 flexcan_has_and_handle_berr(priv, reg_esr)) {
744 /*
745 * The error bits are cleared on read,
746 * save them for later use.
747 */
748 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
749 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
750 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
751 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
752 &regs->ctrl);
753 napi_schedule(&priv->napi);
754 }
755
756 /* FIFO overflow */
757 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
758 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
759 dev->stats.rx_over_errors++;
760 dev->stats.rx_errors++;
761 }
762
763 /* transmission complete interrupt */
764 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
765 stats->tx_bytes += can_get_echo_skb(dev, 0);
766 stats->tx_packets++;
767 can_led_event(dev, CAN_LED_EVENT_TX);
768 /* after sending a RTR frame mailbox is in RX mode */
769 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
770 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
771 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
772 netif_wake_queue(dev);
773 }
774
775 return IRQ_HANDLED;
776 }
777
778 static void flexcan_set_bittiming(struct net_device *dev)
779 {
780 const struct flexcan_priv *priv = netdev_priv(dev);
781 const struct can_bittiming *bt = &priv->can.bittiming;
782 struct flexcan_regs __iomem *regs = priv->base;
783 u32 reg;
784
785 reg = flexcan_read(&regs->ctrl);
786 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
787 FLEXCAN_CTRL_RJW(0x3) |
788 FLEXCAN_CTRL_PSEG1(0x7) |
789 FLEXCAN_CTRL_PSEG2(0x7) |
790 FLEXCAN_CTRL_PROPSEG(0x7) |
791 FLEXCAN_CTRL_LPB |
792 FLEXCAN_CTRL_SMP |
793 FLEXCAN_CTRL_LOM);
794
795 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
796 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
797 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
798 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
799 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
800
801 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
802 reg |= FLEXCAN_CTRL_LPB;
803 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
804 reg |= FLEXCAN_CTRL_LOM;
805 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
806 reg |= FLEXCAN_CTRL_SMP;
807
808 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
809 flexcan_write(reg, &regs->ctrl);
810
811 /* print chip status */
812 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
813 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
814 }
815
816 /*
817 * flexcan_chip_start
818 *
819 * this functions is entered with clocks enabled
820 *
821 */
822 static int flexcan_chip_start(struct net_device *dev)
823 {
824 struct flexcan_priv *priv = netdev_priv(dev);
825 struct flexcan_regs __iomem *regs = priv->base;
826 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
827 int err, i;
828
829 /* enable module */
830 err = flexcan_chip_enable(priv);
831 if (err)
832 return err;
833
834 /* soft reset */
835 err = flexcan_chip_softreset(priv);
836 if (err)
837 goto out_chip_disable;
838
839 flexcan_set_bittiming(dev);
840
841 /*
842 * MCR
843 *
844 * enable freeze
845 * enable fifo
846 * halt now
847 * only supervisor access
848 * enable warning int
849 * choose format C
850 * disable local echo
851 *
852 */
853 reg_mcr = flexcan_read(&regs->mcr);
854 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
855 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
856 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
857 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
858 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
859 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
860 flexcan_write(reg_mcr, &regs->mcr);
861
862 /*
863 * CTRL
864 *
865 * disable timer sync feature
866 *
867 * disable auto busoff recovery
868 * transmit lowest buffer first
869 *
870 * enable tx and rx warning interrupt
871 * enable bus off interrupt
872 * (== FLEXCAN_CTRL_ERR_STATE)
873 */
874 reg_ctrl = flexcan_read(&regs->ctrl);
875 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
876 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
877 FLEXCAN_CTRL_ERR_STATE;
878 /*
879 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
880 * on most Flexcan cores, too. Otherwise we don't get
881 * any error warning or passive interrupts.
882 */
883 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
884 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
885 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
886 else
887 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
888
889 /* save for later use */
890 priv->reg_ctrl_default = reg_ctrl;
891 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
892 flexcan_write(reg_ctrl, &regs->ctrl);
893
894 /* clear and invalidate all mailboxes first */
895 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
896 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
897 &regs->cantxfg[i].can_ctrl);
898 }
899
900 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
901 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
902 &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
903
904 /* mark TX mailbox as INACTIVE */
905 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
906 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
907
908 /* acceptance mask/acceptance code (accept everything) */
909 flexcan_write(0x0, &regs->rxgmask);
910 flexcan_write(0x0, &regs->rx14mask);
911 flexcan_write(0x0, &regs->rx15mask);
912
913 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
914 flexcan_write(0x0, &regs->rxfgmask);
915
916 /*
917 * On Vybrid, disable memory error detection interrupts
918 * and freeze mode.
919 * This also works around errata e5295 which generates
920 * false positive memory errors and put the device in
921 * freeze mode.
922 */
923 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
924 /*
925 * Follow the protocol as described in "Detection
926 * and Correction of Memory Errors" to write to
927 * MECR register
928 */
929 reg_ctrl2 = flexcan_read(&regs->ctrl2);
930 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
931 flexcan_write(reg_ctrl2, &regs->ctrl2);
932
933 reg_mecr = flexcan_read(&regs->mecr);
934 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
935 flexcan_write(reg_mecr, &regs->mecr);
936 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
937 FLEXCAN_MECR_FANCEI_MSK);
938 flexcan_write(reg_mecr, &regs->mecr);
939 }
940
941 err = flexcan_transceiver_enable(priv);
942 if (err)
943 goto out_chip_disable;
944
945 /* synchronize with the can bus */
946 err = flexcan_chip_unfreeze(priv);
947 if (err)
948 goto out_transceiver_disable;
949
950 priv->can.state = CAN_STATE_ERROR_ACTIVE;
951
952 /* enable FIFO interrupts */
953 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
954
955 /* print chip status */
956 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
957 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
958
959 return 0;
960
961 out_transceiver_disable:
962 flexcan_transceiver_disable(priv);
963 out_chip_disable:
964 flexcan_chip_disable(priv);
965 return err;
966 }
967
968 /*
969 * flexcan_chip_stop
970 *
971 * this functions is entered with clocks enabled
972 *
973 */
974 static void flexcan_chip_stop(struct net_device *dev)
975 {
976 struct flexcan_priv *priv = netdev_priv(dev);
977 struct flexcan_regs __iomem *regs = priv->base;
978
979 /* freeze + disable module */
980 flexcan_chip_freeze(priv);
981 flexcan_chip_disable(priv);
982
983 /* Disable all interrupts */
984 flexcan_write(0, &regs->imask1);
985 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
986 &regs->ctrl);
987
988 flexcan_transceiver_disable(priv);
989 priv->can.state = CAN_STATE_STOPPED;
990
991 return;
992 }
993
994 static int flexcan_open(struct net_device *dev)
995 {
996 struct flexcan_priv *priv = netdev_priv(dev);
997 int err;
998
999 err = clk_prepare_enable(priv->clk_ipg);
1000 if (err)
1001 return err;
1002
1003 err = clk_prepare_enable(priv->clk_per);
1004 if (err)
1005 goto out_disable_ipg;
1006
1007 err = open_candev(dev);
1008 if (err)
1009 goto out_disable_per;
1010
1011 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1012 if (err)
1013 goto out_close;
1014
1015 /* start chip and queuing */
1016 err = flexcan_chip_start(dev);
1017 if (err)
1018 goto out_free_irq;
1019
1020 can_led_event(dev, CAN_LED_EVENT_OPEN);
1021
1022 napi_enable(&priv->napi);
1023 netif_start_queue(dev);
1024
1025 return 0;
1026
1027 out_free_irq:
1028 free_irq(dev->irq, dev);
1029 out_close:
1030 close_candev(dev);
1031 out_disable_per:
1032 clk_disable_unprepare(priv->clk_per);
1033 out_disable_ipg:
1034 clk_disable_unprepare(priv->clk_ipg);
1035
1036 return err;
1037 }
1038
1039 static int flexcan_close(struct net_device *dev)
1040 {
1041 struct flexcan_priv *priv = netdev_priv(dev);
1042
1043 netif_stop_queue(dev);
1044 napi_disable(&priv->napi);
1045 flexcan_chip_stop(dev);
1046
1047 free_irq(dev->irq, dev);
1048 clk_disable_unprepare(priv->clk_per);
1049 clk_disable_unprepare(priv->clk_ipg);
1050
1051 close_candev(dev);
1052
1053 can_led_event(dev, CAN_LED_EVENT_STOP);
1054
1055 return 0;
1056 }
1057
1058 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1059 {
1060 int err;
1061
1062 switch (mode) {
1063 case CAN_MODE_START:
1064 err = flexcan_chip_start(dev);
1065 if (err)
1066 return err;
1067
1068 netif_wake_queue(dev);
1069 break;
1070
1071 default:
1072 return -EOPNOTSUPP;
1073 }
1074
1075 return 0;
1076 }
1077
1078 static const struct net_device_ops flexcan_netdev_ops = {
1079 .ndo_open = flexcan_open,
1080 .ndo_stop = flexcan_close,
1081 .ndo_start_xmit = flexcan_start_xmit,
1082 .ndo_change_mtu = can_change_mtu,
1083 };
1084
1085 static int register_flexcandev(struct net_device *dev)
1086 {
1087 struct flexcan_priv *priv = netdev_priv(dev);
1088 struct flexcan_regs __iomem *regs = priv->base;
1089 u32 reg, err;
1090
1091 err = clk_prepare_enable(priv->clk_ipg);
1092 if (err)
1093 return err;
1094
1095 err = clk_prepare_enable(priv->clk_per);
1096 if (err)
1097 goto out_disable_ipg;
1098
1099 /* select "bus clock", chip must be disabled */
1100 err = flexcan_chip_disable(priv);
1101 if (err)
1102 goto out_disable_per;
1103 reg = flexcan_read(&regs->ctrl);
1104 reg |= FLEXCAN_CTRL_CLK_SRC;
1105 flexcan_write(reg, &regs->ctrl);
1106
1107 err = flexcan_chip_enable(priv);
1108 if (err)
1109 goto out_chip_disable;
1110
1111 /* set freeze, halt and activate FIFO, restrict register access */
1112 reg = flexcan_read(&regs->mcr);
1113 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1114 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1115 flexcan_write(reg, &regs->mcr);
1116
1117 /*
1118 * Currently we only support newer versions of this core
1119 * featuring a RX FIFO. Older cores found on some Coldfire
1120 * derivates are not yet supported.
1121 */
1122 reg = flexcan_read(&regs->mcr);
1123 if (!(reg & FLEXCAN_MCR_FEN)) {
1124 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1125 err = -ENODEV;
1126 goto out_chip_disable;
1127 }
1128
1129 err = register_candev(dev);
1130
1131 /* disable core and turn off clocks */
1132 out_chip_disable:
1133 flexcan_chip_disable(priv);
1134 out_disable_per:
1135 clk_disable_unprepare(priv->clk_per);
1136 out_disable_ipg:
1137 clk_disable_unprepare(priv->clk_ipg);
1138
1139 return err;
1140 }
1141
1142 static void unregister_flexcandev(struct net_device *dev)
1143 {
1144 unregister_candev(dev);
1145 }
1146
1147 static const struct of_device_id flexcan_of_match[] = {
1148 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1149 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1150 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1151 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1152 { /* sentinel */ },
1153 };
1154 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1155
1156 static const struct platform_device_id flexcan_id_table[] = {
1157 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1158 { /* sentinel */ },
1159 };
1160 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1161
1162 static int flexcan_probe(struct platform_device *pdev)
1163 {
1164 const struct of_device_id *of_id;
1165 const struct flexcan_devtype_data *devtype_data;
1166 struct net_device *dev;
1167 struct flexcan_priv *priv;
1168 struct regulator *reg_xceiver;
1169 struct resource *mem;
1170 struct clk *clk_ipg = NULL, *clk_per = NULL;
1171 void __iomem *base;
1172 int err, irq;
1173 u32 clock_freq = 0;
1174
1175 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1176 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1177 return -EPROBE_DEFER;
1178 else if (IS_ERR(reg_xceiver))
1179 reg_xceiver = NULL;
1180
1181 if (pdev->dev.of_node)
1182 of_property_read_u32(pdev->dev.of_node,
1183 "clock-frequency", &clock_freq);
1184
1185 if (!clock_freq) {
1186 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1187 if (IS_ERR(clk_ipg)) {
1188 dev_err(&pdev->dev, "no ipg clock defined\n");
1189 return PTR_ERR(clk_ipg);
1190 }
1191
1192 clk_per = devm_clk_get(&pdev->dev, "per");
1193 if (IS_ERR(clk_per)) {
1194 dev_err(&pdev->dev, "no per clock defined\n");
1195 return PTR_ERR(clk_per);
1196 }
1197 clock_freq = clk_get_rate(clk_per);
1198 }
1199
1200 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201 irq = platform_get_irq(pdev, 0);
1202 if (irq <= 0)
1203 return -ENODEV;
1204
1205 base = devm_ioremap_resource(&pdev->dev, mem);
1206 if (IS_ERR(base))
1207 return PTR_ERR(base);
1208
1209 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1210 if (of_id) {
1211 devtype_data = of_id->data;
1212 } else if (platform_get_device_id(pdev)->driver_data) {
1213 devtype_data = (struct flexcan_devtype_data *)
1214 platform_get_device_id(pdev)->driver_data;
1215 } else {
1216 return -ENODEV;
1217 }
1218
1219 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1220 if (!dev)
1221 return -ENOMEM;
1222
1223 dev->netdev_ops = &flexcan_netdev_ops;
1224 dev->irq = irq;
1225 dev->flags |= IFF_ECHO;
1226
1227 priv = netdev_priv(dev);
1228 priv->can.clock.freq = clock_freq;
1229 priv->can.bittiming_const = &flexcan_bittiming_const;
1230 priv->can.do_set_mode = flexcan_set_mode;
1231 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1232 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1233 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1234 CAN_CTRLMODE_BERR_REPORTING;
1235 priv->base = base;
1236 priv->clk_ipg = clk_ipg;
1237 priv->clk_per = clk_per;
1238 priv->pdata = dev_get_platdata(&pdev->dev);
1239 priv->devtype_data = devtype_data;
1240
1241 priv->reg_xceiver = reg_xceiver;
1242
1243 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1244
1245 platform_set_drvdata(pdev, dev);
1246 SET_NETDEV_DEV(dev, &pdev->dev);
1247
1248 err = register_flexcandev(dev);
1249 if (err) {
1250 dev_err(&pdev->dev, "registering netdev failed\n");
1251 goto failed_register;
1252 }
1253
1254 devm_can_led_init(dev);
1255
1256 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1257 priv->base, dev->irq);
1258
1259 return 0;
1260
1261 failed_register:
1262 free_candev(dev);
1263 return err;
1264 }
1265
1266 static int flexcan_remove(struct platform_device *pdev)
1267 {
1268 struct net_device *dev = platform_get_drvdata(pdev);
1269 struct flexcan_priv *priv = netdev_priv(dev);
1270
1271 unregister_flexcandev(dev);
1272 netif_napi_del(&priv->napi);
1273 free_candev(dev);
1274
1275 return 0;
1276 }
1277
1278 static int __maybe_unused flexcan_suspend(struct device *device)
1279 {
1280 struct net_device *dev = dev_get_drvdata(device);
1281 struct flexcan_priv *priv = netdev_priv(dev);
1282 int err;
1283
1284 err = flexcan_chip_disable(priv);
1285 if (err)
1286 return err;
1287
1288 if (netif_running(dev)) {
1289 netif_stop_queue(dev);
1290 netif_device_detach(dev);
1291 }
1292 priv->can.state = CAN_STATE_SLEEPING;
1293
1294 return 0;
1295 }
1296
1297 static int __maybe_unused flexcan_resume(struct device *device)
1298 {
1299 struct net_device *dev = dev_get_drvdata(device);
1300 struct flexcan_priv *priv = netdev_priv(dev);
1301
1302 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1303 if (netif_running(dev)) {
1304 netif_device_attach(dev);
1305 netif_start_queue(dev);
1306 }
1307 return flexcan_chip_enable(priv);
1308 }
1309
1310 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1311
1312 static struct platform_driver flexcan_driver = {
1313 .driver = {
1314 .name = DRV_NAME,
1315 .pm = &flexcan_pm_ops,
1316 .of_match_table = flexcan_of_match,
1317 },
1318 .probe = flexcan_probe,
1319 .remove = flexcan_remove,
1320 .id_table = flexcan_id_table,
1321 };
1322
1323 module_platform_driver(flexcan_driver);
1324
1325 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1326 "Marc Kleine-Budde <kernel@pengutronix.de>");
1327 MODULE_LICENSE("GPL v2");
1328 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux kernel - Deliverables
This page took 0.081287 seconds and 5 git commands to generate.