2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Your platform definition file should specify something like:
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
45 * static struct spi_board_info spi_board_info[] = {
47 * .modalias = "mcp2510",
48 * // or "mcp2515" depending on your controller
49 * .platform_data = &mcp251x_info,
51 * .max_speed_hz = 2*1000*1000,
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
61 #include <linux/can/core.h>
62 #include <linux/can/dev.h>
63 #include <linux/can/platform/mcp251x.h>
64 #include <linux/completion.h>
65 #include <linux/delay.h>
66 #include <linux/device.h>
67 #include <linux/dma-mapping.h>
68 #include <linux/freezer.h>
69 #include <linux/interrupt.h>
71 #include <linux/kernel.h>
72 #include <linux/module.h>
73 #include <linux/netdevice.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
79 /* SPI interface instruction set */
80 #define INSTRUCTION_WRITE 0x02
81 #define INSTRUCTION_READ 0x03
82 #define INSTRUCTION_BIT_MODIFY 0x05
83 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85 #define INSTRUCTION_RESET 0xC0
89 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
92 /* MPC251x registers */
95 # define CANCTRL_REQOP_MASK 0xe0
96 # define CANCTRL_REQOP_CONF 0x80
97 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
98 # define CANCTRL_REQOP_LOOPBACK 0x40
99 # define CANCTRL_REQOP_SLEEP 0x20
100 # define CANCTRL_REQOP_NORMAL 0x00
101 # define CANCTRL_OSM 0x08
102 # define CANCTRL_ABAT 0x10
106 # define CNF1_SJW_SHIFT 6
108 # define CNF2_BTLMODE 0x80
109 # define CNF2_SAM 0x40
110 # define CNF2_PS1_SHIFT 3
112 # define CNF3_SOF 0x08
113 # define CNF3_WAKFIL 0x04
114 # define CNF3_PHSEG2_MASK 0x07
116 # define CANINTE_MERRE 0x80
117 # define CANINTE_WAKIE 0x40
118 # define CANINTE_ERRIE 0x20
119 # define CANINTE_TX2IE 0x10
120 # define CANINTE_TX1IE 0x08
121 # define CANINTE_TX0IE 0x04
122 # define CANINTE_RX1IE 0x02
123 # define CANINTE_RX0IE 0x01
125 # define CANINTF_MERRF 0x80
126 # define CANINTF_WAKIF 0x40
127 # define CANINTF_ERRIF 0x20
128 # define CANINTF_TX2IF 0x10
129 # define CANINTF_TX1IF 0x08
130 # define CANINTF_TX0IF 0x04
131 # define CANINTF_RX1IF 0x02
132 # define CANINTF_RX0IF 0x01
133 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
134 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
135 # define CANINTF_ERR (CANINTF_ERRIF)
137 # define EFLG_EWARN 0x01
138 # define EFLG_RXWAR 0x02
139 # define EFLG_TXWAR 0x04
140 # define EFLG_RXEP 0x08
141 # define EFLG_TXEP 0x10
142 # define EFLG_TXBO 0x20
143 # define EFLG_RX0OVR 0x40
144 # define EFLG_RX1OVR 0x80
145 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
146 # define TXBCTRL_ABTF 0x40
147 # define TXBCTRL_MLOA 0x20
148 # define TXBCTRL_TXERR 0x10
149 # define TXBCTRL_TXREQ 0x08
150 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
151 # define SIDH_SHIFT 3
152 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
153 # define SIDL_SID_MASK 7
154 # define SIDL_SID_SHIFT 5
155 # define SIDL_EXIDE_SHIFT 3
156 # define SIDL_EID_SHIFT 16
157 # define SIDL_EID_MASK 3
158 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
159 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
160 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
161 # define DLC_RTR_SHIFT 6
162 #define TXBCTRL_OFF 0
163 #define TXBSIDH_OFF 1
164 #define TXBSIDL_OFF 2
165 #define TXBEID8_OFF 3
166 #define TXBEID0_OFF 4
169 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
170 # define RXBCTRL_BUKT 0x04
171 # define RXBCTRL_RXM0 0x20
172 # define RXBCTRL_RXM1 0x40
173 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
174 # define RXBSIDH_SHIFT 3
175 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
176 # define RXBSIDL_IDE 0x08
177 # define RXBSIDL_SRR 0x10
178 # define RXBSIDL_EID 3
179 # define RXBSIDL_SHIFT 5
180 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
181 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
182 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
183 # define RXBDLC_LEN_MASK 0x0f
184 # define RXBDLC_RTR 0x40
185 #define RXBCTRL_OFF 0
186 #define RXBSIDH_OFF 1
187 #define RXBSIDL_OFF 2
188 #define RXBEID8_OFF 3
189 #define RXBEID0_OFF 4
192 #define RXFSIDH(n) ((n) * 4)
193 #define RXFSIDL(n) ((n) * 4 + 1)
194 #define RXFEID8(n) ((n) * 4 + 2)
195 #define RXFEID0(n) ((n) * 4 + 3)
196 #define RXMSIDH(n) ((n) * 4 + 0x20)
197 #define RXMSIDL(n) ((n) * 4 + 0x21)
198 #define RXMEID8(n) ((n) * 4 + 0x22)
199 #define RXMEID0(n) ((n) * 4 + 0x23)
201 #define GET_BYTE(val, byte) \
202 (((val) >> ((byte) * 8)) & 0xff)
203 #define SET_BYTE(val, byte) \
204 (((val) & 0xff) << ((byte) * 8))
207 * Buffer size required for the largest SPI transfer (i.e., reading a
210 #define CAN_FRAME_MAX_DATA_LEN 8
211 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
212 #define CAN_FRAME_MAX_BITS 128
214 #define TX_ECHO_SKB_MAX 1
216 #define DEVICE_NAME "mcp251x"
218 static int mcp251x_enable_dma
; /* Enable SPI DMA. Default: 0 (Off) */
219 module_param(mcp251x_enable_dma
, int, S_IRUGO
);
220 MODULE_PARM_DESC(mcp251x_enable_dma
, "Enable SPI DMA. Default: 0 (Off)");
222 static const struct can_bittiming_const mcp251x_bittiming_const
= {
235 CAN_MCP251X_MCP2510
= 0x2510,
236 CAN_MCP251X_MCP2515
= 0x2515,
239 struct mcp251x_priv
{
241 struct net_device
*net
;
242 struct spi_device
*spi
;
243 enum mcp251x_model model
;
245 struct mutex mcp_lock
; /* SPI device lock */
249 dma_addr_t spi_tx_dma
;
250 dma_addr_t spi_rx_dma
;
252 struct sk_buff
*tx_skb
;
255 struct workqueue_struct
*wq
;
256 struct work_struct tx_work
;
257 struct work_struct restart_work
;
261 #define AFTER_SUSPEND_UP 1
262 #define AFTER_SUSPEND_DOWN 2
263 #define AFTER_SUSPEND_POWER 4
264 #define AFTER_SUSPEND_RESTART 8
268 #define MCP251X_IS(_model) \
269 static inline int mcp251x_is_##_model(struct spi_device *spi) \
271 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \
272 return priv->model == CAN_MCP251X_MCP##_model; \
278 static void mcp251x_clean(struct net_device
*net
)
280 struct mcp251x_priv
*priv
= netdev_priv(net
);
282 if (priv
->tx_skb
|| priv
->tx_len
)
283 net
->stats
.tx_errors
++;
285 dev_kfree_skb(priv
->tx_skb
);
287 can_free_echo_skb(priv
->net
, 0);
293 * Note about handling of error return of mcp251x_spi_trans: accessing
294 * registers via SPI is not really different conceptually than using
295 * normal I/O assembler instructions, although it's much more
296 * complicated from a practical POV. So it's not advisable to always
297 * check the return value of this function. Imagine that every
298 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
299 * error();", it would be a great mess (well there are some situation
300 * when exception handling C++ like could be useful after all). So we
301 * just check that transfers are OK at the beginning of our
302 * conversation with the chip and to avoid doing really nasty things
303 * (like injecting bogus packets in the network stack).
305 static int mcp251x_spi_trans(struct spi_device
*spi
, int len
)
307 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
308 struct spi_transfer t
= {
309 .tx_buf
= priv
->spi_tx_buf
,
310 .rx_buf
= priv
->spi_rx_buf
,
314 struct spi_message m
;
317 spi_message_init(&m
);
319 if (mcp251x_enable_dma
) {
320 t
.tx_dma
= priv
->spi_tx_dma
;
321 t
.rx_dma
= priv
->spi_rx_dma
;
325 spi_message_add_tail(&t
, &m
);
327 ret
= spi_sync(spi
, &m
);
329 dev_err(&spi
->dev
, "spi transfer failed: ret = %d\n", ret
);
333 static u8
mcp251x_read_reg(struct spi_device
*spi
, uint8_t reg
)
335 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
338 priv
->spi_tx_buf
[0] = INSTRUCTION_READ
;
339 priv
->spi_tx_buf
[1] = reg
;
341 mcp251x_spi_trans(spi
, 3);
342 val
= priv
->spi_rx_buf
[2];
347 static void mcp251x_read_2regs(struct spi_device
*spi
, uint8_t reg
,
348 uint8_t *v1
, uint8_t *v2
)
350 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
352 priv
->spi_tx_buf
[0] = INSTRUCTION_READ
;
353 priv
->spi_tx_buf
[1] = reg
;
355 mcp251x_spi_trans(spi
, 4);
357 *v1
= priv
->spi_rx_buf
[2];
358 *v2
= priv
->spi_rx_buf
[3];
361 static void mcp251x_write_reg(struct spi_device
*spi
, u8 reg
, uint8_t val
)
363 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
365 priv
->spi_tx_buf
[0] = INSTRUCTION_WRITE
;
366 priv
->spi_tx_buf
[1] = reg
;
367 priv
->spi_tx_buf
[2] = val
;
369 mcp251x_spi_trans(spi
, 3);
372 static void mcp251x_write_bits(struct spi_device
*spi
, u8 reg
,
373 u8 mask
, uint8_t val
)
375 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
377 priv
->spi_tx_buf
[0] = INSTRUCTION_BIT_MODIFY
;
378 priv
->spi_tx_buf
[1] = reg
;
379 priv
->spi_tx_buf
[2] = mask
;
380 priv
->spi_tx_buf
[3] = val
;
382 mcp251x_spi_trans(spi
, 4);
385 static void mcp251x_hw_tx_frame(struct spi_device
*spi
, u8
*buf
,
386 int len
, int tx_buf_idx
)
388 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
390 if (mcp251x_is_2510(spi
)) {
393 for (i
= 1; i
< TXBDAT_OFF
+ len
; i
++)
394 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
) + i
,
397 memcpy(priv
->spi_tx_buf
, buf
, TXBDAT_OFF
+ len
);
398 mcp251x_spi_trans(spi
, TXBDAT_OFF
+ len
);
402 static void mcp251x_hw_tx(struct spi_device
*spi
, struct can_frame
*frame
,
405 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
406 u32 sid
, eid
, exide
, rtr
;
407 u8 buf
[SPI_TRANSFER_BUF_LEN
];
409 exide
= (frame
->can_id
& CAN_EFF_FLAG
) ? 1 : 0; /* Extended ID Enable */
411 sid
= (frame
->can_id
& CAN_EFF_MASK
) >> 18;
413 sid
= frame
->can_id
& CAN_SFF_MASK
; /* Standard ID */
414 eid
= frame
->can_id
& CAN_EFF_MASK
; /* Extended ID */
415 rtr
= (frame
->can_id
& CAN_RTR_FLAG
) ? 1 : 0; /* Remote transmission */
417 buf
[TXBCTRL_OFF
] = INSTRUCTION_LOAD_TXB(tx_buf_idx
);
418 buf
[TXBSIDH_OFF
] = sid
>> SIDH_SHIFT
;
419 buf
[TXBSIDL_OFF
] = ((sid
& SIDL_SID_MASK
) << SIDL_SID_SHIFT
) |
420 (exide
<< SIDL_EXIDE_SHIFT
) |
421 ((eid
>> SIDL_EID_SHIFT
) & SIDL_EID_MASK
);
422 buf
[TXBEID8_OFF
] = GET_BYTE(eid
, 1);
423 buf
[TXBEID0_OFF
] = GET_BYTE(eid
, 0);
424 buf
[TXBDLC_OFF
] = (rtr
<< DLC_RTR_SHIFT
) | frame
->can_dlc
;
425 memcpy(buf
+ TXBDAT_OFF
, frame
->data
, frame
->can_dlc
);
426 mcp251x_hw_tx_frame(spi
, buf
, frame
->can_dlc
, tx_buf_idx
);
428 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
429 priv
->spi_tx_buf
[0] = INSTRUCTION_RTS(1 << tx_buf_idx
);
430 mcp251x_spi_trans(priv
->spi
, 1);
433 static void mcp251x_hw_rx_frame(struct spi_device
*spi
, u8
*buf
,
436 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
438 if (mcp251x_is_2510(spi
)) {
441 for (i
= 1; i
< RXBDAT_OFF
; i
++)
442 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
444 len
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
445 for (; i
< (RXBDAT_OFF
+ len
); i
++)
446 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
448 priv
->spi_tx_buf
[RXBCTRL_OFF
] = INSTRUCTION_READ_RXB(buf_idx
);
449 mcp251x_spi_trans(spi
, SPI_TRANSFER_BUF_LEN
);
450 memcpy(buf
, priv
->spi_rx_buf
, SPI_TRANSFER_BUF_LEN
);
454 static void mcp251x_hw_rx(struct spi_device
*spi
, int buf_idx
)
456 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
458 struct can_frame
*frame
;
459 u8 buf
[SPI_TRANSFER_BUF_LEN
];
461 skb
= alloc_can_skb(priv
->net
, &frame
);
463 dev_err(&spi
->dev
, "cannot allocate RX skb\n");
464 priv
->net
->stats
.rx_dropped
++;
468 mcp251x_hw_rx_frame(spi
, buf
, buf_idx
);
469 if (buf
[RXBSIDL_OFF
] & RXBSIDL_IDE
) {
470 /* Extended ID format */
471 frame
->can_id
= CAN_EFF_FLAG
;
473 /* Extended ID part */
474 SET_BYTE(buf
[RXBSIDL_OFF
] & RXBSIDL_EID
, 2) |
475 SET_BYTE(buf
[RXBEID8_OFF
], 1) |
476 SET_BYTE(buf
[RXBEID0_OFF
], 0) |
477 /* Standard ID part */
478 (((buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
479 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
)) << 18);
480 /* Remote transmission request */
481 if (buf
[RXBDLC_OFF
] & RXBDLC_RTR
)
482 frame
->can_id
|= CAN_RTR_FLAG
;
484 /* Standard ID format */
486 (buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
487 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
);
488 if (buf
[RXBSIDL_OFF
] & RXBSIDL_SRR
)
489 frame
->can_id
|= CAN_RTR_FLAG
;
492 frame
->can_dlc
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
493 memcpy(frame
->data
, buf
+ RXBDAT_OFF
, frame
->can_dlc
);
495 priv
->net
->stats
.rx_packets
++;
496 priv
->net
->stats
.rx_bytes
+= frame
->can_dlc
;
500 static void mcp251x_hw_sleep(struct spi_device
*spi
)
502 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_SLEEP
);
505 static netdev_tx_t
mcp251x_hard_start_xmit(struct sk_buff
*skb
,
506 struct net_device
*net
)
508 struct mcp251x_priv
*priv
= netdev_priv(net
);
509 struct spi_device
*spi
= priv
->spi
;
511 if (priv
->tx_skb
|| priv
->tx_len
) {
512 dev_warn(&spi
->dev
, "hard_xmit called while tx busy\n");
513 return NETDEV_TX_BUSY
;
516 if (can_dropped_invalid_skb(net
, skb
))
519 netif_stop_queue(net
);
521 queue_work(priv
->wq
, &priv
->tx_work
);
526 static int mcp251x_do_set_mode(struct net_device
*net
, enum can_mode mode
)
528 struct mcp251x_priv
*priv
= netdev_priv(net
);
533 /* We have to delay work since SPI I/O may sleep */
534 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
535 priv
->restart_tx
= 1;
536 if (priv
->can
.restart_ms
== 0)
537 priv
->after_suspend
= AFTER_SUSPEND_RESTART
;
538 queue_work(priv
->wq
, &priv
->restart_work
);
547 static int mcp251x_set_normal_mode(struct spi_device
*spi
)
549 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
550 unsigned long timeout
;
552 /* Enable interrupts */
553 mcp251x_write_reg(spi
, CANINTE
,
554 CANINTE_ERRIE
| CANINTE_TX2IE
| CANINTE_TX1IE
|
555 CANINTE_TX0IE
| CANINTE_RX1IE
| CANINTE_RX0IE
);
557 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
) {
558 /* Put device into loopback mode */
559 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LOOPBACK
);
560 } else if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
) {
561 /* Put device into listen-only mode */
562 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LISTEN_ONLY
);
564 /* Put device into normal mode */
565 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_NORMAL
);
567 /* Wait for the device to enter normal mode */
568 timeout
= jiffies
+ HZ
;
569 while (mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
) {
571 if (time_after(jiffies
, timeout
)) {
572 dev_err(&spi
->dev
, "MCP251x didn't"
573 " enter in normal mode\n");
578 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
582 static int mcp251x_do_set_bittiming(struct net_device
*net
)
584 struct mcp251x_priv
*priv
= netdev_priv(net
);
585 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
586 struct spi_device
*spi
= priv
->spi
;
588 mcp251x_write_reg(spi
, CNF1
, ((bt
->sjw
- 1) << CNF1_SJW_SHIFT
) |
590 mcp251x_write_reg(spi
, CNF2
, CNF2_BTLMODE
|
591 (priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
?
593 ((bt
->phase_seg1
- 1) << CNF2_PS1_SHIFT
) |
595 mcp251x_write_bits(spi
, CNF3
, CNF3_PHSEG2_MASK
,
596 (bt
->phase_seg2
- 1));
597 dev_info(&spi
->dev
, "CNF: 0x%02x 0x%02x 0x%02x\n",
598 mcp251x_read_reg(spi
, CNF1
),
599 mcp251x_read_reg(spi
, CNF2
),
600 mcp251x_read_reg(spi
, CNF3
));
605 static int mcp251x_setup(struct net_device
*net
, struct mcp251x_priv
*priv
,
606 struct spi_device
*spi
)
608 mcp251x_do_set_bittiming(net
);
610 mcp251x_write_reg(spi
, RXBCTRL(0),
611 RXBCTRL_BUKT
| RXBCTRL_RXM0
| RXBCTRL_RXM1
);
612 mcp251x_write_reg(spi
, RXBCTRL(1),
613 RXBCTRL_RXM0
| RXBCTRL_RXM1
);
617 static int mcp251x_hw_reset(struct spi_device
*spi
)
619 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
621 unsigned long timeout
;
623 priv
->spi_tx_buf
[0] = INSTRUCTION_RESET
;
624 ret
= spi_write(spi
, priv
->spi_tx_buf
, 1);
626 dev_err(&spi
->dev
, "reset failed: ret = %d\n", ret
);
630 /* Wait for reset to finish */
631 timeout
= jiffies
+ HZ
;
633 while ((mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
)
634 != CANCTRL_REQOP_CONF
) {
636 if (time_after(jiffies
, timeout
)) {
637 dev_err(&spi
->dev
, "MCP251x didn't"
638 " enter in conf mode after reset\n");
645 static int mcp251x_hw_probe(struct spi_device
*spi
)
649 mcp251x_hw_reset(spi
);
652 * Please note that these are "magic values" based on after
653 * reset defaults taken from data sheet which allows us to see
654 * if we really have a chip on the bus (we avoid common all
655 * zeroes or all ones situations)
657 st1
= mcp251x_read_reg(spi
, CANSTAT
) & 0xEE;
658 st2
= mcp251x_read_reg(spi
, CANCTRL
) & 0x17;
660 dev_dbg(&spi
->dev
, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1
, st2
);
662 /* Check for power up default values */
663 return (st1
== 0x80 && st2
== 0x07) ? 1 : 0;
666 static void mcp251x_open_clean(struct net_device
*net
)
668 struct mcp251x_priv
*priv
= netdev_priv(net
);
669 struct spi_device
*spi
= priv
->spi
;
670 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
672 free_irq(spi
->irq
, priv
);
673 mcp251x_hw_sleep(spi
);
674 if (pdata
->transceiver_enable
)
675 pdata
->transceiver_enable(0);
679 static int mcp251x_stop(struct net_device
*net
)
681 struct mcp251x_priv
*priv
= netdev_priv(net
);
682 struct spi_device
*spi
= priv
->spi
;
683 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
687 priv
->force_quit
= 1;
688 free_irq(spi
->irq
, priv
);
689 destroy_workqueue(priv
->wq
);
692 mutex_lock(&priv
->mcp_lock
);
694 /* Disable and clear pending interrupts */
695 mcp251x_write_reg(spi
, CANINTE
, 0x00);
696 mcp251x_write_reg(spi
, CANINTF
, 0x00);
698 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
701 mcp251x_hw_sleep(spi
);
703 if (pdata
->transceiver_enable
)
704 pdata
->transceiver_enable(0);
706 priv
->can
.state
= CAN_STATE_STOPPED
;
708 mutex_unlock(&priv
->mcp_lock
);
713 static void mcp251x_error_skb(struct net_device
*net
, int can_id
, int data1
)
716 struct can_frame
*frame
;
718 skb
= alloc_can_err_skb(net
, &frame
);
720 frame
->can_id
|= can_id
;
721 frame
->data
[1] = data1
;
724 netdev_err(net
, "cannot allocate error skb\n");
728 static void mcp251x_tx_work_handler(struct work_struct
*ws
)
730 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
732 struct spi_device
*spi
= priv
->spi
;
733 struct net_device
*net
= priv
->net
;
734 struct can_frame
*frame
;
736 mutex_lock(&priv
->mcp_lock
);
738 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
741 frame
= (struct can_frame
*)priv
->tx_skb
->data
;
743 if (frame
->can_dlc
> CAN_FRAME_MAX_DATA_LEN
)
744 frame
->can_dlc
= CAN_FRAME_MAX_DATA_LEN
;
745 mcp251x_hw_tx(spi
, frame
, 0);
746 priv
->tx_len
= 1 + frame
->can_dlc
;
747 can_put_echo_skb(priv
->tx_skb
, net
, 0);
751 mutex_unlock(&priv
->mcp_lock
);
754 static void mcp251x_restart_work_handler(struct work_struct
*ws
)
756 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
758 struct spi_device
*spi
= priv
->spi
;
759 struct net_device
*net
= priv
->net
;
761 mutex_lock(&priv
->mcp_lock
);
762 if (priv
->after_suspend
) {
764 mcp251x_hw_reset(spi
);
765 mcp251x_setup(net
, priv
, spi
);
766 if (priv
->after_suspend
& AFTER_SUSPEND_RESTART
) {
767 mcp251x_set_normal_mode(spi
);
768 } else if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
769 netif_device_attach(net
);
771 mcp251x_set_normal_mode(spi
);
772 netif_wake_queue(net
);
774 mcp251x_hw_sleep(spi
);
776 priv
->after_suspend
= 0;
777 priv
->force_quit
= 0;
780 if (priv
->restart_tx
) {
781 priv
->restart_tx
= 0;
782 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
784 netif_wake_queue(net
);
785 mcp251x_error_skb(net
, CAN_ERR_RESTARTED
, 0);
787 mutex_unlock(&priv
->mcp_lock
);
790 static irqreturn_t
mcp251x_can_ist(int irq
, void *dev_id
)
792 struct mcp251x_priv
*priv
= dev_id
;
793 struct spi_device
*spi
= priv
->spi
;
794 struct net_device
*net
= priv
->net
;
796 mutex_lock(&priv
->mcp_lock
);
797 while (!priv
->force_quit
) {
798 enum can_state new_state
;
801 int can_id
= 0, data1
= 0;
803 mcp251x_read_2regs(spi
, CANINTF
, &intf
, &eflag
);
805 /* mask out flags we don't care about */
806 intf
&= CANINTF_RX
| CANINTF_TX
| CANINTF_ERR
;
808 /* receive buffer 0 */
809 if (intf
& CANINTF_RX0IF
) {
810 mcp251x_hw_rx(spi
, 0);
812 * Free one buffer ASAP
813 * (The MCP2515 does this automatically.)
815 if (mcp251x_is_2510(spi
))
816 mcp251x_write_bits(spi
, CANINTF
, CANINTF_RX0IF
, 0x00);
819 /* receive buffer 1 */
820 if (intf
& CANINTF_RX1IF
) {
821 mcp251x_hw_rx(spi
, 1);
822 /* the MCP2515 does this automatically */
823 if (mcp251x_is_2510(spi
))
824 clear_intf
|= CANINTF_RX1IF
;
827 /* any error or tx interrupt we need to clear? */
828 if (intf
& (CANINTF_ERR
| CANINTF_TX
))
829 clear_intf
|= intf
& (CANINTF_ERR
| CANINTF_TX
);
831 mcp251x_write_bits(spi
, CANINTF
, clear_intf
, 0x00);
834 mcp251x_write_bits(spi
, EFLG
, eflag
, 0x00);
836 /* Update can state */
837 if (eflag
& EFLG_TXBO
) {
838 new_state
= CAN_STATE_BUS_OFF
;
839 can_id
|= CAN_ERR_BUSOFF
;
840 } else if (eflag
& EFLG_TXEP
) {
841 new_state
= CAN_STATE_ERROR_PASSIVE
;
842 can_id
|= CAN_ERR_CRTL
;
843 data1
|= CAN_ERR_CRTL_TX_PASSIVE
;
844 } else if (eflag
& EFLG_RXEP
) {
845 new_state
= CAN_STATE_ERROR_PASSIVE
;
846 can_id
|= CAN_ERR_CRTL
;
847 data1
|= CAN_ERR_CRTL_RX_PASSIVE
;
848 } else if (eflag
& EFLG_TXWAR
) {
849 new_state
= CAN_STATE_ERROR_WARNING
;
850 can_id
|= CAN_ERR_CRTL
;
851 data1
|= CAN_ERR_CRTL_TX_WARNING
;
852 } else if (eflag
& EFLG_RXWAR
) {
853 new_state
= CAN_STATE_ERROR_WARNING
;
854 can_id
|= CAN_ERR_CRTL
;
855 data1
|= CAN_ERR_CRTL_RX_WARNING
;
857 new_state
= CAN_STATE_ERROR_ACTIVE
;
860 /* Update can state statistics */
861 switch (priv
->can
.state
) {
862 case CAN_STATE_ERROR_ACTIVE
:
863 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
864 new_state
<= CAN_STATE_BUS_OFF
)
865 priv
->can
.can_stats
.error_warning
++;
866 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
867 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
868 new_state
<= CAN_STATE_BUS_OFF
)
869 priv
->can
.can_stats
.error_passive
++;
874 priv
->can
.state
= new_state
;
876 if (intf
& CANINTF_ERRIF
) {
877 /* Handle overflow counters */
878 if (eflag
& (EFLG_RX0OVR
| EFLG_RX1OVR
)) {
879 if (eflag
& EFLG_RX0OVR
) {
880 net
->stats
.rx_over_errors
++;
881 net
->stats
.rx_errors
++;
883 if (eflag
& EFLG_RX1OVR
) {
884 net
->stats
.rx_over_errors
++;
885 net
->stats
.rx_errors
++;
887 can_id
|= CAN_ERR_CRTL
;
888 data1
|= CAN_ERR_CRTL_RX_OVERFLOW
;
890 mcp251x_error_skb(net
, can_id
, data1
);
893 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
894 if (priv
->can
.restart_ms
== 0) {
895 priv
->force_quit
= 1;
897 mcp251x_hw_sleep(spi
);
905 if (intf
& CANINTF_TX
) {
906 net
->stats
.tx_packets
++;
907 net
->stats
.tx_bytes
+= priv
->tx_len
- 1;
909 can_get_echo_skb(net
, 0);
912 netif_wake_queue(net
);
916 mutex_unlock(&priv
->mcp_lock
);
920 static int mcp251x_open(struct net_device
*net
)
922 struct mcp251x_priv
*priv
= netdev_priv(net
);
923 struct spi_device
*spi
= priv
->spi
;
924 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
927 ret
= open_candev(net
);
929 dev_err(&spi
->dev
, "unable to set initial baudrate!\n");
933 mutex_lock(&priv
->mcp_lock
);
934 if (pdata
->transceiver_enable
)
935 pdata
->transceiver_enable(1);
937 priv
->force_quit
= 0;
941 ret
= request_threaded_irq(spi
->irq
, NULL
, mcp251x_can_ist
,
942 pdata
->irq_flags
? pdata
->irq_flags
: IRQF_TRIGGER_FALLING
,
945 dev_err(&spi
->dev
, "failed to acquire irq %d\n", spi
->irq
);
946 if (pdata
->transceiver_enable
)
947 pdata
->transceiver_enable(0);
952 priv
->wq
= create_freezable_workqueue("mcp251x_wq");
953 INIT_WORK(&priv
->tx_work
, mcp251x_tx_work_handler
);
954 INIT_WORK(&priv
->restart_work
, mcp251x_restart_work_handler
);
956 ret
= mcp251x_hw_reset(spi
);
958 mcp251x_open_clean(net
);
961 ret
= mcp251x_setup(net
, priv
, spi
);
963 mcp251x_open_clean(net
);
966 ret
= mcp251x_set_normal_mode(spi
);
968 mcp251x_open_clean(net
);
971 netif_wake_queue(net
);
974 mutex_unlock(&priv
->mcp_lock
);
978 static const struct net_device_ops mcp251x_netdev_ops
= {
979 .ndo_open
= mcp251x_open
,
980 .ndo_stop
= mcp251x_stop
,
981 .ndo_start_xmit
= mcp251x_hard_start_xmit
,
984 static int __devinit
mcp251x_can_probe(struct spi_device
*spi
)
986 struct net_device
*net
;
987 struct mcp251x_priv
*priv
;
988 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
992 /* Platform data is required for osc freq */
995 /* Allocate can/net device */
996 net
= alloc_candev(sizeof(struct mcp251x_priv
), TX_ECHO_SKB_MAX
);
1002 net
->netdev_ops
= &mcp251x_netdev_ops
;
1003 net
->flags
|= IFF_ECHO
;
1005 priv
= netdev_priv(net
);
1006 priv
->can
.bittiming_const
= &mcp251x_bittiming_const
;
1007 priv
->can
.do_set_mode
= mcp251x_do_set_mode
;
1008 priv
->can
.clock
.freq
= pdata
->oscillator_frequency
/ 2;
1009 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
|
1010 CAN_CTRLMODE_LOOPBACK
| CAN_CTRLMODE_LISTENONLY
;
1011 priv
->model
= spi_get_device_id(spi
)->driver_data
;
1013 dev_set_drvdata(&spi
->dev
, priv
);
1016 mutex_init(&priv
->mcp_lock
);
1018 /* If requested, allocate DMA buffers */
1019 if (mcp251x_enable_dma
) {
1020 spi
->dev
.coherent_dma_mask
= ~0;
1023 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1024 * that much and share it between Tx and Rx DMA buffers.
1026 priv
->spi_tx_buf
= dma_alloc_coherent(&spi
->dev
,
1031 if (priv
->spi_tx_buf
) {
1032 priv
->spi_rx_buf
= (priv
->spi_tx_buf
+ (PAGE_SIZE
/ 2));
1033 priv
->spi_rx_dma
= (dma_addr_t
)(priv
->spi_tx_dma
+
1036 /* Fall back to non-DMA */
1037 mcp251x_enable_dma
= 0;
1041 /* Allocate non-DMA buffers */
1042 if (!mcp251x_enable_dma
) {
1043 priv
->spi_tx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
1044 if (!priv
->spi_tx_buf
) {
1048 priv
->spi_rx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
1049 if (!priv
->spi_rx_buf
) {
1055 if (pdata
->power_enable
)
1056 pdata
->power_enable(1);
1058 /* Call out to platform specific setup */
1059 if (pdata
->board_specific_setup
)
1060 pdata
->board_specific_setup(spi
);
1062 SET_NETDEV_DEV(net
, &spi
->dev
);
1064 /* Configure the SPI bus */
1065 spi
->mode
= SPI_MODE_0
;
1066 spi
->bits_per_word
= 8;
1069 /* Here is OK to not lock the MCP, no one knows about it yet */
1070 if (!mcp251x_hw_probe(spi
)) {
1071 dev_info(&spi
->dev
, "Probe failed\n");
1074 mcp251x_hw_sleep(spi
);
1076 if (pdata
->transceiver_enable
)
1077 pdata
->transceiver_enable(0);
1079 ret
= register_candev(net
);
1081 dev_info(&spi
->dev
, "probed\n");
1085 if (!mcp251x_enable_dma
)
1086 kfree(priv
->spi_rx_buf
);
1088 if (!mcp251x_enable_dma
)
1089 kfree(priv
->spi_tx_buf
);
1092 if (mcp251x_enable_dma
)
1093 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1094 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1096 if (pdata
->power_enable
)
1097 pdata
->power_enable(0);
1098 dev_err(&spi
->dev
, "probe failed\n");
1103 static int __devexit
mcp251x_can_remove(struct spi_device
*spi
)
1105 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1106 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1107 struct net_device
*net
= priv
->net
;
1109 unregister_candev(net
);
1112 if (mcp251x_enable_dma
) {
1113 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1114 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1116 kfree(priv
->spi_tx_buf
);
1117 kfree(priv
->spi_rx_buf
);
1120 if (pdata
->power_enable
)
1121 pdata
->power_enable(0);
1127 static int mcp251x_can_suspend(struct spi_device
*spi
, pm_message_t state
)
1129 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1130 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1131 struct net_device
*net
= priv
->net
;
1133 priv
->force_quit
= 1;
1134 disable_irq(spi
->irq
);
1136 * Note: at this point neither IST nor workqueues are running.
1137 * open/stop cannot be called anyway so locking is not needed
1139 if (netif_running(net
)) {
1140 netif_device_detach(net
);
1142 mcp251x_hw_sleep(spi
);
1143 if (pdata
->transceiver_enable
)
1144 pdata
->transceiver_enable(0);
1145 priv
->after_suspend
= AFTER_SUSPEND_UP
;
1147 priv
->after_suspend
= AFTER_SUSPEND_DOWN
;
1150 if (pdata
->power_enable
) {
1151 pdata
->power_enable(0);
1152 priv
->after_suspend
|= AFTER_SUSPEND_POWER
;
1158 static int mcp251x_can_resume(struct spi_device
*spi
)
1160 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1161 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1163 if (priv
->after_suspend
& AFTER_SUSPEND_POWER
) {
1164 pdata
->power_enable(1);
1165 queue_work(priv
->wq
, &priv
->restart_work
);
1167 if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
1168 if (pdata
->transceiver_enable
)
1169 pdata
->transceiver_enable(1);
1170 queue_work(priv
->wq
, &priv
->restart_work
);
1172 priv
->after_suspend
= 0;
1175 priv
->force_quit
= 0;
1176 enable_irq(spi
->irq
);
1180 #define mcp251x_can_suspend NULL
1181 #define mcp251x_can_resume NULL
1184 static const struct spi_device_id mcp251x_id_table
[] = {
1185 { "mcp2510", CAN_MCP251X_MCP2510
},
1186 { "mcp2515", CAN_MCP251X_MCP2515
},
1190 MODULE_DEVICE_TABLE(spi
, mcp251x_id_table
);
1192 static struct spi_driver mcp251x_can_driver
= {
1194 .name
= DEVICE_NAME
,
1195 .bus
= &spi_bus_type
,
1196 .owner
= THIS_MODULE
,
1199 .id_table
= mcp251x_id_table
,
1200 .probe
= mcp251x_can_probe
,
1201 .remove
= __devexit_p(mcp251x_can_remove
),
1202 .suspend
= mcp251x_can_suspend
,
1203 .resume
= mcp251x_can_resume
,
1206 static int __init
mcp251x_can_init(void)
1208 return spi_register_driver(&mcp251x_can_driver
);
1211 static void __exit
mcp251x_can_exit(void)
1213 spi_unregister_driver(&mcp251x_can_driver
);
1216 module_init(mcp251x_can_init
);
1217 module_exit(mcp251x_can_exit
);
1219 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1220 "Christian Pellegrin <chripell@evolware.org>");
1221 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1222 MODULE_LICENSE("GPL v2");