2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
4 * Derived from the ems_pci.c driver:
5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/pci.h>
29 #include <linux/can/dev.h>
34 #define DRV_NAME "sja1000_plx_pci"
36 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
37 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
39 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
40 "Adlink PCI-7841/cPCI-7841 SE, "
41 "Marathon CAN-bus-PCI, "
42 "TEWS TECHNOLOGIES TPMC810, "
43 "esd CAN-PCI/CPCI/PCI104/200, "
44 "esd CAN-PCI/PMC/266, "
46 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), "
49 MODULE_LICENSE("GPL v2");
51 #define PLX_PCI_MAX_CHAN 2
54 int channels
; /* detected channels count */
55 struct net_device
*net_dev
[PLX_PCI_MAX_CHAN
];
56 void __iomem
*conf_addr
;
58 /* Pointer to device-dependent reset function */
59 void (*reset_func
)(struct pci_dev
*pdev
);
62 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
64 /* PLX9030/9050/9052 registers */
65 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */
66 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
67 * Serial EEPROM, and Initialization
71 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
72 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
73 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
74 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
76 /* PLX9056 registers */
77 #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */
78 #define PLX9056_CNTRL 0x6c /* Control / Software Reset */
80 #define PLX9056_LINTI (1 << 11)
81 #define PLX9056_PCI_INT_EN (1 << 8)
82 #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */
85 * The board configuration is probably following:
86 * RX1 is connected to ground.
87 * TX1 is not connected.
88 * CLKO is not connected.
89 * Setting the OCR register to 0xDA is a good idea.
90 * This means normal output mode, push-pull and the correct polarity.
92 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
95 * In the CDR register, you should set CBP to 1.
96 * You will probably also want to set the clock divider value to 7
97 * (meaning direct oscillator output) because the second SJA1000 chip
98 * is driven by the first one CLKOUT output.
100 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
102 /* SJA1000 Control Register in the BasicCAN Mode */
105 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
106 #define REG_CR_BASICCAN_INITIAL 0x21
107 #define REG_CR_BASICCAN_INITIAL_MASK 0xa1
108 #define REG_SR_BASICCAN_INITIAL 0x0c
109 #define REG_IR_BASICCAN_INITIAL 0xe0
111 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
112 #define REG_MOD_PELICAN_INITIAL 0x01
113 #define REG_SR_PELICAN_INITIAL 0x3c
114 #define REG_IR_PELICAN_INITIAL 0x00
116 #define ADLINK_PCI_VENDOR_ID 0x144A
117 #define ADLINK_PCI_DEVICE_ID 0x7841
119 #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004
120 #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009
121 #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e
122 #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b
123 #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200
124 #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501
126 #define CAN200PCI_DEVICE_ID 0x9030
127 #define CAN200PCI_VENDOR_ID 0x10b5
128 #define CAN200PCI_SUB_DEVICE_ID 0x0301
129 #define CAN200PCI_SUB_VENDOR_ID 0xe1c5
131 #define IXXAT_PCI_VENDOR_ID 0x10b5
132 #define IXXAT_PCI_DEVICE_ID 0x9050
133 #define IXXAT_PCI_SUB_SYS_ID 0x2540
135 #define MARATHON_PCI_DEVICE_ID 0x2715
137 #define TEWS_PCI_VENDOR_ID 0x1498
138 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
140 #define CTI_PCI_VENDOR_ID 0x12c4
141 #define CTI_PCI_DEVICE_ID_CRG001 0x0900
143 static void plx_pci_reset_common(struct pci_dev
*pdev
);
144 static void plx_pci_reset_marathon(struct pci_dev
*pdev
);
145 static void plx9056_pci_reset_common(struct pci_dev
*pdev
);
147 struct plx_pci_channel_map
{
150 u32 size
; /* 0x00 - auto, e.g. length of entire bar */
153 struct plx_pci_card_info
{
157 u8 ocr
; /* output control register */
158 u8 cdr
; /* clock divider register */
160 /* Parameters for mapping local configuration space */
161 struct plx_pci_channel_map conf_map
;
163 /* Parameters for mapping the SJA1000 chips */
164 struct plx_pci_channel_map chan_map_tbl
[PLX_PCI_MAX_CHAN
];
166 /* Pointer to device-dependent reset function */
167 void (*reset_func
)(struct pci_dev
*pdev
);
170 static struct plx_pci_card_info plx_pci_card_info_adlink
= {
171 "Adlink PCI-7841/cPCI-7841", 2,
172 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
173 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
174 &plx_pci_reset_common
175 /* based on PLX9052 */
178 static struct plx_pci_card_info plx_pci_card_info_adlink_se
= {
179 "Adlink PCI-7841/cPCI-7841 SE", 2,
180 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
181 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
182 &plx_pci_reset_common
183 /* based on PLX9052 */
186 static struct plx_pci_card_info plx_pci_card_info_esd200
= {
187 "esd CAN-PCI/CPCI/PCI104/200", 2,
188 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
189 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
190 &plx_pci_reset_common
191 /* based on PLX9030/9050 */
194 static struct plx_pci_card_info plx_pci_card_info_esd266
= {
195 "esd CAN-PCI/PMC/266", 2,
196 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
197 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
198 &plx9056_pci_reset_common
199 /* based on PLX9056 */
202 static struct plx_pci_card_info plx_pci_card_info_esd2000
= {
203 "esd CAN-PCIe/2000", 2,
204 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
205 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
206 &plx9056_pci_reset_common
207 /* based on PEX8311 */
210 static struct plx_pci_card_info plx_pci_card_info_ixxat
= {
211 "IXXAT PC-I 04/PCI", 2,
212 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
213 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
214 &plx_pci_reset_common
215 /* based on PLX9050 */
218 static struct plx_pci_card_info plx_pci_card_info_marathon
= {
219 "Marathon CAN-bus-PCI", 2,
220 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
221 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
222 &plx_pci_reset_marathon
223 /* based on PLX9052 */
226 static struct plx_pci_card_info plx_pci_card_info_tews
= {
227 "TEWS TECHNOLOGIES TPMC810", 2,
228 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
229 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
230 &plx_pci_reset_common
231 /* based on PLX9030 */
234 static struct plx_pci_card_info plx_pci_card_info_cti
= {
235 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
236 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
237 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
238 &plx_pci_reset_common
239 /* based on PLX9030 */
242 static struct plx_pci_card_info plx_pci_card_info_elcus
= {
243 "Eclus CAN-200-PCI", 2,
244 PLX_PCI_CAN_CLOCK
, PLX_PCI_OCR
, PLX_PCI_CDR
,
245 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
246 &plx_pci_reset_common
247 /* based on PLX9030 */
250 static const struct pci_device_id plx_pci_tbl
[] = {
252 /* Adlink PCI-7841/cPCI-7841 */
253 ADLINK_PCI_VENDOR_ID
, ADLINK_PCI_DEVICE_ID
,
254 PCI_ANY_ID
, PCI_ANY_ID
,
255 PCI_CLASS_NETWORK_OTHER
<< 8, ~0,
256 (kernel_ulong_t
)&plx_pci_card_info_adlink
259 /* Adlink PCI-7841/cPCI-7841 SE */
260 ADLINK_PCI_VENDOR_ID
, ADLINK_PCI_DEVICE_ID
,
261 PCI_ANY_ID
, PCI_ANY_ID
,
262 PCI_CLASS_COMMUNICATION_OTHER
<< 8, ~0,
263 (kernel_ulong_t
)&plx_pci_card_info_adlink_se
266 /* esd CAN-PCI/200 */
267 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
268 PCI_VENDOR_ID_ESDGMBH
, ESD_PCI_SUB_SYS_ID_PCI200
,
270 (kernel_ulong_t
)&plx_pci_card_info_esd200
273 /* esd CAN-CPCI/200 */
274 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
275 PCI_VENDOR_ID_ESDGMBH
, ESD_PCI_SUB_SYS_ID_CPCI200
,
277 (kernel_ulong_t
)&plx_pci_card_info_esd200
280 /* esd CAN-PCI104/200 */
281 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
282 PCI_VENDOR_ID_ESDGMBH
, ESD_PCI_SUB_SYS_ID_PCI104200
,
284 (kernel_ulong_t
)&plx_pci_card_info_esd200
287 /* esd CAN-PCI/266 */
288 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9056
,
289 PCI_VENDOR_ID_ESDGMBH
, ESD_PCI_SUB_SYS_ID_PCI266
,
291 (kernel_ulong_t
)&plx_pci_card_info_esd266
294 /* esd CAN-PMC/266 */
295 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9056
,
296 PCI_VENDOR_ID_ESDGMBH
, ESD_PCI_SUB_SYS_ID_PMC266
,
298 (kernel_ulong_t
)&plx_pci_card_info_esd266
301 /* esd CAN-PCIE/2000 */
302 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9056
,
303 PCI_VENDOR_ID_ESDGMBH
, ESD_PCI_SUB_SYS_ID_PCIE2000
,
305 (kernel_ulong_t
)&plx_pci_card_info_esd2000
308 /* IXXAT PC-I 04/PCI card */
309 IXXAT_PCI_VENDOR_ID
, IXXAT_PCI_DEVICE_ID
,
310 PCI_ANY_ID
, IXXAT_PCI_SUB_SYS_ID
,
312 (kernel_ulong_t
)&plx_pci_card_info_ixxat
315 /* Marathon CAN-bus-PCI card */
316 PCI_VENDOR_ID_PLX
, MARATHON_PCI_DEVICE_ID
,
317 PCI_ANY_ID
, PCI_ANY_ID
,
319 (kernel_ulong_t
)&plx_pci_card_info_marathon
322 /* TEWS TECHNOLOGIES TPMC810 card */
323 TEWS_PCI_VENDOR_ID
, TEWS_PCI_DEVICE_ID_TMPC810
,
324 PCI_ANY_ID
, PCI_ANY_ID
,
326 (kernel_ulong_t
)&plx_pci_card_info_tews
329 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
330 PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
331 CTI_PCI_VENDOR_ID
, CTI_PCI_DEVICE_ID_CRG001
,
333 (kernel_ulong_t
)&plx_pci_card_info_cti
336 /* Elcus CAN-200-PCI */
337 CAN200PCI_VENDOR_ID
, CAN200PCI_DEVICE_ID
,
338 CAN200PCI_SUB_VENDOR_ID
, CAN200PCI_SUB_DEVICE_ID
,
340 (kernel_ulong_t
)&plx_pci_card_info_elcus
344 MODULE_DEVICE_TABLE(pci
, plx_pci_tbl
);
346 static u8
plx_pci_read_reg(const struct sja1000_priv
*priv
, int port
)
348 return ioread8(priv
->reg_base
+ port
);
351 static void plx_pci_write_reg(const struct sja1000_priv
*priv
, int port
, u8 val
)
353 iowrite8(val
, priv
->reg_base
+ port
);
357 * Check if a CAN controller is present at the specified location
358 * by trying to switch 'em from the Basic mode into the PeliCAN mode.
359 * Also check states of some registers in reset mode.
361 static inline int plx_pci_check_sja1000(const struct sja1000_priv
*priv
)
366 * Check registers after hardware reset (the Basic mode)
367 * See states on p. 10 of the Datasheet.
369 if ((priv
->read_reg(priv
, REG_CR
) & REG_CR_BASICCAN_INITIAL_MASK
) ==
370 REG_CR_BASICCAN_INITIAL
&&
371 (priv
->read_reg(priv
, SJA1000_SR
) == REG_SR_BASICCAN_INITIAL
) &&
372 (priv
->read_reg(priv
, SJA1000_IR
) == REG_IR_BASICCAN_INITIAL
))
375 /* Bring the SJA1000 into the PeliCAN mode*/
376 priv
->write_reg(priv
, SJA1000_CDR
, CDR_PELICAN
);
379 * Check registers after reset in the PeliCAN mode.
380 * See states on p. 23 of the Datasheet.
382 if (priv
->read_reg(priv
, SJA1000_MOD
) == REG_MOD_PELICAN_INITIAL
&&
383 priv
->read_reg(priv
, SJA1000_SR
) == REG_SR_PELICAN_INITIAL
&&
384 priv
->read_reg(priv
, SJA1000_IR
) == REG_IR_PELICAN_INITIAL
)
391 * PLX9030/50/52 software reset
392 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
393 * For most cards it's enough for reset the SJA1000 chips.
395 static void plx_pci_reset_common(struct pci_dev
*pdev
)
397 struct plx_pci_card
*card
= pci_get_drvdata(pdev
);
400 cntrl
= ioread32(card
->conf_addr
+ PLX_CNTRL
);
401 cntrl
|= PLX_PCI_RESET
;
402 iowrite32(cntrl
, card
->conf_addr
+ PLX_CNTRL
);
404 cntrl
^= PLX_PCI_RESET
;
405 iowrite32(cntrl
, card
->conf_addr
+ PLX_CNTRL
);
409 * PLX9056 software reset
410 * Assert LRESET# and reset device(s) on the Local Bus (if wired).
412 static void plx9056_pci_reset_common(struct pci_dev
*pdev
)
414 struct plx_pci_card
*card
= pci_get_drvdata(pdev
);
417 /* issue a local bus reset */
418 cntrl
= ioread32(card
->conf_addr
+ PLX9056_CNTRL
);
419 cntrl
|= PLX_PCI_RESET
;
420 iowrite32(cntrl
, card
->conf_addr
+ PLX9056_CNTRL
);
422 cntrl
^= PLX_PCI_RESET
;
423 iowrite32(cntrl
, card
->conf_addr
+ PLX9056_CNTRL
);
425 /* reload local configuration from EEPROM */
426 cntrl
|= PLX9056_PCI_RCR
;
427 iowrite32(cntrl
, card
->conf_addr
+ PLX9056_CNTRL
);
430 * There is no safe way to poll for the end
431 * of reconfiguration process. Waiting for 10ms
436 cntrl
^= PLX9056_PCI_RCR
;
437 iowrite32(cntrl
, card
->conf_addr
+ PLX9056_CNTRL
);
440 /* Special reset function for Marathon card */
441 static void plx_pci_reset_marathon(struct pci_dev
*pdev
)
443 void __iomem
*reset_addr
;
445 static const int reset_bar
[2] = {3, 5};
447 plx_pci_reset_common(pdev
);
449 for (i
= 0; i
< 2; i
++) {
450 reset_addr
= pci_iomap(pdev
, reset_bar
[i
], 0);
452 dev_err(&pdev
->dev
, "Failed to remap reset "
453 "space %d (BAR%d)\n", i
, reset_bar
[i
]);
455 /* reset the SJA1000 chip */
456 iowrite8(0x1, reset_addr
);
458 pci_iounmap(pdev
, reset_addr
);
463 static void plx_pci_del_card(struct pci_dev
*pdev
)
465 struct plx_pci_card
*card
= pci_get_drvdata(pdev
);
466 struct net_device
*dev
;
467 struct sja1000_priv
*priv
;
470 for (i
= 0; i
< PLX_PCI_MAX_CHAN
; i
++) {
471 dev
= card
->net_dev
[i
];
475 dev_info(&pdev
->dev
, "Removing %s\n", dev
->name
);
476 unregister_sja1000dev(dev
);
477 priv
= netdev_priv(dev
);
479 pci_iounmap(pdev
, priv
->reg_base
);
480 free_sja1000dev(dev
);
483 card
->reset_func(pdev
);
486 * Disable interrupts from PCI-card and disable local
489 if (pdev
->device
!= PCI_DEVICE_ID_PLX_9056
)
490 iowrite32(0x0, card
->conf_addr
+ PLX_INTCSR
);
492 iowrite32(0x0, card
->conf_addr
+ PLX9056_INTCSR
);
495 pci_iounmap(pdev
, card
->conf_addr
);
499 pci_disable_device(pdev
);
503 * Probe PLX90xx based device for the SJA1000 chips and register each
504 * available CAN channel to SJA1000 Socket-CAN subsystem.
506 static int plx_pci_add_card(struct pci_dev
*pdev
,
507 const struct pci_device_id
*ent
)
509 struct sja1000_priv
*priv
;
510 struct net_device
*dev
;
511 struct plx_pci_card
*card
;
512 struct plx_pci_card_info
*ci
;
517 ci
= (struct plx_pci_card_info
*)ent
->driver_data
;
519 if (pci_enable_device(pdev
) < 0) {
520 dev_err(&pdev
->dev
, "Failed to enable PCI device\n");
524 dev_info(&pdev
->dev
, "Detected \"%s\" card at slot #%i\n",
525 ci
->name
, PCI_SLOT(pdev
->devfn
));
527 /* Allocate card structures to hold addresses, ... */
528 card
= kzalloc(sizeof(*card
), GFP_KERNEL
);
530 pci_disable_device(pdev
);
534 pci_set_drvdata(pdev
, card
);
538 /* Remap PLX90xx configuration space */
539 addr
= pci_iomap(pdev
, ci
->conf_map
.bar
, ci
->conf_map
.size
);
542 dev_err(&pdev
->dev
, "Failed to remap configuration space "
543 "(BAR%d)\n", ci
->conf_map
.bar
);
544 goto failure_cleanup
;
546 card
->conf_addr
= addr
+ ci
->conf_map
.offset
;
548 ci
->reset_func(pdev
);
549 card
->reset_func
= ci
->reset_func
;
551 /* Detect available channels */
552 for (i
= 0; i
< ci
->channel_count
; i
++) {
553 struct plx_pci_channel_map
*cm
= &ci
->chan_map_tbl
[i
];
555 dev
= alloc_sja1000dev(0);
558 goto failure_cleanup
;
561 card
->net_dev
[i
] = dev
;
562 priv
= netdev_priv(dev
);
564 priv
->irq_flags
= IRQF_SHARED
;
566 dev
->irq
= pdev
->irq
;
569 * Remap IO space of the SJA1000 chips
570 * This is device-dependent mapping
572 addr
= pci_iomap(pdev
, cm
->bar
, cm
->size
);
575 dev_err(&pdev
->dev
, "Failed to remap BAR%d\n", cm
->bar
);
576 goto failure_cleanup
;
579 priv
->reg_base
= addr
+ cm
->offset
;
580 priv
->read_reg
= plx_pci_read_reg
;
581 priv
->write_reg
= plx_pci_write_reg
;
583 /* Check if channel is present */
584 if (plx_pci_check_sja1000(priv
)) {
585 priv
->can
.clock
.freq
= ci
->can_clock
;
589 SET_NETDEV_DEV(dev
, &pdev
->dev
);
592 /* Register SJA1000 device */
593 err
= register_sja1000dev(dev
);
595 dev_err(&pdev
->dev
, "Registering device failed "
597 goto failure_cleanup
;
602 dev_info(&pdev
->dev
, "Channel #%d at 0x%p, irq %d "
603 "registered as %s\n", i
+ 1, priv
->reg_base
,
604 dev
->irq
, dev
->name
);
606 dev_err(&pdev
->dev
, "Channel #%d not detected\n",
608 free_sja1000dev(dev
);
609 card
->net_dev
[i
] = NULL
;
613 if (!card
->channels
) {
615 goto failure_cleanup
;
619 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
620 * Local_2 interrupts from the SJA1000 chips
622 if (pdev
->device
!= PCI_DEVICE_ID_PLX_9056
) {
623 val
= ioread32(card
->conf_addr
+ PLX_INTCSR
);
624 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_ESDGMBH
)
625 val
|= PLX_LINT1_EN
| PLX_PCI_INT_EN
;
627 val
|= PLX_LINT1_EN
| PLX_LINT2_EN
| PLX_PCI_INT_EN
;
628 iowrite32(val
, card
->conf_addr
+ PLX_INTCSR
);
630 iowrite32(PLX9056_LINTI
| PLX9056_PCI_INT_EN
,
631 card
->conf_addr
+ PLX9056_INTCSR
);
636 dev_err(&pdev
->dev
, "Error: %d. Cleaning Up.\n", err
);
638 plx_pci_del_card(pdev
);
643 static struct pci_driver plx_pci_driver
= {
645 .id_table
= plx_pci_tbl
,
646 .probe
= plx_pci_add_card
,
647 .remove
= plx_pci_del_card
,
650 module_pci_driver(plx_pci_driver
);