drivers/net/can/sja1000/plx_pci.c

   1 /*
   2  * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
   3  *
   4  * Derived from the ems_pci.c driver:
   5  *      Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
   6  *      Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
   7  *      Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the version 2 of the GNU General Public License
  11  * as published by the Free Software Foundation
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/delay.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30 #include <linux/can/dev.h>
  31 #include <linux/io.h>
  32
  33 #include "sja1000.h"
  34
  35 #define DRV_NAME  "sja1000_plx_pci"
  36
  37 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
  38 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
  39                    "the SJA1000 chips");
  40 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
  41                         "Adlink PCI-7841/cPCI-7841 SE, "
  42                         "Marathon CAN-bus-PCI, "
  43                         "TEWS TECHNOLOGIES TPMC810, "
  44                         "esd CAN-PCI/CPCI/PCI104/200, "
  45                         "esd CAN-PCI/PMC/266, "
  46                         "esd CAN-PCIe/2000, "
  47                         "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), "
  48                         "IXXAT PC-I 04/PCI")
  49 MODULE_LICENSE("GPL v2");
  50
  51 #define PLX_PCI_MAX_CHAN 2
  52
  53 struct plx_pci_card {
  54         int channels;                   /* detected channels count */
  55         struct net_device *net_dev[PLX_PCI_MAX_CHAN];
  56         void __iomem *conf_addr;
  57
  58         /* Pointer to device-dependent reset function */
  59         void (*reset_func)(struct pci_dev *pdev);
  60 };
  61
  62 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
  63
  64 /* PLX9030/9050/9052 registers */
  65 #define PLX_INTCSR      0x4c            /* Interrupt Control/Status */
  66 #define PLX_CNTRL       0x50            /* User I/O, Direct Slave Response,
  67                                          * Serial EEPROM, and Initialization
  68                                          * Control register
  69                                          */
  70
  71 #define PLX_LINT1_EN    0x1             /* Local interrupt 1 enable */
  72 #define PLX_LINT2_EN    (1 << 3)        /* Local interrupt 2 enable */
  73 #define PLX_PCI_INT_EN  (1 << 6)        /* PCI Interrupt Enable */
  74 #define PLX_PCI_RESET   (1 << 30)       /* PCI Adapter Software Reset */
  75
  76 /* PLX9056 registers */
  77 #define PLX9056_INTCSR  0x68            /* Interrupt Control/Status */
  78 #define PLX9056_CNTRL   0x6c            /* Control / Software Reset */
  79
  80 #define PLX9056_LINTI   (1 << 11)
  81 #define PLX9056_PCI_INT_EN (1 << 8)
  82 #define PLX9056_PCI_RCR (1 << 29)       /* Read Configuration Registers */
  83
  84 /*
  85  * The board configuration is probably following:
  86  * RX1 is connected to ground.
  87  * TX1 is not connected.
  88  * CLKO is not connected.
  89  * Setting the OCR register to 0xDA is a good idea.
  90  * This means normal output mode, push-pull and the correct polarity.
  91  */
  92 #define PLX_PCI_OCR     (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  93
  94 /*
  95  * In the CDR register, you should set CBP to 1.
  96  * You will probably also want to set the clock divider value to 7
  97  * (meaning direct oscillator output) because the second SJA1000 chip
  98  * is driven by the first one CLKOUT output.
  99  */
 100 #define PLX_PCI_CDR                     (CDR_CBP | CDR_CLKOUT_MASK)
 101
 102 /* SJA1000 Control Register in the BasicCAN Mode */
 103 #define REG_CR                          0x00
 104
 105 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
 106 #define REG_CR_BASICCAN_INITIAL         0x21
 107 #define REG_CR_BASICCAN_INITIAL_MASK    0xa1
 108 #define REG_SR_BASICCAN_INITIAL         0x0c
 109 #define REG_IR_BASICCAN_INITIAL         0xe0
 110
 111 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
 112 #define REG_MOD_PELICAN_INITIAL         0x01
 113 #define REG_SR_PELICAN_INITIAL          0x3c
 114 #define REG_IR_PELICAN_INITIAL          0x00
 115
 116 #define ADLINK_PCI_VENDOR_ID            0x144A
 117 #define ADLINK_PCI_DEVICE_ID            0x7841
 118
 119 #define ESD_PCI_SUB_SYS_ID_PCI200       0x0004
 120 #define ESD_PCI_SUB_SYS_ID_PCI266       0x0009
 121 #define ESD_PCI_SUB_SYS_ID_PMC266       0x000e
 122 #define ESD_PCI_SUB_SYS_ID_CPCI200      0x010b
 123 #define ESD_PCI_SUB_SYS_ID_PCIE2000     0x0200
 124 #define ESD_PCI_SUB_SYS_ID_PCI104200    0x0501
 125
 126 #define IXXAT_PCI_VENDOR_ID             0x10b5
 127 #define IXXAT_PCI_DEVICE_ID             0x9050
 128 #define IXXAT_PCI_SUB_SYS_ID            0x2540
 129
 130 #define MARATHON_PCI_DEVICE_ID          0x2715
 131
 132 #define TEWS_PCI_VENDOR_ID              0x1498
 133 #define TEWS_PCI_DEVICE_ID_TMPC810      0x032A
 134
 135 #define CTI_PCI_VENDOR_ID               0x12c4
 136 #define CTI_PCI_DEVICE_ID_CRG001        0x0900
 137
 138 static void plx_pci_reset_common(struct pci_dev *pdev);
 139 static void plx_pci_reset_marathon(struct pci_dev *pdev);
 140 static void plx9056_pci_reset_common(struct pci_dev *pdev);
 141
 142 struct plx_pci_channel_map {
 143         u32 bar;
 144         u32 offset;
 145         u32 size;               /* 0x00 - auto, e.g. length of entire bar */
 146 };
 147
 148 struct plx_pci_card_info {
 149         const char *name;
 150         int channel_count;
 151         u32 can_clock;
 152         u8 ocr;                 /* output control register */
 153         u8 cdr;                 /* clock divider register */
 154
 155         /* Parameters for mapping local configuration space */
 156         struct plx_pci_channel_map conf_map;
 157
 158         /* Parameters for mapping the SJA1000 chips */
 159         struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
 160
 161         /* Pointer to device-dependent reset function */
 162         void (*reset_func)(struct pci_dev *pdev);
 163 };
 164
 165 static struct plx_pci_card_info plx_pci_card_info_adlink = {
 166         "Adlink PCI-7841/cPCI-7841", 2,
 167         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 168         {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
 169         &plx_pci_reset_common
 170         /* based on PLX9052 */
 171 };
 172
 173 static struct plx_pci_card_info plx_pci_card_info_adlink_se = {
 174         "Adlink PCI-7841/cPCI-7841 SE", 2,
 175         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 176         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
 177         &plx_pci_reset_common
 178         /* based on PLX9052 */
 179 };
 180
 181 static struct plx_pci_card_info plx_pci_card_info_esd200 = {
 182         "esd CAN-PCI/CPCI/PCI104/200", 2,
 183         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 184         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
 185         &plx_pci_reset_common
 186         /* based on PLX9030/9050 */
 187 };
 188
 189 static struct plx_pci_card_info plx_pci_card_info_esd266 = {
 190         "esd CAN-PCI/PMC/266", 2,
 191         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 192         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
 193         &plx9056_pci_reset_common
 194         /* based on PLX9056 */
 195 };
 196
 197 static struct plx_pci_card_info plx_pci_card_info_esd2000 = {
 198         "esd CAN-PCIe/2000", 2,
 199         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 200         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
 201         &plx9056_pci_reset_common
 202         /* based on PEX8311 */
 203 };
 204
 205 static struct plx_pci_card_info plx_pci_card_info_ixxat = {
 206         "IXXAT PC-I 04/PCI", 2,
 207         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 208         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
 209         &plx_pci_reset_common
 210         /* based on PLX9050 */
 211 };
 212
 213 static struct plx_pci_card_info plx_pci_card_info_marathon = {
 214         "Marathon CAN-bus-PCI", 2,
 215         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 216         {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
 217         &plx_pci_reset_marathon
 218         /* based on PLX9052 */
 219 };
 220
 221 static struct plx_pci_card_info plx_pci_card_info_tews = {
 222         "TEWS TECHNOLOGIES TPMC810", 2,
 223         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 224         {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
 225         &plx_pci_reset_common
 226         /* based on PLX9030 */
 227 };
 228
 229 static struct plx_pci_card_info plx_pci_card_info_cti = {
 230         "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
 231         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 232         {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
 233         &plx_pci_reset_common
 234         /* based on PLX9030 */
 235 };
 236
 237 static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
 238         {
 239                 /* Adlink PCI-7841/cPCI-7841 */
 240                 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
 241                 PCI_ANY_ID, PCI_ANY_ID,
 242                 PCI_CLASS_NETWORK_OTHER << 8, ~0,
 243                 (kernel_ulong_t)&plx_pci_card_info_adlink
 244         },
 245         {
 246                 /* Adlink PCI-7841/cPCI-7841 SE */
 247                 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
 248                 PCI_ANY_ID, PCI_ANY_ID,
 249                 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
 250                 (kernel_ulong_t)&plx_pci_card_info_adlink_se
 251         },
 252         {
 253                 /* esd CAN-PCI/200 */
 254                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
 255                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200,
 256                 0, 0,
 257                 (kernel_ulong_t)&plx_pci_card_info_esd200
 258         },
 259         {
 260                 /* esd CAN-CPCI/200 */
 261                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
 262                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200,
 263                 0, 0,
 264                 (kernel_ulong_t)&plx_pci_card_info_esd200
 265         },
 266         {
 267                 /* esd CAN-PCI104/200 */
 268                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
 269                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200,
 270                 0, 0,
 271                 (kernel_ulong_t)&plx_pci_card_info_esd200
 272         },
 273         {
 274                 /* esd CAN-PCI/266 */
 275                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
 276                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266,
 277                 0, 0,
 278                 (kernel_ulong_t)&plx_pci_card_info_esd266
 279         },
 280         {
 281                 /* esd CAN-PMC/266 */
 282                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
 283                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266,
 284                 0, 0,
 285                 (kernel_ulong_t)&plx_pci_card_info_esd266
 286         },
 287         {
 288                 /* esd CAN-PCIE/2000 */
 289                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
 290                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000,
 291                 0, 0,
 292                 (kernel_ulong_t)&plx_pci_card_info_esd2000
 293         },
 294         {
 295                 /* IXXAT PC-I 04/PCI card */
 296                 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID,
 297                 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID,
 298                 0, 0,
 299                 (kernel_ulong_t)&plx_pci_card_info_ixxat
 300         },
 301         {
 302                 /* Marathon CAN-bus-PCI card */
 303                 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
 304                 PCI_ANY_ID, PCI_ANY_ID,
 305                 0, 0,
 306                 (kernel_ulong_t)&plx_pci_card_info_marathon
 307         },
 308         {
 309                 /* TEWS TECHNOLOGIES TPMC810 card */
 310                 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
 311                 PCI_ANY_ID, PCI_ANY_ID,
 312                 0, 0,
 313                 (kernel_ulong_t)&plx_pci_card_info_tews
 314         },
 315         {
 316                 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
 317                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
 318                 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001,
 319                 0, 0,
 320                 (kernel_ulong_t)&plx_pci_card_info_cti
 321         },
 322         { 0,}
 323 };
 324 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
 325
 326 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
 327 {
 328         return ioread8(priv->reg_base + port);
 329 }
 330
 331 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
 332 {
 333         iowrite8(val, priv->reg_base + port);
 334 }
 335
 336 /*
 337  * Check if a CAN controller is present at the specified location
 338  * by trying to switch 'em from the Basic mode into the PeliCAN mode.
 339  * Also check states of some registers in reset mode.
 340  */
 341 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
 342 {
 343         int flag = 0;
 344
 345         /*
 346          * Check registers after hardware reset (the Basic mode)
 347          * See states on p. 10 of the Datasheet.
 348          */
 349         if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
 350             REG_CR_BASICCAN_INITIAL &&
 351             (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
 352             (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
 353                 flag = 1;
 354
 355         /* Bring the SJA1000 into the PeliCAN mode*/
 356         priv->write_reg(priv, REG_CDR, CDR_PELICAN);
 357
 358         /*
 359          * Check registers after reset in the PeliCAN mode.
 360          * See states on p. 23 of the Datasheet.
 361          */
 362         if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
 363             priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
 364             priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
 365                 return flag;
 366
 367         return 0;
 368 }
 369
 370 /*
 371  * PLX9030/50/52 software reset
 372  * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
 373  * For most cards it's enough for reset the SJA1000 chips.
 374  */
 375 static void plx_pci_reset_common(struct pci_dev *pdev)
 376 {
 377         struct plx_pci_card *card = pci_get_drvdata(pdev);
 378         u32 cntrl;
 379
 380         cntrl = ioread32(card->conf_addr + PLX_CNTRL);
 381         cntrl |= PLX_PCI_RESET;
 382         iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
 383         udelay(100);
 384         cntrl ^= PLX_PCI_RESET;
 385         iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
 386 };
 387
 388 /*
 389  * PLX9056 software reset
 390  * Assert LRESET# and reset device(s) on the Local Bus (if wired).
 391  */
 392 static void plx9056_pci_reset_common(struct pci_dev *pdev)
 393 {
 394         struct plx_pci_card *card = pci_get_drvdata(pdev);
 395         u32 cntrl;
 396
 397         /* issue a local bus reset */
 398         cntrl = ioread32(card->conf_addr + PLX9056_CNTRL);
 399         cntrl |= PLX_PCI_RESET;
 400         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 401         udelay(100);
 402         cntrl ^= PLX_PCI_RESET;
 403         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 404
 405         /* reload local configuration from EEPROM */
 406         cntrl |= PLX9056_PCI_RCR;
 407         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 408
 409         /*
 410          * There is no safe way to poll for the end
 411          * of reconfiguration process. Waiting for 10ms
 412          * is safe.
 413          */
 414         mdelay(10);
 415
 416         cntrl ^= PLX9056_PCI_RCR;
 417         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 418 };
 419
 420 /* Special reset function for Marathon card */
 421 static void plx_pci_reset_marathon(struct pci_dev *pdev)
 422 {
 423         void __iomem *reset_addr;
 424         int i;
 425         static const int reset_bar[2] = {3, 5};
 426
 427         plx_pci_reset_common(pdev);
 428
 429         for (i = 0; i < 2; i++) {
 430                 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
 431                 if (!reset_addr) {
 432                         dev_err(&pdev->dev, "Failed to remap reset "
 433                                 "space %d (BAR%d)\n", i, reset_bar[i]);
 434                 } else {
 435                         /* reset the SJA1000 chip */
 436                         iowrite8(0x1, reset_addr);
 437                         udelay(100);
 438                         pci_iounmap(pdev, reset_addr);
 439                 }
 440         }
 441 }
 442
 443 static void plx_pci_del_card(struct pci_dev *pdev)
 444 {
 445         struct plx_pci_card *card = pci_get_drvdata(pdev);
 446         struct net_device *dev;
 447         struct sja1000_priv *priv;
 448         int i = 0;
 449
 450         for (i = 0; i < PLX_PCI_MAX_CHAN; i++) {
 451                 dev = card->net_dev[i];
 452                 if (!dev)
 453                         continue;
 454
 455                 dev_info(&pdev->dev, "Removing %s\n", dev->name);
 456                 unregister_sja1000dev(dev);
 457                 priv = netdev_priv(dev);
 458                 if (priv->reg_base)
 459                         pci_iounmap(pdev, priv->reg_base);
 460                 free_sja1000dev(dev);
 461         }
 462
 463         card->reset_func(pdev);
 464
 465         /*
 466          * Disable interrupts from PCI-card and disable local
 467          * interrupts
 468          */
 469         if (pdev->device != PCI_DEVICE_ID_PLX_9056)
 470                 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
 471         else
 472                 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR);
 473
 474         if (card->conf_addr)
 475                 pci_iounmap(pdev, card->conf_addr);
 476
 477         kfree(card);
 478
 479         pci_disable_device(pdev);
 480         pci_set_drvdata(pdev, NULL);
 481 }
 482
 483 /*
 484  * Probe PLX90xx based device for the SJA1000 chips and register each
 485  * available CAN channel to SJA1000 Socket-CAN subsystem.
 486  */
 487 static int plx_pci_add_card(struct pci_dev *pdev,
 488                             const struct pci_device_id *ent)
 489 {
 490         struct sja1000_priv *priv;
 491         struct net_device *dev;
 492         struct plx_pci_card *card;
 493         struct plx_pci_card_info *ci;
 494         int err, i;
 495         u32 val;
 496         void __iomem *addr;
 497
 498         ci = (struct plx_pci_card_info *)ent->driver_data;
 499
 500         if (pci_enable_device(pdev) < 0) {
 501                 dev_err(&pdev->dev, "Failed to enable PCI device\n");
 502                 return -ENODEV;
 503         }
 504
 505         dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
 506                  ci->name, PCI_SLOT(pdev->devfn));
 507
 508         /* Allocate card structures to hold addresses, ... */
 509         card = kzalloc(sizeof(*card), GFP_KERNEL);
 510         if (!card) {
 511                 pci_disable_device(pdev);
 512                 return -ENOMEM;
 513         }
 514
 515         pci_set_drvdata(pdev, card);
 516
 517         card->channels = 0;
 518
 519         /* Remap PLX90xx configuration space */
 520         addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
 521         if (!addr) {
 522                 err = -ENOMEM;
 523                 dev_err(&pdev->dev, "Failed to remap configuration space "
 524                         "(BAR%d)\n", ci->conf_map.bar);
 525                 goto failure_cleanup;
 526         }
 527         card->conf_addr = addr + ci->conf_map.offset;
 528
 529         ci->reset_func(pdev);
 530         card->reset_func = ci->reset_func;
 531
 532         /* Detect available channels */
 533         for (i = 0; i < ci->channel_count; i++) {
 534                 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
 535
 536                 dev = alloc_sja1000dev(0);
 537                 if (!dev) {
 538                         err = -ENOMEM;
 539                         goto failure_cleanup;
 540                 }
 541
 542                 card->net_dev[i] = dev;
 543                 priv = netdev_priv(dev);
 544                 priv->priv = card;
 545                 priv->irq_flags = IRQF_SHARED;
 546
 547                 dev->irq = pdev->irq;
 548
 549                 /*
 550                  * Remap IO space of the SJA1000 chips
 551                  * This is device-dependent mapping
 552                  */
 553                 addr = pci_iomap(pdev, cm->bar, cm->size);
 554                 if (!addr) {
 555                         err = -ENOMEM;
 556                         dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
 557                         goto failure_cleanup;
 558                 }
 559
 560                 priv->reg_base = addr + cm->offset;
 561                 priv->read_reg = plx_pci_read_reg;
 562                 priv->write_reg = plx_pci_write_reg;
 563
 564                 /* Check if channel is present */
 565                 if (plx_pci_check_sja1000(priv)) {
 566                         priv->can.clock.freq = ci->can_clock;
 567                         priv->ocr = ci->ocr;
 568                         priv->cdr = ci->cdr;
 569
 570                         SET_NETDEV_DEV(dev, &pdev->dev);
 571
 572                         /* Register SJA1000 device */
 573                         err = register_sja1000dev(dev);
 574                         if (err) {
 575                                 dev_err(&pdev->dev, "Registering device failed "
 576                                         "(err=%d)\n", err);
 577                                 goto failure_cleanup;
 578                         }
 579
 580                         card->channels++;
 581
 582                         dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
 583                                  "registered as %s\n", i + 1, priv->reg_base,
 584                                  dev->irq, dev->name);
 585                 } else {
 586                         dev_err(&pdev->dev, "Channel #%d not detected\n",
 587                                 i + 1);
 588                         free_sja1000dev(dev);
 589                         card->net_dev[i] = NULL;
 590                 }
 591         }
 592
 593         if (!card->channels) {
 594                 err = -ENODEV;
 595                 goto failure_cleanup;
 596         }
 597
 598         /*
 599          * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
 600          * Local_2 interrupts from the SJA1000 chips
 601          */
 602         if (pdev->device != PCI_DEVICE_ID_PLX_9056) {
 603                 val = ioread32(card->conf_addr + PLX_INTCSR);
 604                 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH)
 605                         val |= PLX_LINT1_EN | PLX_PCI_INT_EN;
 606                 else
 607                         val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
 608                 iowrite32(val, card->conf_addr + PLX_INTCSR);
 609         } else {
 610                 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN,
 611                           card->conf_addr + PLX9056_INTCSR);
 612         }
 613         return 0;
 614
 615 failure_cleanup:
 616         dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
 617
 618         plx_pci_del_card(pdev);
 619
 620         return err;
 621 }
 622
 623 static struct pci_driver plx_pci_driver = {
 624         .name = DRV_NAME,
 625         .id_table = plx_pci_tbl,
 626         .probe = plx_pci_add_card,
 627         .remove = plx_pci_del_card,
 628 };
 629
 630 module_pci_driver(plx_pci_driver);