projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
TI Davinci EMAC : Abstract Buffer address translation logic.
[deliverable/linux.git] / drivers / net / davinci_emac.c
1 /*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32 /** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
42 #include <linux/in.h>
43 #include <linux/ioport.h>
44 #include <linux/slab.h>
45 #include <linux/mm.h>
46 #include <linux/interrupt.h>
47 #include <linux/init.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/ethtool.h>
52 #include <linux/highmem.h>
53 #include <linux/proc_fs.h>
54 #include <linux/ctype.h>
55 #include <linux/version.h>
56 #include <linux/spinlock.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/clk.h>
59 #include <linux/platform_device.h>
60 #include <linux/semaphore.h>
61 #include <linux/phy.h>
62 #include <linux/bitops.h>
63 #include <linux/io.h>
64 #include <linux/uaccess.h>
65 #include <linux/davinci_emac.h>
66
67 #include <asm/irq.h>
68 #include <asm/page.h>
69
70 static int debug_level;
71 module_param(debug_level, int, 0);
72 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
73
74 /* Netif debug messages possible */
75 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
76 NETIF_MSG_PROBE | \
77 NETIF_MSG_LINK | \
78 NETIF_MSG_TIMER | \
79 NETIF_MSG_IFDOWN | \
80 NETIF_MSG_IFUP | \
81 NETIF_MSG_RX_ERR | \
82 NETIF_MSG_TX_ERR | \
83 NETIF_MSG_TX_QUEUED | \
84 NETIF_MSG_INTR | \
85 NETIF_MSG_TX_DONE | \
86 NETIF_MSG_RX_STATUS | \
87 NETIF_MSG_PKTDATA | \
88 NETIF_MSG_HW | \
89 NETIF_MSG_WOL)
90
91 /* version info */
92 #define EMAC_MAJOR_VERSION 6
93 #define EMAC_MINOR_VERSION 1
94 #define EMAC_MODULE_VERSION "6.1"
95 MODULE_VERSION(EMAC_MODULE_VERSION);
96 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
97
98 /* Configuration items */
99 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
100 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
101 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
102 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
103 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
104 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
105 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
106 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
107 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
108 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
109 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
110 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
111
112 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
113 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
114
115 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
116 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
117 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
118 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
119 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
120 #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
121 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
122 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
123 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
124
125 /* Buffer descriptor parameters */
126 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
127 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
128
129 /* EMAC register related defines */
130 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
131 #define EMAC_NUM_MULTICAST_BITS (64)
132 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
133 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
134 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
135 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
136 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
137 #define EMAC_INT_MASK_CLEAR (0xFF)
138
139 /* RX MBP register bit positions */
140 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
141 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
142 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
143 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
144 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
145 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
146 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
147 #define EMAC_RXMBP_PROMCH_SHIFT (16)
148 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
149 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
150 #define EMAC_RXMBP_BROADCH_SHIFT (8)
151 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
152 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
153 #define EMAC_RXMBP_MULTICH_SHIFT (0)
154 #define EMAC_RXMBP_MULTICH_MASK (0x7)
155 #define EMAC_RXMBP_CHMASK (0x7)
156
157 /* EMAC register definitions/bit maps used */
158 # define EMAC_MBP_RXPROMISC (0x00200000)
159 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
160 # define EMAC_MBP_RXBCAST (0x00002000)
161 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
162 # define EMAC_MBP_RXMCAST (0x00000020)
163 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
164
165 /* EMAC mac_control register */
166 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
167 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
168 #define EMAC_MACCONTROL_GMIIEN BIT(5)
169 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
170 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
171 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
172
173 /* GIGABIT MODE related bits */
174 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
175 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
176
177 /* EMAC mac_status register */
178 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
179 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
180 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
181 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
182 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
183 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
184 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
185 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
186
187 /* EMAC RX register masks */
188 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
189 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
190
191 /* MAC_IN_VECTOR (0x180) register bit fields */
192 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
193 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
194 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
195 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
196
197 /** NOTE:: For DM646x the IN_VECTOR has changed */
198 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
199 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
200 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
201 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
202
203 /* CPPI bit positions */
204 #define EMAC_CPPI_SOP_BIT BIT(31)
205 #define EMAC_CPPI_EOP_BIT BIT(30)
206 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
207 #define EMAC_CPPI_EOQ_BIT BIT(28)
208 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
209 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
210 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
211 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
212 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
213
214 /* Max hardware defines */
215 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
216 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
217
218 /* EMAC Peripheral Device Register Memory Layout structure */
219 #define EMAC_TXIDVER 0x0
220 #define EMAC_TXCONTROL 0x4
221 #define EMAC_TXTEARDOWN 0x8
222 #define EMAC_RXIDVER 0x10
223 #define EMAC_RXCONTROL 0x14
224 #define EMAC_RXTEARDOWN 0x18
225 #define EMAC_TXINTSTATRAW 0x80
226 #define EMAC_TXINTSTATMASKED 0x84
227 #define EMAC_TXINTMASKSET 0x88
228 #define EMAC_TXINTMASKCLEAR 0x8C
229 #define EMAC_MACINVECTOR 0x90
230
231 #define EMAC_DM646X_MACEOIVECTOR 0x94
232
233 #define EMAC_RXINTSTATRAW 0xA0
234 #define EMAC_RXINTSTATMASKED 0xA4
235 #define EMAC_RXINTMASKSET 0xA8
236 #define EMAC_RXINTMASKCLEAR 0xAC
237 #define EMAC_MACINTSTATRAW 0xB0
238 #define EMAC_MACINTSTATMASKED 0xB4
239 #define EMAC_MACINTMASKSET 0xB8
240 #define EMAC_MACINTMASKCLEAR 0xBC
241
242 #define EMAC_RXMBPENABLE 0x100
243 #define EMAC_RXUNICASTSET 0x104
244 #define EMAC_RXUNICASTCLEAR 0x108
245 #define EMAC_RXMAXLEN 0x10C
246 #define EMAC_RXBUFFEROFFSET 0x110
247 #define EMAC_RXFILTERLOWTHRESH 0x114
248
249 #define EMAC_MACCONTROL 0x160
250 #define EMAC_MACSTATUS 0x164
251 #define EMAC_EMCONTROL 0x168
252 #define EMAC_FIFOCONTROL 0x16C
253 #define EMAC_MACCONFIG 0x170
254 #define EMAC_SOFTRESET 0x174
255 #define EMAC_MACSRCADDRLO 0x1D0
256 #define EMAC_MACSRCADDRHI 0x1D4
257 #define EMAC_MACHASH1 0x1D8
258 #define EMAC_MACHASH2 0x1DC
259 #define EMAC_MACADDRLO 0x500
260 #define EMAC_MACADDRHI 0x504
261 #define EMAC_MACINDEX 0x508
262
263 /* EMAC HDP and Completion registors */
264 #define EMAC_TXHDP(ch) (0x600 + (ch * 4))
265 #define EMAC_RXHDP(ch) (0x620 + (ch * 4))
266 #define EMAC_TXCP(ch) (0x640 + (ch * 4))
267 #define EMAC_RXCP(ch) (0x660 + (ch * 4))
268
269 /* EMAC statistics registers */
270 #define EMAC_RXGOODFRAMES 0x200
271 #define EMAC_RXBCASTFRAMES 0x204
272 #define EMAC_RXMCASTFRAMES 0x208
273 #define EMAC_RXPAUSEFRAMES 0x20C
274 #define EMAC_RXCRCERRORS 0x210
275 #define EMAC_RXALIGNCODEERRORS 0x214
276 #define EMAC_RXOVERSIZED 0x218
277 #define EMAC_RXJABBER 0x21C
278 #define EMAC_RXUNDERSIZED 0x220
279 #define EMAC_RXFRAGMENTS 0x224
280 #define EMAC_RXFILTERED 0x228
281 #define EMAC_RXQOSFILTERED 0x22C
282 #define EMAC_RXOCTETS 0x230
283 #define EMAC_TXGOODFRAMES 0x234
284 #define EMAC_TXBCASTFRAMES 0x238
285 #define EMAC_TXMCASTFRAMES 0x23C
286 #define EMAC_TXPAUSEFRAMES 0x240
287 #define EMAC_TXDEFERRED 0x244
288 #define EMAC_TXCOLLISION 0x248
289 #define EMAC_TXSINGLECOLL 0x24C
290 #define EMAC_TXMULTICOLL 0x250
291 #define EMAC_TXEXCESSIVECOLL 0x254
292 #define EMAC_TXLATECOLL 0x258
293 #define EMAC_TXUNDERRUN 0x25C
294 #define EMAC_TXCARRIERSENSE 0x260
295 #define EMAC_TXOCTETS 0x264
296 #define EMAC_NETOCTETS 0x280
297 #define EMAC_RXSOFOVERRUNS 0x284
298 #define EMAC_RXMOFOVERRUNS 0x288
299 #define EMAC_RXDMAOVERRUNS 0x28C
300
301 /* EMAC DM644x control registers */
302 #define EMAC_CTRL_EWCTL (0x4)
303 #define EMAC_CTRL_EWINTTCNT (0x8)
304
305 /* EMAC MDIO related */
306 /* Mask & Control defines */
307 #define MDIO_CONTROL_CLKDIV (0xFF)
308 #define MDIO_CONTROL_ENABLE BIT(30)
309 #define MDIO_USERACCESS_GO BIT(31)
310 #define MDIO_USERACCESS_WRITE BIT(30)
311 #define MDIO_USERACCESS_READ (0)
312 #define MDIO_USERACCESS_REGADR (0x1F << 21)
313 #define MDIO_USERACCESS_PHYADR (0x1F << 16)
314 #define MDIO_USERACCESS_DATA (0xFFFF)
315 #define MDIO_USERPHYSEL_LINKSEL BIT(7)
316 #define MDIO_VER_MODID (0xFFFF << 16)
317 #define MDIO_VER_REVMAJ (0xFF << 8)
318 #define MDIO_VER_REVMIN (0xFF)
319
320 #define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
321 #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
322 #define MDIO_CONTROL (0x04)
323
324 /* EMAC DM646X control module registers */
325 #define EMAC_DM646X_CMRXINTEN (0x14)
326 #define EMAC_DM646X_CMTXINTEN (0x18)
327
328 /* EMAC EOI codes for C0 */
329 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
330 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
331
332 /* EMAC Stats Clear Mask */
333 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
334
335 /** net_buf_obj: EMAC network bufferdata structure
336 *
337 * EMAC network buffer data structure
338 */
339 struct emac_netbufobj {
340 void *buf_token;
341 char *data_ptr;
342 int length;
343 };
344
345 /** net_pkt_obj: EMAC network packet data structure
346 *
347 * EMAC network packet data structure - supports buffer list (for future)
348 */
349 struct emac_netpktobj {
350 void *pkt_token; /* data token may hold tx/rx chan id */
351 struct emac_netbufobj *buf_list; /* array of network buffer objects */
352 int num_bufs;
353 int pkt_length;
354 };
355
356 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
357 *
358 * EMAC TX Buffer descriptor data structure
359 */
360 struct emac_tx_bd {
361 int h_next;
362 int buff_ptr;
363 int off_b_len;
364 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
365 struct emac_tx_bd __iomem *next;
366 void *buf_token;
367 };
368
369 /** emac_txch: EMAC TX Channel data structure
370 *
371 * EMAC TX Channel data structure
372 */
373 struct emac_txch {
374 /* Config related */
375 u32 num_bd;
376 u32 service_max;
377
378 /* CPPI specific */
379 u32 alloc_size;
380 void __iomem *bd_mem;
381 struct emac_tx_bd __iomem *bd_pool_head;
382 struct emac_tx_bd __iomem *active_queue_head;
383 struct emac_tx_bd __iomem *active_queue_tail;
384 struct emac_tx_bd __iomem *last_hw_bdprocessed;
385 u32 queue_active;
386 u32 teardown_pending;
387 u32 *tx_complete;
388
389 /** statistics */
390 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
391 u32 mis_queued_packets;
392 u32 queue_reinit;
393 u32 end_of_queue_add;
394 u32 out_of_tx_bd;
395 u32 no_active_pkts; /* IRQ when there were no packets to process */
396 u32 active_queue_count;
397 };
398
399 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
400 *
401 * EMAC RX Buffer descriptor data structure
402 */
403 struct emac_rx_bd {
404 int h_next;
405 int buff_ptr;
406 int off_b_len;
407 int mode;
408 struct emac_rx_bd __iomem *next;
409 void *data_ptr;
410 void *buf_token;
411 };
412
413 /** emac_rxch: EMAC RX Channel data structure
414 *
415 * EMAC RX Channel data structure
416 */
417 struct emac_rxch {
418 /* configuration info */
419 u32 num_bd;
420 u32 service_max;
421 u32 buf_size;
422 char mac_addr[6];
423
424 /** CPPI specific */
425 u32 alloc_size;
426 void __iomem *bd_mem;
427 struct emac_rx_bd __iomem *bd_pool_head;
428 struct emac_rx_bd __iomem *active_queue_head;
429 struct emac_rx_bd __iomem *active_queue_tail;
430 u32 queue_active;
431 u32 teardown_pending;
432
433 /* packet and buffer objects */
434 struct emac_netpktobj pkt_queue;
435 struct emac_netbufobj buf_queue;
436
437 /** statistics */
438 u32 proc_count; /* number of times emac_rx_bdproc is called */
439 u32 processed_bd;
440 u32 recycled_bd;
441 u32 out_of_rx_bd;
442 u32 out_of_rx_buffers;
443 u32 queue_reinit;
444 u32 end_of_queue_add;
445 u32 end_of_queue;
446 u32 mis_queued_packets;
447 };
448
449 /* emac_priv: EMAC private data structure
450 *
451 * EMAC adapter private data structure
452 */
453 struct emac_priv {
454 u32 msg_enable;
455 struct net_device *ndev;
456 struct platform_device *pdev;
457 struct napi_struct napi;
458 char mac_addr[6];
459 spinlock_t tx_lock;
460 spinlock_t rx_lock;
461 void __iomem *remap_addr;
462 u32 emac_base_phys;
463 void __iomem *emac_base;
464 void __iomem *ctrl_base;
465 void __iomem *emac_ctrl_ram;
466 u32 ctrl_ram_size;
467 u32 hw_ram_addr;
468 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
469 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
470 u32 link; /* 1=link on, 0=link off */
471 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
472 u32 duplex; /* Link duplex: 0=Half, 1=Full */
473 u32 rx_buf_size;
474 u32 isr_count;
475 u8 rmii_en;
476 u8 version;
477 struct net_device_stats net_dev_stats;
478 u32 mac_hash1;
479 u32 mac_hash2;
480 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
481 u32 rx_addr_type;
482 /* periodic timer required for MDIO polling */
483 struct timer_list periodic_timer;
484 u32 periodic_ticks;
485 u32 timer_active;
486 u32 phy_mask;
487 /* mii_bus,phy members */
488 struct mii_bus *mii_bus;
489 struct phy_device *phydev;
490 spinlock_t lock;
491 /*platform specific members*/
492 void (*int_enable) (void);
493 void (*int_disable) (void);
494 };
495
496 /* clock frequency for EMAC */
497 static struct clk *emac_clk;
498 static unsigned long emac_bus_frequency;
499 static unsigned long mdio_max_freq;
500
501 #define emac_virt_to_phys(addr, priv) \
502 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
503 + priv->hw_ram_addr)
504
505 /* Cache macros - Packet buffers would be from skb pool which is cached */
506 #define EMAC_VIRT_NOCACHE(addr) (addr)
507 #define EMAC_CACHE_INVALIDATE(addr, size) \
508 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
509 #define EMAC_CACHE_WRITEBACK(addr, size) \
510 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
511 #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
512 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
513
514 /* DM644x does not have BD's in cached memory - so no cache functions */
515 #define BD_CACHE_INVALIDATE(addr, size)
516 #define BD_CACHE_WRITEBACK(addr, size)
517 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
518
519 /* EMAC TX Host Error description strings */
520 static char *emac_txhost_errcodes[16] = {
521 "No error", "SOP error", "Ownership bit not set in SOP buffer",
522 "Zero Next Buffer Descriptor Pointer Without EOP",
523 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
524 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
525 "Reserved", "Reserved", "Reserved", "Reserved"
526 };
527
528 /* EMAC RX Host Error description strings */
529 static char *emac_rxhost_errcodes[16] = {
530 "No error", "Reserved", "Ownership bit not set in input buffer",
531 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
532 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
533 "Reserved", "Reserved", "Reserved", "Reserved"
534 };
535
536 /* Helper macros */
537 #define emac_read(reg) ioread32(priv->emac_base + (reg))
538 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
539
540 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
541 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
542
543 #define emac_mdio_read(reg) ioread32(bus->priv + (reg))
544 #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
545
546 /**
547 * emac_dump_regs: Dump important EMAC registers to debug terminal
548 * @priv: The DaVinci EMAC private adapter structure
549 *
550 * Executes ethtool set cmd & sets phy mode
551 *
552 */
553 static void emac_dump_regs(struct emac_priv *priv)
554 {
555 struct device *emac_dev = &priv->ndev->dev;
556
557 /* Print important registers in EMAC */
558 dev_info(emac_dev, "EMAC Basic registers\n");
559 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
560 emac_ctrl_read(EMAC_CTRL_EWCTL),
561 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
562 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
563 emac_read(EMAC_TXIDVER),
564 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
565 emac_read(EMAC_RXIDVER),
566 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
567 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
568 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
569 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
570 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
571 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
572 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
573 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
574 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
575 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
576 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
577 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
578 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
579 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
580 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
581 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
582 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
583 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
584 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
585 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
586 dev_info(emac_dev, "EMAC Statistics\n");
587 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
588 emac_read(EMAC_RXGOODFRAMES));
589 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
590 emac_read(EMAC_RXBCASTFRAMES));
591 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
592 emac_read(EMAC_RXMCASTFRAMES));
593 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
594 emac_read(EMAC_RXPAUSEFRAMES));
595 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
596 emac_read(EMAC_RXCRCERRORS));
597 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
598 emac_read(EMAC_RXALIGNCODEERRORS));
599 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
600 emac_read(EMAC_RXOVERSIZED));
601 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
602 emac_read(EMAC_RXJABBER));
603 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
604 emac_read(EMAC_RXUNDERSIZED));
605 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
606 emac_read(EMAC_RXFRAGMENTS));
607 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
608 emac_read(EMAC_RXFILTERED));
609 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
610 emac_read(EMAC_RXQOSFILTERED));
611 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
612 emac_read(EMAC_RXOCTETS));
613 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
614 emac_read(EMAC_TXGOODFRAMES));
615 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
616 emac_read(EMAC_TXBCASTFRAMES));
617 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
618 emac_read(EMAC_TXMCASTFRAMES));
619 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
620 emac_read(EMAC_TXPAUSEFRAMES));
621 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
622 emac_read(EMAC_TXDEFERRED));
623 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
624 emac_read(EMAC_TXCOLLISION));
625 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
626 emac_read(EMAC_TXSINGLECOLL));
627 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
628 emac_read(EMAC_TXMULTICOLL));
629 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
630 emac_read(EMAC_TXEXCESSIVECOLL));
631 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
632 emac_read(EMAC_TXLATECOLL));
633 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
634 emac_read(EMAC_TXUNDERRUN));
635 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
636 emac_read(EMAC_TXCARRIERSENSE));
637 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
638 emac_read(EMAC_TXOCTETS));
639 dev_info(emac_dev, "EMAC: net_octets:%d\n",
640 emac_read(EMAC_NETOCTETS));
641 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
642 emac_read(EMAC_RXSOFOVERRUNS));
643 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
644 emac_read(EMAC_RXMOFOVERRUNS));
645 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
646 emac_read(EMAC_RXDMAOVERRUNS));
647 }
648
649 /*************************************************************************
650 * EMAC MDIO/Phy Functionality
651 *************************************************************************/
652 /**
653 * emac_get_drvinfo: Get EMAC driver information
654 * @ndev: The DaVinci EMAC network adapter
655 * @info: ethtool info structure containing name and version
656 *
657 * Returns EMAC driver information (name and version)
658 *
659 */
660 static void emac_get_drvinfo(struct net_device *ndev,
661 struct ethtool_drvinfo *info)
662 {
663 strcpy(info->driver, emac_version_string);
664 strcpy(info->version, EMAC_MODULE_VERSION);
665 }
666
667 /**
668 * emac_get_settings: Get EMAC settings
669 * @ndev: The DaVinci EMAC network adapter
670 * @ecmd: ethtool command
671 *
672 * Executes ethool get command
673 *
674 */
675 static int emac_get_settings(struct net_device *ndev,
676 struct ethtool_cmd *ecmd)
677 {
678 struct emac_priv *priv = netdev_priv(ndev);
679 if (priv->phy_mask)
680 return phy_ethtool_gset(priv->phydev, ecmd);
681 else
682 return -EOPNOTSUPP;
683
684 }
685
686 /**
687 * emac_set_settings: Set EMAC settings
688 * @ndev: The DaVinci EMAC network adapter
689 * @ecmd: ethtool command
690 *
691 * Executes ethool set command
692 *
693 */
694 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
695 {
696 struct emac_priv *priv = netdev_priv(ndev);
697 if (priv->phy_mask)
698 return phy_ethtool_sset(priv->phydev, ecmd);
699 else
700 return -EOPNOTSUPP;
701
702 }
703
704 /**
705 * ethtool_ops: DaVinci EMAC Ethtool structure
706 *
707 * Ethtool support for EMAC adapter
708 *
709 */
710 static const struct ethtool_ops ethtool_ops = {
711 .get_drvinfo = emac_get_drvinfo,
712 .get_settings = emac_get_settings,
713 .set_settings = emac_set_settings,
714 .get_link = ethtool_op_get_link,
715 };
716
717 /**
718 * emac_update_phystatus: Update Phy status
719 * @priv: The DaVinci EMAC private adapter structure
720 *
721 * Updates phy status and takes action for network queue if required
722 * based upon link status
723 *
724 */
725 static void emac_update_phystatus(struct emac_priv *priv)
726 {
727 u32 mac_control;
728 u32 new_duplex;
729 u32 cur_duplex;
730 struct net_device *ndev = priv->ndev;
731
732 mac_control = emac_read(EMAC_MACCONTROL);
733 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
734 DUPLEX_FULL : DUPLEX_HALF;
735 if (priv->phy_mask)
736 new_duplex = priv->phydev->duplex;
737 else
738 new_duplex = DUPLEX_FULL;
739
740 /* We get called only if link has changed (speed/duplex/status) */
741 if ((priv->link) && (new_duplex != cur_duplex)) {
742 priv->duplex = new_duplex;
743 if (DUPLEX_FULL == priv->duplex)
744 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
745 else
746 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
747 }
748
749 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
750 mac_control = emac_read(EMAC_MACCONTROL);
751 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
752 EMAC_DM646X_MACCONTORL_GIGFORCE);
753 } else {
754 /* Clear the GIG bit and GIGFORCE bit */
755 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
756 EMAC_DM646X_MACCONTORL_GIG);
757
758 if (priv->rmii_en && (priv->speed == SPEED_100))
759 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
760 else
761 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
762 }
763
764 /* Update mac_control if changed */
765 emac_write(EMAC_MACCONTROL, mac_control);
766
767 if (priv->link) {
768 /* link ON */
769 if (!netif_carrier_ok(ndev))
770 netif_carrier_on(ndev);
771 /* reactivate the transmit queue if it is stopped */
772 if (netif_running(ndev) && netif_queue_stopped(ndev))
773 netif_wake_queue(ndev);
774 } else {
775 /* link OFF */
776 if (netif_carrier_ok(ndev))
777 netif_carrier_off(ndev);
778 if (!netif_queue_stopped(ndev))
779 netif_stop_queue(ndev);
780 }
781 }
782
783 /**
784 * hash_get: Calculate hash value from mac address
785 * @addr: mac address to delete from hash table
786 *
787 * Calculates hash value from mac address
788 *
789 */
790 static u32 hash_get(u8 *addr)
791 {
792 u32 hash;
793 u8 tmpval;
794 int cnt;
795 hash = 0;
796
797 for (cnt = 0; cnt < 2; cnt++) {
798 tmpval = *addr++;
799 hash ^= (tmpval >> 2) ^ (tmpval << 4);
800 tmpval = *addr++;
801 hash ^= (tmpval >> 4) ^ (tmpval << 2);
802 tmpval = *addr++;
803 hash ^= (tmpval >> 6) ^ (tmpval);
804 }
805
806 return hash & 0x3F;
807 }
808
809 /**
810 * hash_add: Hash function to add mac addr from hash table
811 * @priv: The DaVinci EMAC private adapter structure
812 * mac_addr: mac address to delete from hash table
813 *
814 * Adds mac address to the internal hash table
815 *
816 */
817 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
818 {
819 struct device *emac_dev = &priv->ndev->dev;
820 u32 rc = 0;
821 u32 hash_bit;
822 u32 hash_value = hash_get(mac_addr);
823
824 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
825 if (netif_msg_drv(priv)) {
826 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
827 "Hash %08x, should not be greater than %08x",
828 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
829 }
830 return -1;
831 }
832
833 /* set the hash bit only if not previously set */
834 if (priv->multicast_hash_cnt[hash_value] == 0) {
835 rc = 1; /* hash value changed */
836 if (hash_value < 32) {
837 hash_bit = BIT(hash_value);
838 priv->mac_hash1 |= hash_bit;
839 } else {
840 hash_bit = BIT((hash_value - 32));
841 priv->mac_hash2 |= hash_bit;
842 }
843 }
844
845 /* incr counter for num of mcast addr's mapped to "this" hash bit */
846 ++priv->multicast_hash_cnt[hash_value];
847
848 return rc;
849 }
850
851 /**
852 * hash_del: Hash function to delete mac addr from hash table
853 * @priv: The DaVinci EMAC private adapter structure
854 * mac_addr: mac address to delete from hash table
855 *
856 * Removes mac address from the internal hash table
857 *
858 */
859 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
860 {
861 u32 hash_value;
862 u32 hash_bit;
863
864 hash_value = hash_get(mac_addr);
865 if (priv->multicast_hash_cnt[hash_value] > 0) {
866 /* dec cntr for num of mcast addr's mapped to this hash bit */
867 --priv->multicast_hash_cnt[hash_value];
868 }
869
870 /* if counter still > 0, at least one multicast address refers
871 * to this hash bit. so return 0 */
872 if (priv->multicast_hash_cnt[hash_value] > 0)
873 return 0;
874
875 if (hash_value < 32) {
876 hash_bit = BIT(hash_value);
877 priv->mac_hash1 &= ~hash_bit;
878 } else {
879 hash_bit = BIT((hash_value - 32));
880 priv->mac_hash2 &= ~hash_bit;
881 }
882
883 /* return 1 to indicate change in mac_hash registers reqd */
884 return 1;
885 }
886
887 /* EMAC multicast operation */
888 #define EMAC_MULTICAST_ADD 0
889 #define EMAC_MULTICAST_DEL 1
890 #define EMAC_ALL_MULTI_SET 2
891 #define EMAC_ALL_MULTI_CLR 3
892
893 /**
894 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
895 * @priv: The DaVinci EMAC private adapter structure
896 * @action: multicast operation to perform
897 * mac_addr: mac address to set
898 *
899 * Set multicast addresses in EMAC adapter - internal function
900 *
901 */
902 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
903 {
904 struct device *emac_dev = &priv->ndev->dev;
905 int update = -1;
906
907 switch (action) {
908 case EMAC_MULTICAST_ADD:
909 update = hash_add(priv, mac_addr);
910 break;
911 case EMAC_MULTICAST_DEL:
912 update = hash_del(priv, mac_addr);
913 break;
914 case EMAC_ALL_MULTI_SET:
915 update = 1;
916 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
917 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
918 break;
919 case EMAC_ALL_MULTI_CLR:
920 update = 1;
921 priv->mac_hash1 = 0;
922 priv->mac_hash2 = 0;
923 memset(&(priv->multicast_hash_cnt[0]), 0,
924 sizeof(priv->multicast_hash_cnt[0]) *
925 EMAC_NUM_MULTICAST_BITS);
926 break;
927 default:
928 if (netif_msg_drv(priv))
929 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
930 ": bad operation %d", action);
931 break;
932 }
933
934 /* write to the hardware only if the register status chances */
935 if (update > 0) {
936 emac_write(EMAC_MACHASH1, priv->mac_hash1);
937 emac_write(EMAC_MACHASH2, priv->mac_hash2);
938 }
939 }
940
941 /**
942 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
943 * @ndev: The DaVinci EMAC network adapter
944 *
945 * Set multicast addresses in EMAC adapter
946 *
947 */
948 static void emac_dev_mcast_set(struct net_device *ndev)
949 {
950 u32 mbp_enable;
951 struct emac_priv *priv = netdev_priv(ndev);
952
953 mbp_enable = emac_read(EMAC_RXMBPENABLE);
954 if (ndev->flags & IFF_PROMISC) {
955 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
956 mbp_enable |= (EMAC_MBP_RXPROMISC);
957 } else {
958 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
959 if ((ndev->flags & IFF_ALLMULTI) ||
960 (ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) {
961 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
962 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
963 }
964 if (ndev->mc_count > 0) {
965 struct dev_mc_list *mc_ptr;
966 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
967 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
968 /* program multicast address list into EMAC hardware */
969 for (mc_ptr = ndev->mc_list; mc_ptr;
970 mc_ptr = mc_ptr->next) {
971 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
972 (u8 *)mc_ptr->dmi_addr);
973 }
974 } else {
975 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
976 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
977 }
978 }
979 /* Set mbp config register */
980 emac_write(EMAC_RXMBPENABLE, mbp_enable);
981 }
982
983 /*************************************************************************
984 * EMAC Hardware manipulation
985 *************************************************************************/
986
987 /**
988 * emac_int_disable: Disable EMAC module interrupt (from adapter)
989 * @priv: The DaVinci EMAC private adapter structure
990 *
991 * Disable EMAC interrupt on the adapter
992 *
993 */
994 static void emac_int_disable(struct emac_priv *priv)
995 {
996 if (priv->version == EMAC_VERSION_2) {
997 unsigned long flags;
998
999 local_irq_save(flags);
1000
1001 /* Program C0_Int_En to zero to turn off
1002 * interrupts to the CPU */
1003 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1004 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1005 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1006 if (priv->int_disable)
1007 priv->int_disable();
1008
1009 local_irq_restore(flags);
1010
1011 } else {
1012 /* Set DM644x control registers for interrupt control */
1013 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1014 }
1015 }
1016
1017 /**
1018 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1019 * @priv: The DaVinci EMAC private adapter structure
1020 *
1021 * Enable EMAC interrupt on the adapter
1022 *
1023 */
1024 static void emac_int_enable(struct emac_priv *priv)
1025 {
1026 if (priv->version == EMAC_VERSION_2) {
1027 if (priv->int_enable)
1028 priv->int_enable();
1029
1030 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1031 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1032
1033 /* In addition to turning on interrupt Enable, we need
1034 * ack by writing appropriate values to the EOI
1035 * register */
1036
1037 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1038
1039 /* ack rxen only then a new pulse will be generated */
1040 emac_write(EMAC_DM646X_MACEOIVECTOR,
1041 EMAC_DM646X_MAC_EOI_C0_RXEN);
1042
1043 /* ack txen- only then a new pulse will be generated */
1044 emac_write(EMAC_DM646X_MACEOIVECTOR,
1045 EMAC_DM646X_MAC_EOI_C0_TXEN);
1046
1047 } else {
1048 /* Set DM644x control registers for interrupt control */
1049 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1050 }
1051 }
1052
1053 /**
1054 * emac_irq: EMAC interrupt handler
1055 * @irq: interrupt number
1056 * @dev_id: EMAC network adapter data structure ptr
1057 *
1058 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1059 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1060 *
1061 * Returns interrupt handled condition
1062 */
1063 static irqreturn_t emac_irq(int irq, void *dev_id)
1064 {
1065 struct net_device *ndev = (struct net_device *)dev_id;
1066 struct emac_priv *priv = netdev_priv(ndev);
1067
1068 ++priv->isr_count;
1069 if (likely(netif_running(priv->ndev))) {
1070 emac_int_disable(priv);
1071 napi_schedule(&priv->napi);
1072 } else {
1073 /* we are closing down, so dont process anything */
1074 }
1075 return IRQ_HANDLED;
1076 }
1077
1078 /** EMAC on-chip buffer descriptor memory
1079 *
1080 * WARNING: Please note that the on chip memory is used for both TX and RX
1081 * buffer descriptor queues and is equally divided between TX and RX desc's
1082 * If the number of TX or RX descriptors change this memory pointers need
1083 * to be adjusted. If external memory is allocated then these pointers can
1084 * pointer to the memory
1085 *
1086 */
1087 #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1088 #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1089 (((priv)->ctrl_ram_size) >> 1))
1090
1091 /**
1092 * emac_init_txch: TX channel initialization
1093 * @priv: The DaVinci EMAC private adapter structure
1094 * @ch: RX channel number
1095 *
1096 * Called during device init to setup a TX channel (allocate buffer desc
1097 * create free pool and keep ready for transmission
1098 *
1099 * Returns success(0) or mem alloc failures error code
1100 */
1101 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1102 {
1103 struct device *emac_dev = &priv->ndev->dev;
1104 u32 cnt, bd_size;
1105 void __iomem *mem;
1106 struct emac_tx_bd __iomem *curr_bd;
1107 struct emac_txch *txch = NULL;
1108
1109 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1110 if (NULL == txch) {
1111 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1112 return -ENOMEM;
1113 }
1114 priv->txch[ch] = txch;
1115 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1116 txch->active_queue_head = NULL;
1117 txch->active_queue_tail = NULL;
1118 txch->queue_active = 0;
1119 txch->teardown_pending = 0;
1120
1121 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1122 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1123 GFP_KERNEL);
1124 if (NULL == txch->tx_complete) {
1125 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1126 kfree(txch);
1127 return -ENOMEM;
1128 }
1129
1130 /* allocate buffer descriptor pool align every BD on four word
1131 * boundry for future requirements */
1132 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1133 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1134 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1135
1136 /* alloc TX BD memory */
1137 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1138 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1139
1140 /* initialize the BD linked list */
1141 mem = (void __force __iomem *)
1142 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1143 txch->bd_pool_head = NULL;
1144 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1145 curr_bd = mem + (cnt * bd_size);
1146 curr_bd->next = txch->bd_pool_head;
1147 txch->bd_pool_head = curr_bd;
1148 }
1149
1150 /* reset statistics counters */
1151 txch->out_of_tx_bd = 0;
1152 txch->no_active_pkts = 0;
1153 txch->active_queue_count = 0;
1154
1155 return 0;
1156 }
1157
1158 /**
1159 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1160 * @priv: The DaVinci EMAC private adapter structure
1161 * @ch: TX channel number
1162 *
1163 * Called to clean up TX channel resources
1164 *
1165 */
1166 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1167 {
1168 struct emac_txch *txch = priv->txch[ch];
1169
1170 if (txch) {
1171 if (txch->bd_mem)
1172 txch->bd_mem = NULL;
1173 kfree(txch->tx_complete);
1174 kfree(txch);
1175 priv->txch[ch] = NULL;
1176 }
1177 }
1178
1179 /**
1180 * emac_net_tx_complete: TX packet completion function
1181 * @priv: The DaVinci EMAC private adapter structure
1182 * @net_data_tokens: packet token - skb pointer
1183 * @num_tokens: number of skb's to free
1184 * @ch: TX channel number
1185 *
1186 * Frees the skb once packet is transmitted
1187 *
1188 */
1189 static int emac_net_tx_complete(struct emac_priv *priv,
1190 void **net_data_tokens,
1191 int num_tokens, u32 ch)
1192 {
1193 u32 cnt;
1194
1195 if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1196 netif_start_queue(priv->ndev);
1197 for (cnt = 0; cnt < num_tokens; cnt++) {
1198 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1199 if (skb == NULL)
1200 continue;
1201 priv->net_dev_stats.tx_packets++;
1202 priv->net_dev_stats.tx_bytes += skb->len;
1203 dev_kfree_skb_any(skb);
1204 }
1205 return 0;
1206 }
1207
1208 /**
1209 * emac_txch_teardown: TX channel teardown
1210 * @priv: The DaVinci EMAC private adapter structure
1211 * @ch: TX channel number
1212 *
1213 * Called to teardown TX channel
1214 *
1215 */
1216 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1217 {
1218 struct device *emac_dev = &priv->ndev->dev;
1219 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1220 struct emac_txch *txch = priv->txch[ch];
1221 struct emac_tx_bd __iomem *curr_bd;
1222
1223 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1224 EMAC_TEARDOWN_VALUE) {
1225 /* wait till tx teardown complete */
1226 cpu_relax(); /* TODO: check if this helps ... */
1227 --teardown_cnt;
1228 if (0 == teardown_cnt) {
1229 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1230 break;
1231 }
1232 }
1233 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1234
1235 /* process sent packets and return skb's to upper layer */
1236 if (1 == txch->queue_active) {
1237 curr_bd = txch->active_queue_head;
1238 while (curr_bd != NULL) {
1239 emac_net_tx_complete(priv, (void __force *)
1240 &curr_bd->buf_token, 1, ch);
1241 if (curr_bd != txch->active_queue_tail)
1242 curr_bd = curr_bd->next;
1243 else
1244 break;
1245 }
1246 txch->bd_pool_head = txch->active_queue_head;
1247 txch->active_queue_head =
1248 txch->active_queue_tail = NULL;
1249 }
1250 }
1251
1252 /**
1253 * emac_stop_txch: Stop TX channel operation
1254 * @priv: The DaVinci EMAC private adapter structure
1255 * @ch: TX channel number
1256 *
1257 * Called to stop TX channel operation
1258 *
1259 */
1260 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1261 {
1262 struct emac_txch *txch = priv->txch[ch];
1263
1264 if (txch) {
1265 txch->teardown_pending = 1;
1266 emac_write(EMAC_TXTEARDOWN, 0);
1267 emac_txch_teardown(priv, ch);
1268 txch->teardown_pending = 0;
1269 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1270 }
1271 }
1272
1273 /**
1274 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1275 * @priv: The DaVinci EMAC private adapter structure
1276 * @ch: TX channel number to process buffer descriptors for
1277 * @budget: number of packets allowed to process
1278 * @pending: indication to caller that packets are pending to process
1279 *
1280 * Processes TX buffer descriptors after packets are transmitted - checks
1281 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1282 * the SKB buffer. Only "budget" number of packets are processed and
1283 * indication of pending packets provided to the caller
1284 *
1285 * Returns number of packets processed
1286 */
1287 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1288 {
1289 struct device *emac_dev = &priv->ndev->dev;
1290 unsigned long flags;
1291 u32 frame_status;
1292 u32 pkts_processed = 0;
1293 u32 tx_complete_cnt = 0;
1294 struct emac_tx_bd __iomem *curr_bd;
1295 struct emac_txch *txch = priv->txch[ch];
1296 u32 *tx_complete_ptr = txch->tx_complete;
1297
1298 if (unlikely(1 == txch->teardown_pending)) {
1299 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1300 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1301 "teardown pending\n");
1302 }
1303 return 0; /* dont handle any pkt completions */
1304 }
1305
1306 ++txch->proc_count;
1307 spin_lock_irqsave(&priv->tx_lock, flags);
1308 curr_bd = txch->active_queue_head;
1309 if (NULL == curr_bd) {
1310 emac_write(EMAC_TXCP(ch),
1311 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1312 txch->no_active_pkts++;
1313 spin_unlock_irqrestore(&priv->tx_lock, flags);
1314 return 0;
1315 }
1316 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1317 frame_status = curr_bd->mode;
1318 while ((curr_bd) &&
1319 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1320 (pkts_processed < budget)) {
1321 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1322 txch->active_queue_head = curr_bd->next;
1323 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1324 if (curr_bd->next) { /* misqueued packet */
1325 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1326 ++txch->mis_queued_packets;
1327 } else {
1328 txch->queue_active = 0; /* end of queue */
1329 }
1330 }
1331 *tx_complete_ptr = (u32) curr_bd->buf_token;
1332 ++tx_complete_ptr;
1333 ++tx_complete_cnt;
1334 curr_bd->next = txch->bd_pool_head;
1335 txch->bd_pool_head = curr_bd;
1336 --txch->active_queue_count;
1337 pkts_processed++;
1338 txch->last_hw_bdprocessed = curr_bd;
1339 curr_bd = txch->active_queue_head;
1340 if (curr_bd) {
1341 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1342 frame_status = curr_bd->mode;
1343 }
1344 } /* end of pkt processing loop */
1345
1346 emac_net_tx_complete(priv,
1347 (void *)&txch->tx_complete[0],
1348 tx_complete_cnt, ch);
1349 spin_unlock_irqrestore(&priv->tx_lock, flags);
1350 return pkts_processed;
1351 }
1352
1353 #define EMAC_ERR_TX_OUT_OF_BD -1
1354
1355 /**
1356 * emac_send: EMAC Transmit function (internal)
1357 * @priv: The DaVinci EMAC private adapter structure
1358 * @pkt: packet pointer (contains skb ptr)
1359 * @ch: TX channel number
1360 *
1361 * Called by the transmit function to queue the packet in EMAC hardware queue
1362 *
1363 * Returns success(0) or error code (typically out of desc's)
1364 */
1365 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1366 {
1367 unsigned long flags;
1368 struct emac_tx_bd __iomem *curr_bd;
1369 struct emac_txch *txch;
1370 struct emac_netbufobj *buf_list;
1371
1372 txch = priv->txch[ch];
1373 buf_list = pkt->buf_list; /* get handle to the buffer array */
1374
1375 /* check packet size and pad if short */
1376 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1377 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1378 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1379 }
1380
1381 spin_lock_irqsave(&priv->tx_lock, flags);
1382 curr_bd = txch->bd_pool_head;
1383 if (curr_bd == NULL) {
1384 txch->out_of_tx_bd++;
1385 spin_unlock_irqrestore(&priv->tx_lock, flags);
1386 return EMAC_ERR_TX_OUT_OF_BD;
1387 }
1388
1389 txch->bd_pool_head = curr_bd->next;
1390 curr_bd->buf_token = buf_list->buf_token;
1391 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1392 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1393 curr_bd->off_b_len = buf_list->length;
1394 curr_bd->h_next = 0;
1395 curr_bd->next = NULL;
1396 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1397 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1398
1399 /* flush the packet from cache if write back cache is present */
1400 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1401
1402 /* send the packet */
1403 if (txch->active_queue_head == NULL) {
1404 txch->active_queue_head = curr_bd;
1405 txch->active_queue_tail = curr_bd;
1406 if (1 != txch->queue_active) {
1407 emac_write(EMAC_TXHDP(ch),
1408 emac_virt_to_phys(curr_bd, priv));
1409 txch->queue_active = 1;
1410 }
1411 ++txch->queue_reinit;
1412 } else {
1413 register struct emac_tx_bd __iomem *tail_bd;
1414 register u32 frame_status;
1415
1416 tail_bd = txch->active_queue_tail;
1417 tail_bd->next = curr_bd;
1418 txch->active_queue_tail = curr_bd;
1419 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1420 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1421 frame_status = tail_bd->mode;
1422 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1423 emac_write(EMAC_TXHDP(ch),
1424 emac_virt_to_phys(curr_bd, priv));
1425 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1426 tail_bd->mode = frame_status;
1427 ++txch->end_of_queue_add;
1428 }
1429 }
1430 txch->active_queue_count++;
1431 spin_unlock_irqrestore(&priv->tx_lock, flags);
1432 return 0;
1433 }
1434
1435 /**
1436 * emac_dev_xmit: EMAC Transmit function
1437 * @skb: SKB pointer
1438 * @ndev: The DaVinci EMAC network adapter
1439 *
1440 * Called by the system to transmit a packet - we queue the packet in
1441 * EMAC hardware transmit queue
1442 *
1443 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1444 */
1445 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1446 {
1447 struct device *emac_dev = &ndev->dev;
1448 int ret_code;
1449 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1450 struct emac_netpktobj tx_packet; /* packet object */
1451 struct emac_priv *priv = netdev_priv(ndev);
1452
1453 /* If no link, return */
1454 if (unlikely(!priv->link)) {
1455 if (netif_msg_tx_err(priv) && net_ratelimit())
1456 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1457 return NETDEV_TX_BUSY;
1458 }
1459
1460 /* Build the buffer and packet objects - Since only single fragment is
1461 * supported, need not set length and token in both packet & object.
1462 * Doing so for completeness sake & to show that this needs to be done
1463 * in multifragment case
1464 */
1465 tx_packet.buf_list = &tx_buf;
1466 tx_packet.num_bufs = 1; /* only single fragment supported */
1467 tx_packet.pkt_length = skb->len;
1468 tx_packet.pkt_token = (void *)skb;
1469 tx_buf.length = skb->len;
1470 tx_buf.buf_token = (void *)skb;
1471 tx_buf.data_ptr = skb->data;
1472 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1473 ndev->trans_start = jiffies;
1474 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1475 if (unlikely(ret_code != 0)) {
1476 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1477 if (netif_msg_tx_err(priv) && net_ratelimit())
1478 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1479 " err. Out of TX BD's");
1480 netif_stop_queue(priv->ndev);
1481 }
1482 priv->net_dev_stats.tx_dropped++;
1483 return NETDEV_TX_BUSY;
1484 }
1485
1486 return NETDEV_TX_OK;
1487 }
1488
1489 /**
1490 * emac_dev_tx_timeout: EMAC Transmit timeout function
1491 * @ndev: The DaVinci EMAC network adapter
1492 *
1493 * Called when system detects that a skb timeout period has expired
1494 * potentially due to a fault in the adapter in not being able to send
1495 * it out on the wire. We teardown the TX channel assuming a hardware
1496 * error and re-initialize the TX channel for hardware operation
1497 *
1498 */
1499 static void emac_dev_tx_timeout(struct net_device *ndev)
1500 {
1501 struct emac_priv *priv = netdev_priv(ndev);
1502 struct device *emac_dev = &ndev->dev;
1503
1504 if (netif_msg_tx_err(priv))
1505 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1506
1507 priv->net_dev_stats.tx_errors++;
1508 emac_int_disable(priv);
1509 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1510 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1511 emac_init_txch(priv, EMAC_DEF_TX_CH);
1512 emac_write(EMAC_TXHDP(0), 0);
1513 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1514 emac_int_enable(priv);
1515 }
1516
1517 /**
1518 * emac_net_alloc_rx_buf: Allocate a skb for RX
1519 * @priv: The DaVinci EMAC private adapter structure
1520 * @buf_size: size of SKB data buffer to allocate
1521 * @data_token: data token returned (skb handle for storing in buffer desc)
1522 * @ch: RX channel number
1523 *
1524 * Called during RX channel setup - allocates skb buffer of required size
1525 * and provides the skb handle and allocated buffer data pointer to caller
1526 *
1527 * Returns skb data pointer or 0 on failure to alloc skb
1528 */
1529 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1530 void **data_token, u32 ch)
1531 {
1532 struct net_device *ndev = priv->ndev;
1533 struct device *emac_dev = &ndev->dev;
1534 struct sk_buff *p_skb;
1535
1536 p_skb = dev_alloc_skb(buf_size);
1537 if (unlikely(NULL == p_skb)) {
1538 if (netif_msg_rx_err(priv) && net_ratelimit())
1539 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1540 return NULL;
1541 }
1542
1543 /* set device pointer in skb and reserve space for extra bytes */
1544 p_skb->dev = ndev;
1545 skb_reserve(p_skb, NET_IP_ALIGN);
1546 *data_token = (void *) p_skb;
1547 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1548 return p_skb->data;
1549 }
1550
1551 /**
1552 * emac_init_rxch: RX channel initialization
1553 * @priv: The DaVinci EMAC private adapter structure
1554 * @ch: RX channel number
1555 * @param: mac address for RX channel
1556 *
1557 * Called during device init to setup a RX channel (allocate buffers and
1558 * buffer descriptors, create queue and keep ready for reception
1559 *
1560 * Returns success(0) or mem alloc failures error code
1561 */
1562 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1563 {
1564 struct device *emac_dev = &priv->ndev->dev;
1565 u32 cnt, bd_size;
1566 void __iomem *mem;
1567 struct emac_rx_bd __iomem *curr_bd;
1568 struct emac_rxch *rxch = NULL;
1569
1570 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1571 if (NULL == rxch) {
1572 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1573 return -ENOMEM;
1574 }
1575 priv->rxch[ch] = rxch;
1576 rxch->buf_size = priv->rx_buf_size;
1577 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1578 rxch->queue_active = 0;
1579 rxch->teardown_pending = 0;
1580
1581 /* save mac address */
1582 for (cnt = 0; cnt < 6; cnt++)
1583 rxch->mac_addr[cnt] = param[cnt];
1584
1585 /* allocate buffer descriptor pool align every BD on four word
1586 * boundry for future requirements */
1587 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1588 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1589 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1590 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1591 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1592 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1593
1594 /* allocate RX buffer and initialize the BD linked list */
1595 mem = (void __force __iomem *)
1596 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1597 rxch->active_queue_head = NULL;
1598 rxch->active_queue_tail = mem;
1599 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1600 curr_bd = mem + (cnt * bd_size);
1601 /* for future use the last parameter contains the BD ptr */
1602 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1603 rxch->buf_size,
1604 (void __force **)&curr_bd->buf_token,
1605 EMAC_DEF_RX_CH);
1606 if (curr_bd->data_ptr == NULL) {
1607 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1608 "failed for ch %d\n", ch);
1609 kfree(rxch);
1610 return -ENOMEM;
1611 }
1612
1613 /* populate the hardware descriptor */
1614 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1615 priv);
1616 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1617 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1618 curr_bd->off_b_len = rxch->buf_size;
1619 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1620
1621 /* write back to hardware memory */
1622 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1623 EMAC_BD_LENGTH_FOR_CACHE);
1624 curr_bd->next = rxch->active_queue_head;
1625 rxch->active_queue_head = curr_bd;
1626 }
1627
1628 /* At this point rxCppi->activeQueueHead points to the first
1629 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1630 points to the last RX BD
1631 */
1632 return 0;
1633 }
1634
1635 /**
1636 * emac_rxch_teardown: RX channel teardown
1637 * @priv: The DaVinci EMAC private adapter structure
1638 * @ch: RX channel number
1639 *
1640 * Called during device stop to teardown RX channel
1641 *
1642 */
1643 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1644 {
1645 struct device *emac_dev = &priv->ndev->dev;
1646 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1647
1648 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1649 EMAC_TEARDOWN_VALUE) {
1650 /* wait till tx teardown complete */
1651 cpu_relax(); /* TODO: check if this helps ... */
1652 --teardown_cnt;
1653 if (0 == teardown_cnt) {
1654 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1655 break;
1656 }
1657 }
1658 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1659 }
1660
1661 /**
1662 * emac_stop_rxch: Stop RX channel operation
1663 * @priv: The DaVinci EMAC private adapter structure
1664 * @ch: RX channel number
1665 *
1666 * Called during device stop to stop RX channel operation
1667 *
1668 */
1669 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1670 {
1671 struct emac_rxch *rxch = priv->rxch[ch];
1672
1673 if (rxch) {
1674 rxch->teardown_pending = 1;
1675 emac_write(EMAC_RXTEARDOWN, ch);
1676 /* wait for teardown complete */
1677 emac_rxch_teardown(priv, ch);
1678 rxch->teardown_pending = 0;
1679 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1680 }
1681 }
1682
1683 /**
1684 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1685 * @priv: The DaVinci EMAC private adapter structure
1686 * @ch: RX channel number
1687 *
1688 * Called during device stop to clean up RX channel resources
1689 *
1690 */
1691 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1692 {
1693 struct emac_rxch *rxch = priv->rxch[ch];
1694 struct emac_rx_bd __iomem *curr_bd;
1695
1696 if (rxch) {
1697 /* free the receive buffers previously allocated */
1698 curr_bd = rxch->active_queue_head;
1699 while (curr_bd) {
1700 if (curr_bd->buf_token) {
1701 dev_kfree_skb_any((struct sk_buff *)\
1702 curr_bd->buf_token);
1703 }
1704 curr_bd = curr_bd->next;
1705 }
1706 if (rxch->bd_mem)
1707 rxch->bd_mem = NULL;
1708 kfree(rxch);
1709 priv->rxch[ch] = NULL;
1710 }
1711 }
1712
1713 /**
1714 * emac_set_type0addr: Set EMAC Type0 mac address
1715 * @priv: The DaVinci EMAC private adapter structure
1716 * @ch: RX channel number
1717 * @mac_addr: MAC address to set in device
1718 *
1719 * Called internally to set Type0 mac address of the adapter (Device)
1720 *
1721 * Returns success (0) or appropriate error code (none as of now)
1722 */
1723 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1724 {
1725 u32 val;
1726 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1727 emac_write(EMAC_MACSRCADDRLO, val);
1728
1729 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1730 (mac_addr[1] << 8) | (mac_addr[0]));
1731 emac_write(EMAC_MACSRCADDRHI, val);
1732 val = emac_read(EMAC_RXUNICASTSET);
1733 val |= BIT(ch);
1734 emac_write(EMAC_RXUNICASTSET, val);
1735 val = emac_read(EMAC_RXUNICASTCLEAR);
1736 val &= ~BIT(ch);
1737 emac_write(EMAC_RXUNICASTCLEAR, val);
1738 }
1739
1740 /**
1741 * emac_set_type1addr: Set EMAC Type1 mac address
1742 * @priv: The DaVinci EMAC private adapter structure
1743 * @ch: RX channel number
1744 * @mac_addr: MAC address to set in device
1745 *
1746 * Called internally to set Type1 mac address of the adapter (Device)
1747 *
1748 * Returns success (0) or appropriate error code (none as of now)
1749 */
1750 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1751 {
1752 u32 val;
1753 emac_write(EMAC_MACINDEX, ch);
1754 val = ((mac_addr[5] << 8) | mac_addr[4]);
1755 emac_write(EMAC_MACADDRLO, val);
1756 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1757 (mac_addr[1] << 8) | (mac_addr[0]));
1758 emac_write(EMAC_MACADDRHI, val);
1759 emac_set_type0addr(priv, ch, mac_addr);
1760 }
1761
1762 /**
1763 * emac_set_type2addr: Set EMAC Type2 mac address
1764 * @priv: The DaVinci EMAC private adapter structure
1765 * @ch: RX channel number
1766 * @mac_addr: MAC address to set in device
1767 * @index: index into RX address entries
1768 * @match: match parameter for RX address matching logic
1769 *
1770 * Called internally to set Type2 mac address of the adapter (Device)
1771 *
1772 * Returns success (0) or appropriate error code (none as of now)
1773 */
1774 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1775 char *mac_addr, int index, int match)
1776 {
1777 u32 val;
1778 emac_write(EMAC_MACINDEX, index);
1779 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1780 (mac_addr[1] << 8) | (mac_addr[0]));
1781 emac_write(EMAC_MACADDRHI, val);
1782 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1783 (match << 19) | BIT(20));
1784 emac_write(EMAC_MACADDRLO, val);
1785 emac_set_type0addr(priv, ch, mac_addr);
1786 }
1787
1788 /**
1789 * emac_setmac: Set mac address in the adapter (internal function)
1790 * @priv: The DaVinci EMAC private adapter structure
1791 * @ch: RX channel number
1792 * @mac_addr: MAC address to set in device
1793 *
1794 * Called internally to set the mac address of the adapter (Device)
1795 *
1796 * Returns success (0) or appropriate error code (none as of now)
1797 */
1798 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1799 {
1800 struct device *emac_dev = &priv->ndev->dev;
1801
1802 if (priv->rx_addr_type == 0) {
1803 emac_set_type0addr(priv, ch, mac_addr);
1804 } else if (priv->rx_addr_type == 1) {
1805 u32 cnt;
1806 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1807 emac_set_type1addr(priv, ch, mac_addr);
1808 } else if (priv->rx_addr_type == 2) {
1809 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1810 emac_set_type0addr(priv, ch, mac_addr);
1811 } else {
1812 if (netif_msg_drv(priv))
1813 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1814 }
1815 }
1816
1817 /**
1818 * emac_dev_setmac_addr: Set mac address in the adapter
1819 * @ndev: The DaVinci EMAC network adapter
1820 * @addr: MAC address to set in device
1821 *
1822 * Called by the system to set the mac address of the adapter (Device)
1823 *
1824 * Returns success (0) or appropriate error code (none as of now)
1825 */
1826 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1827 {
1828 struct emac_priv *priv = netdev_priv(ndev);
1829 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1830 struct device *emac_dev = &priv->ndev->dev;
1831 struct sockaddr *sa = addr;
1832
1833 if (!is_valid_ether_addr(sa->sa_data))
1834 return -EINVAL;
1835
1836 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1837 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1838 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1839
1840 /* If the interface is down - rxch is NULL. */
1841 /* MAC address is configured only after the interface is enabled. */
1842 if (netif_running(ndev)) {
1843 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1844 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1845 }
1846
1847 if (netif_msg_drv(priv))
1848 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1849 priv->mac_addr);
1850
1851 return 0;
1852 }
1853
1854 /**
1855 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1856 * @priv: The DaVinci EMAC private adapter structure
1857 * @ch: RX channel number to process buffer descriptors for
1858 * @curr_bd: current buffer descriptor
1859 * @buffer: buffer pointer for descriptor
1860 * @buf_token: buffer token (stores skb information)
1861 *
1862 * Prepares the recycled buffer descriptor and addes it to hardware
1863 * receive queue - if queue empty this descriptor becomes the head
1864 * else addes the descriptor to end of queue
1865 *
1866 */
1867 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1868 struct emac_rx_bd __iomem *curr_bd,
1869 char *buffer, void *buf_token)
1870 {
1871 struct emac_rxch *rxch = priv->rxch[ch];
1872
1873 /* populate the hardware descriptor */
1874 curr_bd->h_next = 0;
1875 /* FIXME buff_ptr = dma_map_single(... buffer ...) */
1876 curr_bd->buff_ptr = virt_to_phys(buffer);
1877 curr_bd->off_b_len = rxch->buf_size;
1878 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1879 curr_bd->next = NULL;
1880 curr_bd->data_ptr = buffer;
1881 curr_bd->buf_token = buf_token;
1882
1883 /* write back */
1884 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1885 if (rxch->active_queue_head == NULL) {
1886 rxch->active_queue_head = curr_bd;
1887 rxch->active_queue_tail = curr_bd;
1888 if (0 != rxch->queue_active) {
1889 emac_write(EMAC_RXHDP(ch),
1890 emac_virt_to_phys(rxch->active_queue_head, priv));
1891 rxch->queue_active = 1;
1892 }
1893 } else {
1894 struct emac_rx_bd __iomem *tail_bd;
1895 u32 frame_status;
1896
1897 tail_bd = rxch->active_queue_tail;
1898 rxch->active_queue_tail = curr_bd;
1899 tail_bd->next = curr_bd;
1900 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1901 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
1902 frame_status = tail_bd->mode;
1903 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1904 emac_write(EMAC_RXHDP(ch),
1905 emac_virt_to_phys(curr_bd, priv));
1906 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1907 tail_bd->mode = frame_status;
1908 ++rxch->end_of_queue_add;
1909 }
1910 }
1911 ++rxch->recycled_bd;
1912 }
1913
1914 /**
1915 * emac_net_rx_cb: Prepares packet and sends to upper layer
1916 * @priv: The DaVinci EMAC private adapter structure
1917 * @net_pkt_list: Network packet list (received packets)
1918 *
1919 * Invalidates packet buffer memory and sends the received packet to upper
1920 * layer
1921 *
1922 * Returns success or appropriate error code (none as of now)
1923 */
1924 static int emac_net_rx_cb(struct emac_priv *priv,
1925 struct emac_netpktobj *net_pkt_list)
1926 {
1927 struct sk_buff *p_skb;
1928 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1929 /* set length of packet */
1930 skb_put(p_skb, net_pkt_list->pkt_length);
1931 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1932 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
1933 netif_receive_skb(p_skb);
1934 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1935 priv->net_dev_stats.rx_packets++;
1936 return 0;
1937 }
1938
1939 /**
1940 * emac_rx_bdproc: RX buffer descriptor (packet) processing
1941 * @priv: The DaVinci EMAC private adapter structure
1942 * @ch: RX channel number to process buffer descriptors for
1943 * @budget: number of packets allowed to process
1944 * @pending: indication to caller that packets are pending to process
1945 *
1946 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
1947 * descriptor, sends the receive packet to upper layer, allocates a new SKB
1948 * and recycles the buffer descriptor (requeues it in hardware RX queue).
1949 * Only "budget" number of packets are processed and indication of pending
1950 * packets provided to the caller.
1951 *
1952 * Returns number of packets processed (and indication of pending packets)
1953 */
1954 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1955 {
1956 unsigned long flags;
1957 u32 frame_status;
1958 u32 pkts_processed = 0;
1959 char *new_buffer;
1960 struct emac_rx_bd __iomem *curr_bd;
1961 struct emac_rx_bd __iomem *last_bd;
1962 struct emac_netpktobj *curr_pkt, pkt_obj;
1963 struct emac_netbufobj buf_obj;
1964 struct emac_netbufobj *rx_buf_obj;
1965 void *new_buf_token;
1966 struct emac_rxch *rxch = priv->rxch[ch];
1967
1968 if (unlikely(1 == rxch->teardown_pending))
1969 return 0;
1970 ++rxch->proc_count;
1971 spin_lock_irqsave(&priv->rx_lock, flags);
1972 pkt_obj.buf_list = &buf_obj;
1973 curr_pkt = &pkt_obj;
1974 curr_bd = rxch->active_queue_head;
1975 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1976 frame_status = curr_bd->mode;
1977
1978 while ((curr_bd) &&
1979 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1980 (pkts_processed < budget)) {
1981
1982 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1983 &new_buf_token, EMAC_DEF_RX_CH);
1984 if (unlikely(NULL == new_buffer)) {
1985 ++rxch->out_of_rx_buffers;
1986 goto end_emac_rx_bdproc;
1987 }
1988
1989 /* populate received packet data structure */
1990 rx_buf_obj = &curr_pkt->buf_list[0];
1991 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1992 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1993 rx_buf_obj->buf_token = curr_bd->buf_token;
1994 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1995 curr_pkt->num_bufs = 1;
1996 curr_pkt->pkt_length =
1997 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1998 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
1999 ++rxch->processed_bd;
2000 last_bd = curr_bd;
2001 curr_bd = last_bd->next;
2002 rxch->active_queue_head = curr_bd;
2003
2004 /* check if end of RX queue ? */
2005 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2006 if (curr_bd) {
2007 ++rxch->mis_queued_packets;
2008 emac_write(EMAC_RXHDP(ch),
2009 emac_virt_to_phys(curr_bd, priv));
2010 } else {
2011 ++rxch->end_of_queue;
2012 rxch->queue_active = 0;
2013 }
2014 }
2015
2016 /* recycle BD */
2017 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2018 new_buf_token);
2019
2020 /* return the packet to the user - BD ptr passed in
2021 * last parameter for potential *future* use */
2022 spin_unlock_irqrestore(&priv->rx_lock, flags);
2023 emac_net_rx_cb(priv, curr_pkt);
2024 spin_lock_irqsave(&priv->rx_lock, flags);
2025 curr_bd = rxch->active_queue_head;
2026 if (curr_bd) {
2027 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2028 frame_status = curr_bd->mode;
2029 }
2030 ++pkts_processed;
2031 }
2032
2033 end_emac_rx_bdproc:
2034 spin_unlock_irqrestore(&priv->rx_lock, flags);
2035 return pkts_processed;
2036 }
2037
2038 /**
2039 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2040 * @priv: The DaVinci EMAC private adapter structure
2041 *
2042 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2043 * for packet reception and enables device interrupts and then NAPI
2044 *
2045 * Returns success (0) or appropriate error code (none right now)
2046 */
2047 static int emac_hw_enable(struct emac_priv *priv)
2048 {
2049 u32 ch, val, mbp_enable, mac_control;
2050
2051 /* Soft reset */
2052 emac_write(EMAC_SOFTRESET, 1);
2053 while (emac_read(EMAC_SOFTRESET))
2054 cpu_relax();
2055
2056 /* Disable interrupt & Set pacing for more interrupts initially */
2057 emac_int_disable(priv);
2058
2059 /* Full duplex enable bit set when auto negotiation happens */
2060 mac_control =
2061 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2062 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2063 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2064 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2065 emac_write(EMAC_MACCONTROL, mac_control);
2066
2067 mbp_enable =
2068 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2069 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2070 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2071 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2072 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2073 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2074 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2075 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2076 EMAC_RXMBP_PROMCH_SHIFT) |
2077 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2078 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2079 EMAC_RXMBP_BROADCH_SHIFT) |
2080 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2081 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2082 EMAC_RXMBP_MULTICH_SHIFT));
2083 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2084 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2085 EMAC_RX_MAX_LEN_MASK));
2086 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2087 EMAC_RX_BUFFER_OFFSET_MASK));
2088 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2089 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2090 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2091
2092 val = emac_read(EMAC_TXCONTROL);
2093 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2094 emac_write(EMAC_TXCONTROL, val);
2095 val = emac_read(EMAC_RXCONTROL);
2096 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2097 emac_write(EMAC_RXCONTROL, val);
2098 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2099
2100 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2101 emac_write(EMAC_TXHDP(ch), 0);
2102 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2103 }
2104 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2105 struct emac_rxch *rxch = priv->rxch[ch];
2106 emac_setmac(priv, ch, rxch->mac_addr);
2107 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2108 rxch->queue_active = 1;
2109 emac_write(EMAC_RXHDP(ch),
2110 emac_virt_to_phys(rxch->active_queue_head, priv));
2111 }
2112
2113 /* Enable MII */
2114 val = emac_read(EMAC_MACCONTROL);
2115 val |= (EMAC_MACCONTROL_GMIIEN);
2116 emac_write(EMAC_MACCONTROL, val);
2117
2118 /* Enable NAPI and interrupts */
2119 napi_enable(&priv->napi);
2120 emac_int_enable(priv);
2121 return 0;
2122
2123 }
2124
2125 /**
2126 * emac_poll: EMAC NAPI Poll function
2127 * @ndev: The DaVinci EMAC network adapter
2128 * @budget: Number of receive packets to process (as told by NAPI layer)
2129 *
2130 * NAPI Poll function implemented to process packets as per budget. We check
2131 * the type of interrupt on the device and accordingly call the TX or RX
2132 * packet processing functions. We follow the budget for RX processing and
2133 * also put a cap on number of TX pkts processed through config param. The
2134 * NAPI schedule function is called if more packets pending.
2135 *
2136 * Returns number of packets received (in most cases; else TX pkts - rarely)
2137 */
2138 static int emac_poll(struct napi_struct *napi, int budget)
2139 {
2140 unsigned int mask;
2141 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2142 struct net_device *ndev = priv->ndev;
2143 struct device *emac_dev = &ndev->dev;
2144 u32 status = 0;
2145 u32 num_pkts = 0;
2146
2147 /* Check interrupt vectors and call packet processing */
2148 status = emac_read(EMAC_MACINVECTOR);
2149
2150 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2151
2152 if (priv->version == EMAC_VERSION_2)
2153 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2154
2155 if (status & mask) {
2156 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2157 EMAC_DEF_TX_MAX_SERVICE);
2158 } /* TX processing */
2159
2160 if (num_pkts)
2161 return budget;
2162
2163 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2164
2165 if (priv->version == EMAC_VERSION_2)
2166 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2167
2168 if (status & mask) {
2169 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2170 } /* RX processing */
2171
2172 if (num_pkts < budget) {
2173 napi_complete(napi);
2174 emac_int_enable(priv);
2175 }
2176
2177 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2178 if (priv->version == EMAC_VERSION_2)
2179 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2180
2181 if (unlikely(status & mask)) {
2182 u32 ch, cause;
2183 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2184 netif_stop_queue(ndev);
2185 napi_disable(&priv->napi);
2186
2187 status = emac_read(EMAC_MACSTATUS);
2188 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2189 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2190 if (cause) {
2191 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2192 EMAC_MACSTATUS_TXERRCH_SHIFT);
2193 if (net_ratelimit()) {
2194 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2195 &emac_txhost_errcodes[cause][0], ch);
2196 }
2197 }
2198 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2199 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2200 if (cause) {
2201 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2202 EMAC_MACSTATUS_RXERRCH_SHIFT);
2203 if (netif_msg_hw(priv) && net_ratelimit())
2204 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2205 &emac_rxhost_errcodes[cause][0], ch);
2206 }
2207 } /* Host error processing */
2208
2209 return num_pkts;
2210 }
2211
2212 #ifdef CONFIG_NET_POLL_CONTROLLER
2213 /**
2214 * emac_poll_controller: EMAC Poll controller function
2215 * @ndev: The DaVinci EMAC network adapter
2216 *
2217 * Polled functionality used by netconsole and others in non interrupt mode
2218 *
2219 */
2220 void emac_poll_controller(struct net_device *ndev)
2221 {
2222 struct emac_priv *priv = netdev_priv(ndev);
2223
2224 emac_int_disable(priv);
2225 emac_irq(ndev->irq, ndev);
2226 emac_int_enable(priv);
2227 }
2228 #endif
2229
2230 /* PHY/MII bus related */
2231
2232 /* Wait until mdio is ready for next command */
2233 #define MDIO_WAIT_FOR_USER_ACCESS\
2234 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2235 MDIO_USERACCESS_GO) != 0)
2236
2237 static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2238 {
2239 unsigned int phy_data = 0;
2240 unsigned int phy_control;
2241
2242 /* Wait until mdio is ready for next command */
2243 MDIO_WAIT_FOR_USER_ACCESS;
2244
2245 phy_control = (MDIO_USERACCESS_GO |
2246 MDIO_USERACCESS_READ |
2247 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2248 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2249 (phy_data & MDIO_USERACCESS_DATA));
2250 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2251
2252 /* Wait until mdio is ready for next command */
2253 MDIO_WAIT_FOR_USER_ACCESS;
2254
2255 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2256
2257 }
2258
2259 static int emac_mii_write(struct mii_bus *bus, int phy_id,
2260 int phy_reg, u16 phy_data)
2261 {
2262
2263 unsigned int control;
2264
2265 /* until mdio is ready for next command */
2266 MDIO_WAIT_FOR_USER_ACCESS;
2267
2268 control = (MDIO_USERACCESS_GO |
2269 MDIO_USERACCESS_WRITE |
2270 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2271 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2272 (phy_data & MDIO_USERACCESS_DATA));
2273 emac_mdio_write(MDIO_USERACCESS(0), control);
2274
2275 return 0;
2276 }
2277
2278 static int emac_mii_reset(struct mii_bus *bus)
2279 {
2280 unsigned int clk_div;
2281 int mdio_bus_freq = emac_bus_frequency;
2282
2283 if (mdio_max_freq && mdio_bus_freq)
2284 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2285 else
2286 clk_div = 0xFF;
2287
2288 clk_div &= MDIO_CONTROL_CLKDIV;
2289
2290 /* Set enable and clock divider in MDIOControl */
2291 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2292
2293 return 0;
2294
2295 }
2296
2297 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2298
2299 /* emac_driver: EMAC MII bus structure */
2300
2301 static struct mii_bus *emac_mii;
2302
2303 static void emac_adjust_link(struct net_device *ndev)
2304 {
2305 struct emac_priv *priv = netdev_priv(ndev);
2306 struct phy_device *phydev = priv->phydev;
2307 unsigned long flags;
2308 int new_state = 0;
2309
2310 spin_lock_irqsave(&priv->lock, flags);
2311
2312 if (phydev->link) {
2313 /* check the mode of operation - full/half duplex */
2314 if (phydev->duplex != priv->duplex) {
2315 new_state = 1;
2316 priv->duplex = phydev->duplex;
2317 }
2318 if (phydev->speed != priv->speed) {
2319 new_state = 1;
2320 priv->speed = phydev->speed;
2321 }
2322 if (!priv->link) {
2323 new_state = 1;
2324 priv->link = 1;
2325 }
2326
2327 } else if (priv->link) {
2328 new_state = 1;
2329 priv->link = 0;
2330 priv->speed = 0;
2331 priv->duplex = ~0;
2332 }
2333 if (new_state) {
2334 emac_update_phystatus(priv);
2335 phy_print_status(priv->phydev);
2336 }
2337
2338 spin_unlock_irqrestore(&priv->lock, flags);
2339 }
2340
2341 /*************************************************************************
2342 * Linux Driver Model
2343 *************************************************************************/
2344
2345 /**
2346 * emac_devioctl: EMAC adapter ioctl
2347 * @ndev: The DaVinci EMAC network adapter
2348 * @ifrq: request parameter
2349 * @cmd: command parameter
2350 *
2351 * EMAC driver ioctl function
2352 *
2353 * Returns success(0) or appropriate error code
2354 */
2355 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2356 {
2357 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2358
2359 if (!(netif_running(ndev)))
2360 return -EINVAL;
2361
2362 /* TODO: Add phy read and write and private statistics get feature */
2363
2364 return -EOPNOTSUPP;
2365 }
2366
2367 /**
2368 * emac_dev_open: EMAC device open
2369 * @ndev: The DaVinci EMAC network adapter
2370 *
2371 * Called when system wants to start the interface. We init TX/RX channels
2372 * and enable the hardware for packet reception/transmission and start the
2373 * network queue.
2374 *
2375 * Returns 0 for a successful open, or appropriate error code
2376 */
2377 static int emac_dev_open(struct net_device *ndev)
2378 {
2379 struct device *emac_dev = &ndev->dev;
2380 u32 rc, cnt, ch;
2381 int phy_addr;
2382 struct resource *res;
2383 int q, m;
2384 int i = 0;
2385 int k = 0;
2386 struct emac_priv *priv = netdev_priv(ndev);
2387
2388 netif_carrier_off(ndev);
2389 for (cnt = 0; cnt <= ETH_ALEN; cnt++)
2390 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2391
2392 /* Configuration items */
2393 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2394
2395 /* Clear basic hardware */
2396 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2397 emac_write(EMAC_TXHDP(ch), 0);
2398 emac_write(EMAC_RXHDP(ch), 0);
2399 emac_write(EMAC_RXHDP(ch), 0);
2400 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2401 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2402 }
2403 priv->mac_hash1 = 0;
2404 priv->mac_hash2 = 0;
2405 emac_write(EMAC_MACHASH1, 0);
2406 emac_write(EMAC_MACHASH2, 0);
2407
2408 /* multi ch not supported - open 1 TX, 1RX ch by default */
2409 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2410 if (0 != rc) {
2411 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2412 return rc;
2413 }
2414 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2415 if (0 != rc) {
2416 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2417 return rc;
2418 }
2419
2420 /* Request IRQ */
2421
2422 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2423 for (i = res->start; i <= res->end; i++) {
2424 if (request_irq(i, emac_irq, IRQF_DISABLED,
2425 ndev->name, ndev))
2426 goto rollback;
2427 }
2428 k++;
2429 }
2430
2431 /* Start/Enable EMAC hardware */
2432 emac_hw_enable(priv);
2433
2434 /* find the first phy */
2435 priv->phydev = NULL;
2436 if (priv->phy_mask) {
2437 emac_mii_reset(priv->mii_bus);
2438 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2439 if (priv->mii_bus->phy_map[phy_addr]) {
2440 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2441 break;
2442 }
2443 }
2444
2445 if (!priv->phydev) {
2446 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2447 return -1;
2448 }
2449
2450 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2451 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2452
2453 if (IS_ERR(priv->phydev)) {
2454 printk(KERN_ERR "%s: Could not attach to PHY\n",
2455 ndev->name);
2456 return PTR_ERR(priv->phydev);
2457 }
2458
2459 priv->link = 0;
2460 priv->speed = 0;
2461 priv->duplex = ~0;
2462
2463 printk(KERN_INFO "%s: attached PHY driver [%s] "
2464 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2465 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2466 priv->phydev->phy_id);
2467 } else{
2468 /* No PHY , fix the link, speed and duplex settings */
2469 priv->link = 1;
2470 priv->speed = SPEED_100;
2471 priv->duplex = DUPLEX_FULL;
2472 emac_update_phystatus(priv);
2473 }
2474
2475 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2476 emac_dump_regs(priv);
2477
2478 if (netif_msg_drv(priv))
2479 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2480
2481 if (priv->phy_mask)
2482 phy_start(priv->phydev);
2483
2484 return 0;
2485
2486 rollback:
2487
2488 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2489
2490 for (q = k; k >= 0; k--) {
2491 for (m = i; m >= res->start; m--)
2492 free_irq(m, ndev);
2493 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2494 m = res->end;
2495 }
2496 return -EBUSY;
2497 }
2498
2499 /**
2500 * emac_dev_stop: EMAC device stop
2501 * @ndev: The DaVinci EMAC network adapter
2502 *
2503 * Called when system wants to stop or down the interface. We stop the network
2504 * queue, disable interrupts and cleanup TX/RX channels.
2505 *
2506 * We return the statistics in net_device_stats structure pulled from emac
2507 */
2508 static int emac_dev_stop(struct net_device *ndev)
2509 {
2510 struct resource *res;
2511 int i = 0;
2512 int irq_num;
2513 struct emac_priv *priv = netdev_priv(ndev);
2514 struct device *emac_dev = &ndev->dev;
2515
2516 /* inform the upper layers. */
2517 netif_stop_queue(ndev);
2518 napi_disable(&priv->napi);
2519
2520 netif_carrier_off(ndev);
2521 emac_int_disable(priv);
2522 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2523 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2524 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2525 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2526 emac_write(EMAC_SOFTRESET, 1);
2527
2528 if (priv->phydev)
2529 phy_disconnect(priv->phydev);
2530
2531 /* Free IRQ */
2532 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2533 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2534 free_irq(irq_num, priv->ndev);
2535 i++;
2536 }
2537
2538 if (netif_msg_drv(priv))
2539 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2540
2541 return 0;
2542 }
2543
2544 /**
2545 * emac_dev_getnetstats: EMAC get statistics function
2546 * @ndev: The DaVinci EMAC network adapter
2547 *
2548 * Called when system wants to get statistics from the device.
2549 *
2550 * We return the statistics in net_device_stats structure pulled from emac
2551 */
2552 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2553 {
2554 struct emac_priv *priv = netdev_priv(ndev);
2555 u32 mac_control;
2556 u32 stats_clear_mask;
2557
2558 /* update emac hardware stats and reset the registers*/
2559
2560 mac_control = emac_read(EMAC_MACCONTROL);
2561
2562 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2563 stats_clear_mask = EMAC_STATS_CLR_MASK;
2564 else
2565 stats_clear_mask = 0;
2566
2567 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2568 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2569
2570 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2571 emac_read(EMAC_TXSINGLECOLL) +
2572 emac_read(EMAC_TXMULTICOLL));
2573 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2574 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2575 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2576
2577 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2578 emac_read(EMAC_RXJABBER) +
2579 emac_read(EMAC_RXUNDERSIZED));
2580 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2581 emac_write(EMAC_RXJABBER, stats_clear_mask);
2582 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2583
2584 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2585 emac_read(EMAC_RXMOFOVERRUNS));
2586 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2587 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2588
2589 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2590 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2591
2592 priv->net_dev_stats.tx_carrier_errors +=
2593 emac_read(EMAC_TXCARRIERSENSE);
2594 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2595
2596 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2597 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2598
2599 return &priv->net_dev_stats;
2600 }
2601
2602 static const struct net_device_ops emac_netdev_ops = {
2603 .ndo_open = emac_dev_open,
2604 .ndo_stop = emac_dev_stop,
2605 .ndo_start_xmit = emac_dev_xmit,
2606 .ndo_set_multicast_list = emac_dev_mcast_set,
2607 .ndo_set_mac_address = emac_dev_setmac_addr,
2608 .ndo_do_ioctl = emac_devioctl,
2609 .ndo_tx_timeout = emac_dev_tx_timeout,
2610 .ndo_get_stats = emac_dev_getnetstats,
2611 #ifdef CONFIG_NET_POLL_CONTROLLER
2612 .ndo_poll_controller = emac_poll_controller,
2613 #endif
2614 };
2615
2616 /**
2617 * davinci_emac_probe: EMAC device probe
2618 * @pdev: The DaVinci EMAC device that we are removing
2619 *
2620 * Called when probing for emac devicesr. We get details of instances and
2621 * resource information from platform init and register a network device
2622 * and allocate resources necessary for driver to perform
2623 */
2624 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2625 {
2626 int rc = 0;
2627 struct resource *res;
2628 struct net_device *ndev;
2629 struct emac_priv *priv;
2630 unsigned long size;
2631 struct emac_platform_data *pdata;
2632 struct device *emac_dev;
2633
2634 /* obtain emac clock from kernel */
2635 emac_clk = clk_get(&pdev->dev, NULL);
2636 if (IS_ERR(emac_clk)) {
2637 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2638 return -EBUSY;
2639 }
2640 emac_bus_frequency = clk_get_rate(emac_clk);
2641 /* TODO: Probe PHY here if possible */
2642
2643 ndev = alloc_etherdev(sizeof(struct emac_priv));
2644 if (!ndev) {
2645 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2646 clk_put(emac_clk);
2647 return -ENOMEM;
2648 }
2649
2650 platform_set_drvdata(pdev, ndev);
2651 priv = netdev_priv(ndev);
2652 priv->pdev = pdev;
2653 priv->ndev = ndev;
2654 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2655
2656 spin_lock_init(&priv->tx_lock);
2657 spin_lock_init(&priv->rx_lock);
2658 spin_lock_init(&priv->lock);
2659
2660 pdata = pdev->dev.platform_data;
2661 if (!pdata) {
2662 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2663 return -ENODEV;
2664 }
2665
2666 /* MAC addr and PHY mask , RMII enable info from platform_data */
2667 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2668 priv->phy_mask = pdata->phy_mask;
2669 priv->rmii_en = pdata->rmii_en;
2670 priv->version = pdata->version;
2671 priv->int_enable = pdata->interrupt_enable;
2672 priv->int_disable = pdata->interrupt_disable;
2673
2674 emac_dev = &ndev->dev;
2675 /* Get EMAC platform data */
2676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2677 if (!res) {
2678 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2679 rc = -ENOENT;
2680 goto probe_quit;
2681 }
2682
2683 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2684 size = res->end - res->start + 1;
2685 if (!request_mem_region(res->start, size, ndev->name)) {
2686 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \
2687 for regs\n");
2688 rc = -ENXIO;
2689 goto probe_quit;
2690 }
2691
2692 priv->remap_addr = ioremap(res->start, size);
2693 if (!priv->remap_addr) {
2694 dev_err(emac_dev, "Unable to map IO\n");
2695 rc = -ENOMEM;
2696 release_mem_region(res->start, size);
2697 goto probe_quit;
2698 }
2699 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2700 ndev->base_addr = (unsigned long)priv->remap_addr;
2701
2702 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2703 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2704 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2705
2706 if (pdata->hw_ram_addr)
2707 priv->hw_ram_addr = pdata->hw_ram_addr;
2708 else
2709 priv->hw_ram_addr = (u32 __force)res->start +
2710 pdata->ctrl_ram_offset;
2711
2712 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2713 if (!res) {
2714 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2715 rc = -ENOENT;
2716 goto no_irq_res;
2717 }
2718 ndev->irq = res->start;
2719
2720 if (!is_valid_ether_addr(priv->mac_addr)) {
2721 /* Use random MAC if none passed */
2722 random_ether_addr(priv->mac_addr);
2723 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2724 __func__, priv->mac_addr);
2725 }
2726
2727 ndev->netdev_ops = &emac_netdev_ops;
2728 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2729 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2730
2731 clk_enable(emac_clk);
2732
2733 /* register the network device */
2734 SET_NETDEV_DEV(ndev, &pdev->dev);
2735 rc = register_netdev(ndev);
2736 if (rc) {
2737 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2738 rc = -ENODEV;
2739 goto netdev_reg_err;
2740 }
2741
2742
2743 /* MII/Phy intialisation, mdio bus registration */
2744 emac_mii = mdiobus_alloc();
2745 if (emac_mii == NULL) {
2746 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2747 rc = -ENOMEM;
2748 goto mdio_alloc_err;
2749 }
2750
2751 priv->mii_bus = emac_mii;
2752 emac_mii->name = "emac-mii",
2753 emac_mii->read = emac_mii_read,
2754 emac_mii->write = emac_mii_write,
2755 emac_mii->reset = emac_mii_reset,
2756 emac_mii->irq = mii_irqs,
2757 emac_mii->phy_mask = ~(priv->phy_mask);
2758 emac_mii->parent = &pdev->dev;
2759 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2760 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2761 mdio_max_freq = pdata->mdio_max_freq;
2762 emac_mii->reset(emac_mii);
2763
2764 /* Register the MII bus */
2765 rc = mdiobus_register(emac_mii);
2766 if (rc)
2767 goto mdiobus_quit;
2768
2769 if (netif_msg_probe(priv)) {
2770 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2771 "(regs: %p, irq: %d)\n",
2772 (void *)priv->emac_base_phys, ndev->irq);
2773 }
2774 return 0;
2775
2776 mdiobus_quit:
2777 mdiobus_free(emac_mii);
2778
2779 netdev_reg_err:
2780 mdio_alloc_err:
2781 clk_disable(emac_clk);
2782 no_irq_res:
2783 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2784 release_mem_region(res->start, res->end - res->start + 1);
2785 iounmap(priv->remap_addr);
2786
2787 probe_quit:
2788 clk_put(emac_clk);
2789 free_netdev(ndev);
2790 return rc;
2791 }
2792
2793 /**
2794 * davinci_emac_remove: EMAC device remove
2795 * @pdev: The DaVinci EMAC device that we are removing
2796 *
2797 * Called when removing the device driver. We disable clock usage and release
2798 * the resources taken up by the driver and unregister network device
2799 */
2800 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2801 {
2802 struct resource *res;
2803 struct net_device *ndev = platform_get_drvdata(pdev);
2804 struct emac_priv *priv = netdev_priv(ndev);
2805
2806 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2807
2808 platform_set_drvdata(pdev, NULL);
2809 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2810 mdiobus_unregister(priv->mii_bus);
2811 mdiobus_free(priv->mii_bus);
2812
2813 release_mem_region(res->start, res->end - res->start + 1);
2814
2815 unregister_netdev(ndev);
2816 free_netdev(ndev);
2817 iounmap(priv->remap_addr);
2818
2819 clk_disable(emac_clk);
2820 clk_put(emac_clk);
2821
2822 return 0;
2823 }
2824
2825 static
2826 int davinci_emac_suspend(struct platform_device *pdev, pm_message_t state)
2827 {
2828 struct net_device *dev = platform_get_drvdata(pdev);
2829
2830 if (netif_running(dev))
2831 emac_dev_stop(dev);
2832
2833 clk_disable(emac_clk);
2834
2835 return 0;
2836 }
2837
2838 static int davinci_emac_resume(struct platform_device *pdev)
2839 {
2840 struct net_device *dev = platform_get_drvdata(pdev);
2841
2842 clk_enable(emac_clk);
2843
2844 if (netif_running(dev))
2845 emac_dev_open(dev);
2846
2847 return 0;
2848 }
2849
2850 /**
2851 * davinci_emac_driver: EMAC platform driver structure
2852 */
2853 static struct platform_driver davinci_emac_driver = {
2854 .driver = {
2855 .name = "davinci_emac",
2856 .owner = THIS_MODULE,
2857 },
2858 .probe = davinci_emac_probe,
2859 .remove = __devexit_p(davinci_emac_remove),
2860 .suspend = davinci_emac_suspend,
2861 .resume = davinci_emac_resume,
2862 };
2863
2864 /**
2865 * davinci_emac_init: EMAC driver module init
2866 *
2867 * Called when initializing the driver. We register the driver with
2868 * the platform.
2869 */
2870 static int __init davinci_emac_init(void)
2871 {
2872 return platform_driver_register(&davinci_emac_driver);
2873 }
2874 late_initcall(davinci_emac_init);
2875
2876 /**
2877 * davinci_emac_exit: EMAC driver module exit
2878 *
2879 * Called when exiting the driver completely. We unregister the driver with
2880 * the platform and exit
2881 */
2882 static void __exit davinci_emac_exit(void)
2883 {
2884 platform_driver_unregister(&davinci_emac_driver);
2885 }
2886 module_exit(davinci_emac_exit);
2887
2888 MODULE_LICENSE("GPL");
2889 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2890 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2891 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
Linux kernel - Deliverables
This page took 0.115915 seconds and 5 git commands to generate.