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Merge branch 'master' into upstream-fixes
[deliverable/linux.git] / drivers / net / dl2k.c
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12 /*
13 Rev Date Description
14 ==========================================================================
15 0.01 2001/05/03 Created DL2000-based linux driver
16 0.02 2001/05/21 Added VLAN and hardware checksum support.
17 1.00 2001/06/26 Added jumbo frame support.
18 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
19 1.02 2001/10/08 Supported fiber media.
20 Added flow control parameters.
21 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
22 the fiber devices.
23 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
24 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
25 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
26 Fixed tx_full flag incorrect.
27 Added tx_coalesce paramter.
28 1.07 2002/01/03 Fixed miscount of RX frame error.
29 1.08 2002/01/17 Fixed the multicast bug.
30 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
31 Added rio_timer() to watch rx buffers.
32 1.10 2002/04/16 Fixed miscount of carrier error.
33 1.11 2002/05/23 Added ISR schedule scheme
34 Fixed miscount of rx frame error for DGE-550SX.
35 Fixed VLAN bug.
36 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
37 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
38 errs) with some mainboards.
39 2. Use definition "DRV_NAME" "DRV_VERSION"
40 "DRV_RELDATE" for flexibility.
41 1.14 2002/08/14 Support ethtool.
42 1.15 2002/08/27 Changed the default media to Auto-Negotiation
43 for the fiber devices.
44 1.16 2002/09/04 More power down time for fiber devices auto-
45 negotiation.
46 Fix disconnect bug after ifup and ifdown.
47 1.17 2002/10/03 Fix RMON statistics overflow.
48 Always use I/O mapping to access eeprom,
49 avoid system freezing with some chipsets.
50
51 */
52 #define DRV_NAME "D-Link DL2000-based linux driver"
53 #define DRV_VERSION "v1.17b"
54 #define DRV_RELDATE "2006/03/10"
55 #include "dl2k.h"
56
57 static char version[] __devinitdata =
58 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
59 #define MAX_UNITS 8
60 static int mtu[MAX_UNITS];
61 static int vlan[MAX_UNITS];
62 static int jumbo[MAX_UNITS];
63 static char *media[MAX_UNITS];
64 static int tx_flow=-1;
65 static int rx_flow=-1;
66 static int copy_thresh;
67 static int rx_coalesce=10; /* Rx frame count each interrupt */
68 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
69 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
70
71
72 MODULE_AUTHOR ("Edward Peng");
73 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
74 MODULE_LICENSE("GPL");
75 module_param_array(mtu, int, NULL, 0);
76 module_param_array(media, charp, NULL, 0);
77 module_param_array(vlan, int, NULL, 0);
78 module_param_array(jumbo, int, NULL, 0);
79 module_param(tx_flow, int, 0);
80 module_param(rx_flow, int, 0);
81 module_param(copy_thresh, int, 0);
82 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
83 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
84 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
85
86
87 /* Enable the default interrupts */
88 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
89 UpdateStats | LinkEvent)
90 #define EnableInt() \
91 writew(DEFAULT_INTR, ioaddr + IntEnable)
92
93 static const int max_intrloop = 50;
94 static const int multicast_filter_limit = 0x40;
95
96 static int rio_open (struct net_device *dev);
97 static void rio_timer (unsigned long data);
98 static void rio_tx_timeout (struct net_device *dev);
99 static void alloc_list (struct net_device *dev);
100 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
101 static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
102 static void rio_free_tx (struct net_device *dev, int irq);
103 static void tx_error (struct net_device *dev, int tx_status);
104 static int receive_packet (struct net_device *dev);
105 static void rio_error (struct net_device *dev, int int_status);
106 static int change_mtu (struct net_device *dev, int new_mtu);
107 static void set_multicast (struct net_device *dev);
108 static struct net_device_stats *get_stats (struct net_device *dev);
109 static int clear_stats (struct net_device *dev);
110 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
111 static int rio_close (struct net_device *dev);
112 static int find_miiphy (struct net_device *dev);
113 static int parse_eeprom (struct net_device *dev);
114 static int read_eeprom (long ioaddr, int eep_addr);
115 static int mii_wait_link (struct net_device *dev, int wait);
116 static int mii_set_media (struct net_device *dev);
117 static int mii_get_media (struct net_device *dev);
118 static int mii_set_media_pcs (struct net_device *dev);
119 static int mii_get_media_pcs (struct net_device *dev);
120 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
121 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
122 u16 data);
123
124 static struct ethtool_ops ethtool_ops;
125
126 static int __devinit
127 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
128 {
129 struct net_device *dev;
130 struct netdev_private *np;
131 static int card_idx;
132 int chip_idx = ent->driver_data;
133 int err, irq;
134 long ioaddr;
135 static int version_printed;
136 void *ring_space;
137 dma_addr_t ring_dma;
138
139 if (!version_printed++)
140 printk ("%s", version);
141
142 err = pci_enable_device (pdev);
143 if (err)
144 return err;
145
146 irq = pdev->irq;
147 err = pci_request_regions (pdev, "dl2k");
148 if (err)
149 goto err_out_disable;
150
151 pci_set_master (pdev);
152 dev = alloc_etherdev (sizeof (*np));
153 if (!dev) {
154 err = -ENOMEM;
155 goto err_out_res;
156 }
157 SET_MODULE_OWNER (dev);
158 SET_NETDEV_DEV(dev, &pdev->dev);
159
160 #ifdef MEM_MAPPING
161 ioaddr = pci_resource_start (pdev, 1);
162 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
163 if (!ioaddr) {
164 err = -ENOMEM;
165 goto err_out_dev;
166 }
167 #else
168 ioaddr = pci_resource_start (pdev, 0);
169 #endif
170 dev->base_addr = ioaddr;
171 dev->irq = irq;
172 np = netdev_priv(dev);
173 np->chip_id = chip_idx;
174 np->pdev = pdev;
175 spin_lock_init (&np->tx_lock);
176 spin_lock_init (&np->rx_lock);
177
178 /* Parse manual configuration */
179 np->an_enable = 1;
180 np->tx_coalesce = 1;
181 if (card_idx < MAX_UNITS) {
182 if (media[card_idx] != NULL) {
183 np->an_enable = 0;
184 if (strcmp (media[card_idx], "auto") == 0 ||
185 strcmp (media[card_idx], "autosense") == 0 ||
186 strcmp (media[card_idx], "0") == 0 ) {
187 np->an_enable = 2;
188 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
189 strcmp (media[card_idx], "4") == 0) {
190 np->speed = 100;
191 np->full_duplex = 1;
192 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
193 || strcmp (media[card_idx], "3") == 0) {
194 np->speed = 100;
195 np->full_duplex = 0;
196 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
197 strcmp (media[card_idx], "2") == 0) {
198 np->speed = 10;
199 np->full_duplex = 1;
200 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
201 strcmp (media[card_idx], "1") == 0) {
202 np->speed = 10;
203 np->full_duplex = 0;
204 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
205 strcmp (media[card_idx], "6") == 0) {
206 np->speed=1000;
207 np->full_duplex=1;
208 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
209 strcmp (media[card_idx], "5") == 0) {
210 np->speed = 1000;
211 np->full_duplex = 0;
212 } else {
213 np->an_enable = 1;
214 }
215 }
216 if (jumbo[card_idx] != 0) {
217 np->jumbo = 1;
218 dev->mtu = MAX_JUMBO;
219 } else {
220 np->jumbo = 0;
221 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
222 dev->mtu = mtu[card_idx];
223 }
224 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
225 vlan[card_idx] : 0;
226 if (rx_coalesce > 0 && rx_timeout > 0) {
227 np->rx_coalesce = rx_coalesce;
228 np->rx_timeout = rx_timeout;
229 np->coalesce = 1;
230 }
231 np->tx_flow = (tx_flow == 0) ? 0 : 1;
232 np->rx_flow = (rx_flow == 0) ? 0 : 1;
233
234 if (tx_coalesce < 1)
235 tx_coalesce = 1;
236 else if (tx_coalesce > TX_RING_SIZE-1)
237 tx_coalesce = TX_RING_SIZE - 1;
238 }
239 dev->open = &rio_open;
240 dev->hard_start_xmit = &start_xmit;
241 dev->stop = &rio_close;
242 dev->get_stats = &get_stats;
243 dev->set_multicast_list = &set_multicast;
244 dev->do_ioctl = &rio_ioctl;
245 dev->tx_timeout = &rio_tx_timeout;
246 dev->watchdog_timeo = TX_TIMEOUT;
247 dev->change_mtu = &change_mtu;
248 SET_ETHTOOL_OPS(dev, &ethtool_ops);
249 #if 0
250 dev->features = NETIF_F_IP_CSUM;
251 #endif
252 pci_set_drvdata (pdev, dev);
253
254 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
255 if (!ring_space)
256 goto err_out_iounmap;
257 np->tx_ring = (struct netdev_desc *) ring_space;
258 np->tx_ring_dma = ring_dma;
259
260 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
261 if (!ring_space)
262 goto err_out_unmap_tx;
263 np->rx_ring = (struct netdev_desc *) ring_space;
264 np->rx_ring_dma = ring_dma;
265
266 /* Parse eeprom data */
267 parse_eeprom (dev);
268
269 /* Find PHY address */
270 err = find_miiphy (dev);
271 if (err)
272 goto err_out_unmap_rx;
273
274 /* Fiber device? */
275 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
276 np->link_status = 0;
277 /* Set media and reset PHY */
278 if (np->phy_media) {
279 /* default Auto-Negotiation for fiber deivices */
280 if (np->an_enable == 2) {
281 np->an_enable = 1;
282 }
283 mii_set_media_pcs (dev);
284 } else {
285 /* Auto-Negotiation is mandatory for 1000BASE-T,
286 IEEE 802.3ab Annex 28D page 14 */
287 if (np->speed == 1000)
288 np->an_enable = 1;
289 mii_set_media (dev);
290 }
291 pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
292
293 err = register_netdev (dev);
294 if (err)
295 goto err_out_unmap_rx;
296
297 card_idx++;
298
299 printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
300 dev->name, np->name,
301 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
302 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
303 if (tx_coalesce > 1)
304 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
305 tx_coalesce);
306 if (np->coalesce)
307 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
308 KERN_INFO "rx_timeout: \t%d ns\n",
309 np->rx_coalesce, np->rx_timeout*640);
310 if (np->vlan)
311 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
312 return 0;
313
314 err_out_unmap_rx:
315 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
316 err_out_unmap_tx:
317 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
318 err_out_iounmap:
319 #ifdef MEM_MAPPING
320 iounmap ((void *) ioaddr);
321
322 err_out_dev:
323 #endif
324 free_netdev (dev);
325
326 err_out_res:
327 pci_release_regions (pdev);
328
329 err_out_disable:
330 pci_disable_device (pdev);
331 return err;
332 }
333
334 int
335 find_miiphy (struct net_device *dev)
336 {
337 int i, phy_found = 0;
338 struct netdev_private *np;
339 long ioaddr;
340 np = netdev_priv(dev);
341 ioaddr = dev->base_addr;
342 np->phy_addr = 1;
343
344 for (i = 31; i >= 0; i--) {
345 int mii_status = mii_read (dev, i, 1);
346 if (mii_status != 0xffff && mii_status != 0x0000) {
347 np->phy_addr = i;
348 phy_found++;
349 }
350 }
351 if (!phy_found) {
352 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
353 return -ENODEV;
354 }
355 return 0;
356 }
357
358 int
359 parse_eeprom (struct net_device *dev)
360 {
361 int i, j;
362 long ioaddr = dev->base_addr;
363 u8 sromdata[256];
364 u8 *psib;
365 u32 crc;
366 PSROM_t psrom = (PSROM_t) sromdata;
367 struct netdev_private *np = netdev_priv(dev);
368
369 int cid, next;
370
371 #ifdef MEM_MAPPING
372 ioaddr = pci_resource_start (np->pdev, 0);
373 #endif
374 /* Read eeprom */
375 for (i = 0; i < 128; i++) {
376 ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
377 }
378 #ifdef MEM_MAPPING
379 ioaddr = dev->base_addr;
380 #endif
381 /* Check CRC */
382 crc = ~ether_crc_le (256 - 4, sromdata);
383 if (psrom->crc != crc) {
384 printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
385 return -1;
386 }
387
388 /* Set MAC address */
389 for (i = 0; i < 6; i++)
390 dev->dev_addr[i] = psrom->mac_addr[i];
391
392 /* Parse Software Infomation Block */
393 i = 0x30;
394 psib = (u8 *) sromdata;
395 do {
396 cid = psib[i++];
397 next = psib[i++];
398 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
399 printk (KERN_ERR "Cell data error\n");
400 return -1;
401 }
402 switch (cid) {
403 case 0: /* Format version */
404 break;
405 case 1: /* End of cell */
406 return 0;
407 case 2: /* Duplex Polarity */
408 np->duplex_polarity = psib[i];
409 writeb (readb (ioaddr + PhyCtrl) | psib[i],
410 ioaddr + PhyCtrl);
411 break;
412 case 3: /* Wake Polarity */
413 np->wake_polarity = psib[i];
414 break;
415 case 9: /* Adapter description */
416 j = (next - i > 255) ? 255 : next - i;
417 memcpy (np->name, &(psib[i]), j);
418 break;
419 case 4:
420 case 5:
421 case 6:
422 case 7:
423 case 8: /* Reversed */
424 break;
425 default: /* Unknown cell */
426 return -1;
427 }
428 i = next;
429 } while (1);
430
431 return 0;
432 }
433
434 static int
435 rio_open (struct net_device *dev)
436 {
437 struct netdev_private *np = netdev_priv(dev);
438 long ioaddr = dev->base_addr;
439 int i;
440 u16 macctrl;
441
442 i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
443 if (i)
444 return i;
445
446 /* Reset all logic functions */
447 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
448 ioaddr + ASICCtrl + 2);
449 mdelay(10);
450
451 /* DebugCtrl bit 4, 5, 9 must set */
452 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
453
454 /* Jumbo frame */
455 if (np->jumbo != 0)
456 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
457
458 alloc_list (dev);
459
460 /* Get station address */
461 for (i = 0; i < 6; i++)
462 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
463
464 set_multicast (dev);
465 if (np->coalesce) {
466 writel (np->rx_coalesce | np->rx_timeout << 16,
467 ioaddr + RxDMAIntCtrl);
468 }
469 /* Set RIO to poll every N*320nsec. */
470 writeb (0x20, ioaddr + RxDMAPollPeriod);
471 writeb (0xff, ioaddr + TxDMAPollPeriod);
472 writeb (0x30, ioaddr + RxDMABurstThresh);
473 writeb (0x30, ioaddr + RxDMAUrgentThresh);
474 writel (0x0007ffff, ioaddr + RmonStatMask);
475 /* clear statistics */
476 clear_stats (dev);
477
478 /* VLAN supported */
479 if (np->vlan) {
480 /* priority field in RxDMAIntCtrl */
481 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
482 ioaddr + RxDMAIntCtrl);
483 /* VLANId */
484 writew (np->vlan, ioaddr + VLANId);
485 /* Length/Type should be 0x8100 */
486 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
487 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
488 VLAN information tagged by TFC' VID, CFI fields. */
489 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
490 ioaddr + MACCtrl);
491 }
492
493 init_timer (&np->timer);
494 np->timer.expires = jiffies + 1*HZ;
495 np->timer.data = (unsigned long) dev;
496 np->timer.function = &rio_timer;
497 add_timer (&np->timer);
498
499 /* Start Tx/Rx */
500 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
501 ioaddr + MACCtrl);
502
503 macctrl = 0;
504 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
505 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
506 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
507 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
508 writew(macctrl, ioaddr + MACCtrl);
509
510 netif_start_queue (dev);
511
512 /* Enable default interrupts */
513 EnableInt ();
514 return 0;
515 }
516
517 static void
518 rio_timer (unsigned long data)
519 {
520 struct net_device *dev = (struct net_device *)data;
521 struct netdev_private *np = netdev_priv(dev);
522 unsigned int entry;
523 int next_tick = 1*HZ;
524 unsigned long flags;
525
526 spin_lock_irqsave(&np->rx_lock, flags);
527 /* Recover rx ring exhausted error */
528 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
529 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
530 /* Re-allocate skbuffs to fill the descriptor ring */
531 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
532 struct sk_buff *skb;
533 entry = np->old_rx % RX_RING_SIZE;
534 /* Dropped packets don't need to re-allocate */
535 if (np->rx_skbuff[entry] == NULL) {
536 skb = dev_alloc_skb (np->rx_buf_sz);
537 if (skb == NULL) {
538 np->rx_ring[entry].fraginfo = 0;
539 printk (KERN_INFO
540 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
541 dev->name, entry);
542 break;
543 }
544 np->rx_skbuff[entry] = skb;
545 skb->dev = dev;
546 /* 16 byte align the IP header */
547 skb_reserve (skb, 2);
548 np->rx_ring[entry].fraginfo =
549 cpu_to_le64 (pci_map_single
550 (np->pdev, skb->data, np->rx_buf_sz,
551 PCI_DMA_FROMDEVICE));
552 }
553 np->rx_ring[entry].fraginfo |=
554 cpu_to_le64 (np->rx_buf_sz) << 48;
555 np->rx_ring[entry].status = 0;
556 } /* end for */
557 } /* end if */
558 spin_unlock_irqrestore (&np->rx_lock, flags);
559 np->timer.expires = jiffies + next_tick;
560 add_timer(&np->timer);
561 }
562
563 static void
564 rio_tx_timeout (struct net_device *dev)
565 {
566 long ioaddr = dev->base_addr;
567
568 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
569 dev->name, readl (ioaddr + TxStatus));
570 rio_free_tx(dev, 0);
571 dev->if_port = 0;
572 dev->trans_start = jiffies;
573 }
574
575 /* allocate and initialize Tx and Rx descriptors */
576 static void
577 alloc_list (struct net_device *dev)
578 {
579 struct netdev_private *np = netdev_priv(dev);
580 int i;
581
582 np->cur_rx = np->cur_tx = 0;
583 np->old_rx = np->old_tx = 0;
584 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
585
586 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
587 for (i = 0; i < TX_RING_SIZE; i++) {
588 np->tx_skbuff[i] = NULL;
589 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
590 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
591 ((i+1)%TX_RING_SIZE) *
592 sizeof (struct netdev_desc));
593 }
594
595 /* Initialize Rx descriptors */
596 for (i = 0; i < RX_RING_SIZE; i++) {
597 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
598 ((i + 1) % RX_RING_SIZE) *
599 sizeof (struct netdev_desc));
600 np->rx_ring[i].status = 0;
601 np->rx_ring[i].fraginfo = 0;
602 np->rx_skbuff[i] = NULL;
603 }
604
605 /* Allocate the rx buffers */
606 for (i = 0; i < RX_RING_SIZE; i++) {
607 /* Allocated fixed size of skbuff */
608 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
609 np->rx_skbuff[i] = skb;
610 if (skb == NULL) {
611 printk (KERN_ERR
612 "%s: alloc_list: allocate Rx buffer error! ",
613 dev->name);
614 break;
615 }
616 skb->dev = dev; /* Mark as being used by this device. */
617 skb_reserve (skb, 2); /* 16 byte align the IP header. */
618 /* Rubicon now supports 40 bits of addressing space. */
619 np->rx_ring[i].fraginfo =
620 cpu_to_le64 ( pci_map_single (
621 np->pdev, skb->data, np->rx_buf_sz,
622 PCI_DMA_FROMDEVICE));
623 np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
624 }
625
626 /* Set RFDListPtr */
627 writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
628 writel (0, dev->base_addr + RFDListPtr1);
629
630 return;
631 }
632
633 static int
634 start_xmit (struct sk_buff *skb, struct net_device *dev)
635 {
636 struct netdev_private *np = netdev_priv(dev);
637 struct netdev_desc *txdesc;
638 unsigned entry;
639 u32 ioaddr;
640 u64 tfc_vlan_tag = 0;
641
642 if (np->link_status == 0) { /* Link Down */
643 dev_kfree_skb(skb);
644 return 0;
645 }
646 ioaddr = dev->base_addr;
647 entry = np->cur_tx % TX_RING_SIZE;
648 np->tx_skbuff[entry] = skb;
649 txdesc = &np->tx_ring[entry];
650
651 #if 0
652 if (skb->ip_summed == CHECKSUM_HW) {
653 txdesc->status |=
654 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
655 IPChecksumEnable);
656 }
657 #endif
658 if (np->vlan) {
659 tfc_vlan_tag =
660 cpu_to_le64 (VLANTagInsert) |
661 (cpu_to_le64 (np->vlan) << 32) |
662 (cpu_to_le64 (skb->priority) << 45);
663 }
664 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
665 skb->len,
666 PCI_DMA_TODEVICE));
667 txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
668
669 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
670 * Work around: Always use 1 descriptor in 10Mbps mode */
671 if (entry % np->tx_coalesce == 0 || np->speed == 10)
672 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
673 WordAlignDisable |
674 TxDMAIndicate |
675 (1 << FragCountShift));
676 else
677 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
678 WordAlignDisable |
679 (1 << FragCountShift));
680
681 /* TxDMAPollNow */
682 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
683 /* Schedule ISR */
684 writel(10000, ioaddr + CountDown);
685 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
686 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
687 < TX_QUEUE_LEN - 1 && np->speed != 10) {
688 /* do nothing */
689 } else if (!netif_queue_stopped(dev)) {
690 netif_stop_queue (dev);
691 }
692
693 /* The first TFDListPtr */
694 if (readl (dev->base_addr + TFDListPtr0) == 0) {
695 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
696 dev->base_addr + TFDListPtr0);
697 writel (0, dev->base_addr + TFDListPtr1);
698 }
699
700 /* NETDEV WATCHDOG timer */
701 dev->trans_start = jiffies;
702 return 0;
703 }
704
705 static irqreturn_t
706 rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
707 {
708 struct net_device *dev = dev_instance;
709 struct netdev_private *np;
710 unsigned int_status;
711 long ioaddr;
712 int cnt = max_intrloop;
713 int handled = 0;
714
715 ioaddr = dev->base_addr;
716 np = netdev_priv(dev);
717 while (1) {
718 int_status = readw (ioaddr + IntStatus);
719 writew (int_status, ioaddr + IntStatus);
720 int_status &= DEFAULT_INTR;
721 if (int_status == 0 || --cnt < 0)
722 break;
723 handled = 1;
724 /* Processing received packets */
725 if (int_status & RxDMAComplete)
726 receive_packet (dev);
727 /* TxDMAComplete interrupt */
728 if ((int_status & (TxDMAComplete|IntRequested))) {
729 int tx_status;
730 tx_status = readl (ioaddr + TxStatus);
731 if (tx_status & 0x01)
732 tx_error (dev, tx_status);
733 /* Free used tx skbuffs */
734 rio_free_tx (dev, 1);
735 }
736
737 /* Handle uncommon events */
738 if (int_status &
739 (HostError | LinkEvent | UpdateStats))
740 rio_error (dev, int_status);
741 }
742 if (np->cur_tx != np->old_tx)
743 writel (100, ioaddr + CountDown);
744 return IRQ_RETVAL(handled);
745 }
746
747 static void
748 rio_free_tx (struct net_device *dev, int irq)
749 {
750 struct netdev_private *np = netdev_priv(dev);
751 int entry = np->old_tx % TX_RING_SIZE;
752 int tx_use = 0;
753 unsigned long flag = 0;
754
755 if (irq)
756 spin_lock(&np->tx_lock);
757 else
758 spin_lock_irqsave(&np->tx_lock, flag);
759
760 /* Free used tx skbuffs */
761 while (entry != np->cur_tx) {
762 struct sk_buff *skb;
763
764 if (!(np->tx_ring[entry].status & TFDDone))
765 break;
766 skb = np->tx_skbuff[entry];
767 pci_unmap_single (np->pdev,
768 np->tx_ring[entry].fraginfo & 0xffffffffffff,
769 skb->len, PCI_DMA_TODEVICE);
770 if (irq)
771 dev_kfree_skb_irq (skb);
772 else
773 dev_kfree_skb (skb);
774
775 np->tx_skbuff[entry] = NULL;
776 entry = (entry + 1) % TX_RING_SIZE;
777 tx_use++;
778 }
779 if (irq)
780 spin_unlock(&np->tx_lock);
781 else
782 spin_unlock_irqrestore(&np->tx_lock, flag);
783 np->old_tx = entry;
784
785 /* If the ring is no longer full, clear tx_full and
786 call netif_wake_queue() */
787
788 if (netif_queue_stopped(dev) &&
789 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
790 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
791 netif_wake_queue (dev);
792 }
793 }
794
795 static void
796 tx_error (struct net_device *dev, int tx_status)
797 {
798 struct netdev_private *np;
799 long ioaddr = dev->base_addr;
800 int frame_id;
801 int i;
802
803 np = netdev_priv(dev);
804
805 frame_id = (tx_status & 0xffff0000);
806 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
807 dev->name, tx_status, frame_id);
808 np->stats.tx_errors++;
809 /* Ttransmit Underrun */
810 if (tx_status & 0x10) {
811 np->stats.tx_fifo_errors++;
812 writew (readw (ioaddr + TxStartThresh) + 0x10,
813 ioaddr + TxStartThresh);
814 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
815 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
816 ioaddr + ASICCtrl + 2);
817 /* Wait for ResetBusy bit clear */
818 for (i = 50; i > 0; i--) {
819 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
820 break;
821 mdelay (1);
822 }
823 rio_free_tx (dev, 1);
824 /* Reset TFDListPtr */
825 writel (np->tx_ring_dma +
826 np->old_tx * sizeof (struct netdev_desc),
827 dev->base_addr + TFDListPtr0);
828 writel (0, dev->base_addr + TFDListPtr1);
829
830 /* Let TxStartThresh stay default value */
831 }
832 /* Late Collision */
833 if (tx_status & 0x04) {
834 np->stats.tx_fifo_errors++;
835 /* TxReset and clear FIFO */
836 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
837 /* Wait reset done */
838 for (i = 50; i > 0; i--) {
839 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
840 break;
841 mdelay (1);
842 }
843 /* Let TxStartThresh stay default value */
844 }
845 /* Maximum Collisions */
846 #ifdef ETHER_STATS
847 if (tx_status & 0x08)
848 np->stats.collisions16++;
849 #else
850 if (tx_status & 0x08)
851 np->stats.collisions++;
852 #endif
853 /* Restart the Tx */
854 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
855 }
856
857 static int
858 receive_packet (struct net_device *dev)
859 {
860 struct netdev_private *np = netdev_priv(dev);
861 int entry = np->cur_rx % RX_RING_SIZE;
862 int cnt = 30;
863
864 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
865 while (1) {
866 struct netdev_desc *desc = &np->rx_ring[entry];
867 int pkt_len;
868 u64 frame_status;
869
870 if (!(desc->status & RFDDone) ||
871 !(desc->status & FrameStart) || !(desc->status & FrameEnd))
872 break;
873
874 /* Chip omits the CRC. */
875 pkt_len = le64_to_cpu (desc->status & 0xffff);
876 frame_status = le64_to_cpu (desc->status);
877 if (--cnt < 0)
878 break;
879 /* Update rx error statistics, drop packet. */
880 if (frame_status & RFS_Errors) {
881 np->stats.rx_errors++;
882 if (frame_status & (RxRuntFrame | RxLengthError))
883 np->stats.rx_length_errors++;
884 if (frame_status & RxFCSError)
885 np->stats.rx_crc_errors++;
886 if (frame_status & RxAlignmentError && np->speed != 1000)
887 np->stats.rx_frame_errors++;
888 if (frame_status & RxFIFOOverrun)
889 np->stats.rx_fifo_errors++;
890 } else {
891 struct sk_buff *skb;
892
893 /* Small skbuffs for short packets */
894 if (pkt_len > copy_thresh) {
895 pci_unmap_single (np->pdev,
896 desc->fraginfo & 0xffffffffffff,
897 np->rx_buf_sz,
898 PCI_DMA_FROMDEVICE);
899 skb_put (skb = np->rx_skbuff[entry], pkt_len);
900 np->rx_skbuff[entry] = NULL;
901 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
902 pci_dma_sync_single_for_cpu(np->pdev,
903 desc->fraginfo &
904 0xffffffffffff,
905 np->rx_buf_sz,
906 PCI_DMA_FROMDEVICE);
907 skb->dev = dev;
908 /* 16 byte align the IP header */
909 skb_reserve (skb, 2);
910 eth_copy_and_sum (skb,
911 np->rx_skbuff[entry]->data,
912 pkt_len, 0);
913 skb_put (skb, pkt_len);
914 pci_dma_sync_single_for_device(np->pdev,
915 desc->fraginfo &
916 0xffffffffffff,
917 np->rx_buf_sz,
918 PCI_DMA_FROMDEVICE);
919 }
920 skb->protocol = eth_type_trans (skb, dev);
921 #if 0
922 /* Checksum done by hw, but csum value unavailable. */
923 if (np->pci_rev_id >= 0x0c &&
924 !(frame_status & (TCPError | UDPError | IPError))) {
925 skb->ip_summed = CHECKSUM_UNNECESSARY;
926 }
927 #endif
928 netif_rx (skb);
929 dev->last_rx = jiffies;
930 }
931 entry = (entry + 1) % RX_RING_SIZE;
932 }
933 spin_lock(&np->rx_lock);
934 np->cur_rx = entry;
935 /* Re-allocate skbuffs to fill the descriptor ring */
936 entry = np->old_rx;
937 while (entry != np->cur_rx) {
938 struct sk_buff *skb;
939 /* Dropped packets don't need to re-allocate */
940 if (np->rx_skbuff[entry] == NULL) {
941 skb = dev_alloc_skb (np->rx_buf_sz);
942 if (skb == NULL) {
943 np->rx_ring[entry].fraginfo = 0;
944 printk (KERN_INFO
945 "%s: receive_packet: "
946 "Unable to re-allocate Rx skbuff.#%d\n",
947 dev->name, entry);
948 break;
949 }
950 np->rx_skbuff[entry] = skb;
951 skb->dev = dev;
952 /* 16 byte align the IP header */
953 skb_reserve (skb, 2);
954 np->rx_ring[entry].fraginfo =
955 cpu_to_le64 (pci_map_single
956 (np->pdev, skb->data, np->rx_buf_sz,
957 PCI_DMA_FROMDEVICE));
958 }
959 np->rx_ring[entry].fraginfo |=
960 cpu_to_le64 (np->rx_buf_sz) << 48;
961 np->rx_ring[entry].status = 0;
962 entry = (entry + 1) % RX_RING_SIZE;
963 }
964 np->old_rx = entry;
965 spin_unlock(&np->rx_lock);
966 return 0;
967 }
968
969 static void
970 rio_error (struct net_device *dev, int int_status)
971 {
972 long ioaddr = dev->base_addr;
973 struct netdev_private *np = netdev_priv(dev);
974 u16 macctrl;
975
976 /* Link change event */
977 if (int_status & LinkEvent) {
978 if (mii_wait_link (dev, 10) == 0) {
979 printk (KERN_INFO "%s: Link up\n", dev->name);
980 if (np->phy_media)
981 mii_get_media_pcs (dev);
982 else
983 mii_get_media (dev);
984 if (np->speed == 1000)
985 np->tx_coalesce = tx_coalesce;
986 else
987 np->tx_coalesce = 1;
988 macctrl = 0;
989 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
990 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
991 macctrl |= (np->tx_flow) ?
992 TxFlowControlEnable : 0;
993 macctrl |= (np->rx_flow) ?
994 RxFlowControlEnable : 0;
995 writew(macctrl, ioaddr + MACCtrl);
996 np->link_status = 1;
997 netif_carrier_on(dev);
998 } else {
999 printk (KERN_INFO "%s: Link off\n", dev->name);
1000 np->link_status = 0;
1001 netif_carrier_off(dev);
1002 }
1003 }
1004
1005 /* UpdateStats statistics registers */
1006 if (int_status & UpdateStats) {
1007 get_stats (dev);
1008 }
1009
1010 /* PCI Error, a catastronphic error related to the bus interface
1011 occurs, set GlobalReset and HostReset to reset. */
1012 if (int_status & HostError) {
1013 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1014 dev->name, int_status);
1015 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
1016 mdelay (500);
1017 }
1018 }
1019
1020 static struct net_device_stats *
1021 get_stats (struct net_device *dev)
1022 {
1023 long ioaddr = dev->base_addr;
1024 struct netdev_private *np = netdev_priv(dev);
1025 #ifdef MEM_MAPPING
1026 int i;
1027 #endif
1028 unsigned int stat_reg;
1029
1030 /* All statistics registers need to be acknowledged,
1031 else statistic overflow could cause problems */
1032
1033 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1034 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1035 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1036 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1037
1038 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1039 np->stats.collisions += readl (ioaddr + SingleColFrames)
1040 + readl (ioaddr + MultiColFrames);
1041
1042 /* detailed tx errors */
1043 stat_reg = readw (ioaddr + FramesAbortXSColls);
1044 np->stats.tx_aborted_errors += stat_reg;
1045 np->stats.tx_errors += stat_reg;
1046
1047 stat_reg = readw (ioaddr + CarrierSenseErrors);
1048 np->stats.tx_carrier_errors += stat_reg;
1049 np->stats.tx_errors += stat_reg;
1050
1051 /* Clear all other statistic register. */
1052 readl (ioaddr + McstOctetXmtOk);
1053 readw (ioaddr + BcstFramesXmtdOk);
1054 readl (ioaddr + McstFramesXmtdOk);
1055 readw (ioaddr + BcstFramesRcvdOk);
1056 readw (ioaddr + MacControlFramesRcvd);
1057 readw (ioaddr + FrameTooLongErrors);
1058 readw (ioaddr + InRangeLengthErrors);
1059 readw (ioaddr + FramesCheckSeqErrors);
1060 readw (ioaddr + FramesLostRxErrors);
1061 readl (ioaddr + McstOctetXmtOk);
1062 readl (ioaddr + BcstOctetXmtOk);
1063 readl (ioaddr + McstFramesXmtdOk);
1064 readl (ioaddr + FramesWDeferredXmt);
1065 readl (ioaddr + LateCollisions);
1066 readw (ioaddr + BcstFramesXmtdOk);
1067 readw (ioaddr + MacControlFramesXmtd);
1068 readw (ioaddr + FramesWEXDeferal);
1069
1070 #ifdef MEM_MAPPING
1071 for (i = 0x100; i <= 0x150; i += 4)
1072 readl (ioaddr + i);
1073 #endif
1074 readw (ioaddr + TxJumboFrames);
1075 readw (ioaddr + RxJumboFrames);
1076 readw (ioaddr + TCPCheckSumErrors);
1077 readw (ioaddr + UDPCheckSumErrors);
1078 readw (ioaddr + IPCheckSumErrors);
1079 return &np->stats;
1080 }
1081
1082 static int
1083 clear_stats (struct net_device *dev)
1084 {
1085 long ioaddr = dev->base_addr;
1086 #ifdef MEM_MAPPING
1087 int i;
1088 #endif
1089
1090 /* All statistics registers need to be acknowledged,
1091 else statistic overflow could cause problems */
1092 readl (ioaddr + FramesRcvOk);
1093 readl (ioaddr + FramesXmtOk);
1094 readl (ioaddr + OctetRcvOk);
1095 readl (ioaddr + OctetXmtOk);
1096
1097 readl (ioaddr + McstFramesRcvdOk);
1098 readl (ioaddr + SingleColFrames);
1099 readl (ioaddr + MultiColFrames);
1100 readl (ioaddr + LateCollisions);
1101 /* detailed rx errors */
1102 readw (ioaddr + FrameTooLongErrors);
1103 readw (ioaddr + InRangeLengthErrors);
1104 readw (ioaddr + FramesCheckSeqErrors);
1105 readw (ioaddr + FramesLostRxErrors);
1106
1107 /* detailed tx errors */
1108 readw (ioaddr + FramesAbortXSColls);
1109 readw (ioaddr + CarrierSenseErrors);
1110
1111 /* Clear all other statistic register. */
1112 readl (ioaddr + McstOctetXmtOk);
1113 readw (ioaddr + BcstFramesXmtdOk);
1114 readl (ioaddr + McstFramesXmtdOk);
1115 readw (ioaddr + BcstFramesRcvdOk);
1116 readw (ioaddr + MacControlFramesRcvd);
1117 readl (ioaddr + McstOctetXmtOk);
1118 readl (ioaddr + BcstOctetXmtOk);
1119 readl (ioaddr + McstFramesXmtdOk);
1120 readl (ioaddr + FramesWDeferredXmt);
1121 readw (ioaddr + BcstFramesXmtdOk);
1122 readw (ioaddr + MacControlFramesXmtd);
1123 readw (ioaddr + FramesWEXDeferal);
1124 #ifdef MEM_MAPPING
1125 for (i = 0x100; i <= 0x150; i += 4)
1126 readl (ioaddr + i);
1127 #endif
1128 readw (ioaddr + TxJumboFrames);
1129 readw (ioaddr + RxJumboFrames);
1130 readw (ioaddr + TCPCheckSumErrors);
1131 readw (ioaddr + UDPCheckSumErrors);
1132 readw (ioaddr + IPCheckSumErrors);
1133 return 0;
1134 }
1135
1136
1137 int
1138 change_mtu (struct net_device *dev, int new_mtu)
1139 {
1140 struct netdev_private *np = netdev_priv(dev);
1141 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1142
1143 if ((new_mtu < 68) || (new_mtu > max)) {
1144 return -EINVAL;
1145 }
1146
1147 dev->mtu = new_mtu;
1148
1149 return 0;
1150 }
1151
1152 static void
1153 set_multicast (struct net_device *dev)
1154 {
1155 long ioaddr = dev->base_addr;
1156 u32 hash_table[2];
1157 u16 rx_mode = 0;
1158 struct netdev_private *np = netdev_priv(dev);
1159
1160 hash_table[0] = hash_table[1] = 0;
1161 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1162 hash_table[1] |= cpu_to_le32(0x02000000);
1163 if (dev->flags & IFF_PROMISC) {
1164 /* Receive all frames promiscuously. */
1165 rx_mode = ReceiveAllFrames;
1166 } else if ((dev->flags & IFF_ALLMULTI) ||
1167 (dev->mc_count > multicast_filter_limit)) {
1168 /* Receive broadcast and multicast frames */
1169 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1170 } else if (dev->mc_count > 0) {
1171 int i;
1172 struct dev_mc_list *mclist;
1173 /* Receive broadcast frames and multicast frames filtering
1174 by Hashtable */
1175 rx_mode =
1176 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1177 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1178 i++, mclist=mclist->next)
1179 {
1180 int bit, index = 0;
1181 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1182 /* The inverted high significant 6 bits of CRC are
1183 used as an index to hashtable */
1184 for (bit = 0; bit < 6; bit++)
1185 if (crc & (1 << (31 - bit)))
1186 index |= (1 << bit);
1187 hash_table[index / 32] |= (1 << (index % 32));
1188 }
1189 } else {
1190 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1191 }
1192 if (np->vlan) {
1193 /* ReceiveVLANMatch field in ReceiveMode */
1194 rx_mode |= ReceiveVLANMatch;
1195 }
1196
1197 writel (hash_table[0], ioaddr + HashTable0);
1198 writel (hash_table[1], ioaddr + HashTable1);
1199 writew (rx_mode, ioaddr + ReceiveMode);
1200 }
1201
1202 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1203 {
1204 struct netdev_private *np = netdev_priv(dev);
1205 strcpy(info->driver, "dl2k");
1206 strcpy(info->version, DRV_VERSION);
1207 strcpy(info->bus_info, pci_name(np->pdev));
1208 }
1209
1210 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1211 {
1212 struct netdev_private *np = netdev_priv(dev);
1213 if (np->phy_media) {
1214 /* fiber device */
1215 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1216 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1217 cmd->port = PORT_FIBRE;
1218 cmd->transceiver = XCVR_INTERNAL;
1219 } else {
1220 /* copper device */
1221 cmd->supported = SUPPORTED_10baseT_Half |
1222 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1223 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1224 SUPPORTED_Autoneg | SUPPORTED_MII;
1225 cmd->advertising = ADVERTISED_10baseT_Half |
1226 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1227 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1228 ADVERTISED_Autoneg | ADVERTISED_MII;
1229 cmd->port = PORT_MII;
1230 cmd->transceiver = XCVR_INTERNAL;
1231 }
1232 if ( np->link_status ) {
1233 cmd->speed = np->speed;
1234 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1235 } else {
1236 cmd->speed = -1;
1237 cmd->duplex = -1;
1238 }
1239 if ( np->an_enable)
1240 cmd->autoneg = AUTONEG_ENABLE;
1241 else
1242 cmd->autoneg = AUTONEG_DISABLE;
1243
1244 cmd->phy_address = np->phy_addr;
1245 return 0;
1246 }
1247
1248 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1249 {
1250 struct netdev_private *np = netdev_priv(dev);
1251 netif_carrier_off(dev);
1252 if (cmd->autoneg == AUTONEG_ENABLE) {
1253 if (np->an_enable)
1254 return 0;
1255 else {
1256 np->an_enable = 1;
1257 mii_set_media(dev);
1258 return 0;
1259 }
1260 } else {
1261 np->an_enable = 0;
1262 if (np->speed == 1000) {
1263 cmd->speed = SPEED_100;
1264 cmd->duplex = DUPLEX_FULL;
1265 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1266 }
1267 switch(cmd->speed + cmd->duplex) {
1268
1269 case SPEED_10 + DUPLEX_HALF:
1270 np->speed = 10;
1271 np->full_duplex = 0;
1272 break;
1273
1274 case SPEED_10 + DUPLEX_FULL:
1275 np->speed = 10;
1276 np->full_duplex = 1;
1277 break;
1278 case SPEED_100 + DUPLEX_HALF:
1279 np->speed = 100;
1280 np->full_duplex = 0;
1281 break;
1282 case SPEED_100 + DUPLEX_FULL:
1283 np->speed = 100;
1284 np->full_duplex = 1;
1285 break;
1286 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1287 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1288 default:
1289 return -EINVAL;
1290 }
1291 mii_set_media(dev);
1292 }
1293 return 0;
1294 }
1295
1296 static u32 rio_get_link(struct net_device *dev)
1297 {
1298 struct netdev_private *np = netdev_priv(dev);
1299 return np->link_status;
1300 }
1301
1302 static struct ethtool_ops ethtool_ops = {
1303 .get_drvinfo = rio_get_drvinfo,
1304 .get_settings = rio_get_settings,
1305 .set_settings = rio_set_settings,
1306 .get_link = rio_get_link,
1307 };
1308
1309 static int
1310 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1311 {
1312 int phy_addr;
1313 struct netdev_private *np = netdev_priv(dev);
1314 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1315
1316 struct netdev_desc *desc;
1317 int i;
1318
1319 phy_addr = np->phy_addr;
1320 switch (cmd) {
1321 case SIOCDEVPRIVATE:
1322 break;
1323
1324 case SIOCDEVPRIVATE + 1:
1325 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1326 break;
1327 case SIOCDEVPRIVATE + 2:
1328 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1329 break;
1330 case SIOCDEVPRIVATE + 3:
1331 break;
1332 case SIOCDEVPRIVATE + 4:
1333 break;
1334 case SIOCDEVPRIVATE + 5:
1335 netif_stop_queue (dev);
1336 break;
1337 case SIOCDEVPRIVATE + 6:
1338 netif_wake_queue (dev);
1339 break;
1340 case SIOCDEVPRIVATE + 7:
1341 printk
1342 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1343 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1344 np->old_rx);
1345 break;
1346 case SIOCDEVPRIVATE + 8:
1347 printk("TX ring:\n");
1348 for (i = 0; i < TX_RING_SIZE; i++) {
1349 desc = &np->tx_ring[i];
1350 printk
1351 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1352 i,
1353 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1354 (u32) desc->next_desc,
1355 (u32) desc->status, (u32) (desc->fraginfo >> 32),
1356 (u32) desc->fraginfo);
1357 printk ("\n");
1358 }
1359 printk ("\n");
1360 break;
1361
1362 default:
1363 return -EOPNOTSUPP;
1364 }
1365 return 0;
1366 }
1367
1368 #define EEP_READ 0x0200
1369 #define EEP_BUSY 0x8000
1370 /* Read the EEPROM word */
1371 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1372 int
1373 read_eeprom (long ioaddr, int eep_addr)
1374 {
1375 int i = 1000;
1376 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1377 while (i-- > 0) {
1378 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1379 return inw (ioaddr + EepromData);
1380 }
1381 }
1382 return 0;
1383 }
1384
1385 enum phy_ctrl_bits {
1386 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1387 MII_DUPLEX = 0x08,
1388 };
1389
1390 #define mii_delay() readb(ioaddr)
1391 static void
1392 mii_sendbit (struct net_device *dev, u32 data)
1393 {
1394 long ioaddr = dev->base_addr + PhyCtrl;
1395 data = (data) ? MII_DATA1 : 0;
1396 data |= MII_WRITE;
1397 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1398 writeb (data, ioaddr);
1399 mii_delay ();
1400 writeb (data | MII_CLK, ioaddr);
1401 mii_delay ();
1402 }
1403
1404 static int
1405 mii_getbit (struct net_device *dev)
1406 {
1407 long ioaddr = dev->base_addr + PhyCtrl;
1408 u8 data;
1409
1410 data = (readb (ioaddr) & 0xf8) | MII_READ;
1411 writeb (data, ioaddr);
1412 mii_delay ();
1413 writeb (data | MII_CLK, ioaddr);
1414 mii_delay ();
1415 return ((readb (ioaddr) >> 1) & 1);
1416 }
1417
1418 static void
1419 mii_send_bits (struct net_device *dev, u32 data, int len)
1420 {
1421 int i;
1422 for (i = len - 1; i >= 0; i--) {
1423 mii_sendbit (dev, data & (1 << i));
1424 }
1425 }
1426
1427 static int
1428 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1429 {
1430 u32 cmd;
1431 int i;
1432 u32 retval = 0;
1433
1434 /* Preamble */
1435 mii_send_bits (dev, 0xffffffff, 32);
1436 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1437 /* ST,OP = 0110'b for read operation */
1438 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1439 mii_send_bits (dev, cmd, 14);
1440 /* Turnaround */
1441 if (mii_getbit (dev))
1442 goto err_out;
1443 /* Read data */
1444 for (i = 0; i < 16; i++) {
1445 retval |= mii_getbit (dev);
1446 retval <<= 1;
1447 }
1448 /* End cycle */
1449 mii_getbit (dev);
1450 return (retval >> 1) & 0xffff;
1451
1452 err_out:
1453 return 0;
1454 }
1455 static int
1456 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1457 {
1458 u32 cmd;
1459
1460 /* Preamble */
1461 mii_send_bits (dev, 0xffffffff, 32);
1462 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1463 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1464 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1465 mii_send_bits (dev, cmd, 32);
1466 /* End cycle */
1467 mii_getbit (dev);
1468 return 0;
1469 }
1470 static int
1471 mii_wait_link (struct net_device *dev, int wait)
1472 {
1473 BMSR_t bmsr;
1474 int phy_addr;
1475 struct netdev_private *np;
1476
1477 np = netdev_priv(dev);
1478 phy_addr = np->phy_addr;
1479
1480 do {
1481 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1482 if (bmsr.bits.link_status)
1483 return 0;
1484 mdelay (1);
1485 } while (--wait > 0);
1486 return -1;
1487 }
1488 static int
1489 mii_get_media (struct net_device *dev)
1490 {
1491 ANAR_t negotiate;
1492 BMSR_t bmsr;
1493 BMCR_t bmcr;
1494 MSCR_t mscr;
1495 MSSR_t mssr;
1496 int phy_addr;
1497 struct netdev_private *np;
1498
1499 np = netdev_priv(dev);
1500 phy_addr = np->phy_addr;
1501
1502 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1503 if (np->an_enable) {
1504 if (!bmsr.bits.an_complete) {
1505 /* Auto-Negotiation not completed */
1506 return -1;
1507 }
1508 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
1509 mii_read (dev, phy_addr, MII_ANLPAR);
1510 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1511 mssr.image = mii_read (dev, phy_addr, MII_MSSR);
1512 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
1513 np->speed = 1000;
1514 np->full_duplex = 1;
1515 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1516 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
1517 np->speed = 1000;
1518 np->full_duplex = 0;
1519 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1520 } else if (negotiate.bits.media_100BX_FD) {
1521 np->speed = 100;
1522 np->full_duplex = 1;
1523 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1524 } else if (negotiate.bits.media_100BX_HD) {
1525 np->speed = 100;
1526 np->full_duplex = 0;
1527 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1528 } else if (negotiate.bits.media_10BT_FD) {
1529 np->speed = 10;
1530 np->full_duplex = 1;
1531 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1532 } else if (negotiate.bits.media_10BT_HD) {
1533 np->speed = 10;
1534 np->full_duplex = 0;
1535 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1536 }
1537 if (negotiate.bits.pause) {
1538 np->tx_flow &= 1;
1539 np->rx_flow &= 1;
1540 } else if (negotiate.bits.asymmetric) {
1541 np->tx_flow = 0;
1542 np->rx_flow &= 1;
1543 }
1544 /* else tx_flow, rx_flow = user select */
1545 } else {
1546 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1547 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
1548 printk (KERN_INFO "Operating at 100 Mbps, ");
1549 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
1550 printk (KERN_INFO "Operating at 10 Mbps, ");
1551 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1552 printk (KERN_INFO "Operating at 1000 Mbps, ");
1553 }
1554 if (bmcr.bits.duplex_mode) {
1555 printk ("Full duplex\n");
1556 } else {
1557 printk ("Half duplex\n");
1558 }
1559 }
1560 if (np->tx_flow)
1561 printk(KERN_INFO "Enable Tx Flow Control\n");
1562 else
1563 printk(KERN_INFO "Disable Tx Flow Control\n");
1564 if (np->rx_flow)
1565 printk(KERN_INFO "Enable Rx Flow Control\n");
1566 else
1567 printk(KERN_INFO "Disable Rx Flow Control\n");
1568
1569 return 0;
1570 }
1571
1572 static int
1573 mii_set_media (struct net_device *dev)
1574 {
1575 PHY_SCR_t pscr;
1576 BMCR_t bmcr;
1577 BMSR_t bmsr;
1578 ANAR_t anar;
1579 int phy_addr;
1580 struct netdev_private *np;
1581 np = netdev_priv(dev);
1582 phy_addr = np->phy_addr;
1583
1584 /* Does user set speed? */
1585 if (np->an_enable) {
1586 /* Advertise capabilities */
1587 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1588 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1589 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
1590 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
1591 anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
1592 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
1593 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
1594 anar.bits.pause = 1;
1595 anar.bits.asymmetric = 1;
1596 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1597
1598 /* Enable Auto crossover */
1599 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1600 pscr.bits.mdi_crossover_mode = 3; /* 11'b */
1601 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1602
1603 /* Soft reset PHY */
1604 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1605 bmcr.image = 0;
1606 bmcr.bits.an_enable = 1;
1607 bmcr.bits.restart_an = 1;
1608 bmcr.bits.reset = 1;
1609 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1610 mdelay(1);
1611 } else {
1612 /* Force speed setting */
1613 /* 1) Disable Auto crossover */
1614 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1615 pscr.bits.mdi_crossover_mode = 0;
1616 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1617
1618 /* 2) PHY Reset */
1619 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1620 bmcr.bits.reset = 1;
1621 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1622
1623 /* 3) Power Down */
1624 bmcr.image = 0x1940; /* must be 0x1940 */
1625 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1626 mdelay (100); /* wait a certain time */
1627
1628 /* 4) Advertise nothing */
1629 mii_write (dev, phy_addr, MII_ANAR, 0);
1630
1631 /* 5) Set media and Power Up */
1632 bmcr.image = 0;
1633 bmcr.bits.power_down = 1;
1634 if (np->speed == 100) {
1635 bmcr.bits.speed100 = 1;
1636 bmcr.bits.speed1000 = 0;
1637 printk (KERN_INFO "Manual 100 Mbps, ");
1638 } else if (np->speed == 10) {
1639 bmcr.bits.speed100 = 0;
1640 bmcr.bits.speed1000 = 0;
1641 printk (KERN_INFO "Manual 10 Mbps, ");
1642 }
1643 if (np->full_duplex) {
1644 bmcr.bits.duplex_mode = 1;
1645 printk ("Full duplex\n");
1646 } else {
1647 bmcr.bits.duplex_mode = 0;
1648 printk ("Half duplex\n");
1649 }
1650 #if 0
1651 /* Set 1000BaseT Master/Slave setting */
1652 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1653 mscr.bits.cfg_enable = 1;
1654 mscr.bits.cfg_value = 0;
1655 #endif
1656 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1657 mdelay(10);
1658 }
1659 return 0;
1660 }
1661
1662 static int
1663 mii_get_media_pcs (struct net_device *dev)
1664 {
1665 ANAR_PCS_t negotiate;
1666 BMSR_t bmsr;
1667 BMCR_t bmcr;
1668 int phy_addr;
1669 struct netdev_private *np;
1670
1671 np = netdev_priv(dev);
1672 phy_addr = np->phy_addr;
1673
1674 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
1675 if (np->an_enable) {
1676 if (!bmsr.bits.an_complete) {
1677 /* Auto-Negotiation not completed */
1678 return -1;
1679 }
1680 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
1681 mii_read (dev, phy_addr, PCS_ANLPAR);
1682 np->speed = 1000;
1683 if (negotiate.bits.full_duplex) {
1684 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1685 np->full_duplex = 1;
1686 } else {
1687 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1688 np->full_duplex = 0;
1689 }
1690 if (negotiate.bits.pause) {
1691 np->tx_flow &= 1;
1692 np->rx_flow &= 1;
1693 } else if (negotiate.bits.asymmetric) {
1694 np->tx_flow = 0;
1695 np->rx_flow &= 1;
1696 }
1697 /* else tx_flow, rx_flow = user select */
1698 } else {
1699 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
1700 printk (KERN_INFO "Operating at 1000 Mbps, ");
1701 if (bmcr.bits.duplex_mode) {
1702 printk ("Full duplex\n");
1703 } else {
1704 printk ("Half duplex\n");
1705 }
1706 }
1707 if (np->tx_flow)
1708 printk(KERN_INFO "Enable Tx Flow Control\n");
1709 else
1710 printk(KERN_INFO "Disable Tx Flow Control\n");
1711 if (np->rx_flow)
1712 printk(KERN_INFO "Enable Rx Flow Control\n");
1713 else
1714 printk(KERN_INFO "Disable Rx Flow Control\n");
1715
1716 return 0;
1717 }
1718
1719 static int
1720 mii_set_media_pcs (struct net_device *dev)
1721 {
1722 BMCR_t bmcr;
1723 ESR_t esr;
1724 ANAR_PCS_t anar;
1725 int phy_addr;
1726 struct netdev_private *np;
1727 np = netdev_priv(dev);
1728 phy_addr = np->phy_addr;
1729
1730 /* Auto-Negotiation? */
1731 if (np->an_enable) {
1732 /* Advertise capabilities */
1733 esr.image = mii_read (dev, phy_addr, PCS_ESR);
1734 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1735 anar.bits.half_duplex =
1736 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
1737 anar.bits.full_duplex =
1738 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
1739 anar.bits.pause = 1;
1740 anar.bits.asymmetric = 1;
1741 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1742
1743 /* Soft reset PHY */
1744 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1745 bmcr.image = 0;
1746 bmcr.bits.an_enable = 1;
1747 bmcr.bits.restart_an = 1;
1748 bmcr.bits.reset = 1;
1749 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1750 mdelay(1);
1751 } else {
1752 /* Force speed setting */
1753 /* PHY Reset */
1754 bmcr.image = 0;
1755 bmcr.bits.reset = 1;
1756 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1757 mdelay(10);
1758 bmcr.image = 0;
1759 bmcr.bits.an_enable = 0;
1760 if (np->full_duplex) {
1761 bmcr.bits.duplex_mode = 1;
1762 printk (KERN_INFO "Manual full duplex\n");
1763 } else {
1764 bmcr.bits.duplex_mode = 0;
1765 printk (KERN_INFO "Manual half duplex\n");
1766 }
1767 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1768 mdelay(10);
1769
1770 /* Advertise nothing */
1771 mii_write (dev, phy_addr, MII_ANAR, 0);
1772 }
1773 return 0;
1774 }
1775
1776
1777 static int
1778 rio_close (struct net_device *dev)
1779 {
1780 long ioaddr = dev->base_addr;
1781 struct netdev_private *np = netdev_priv(dev);
1782 struct sk_buff *skb;
1783 int i;
1784
1785 netif_stop_queue (dev);
1786
1787 /* Disable interrupts */
1788 writew (0, ioaddr + IntEnable);
1789
1790 /* Stop Tx and Rx logics */
1791 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1792 synchronize_irq (dev->irq);
1793 free_irq (dev->irq, dev);
1794 del_timer_sync (&np->timer);
1795
1796 /* Free all the skbuffs in the queue. */
1797 for (i = 0; i < RX_RING_SIZE; i++) {
1798 np->rx_ring[i].status = 0;
1799 np->rx_ring[i].fraginfo = 0;
1800 skb = np->rx_skbuff[i];
1801 if (skb) {
1802 pci_unmap_single(np->pdev,
1803 np->rx_ring[i].fraginfo & 0xffffffffffff,
1804 skb->len, PCI_DMA_FROMDEVICE);
1805 dev_kfree_skb (skb);
1806 np->rx_skbuff[i] = NULL;
1807 }
1808 }
1809 for (i = 0; i < TX_RING_SIZE; i++) {
1810 skb = np->tx_skbuff[i];
1811 if (skb) {
1812 pci_unmap_single(np->pdev,
1813 np->tx_ring[i].fraginfo & 0xffffffffffff,
1814 skb->len, PCI_DMA_TODEVICE);
1815 dev_kfree_skb (skb);
1816 np->tx_skbuff[i] = NULL;
1817 }
1818 }
1819
1820 return 0;
1821 }
1822
1823 static void __devexit
1824 rio_remove1 (struct pci_dev *pdev)
1825 {
1826 struct net_device *dev = pci_get_drvdata (pdev);
1827
1828 if (dev) {
1829 struct netdev_private *np = netdev_priv(dev);
1830
1831 unregister_netdev (dev);
1832 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1833 np->rx_ring_dma);
1834 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1835 np->tx_ring_dma);
1836 #ifdef MEM_MAPPING
1837 iounmap ((char *) (dev->base_addr));
1838 #endif
1839 free_netdev (dev);
1840 pci_release_regions (pdev);
1841 pci_disable_device (pdev);
1842 }
1843 pci_set_drvdata (pdev, NULL);
1844 }
1845
1846 static struct pci_driver rio_driver = {
1847 .name = "dl2k",
1848 .id_table = rio_pci_tbl,
1849 .probe = rio_probe1,
1850 .remove = __devexit_p(rio_remove1),
1851 };
1852
1853 static int __init
1854 rio_init (void)
1855 {
1856 return pci_module_init (&rio_driver);
1857 }
1858
1859 static void __exit
1860 rio_exit (void)
1861 {
1862 pci_unregister_driver (&rio_driver);
1863 }
1864
1865 module_init (rio_init);
1866 module_exit (rio_exit);
1867
1868 /*
1869
1870 Compile command:
1871
1872 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1873
1874 Read Documentation/networking/dl2k.txt for details.
1875
1876 */
1877
Linux kernel - Deliverables
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