drivers/net/dl2k.h

   1 /*  D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
   2 /*
   3     Copyright (c) 2001, 2002 by D-Link Corporation
   4     Written by Edward Peng.<edward_peng@dlink.com.tw>
   5     Created 03-May-2001, base on Linux' sundance.c.
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11 */
  12
  13 #ifndef __DL2K_H__
  14 #define __DL2K_H__
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/string.h>
  19 #include <linux/timer.h>
  20 #include <linux/errno.h>
  21 #include <linux/ioport.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/pci.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/init.h>
  29 #include <linux/crc32.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/bitops.h>
  32 #include <asm/processor.h>      /* Processor type for cache alignment. */
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35 #include <linux/delay.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/time.h>
  38 #define TX_RING_SIZE    256
  39 #define TX_QUEUE_LEN    (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
  40 #define RX_RING_SIZE    256
  41 #define TX_TOTAL_SIZE   TX_RING_SIZE*sizeof(struct netdev_desc)
  42 #define RX_TOTAL_SIZE   RX_RING_SIZE*sizeof(struct netdev_desc)
  43
  44 /* This driver was written to use PCI memory space, however x86-oriented
  45    hardware often uses I/O space accesses. */
  46 #ifndef MEM_MAPPING
  47 #undef readb
  48 #undef readw
  49 #undef readl
  50 #undef writeb
  51 #undef writew
  52 #undef writel
  53 #define readb inb
  54 #define readw inw
  55 #define readl inl
  56 #define writeb outb
  57 #define writew outw
  58 #define writel outl
  59 #endif
  60
  61 /* Offsets to the device registers.
  62    Unlike software-only systems, device drivers interact with complex hardware.
  63    It's not useful to define symbolic names for every register bit in the
  64    device.  The name can only partially document the semantics and make
  65    the driver longer and more difficult to read.
  66    In general, only the important configuration values or bits changed
  67    multiple times should be defined symbolically.
  68 */
  69 enum dl2x_offsets {
  70         /* I/O register offsets */
  71         DMACtrl = 0x00,
  72         RxDMAStatus = 0x08,
  73         TFDListPtr0 = 0x10,
  74         TFDListPtr1 = 0x14,
  75         TxDMABurstThresh = 0x18,
  76         TxDMAUrgentThresh = 0x19,
  77         TxDMAPollPeriod = 0x1a,
  78         RFDListPtr0 = 0x1c,
  79         RFDListPtr1 = 0x20,
  80         RxDMABurstThresh = 0x24,
  81         RxDMAUrgentThresh = 0x25,
  82         RxDMAPollPeriod = 0x26,
  83         RxDMAIntCtrl = 0x28,
  84         DebugCtrl = 0x2c,
  85         ASICCtrl = 0x30,
  86         FifoCtrl = 0x38,
  87         RxEarlyThresh = 0x3a,
  88         FlowOffThresh = 0x3c,
  89         FlowOnThresh = 0x3e,
  90         TxStartThresh = 0x44,
  91         EepromData = 0x48,
  92         EepromCtrl = 0x4a,
  93         ExpromAddr = 0x4c,
  94         Exprodata = 0x50,
  95         WakeEvent = 0x51,
  96         CountDown = 0x54,
  97         IntStatusAck = 0x5a,
  98         IntEnable = 0x5c,
  99         IntStatus = 0x5e,
 100         TxStatus = 0x60,
 101         MACCtrl = 0x6c,
 102         VLANTag = 0x70,
 103         PhyCtrl = 0x76,
 104         StationAddr0 = 0x78,
 105         StationAddr1 = 0x7a,
 106         StationAddr2 = 0x7c,
 107         VLANId = 0x80,
 108         MaxFrameSize = 0x86,
 109         ReceiveMode = 0x88,
 110         HashTable0 = 0x8c,
 111         HashTable1 = 0x90,
 112         RmonStatMask = 0x98,
 113         StatMask = 0x9c,
 114         RxJumboFrames = 0xbc,
 115         TCPCheckSumErrors = 0xc0,
 116         IPCheckSumErrors = 0xc2,
 117         UDPCheckSumErrors = 0xc4,
 118         TxJumboFrames = 0xf4,
 119         /* Ethernet MIB statistic register offsets */
 120         OctetRcvOk = 0xa8,
 121         McstOctetRcvOk = 0xac,
 122         BcstOctetRcvOk = 0xb0,
 123         FramesRcvOk = 0xb4,
 124         McstFramesRcvdOk = 0xb8,
 125         BcstFramesRcvdOk = 0xbe,
 126         MacControlFramesRcvd = 0xc6,
 127         FrameTooLongErrors = 0xc8,
 128         InRangeLengthErrors = 0xca,
 129         FramesCheckSeqErrors = 0xcc,
 130         FramesLostRxErrors = 0xce,
 131         OctetXmtOk = 0xd0,
 132         McstOctetXmtOk = 0xd4,
 133         BcstOctetXmtOk = 0xd8,
 134         FramesXmtOk = 0xdc,
 135         McstFramesXmtdOk = 0xe0,
 136         FramesWDeferredXmt = 0xe4,
 137         LateCollisions = 0xe8,
 138         MultiColFrames = 0xec,
 139         SingleColFrames = 0xf0,
 140         BcstFramesXmtdOk = 0xf6,
 141         CarrierSenseErrors = 0xf8,
 142         MacControlFramesXmtd = 0xfa,
 143         FramesAbortXSColls = 0xfc,
 144         FramesWEXDeferal = 0xfe,
 145         /* RMON statistic register offsets */
 146         EtherStatsCollisions = 0x100,
 147         EtherStatsOctetsTransmit = 0x104,
 148         EtherStatsPktsTransmit = 0x108,
 149         EtherStatsPkts64OctetTransmit = 0x10c,
 150         EtherStats65to127OctetsTransmit = 0x110,
 151         EtherStatsPkts128to255OctetsTransmit = 0x114,
 152         EtherStatsPkts256to511OctetsTransmit = 0x118,
 153         EtherStatsPkts512to1023OctetsTransmit = 0x11c,
 154         EtherStatsPkts1024to1518OctetsTransmit = 0x120,
 155         EtherStatsCRCAlignErrors = 0x124,
 156         EtherStatsUndersizePkts = 0x128,
 157         EtherStatsFragments = 0x12c,
 158         EtherStatsJabbers = 0x130,
 159         EtherStatsOctets = 0x134,
 160         EtherStatsPkts = 0x138,
 161         EtherStats64Octets = 0x13c,
 162         EtherStatsPkts65to127Octets = 0x140,
 163         EtherStatsPkts128to255Octets = 0x144,
 164         EtherStatsPkts256to511Octets = 0x148,
 165         EtherStatsPkts512to1023Octets = 0x14c,
 166         EtherStatsPkts1024to1518Octets = 0x150,
 167 };
 168
 169 /* Bits in the interrupt status/mask registers. */
 170 enum IntStatus_bits {
 171         InterruptStatus = 0x0001,
 172         HostError = 0x0002,
 173         MACCtrlFrame = 0x0008,
 174         TxComplete = 0x0004,
 175         RxComplete = 0x0010,
 176         RxEarly = 0x0020,
 177         IntRequested = 0x0040,
 178         UpdateStats = 0x0080,
 179         LinkEvent = 0x0100,
 180         TxDMAComplete = 0x0200,
 181         RxDMAComplete = 0x0400,
 182         RFDListEnd = 0x0800,
 183         RxDMAPriority = 0x1000,
 184 };
 185
 186 /* Bits in the ReceiveMode register. */
 187 enum ReceiveMode_bits {
 188         ReceiveUnicast = 0x0001,
 189         ReceiveMulticast = 0x0002,
 190         ReceiveBroadcast = 0x0004,
 191         ReceiveAllFrames = 0x0008,
 192         ReceiveMulticastHash = 0x0010,
 193         ReceiveIPMulticast = 0x0020,
 194         ReceiveVLANMatch = 0x0100,
 195         ReceiveVLANHash = 0x0200,
 196 };
 197 /* Bits in MACCtrl. */
 198 enum MACCtrl_bits {
 199         DuplexSelect = 0x20,
 200         TxFlowControlEnable = 0x80,
 201         RxFlowControlEnable = 0x0100,
 202         RcvFCS = 0x200,
 203         AutoVLANtagging = 0x1000,
 204         AutoVLANuntagging = 0x2000,
 205         StatsEnable = 0x00200000,
 206         StatsDisable = 0x00400000,
 207         StatsEnabled = 0x00800000,
 208         TxEnable = 0x01000000,
 209         TxDisable = 0x02000000,
 210         TxEnabled = 0x04000000,
 211         RxEnable = 0x08000000,
 212         RxDisable = 0x10000000,
 213         RxEnabled = 0x20000000,
 214 };
 215
 216 enum ASICCtrl_LoWord_bits {
 217         PhyMedia = 0x0080,
 218 };
 219
 220 enum ASICCtrl_HiWord_bits {
 221         GlobalReset = 0x0001,
 222         RxReset = 0x0002,
 223         TxReset = 0x0004,
 224         DMAReset = 0x0008,
 225         FIFOReset = 0x0010,
 226         NetworkReset = 0x0020,
 227         HostReset = 0x0040,
 228         ResetBusy = 0x0400,
 229 };
 230
 231 /* Transmit Frame Control bits */
 232 enum TFC_bits {
 233         DwordAlign = 0x00000000,
 234         WordAlignDisable = 0x00030000,
 235         WordAlign = 0x00020000,
 236         TCPChecksumEnable = 0x00040000,
 237         UDPChecksumEnable = 0x00080000,
 238         IPChecksumEnable = 0x00100000,
 239         FCSAppendDisable = 0x00200000,
 240         TxIndicate = 0x00400000,
 241         TxDMAIndicate = 0x00800000,
 242         FragCountShift = 24,
 243         VLANTagInsert = 0x0000000010000000,
 244         TFDDone = 0x80000000,
 245         VIDShift = 32,
 246         UsePriorityShift = 48,
 247 };
 248
 249 /* Receive Frames Status bits */
 250 enum RFS_bits {
 251         RxFIFOOverrun = 0x00010000,
 252         RxRuntFrame = 0x00020000,
 253         RxAlignmentError = 0x00040000,
 254         RxFCSError = 0x00080000,
 255         RxOverSizedFrame = 0x00100000,
 256         RxLengthError = 0x00200000,
 257         VLANDetected = 0x00400000,
 258         TCPDetected = 0x00800000,
 259         TCPError = 0x01000000,
 260         UDPDetected = 0x02000000,
 261         UDPError = 0x04000000,
 262         IPDetected = 0x08000000,
 263         IPError = 0x10000000,
 264         FrameStart = 0x20000000,
 265         FrameEnd = 0x40000000,
 266         RFDDone = 0x80000000,
 267         TCIShift = 32,
 268         RFS_Errors = 0x003f0000,
 269 };
 270
 271 #define MII_RESET_TIME_OUT              10000
 272 /* MII register */
 273 enum _mii_reg {
 274         MII_BMCR = 0,
 275         MII_BMSR = 1,
 276         MII_PHY_ID1 = 2,
 277         MII_PHY_ID2 = 3,
 278         MII_ANAR = 4,
 279         MII_ANLPAR = 5,
 280         MII_ANER = 6,
 281         MII_ANNPT = 7,
 282         MII_ANLPRNP = 8,
 283         MII_MSCR = 9,
 284         MII_MSSR = 10,
 285         MII_ESR = 15,
 286         MII_PHY_SCR = 16,
 287 };
 288 /* PCS register */
 289 enum _pcs_reg {
 290         PCS_BMCR = 0,
 291         PCS_BMSR = 1,
 292         PCS_ANAR = 4,
 293         PCS_ANLPAR = 5,
 294         PCS_ANER = 6,
 295         PCS_ANNPT = 7,
 296         PCS_ANLPRNP = 8,
 297         PCS_ESR = 15,
 298 };
 299
 300 /* Basic Mode Control Register */
 301 enum _mii_bmcr {
 302         MII_BMCR_RESET = 0x8000,
 303         MII_BMCR_LOOP_BACK = 0x4000,
 304         MII_BMCR_SPEED_LSB = 0x2000,
 305         MII_BMCR_AN_ENABLE = 0x1000,
 306         MII_BMCR_POWER_DOWN = 0x0800,
 307         MII_BMCR_ISOLATE = 0x0400,
 308         MII_BMCR_RESTART_AN = 0x0200,
 309         MII_BMCR_DUPLEX_MODE = 0x0100,
 310         MII_BMCR_COL_TEST = 0x0080,
 311         MII_BMCR_SPEED_MSB = 0x0040,
 312         MII_BMCR_SPEED_RESERVED = 0x003f,
 313         MII_BMCR_SPEED_10 = 0,
 314         MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
 315         MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
 316 };
 317
 318 /* Basic Mode Status Register */
 319 typedef union t_MII_BMSR {
 320         u16 image;
 321         struct {
 322                 u16 ext_capability:1;   // bit 0
 323                 u16 japper_detect:1;    // bit 1
 324                 u16 link_status:1;      // bit 2
 325                 u16 an_ability:1;       // bit 3
 326                 u16 remote_fault:1;     // bit 4
 327                 u16 an_complete:1;      // bit 5
 328                 u16 preamble_supp:1;    // bit 6
 329                 u16 _bit_7:1;   // bit 7
 330                 u16 ext_status:1;       // bit 8
 331                 u16 media_100BT2_HD:1;  // bit 9
 332                 u16 media_100BT2_FD:1;  // bit 10
 333                 u16 media_10BT_HD:1;    // bit 11
 334                 u16 media_10BT_FD:1;    // bit 12
 335                 u16 media_100BX_HD:1;   // bit 13
 336                 u16 media_100BX_FD:1;   // bit 14
 337                 u16 media_100BT4:1;     // bit 15
 338         } bits;
 339 } BMSR_t, *PBMSR_t;
 340
 341 enum _mii_bmsr {
 342         MII_BMSR_100BT4 = 0x8000,
 343         MII_BMSR_100BX_FD = 0x4000,
 344         MII_BMSR_100BX_HD = 0x2000,
 345         MII_BMSR_10BT_FD = 0x1000,
 346         MII_BMSR_10BT_HD = 0x0800,
 347         MII_BMSR_100BT2_FD = 0x0400,
 348         MII_BMSR_100BT2_HD = 0x0200,
 349         MII_BMSR_EXT_STATUS = 0x0100,
 350         MII_BMSR_PREAMBLE_SUPP = 0x0040,
 351         MII_BMSR_AN_COMPLETE = 0x0020,
 352         MII_BMSR_REMOTE_FAULT = 0x0010,
 353         MII_BMSR_AN_ABILITY = 0x0008,
 354         MII_BMSR_LINK_STATUS = 0x0004,
 355         MII_BMSR_JABBER_DETECT = 0x0002,
 356         MII_BMSR_EXT_CAP = 0x0001,
 357 };
 358
 359 /* ANAR */
 360 enum _mii_anar {
 361         MII_ANAR_NEXT_PAGE = 0x8000,
 362         MII_ANAR_REMOTE_FAULT = 0x4000,
 363         MII_ANAR_ASYMMETRIC = 0x0800,
 364         MII_ANAR_PAUSE = 0x0400,
 365         MII_ANAR_100BT4 = 0x0200,
 366         MII_ANAR_100BX_FD = 0x0100,
 367         MII_ANAR_100BX_HD = 0x0080,
 368         MII_ANAR_10BT_FD = 0x0020,
 369         MII_ANAR_10BT_HD = 0x0010,
 370         MII_ANAR_SELECTOR = 0x001f,
 371         MII_IEEE8023_CSMACD = 0x0001,
 372 };
 373
 374 /* ANLPAR */
 375 enum _mii_anlpar {
 376         MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
 377         MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
 378         MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
 379         MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
 380         MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
 381         MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
 382         MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
 383         MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
 384         MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
 385         MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
 386 };
 387
 388 /* Auto-Negotiation Expansion Register */
 389 typedef union t_MII_ANER {
 390         u16 image;
 391         struct {
 392                 u16 lp_negotiable:1;    // bit 0
 393                 u16 page_received:1;    // bit 1
 394                 u16 nextpagable:1;      // bit 2
 395                 u16 lp_nextpagable:1;   // bit 3
 396                 u16 pdetect_fault:1;    // bit 4
 397                 u16 _bit15_5:11;        // bit 15:5
 398         } bits;
 399 } ANER_t, *PANER_t;
 400
 401 enum _mii_aner {
 402         MII_ANER_PAR_DETECT_FAULT = 0x0010,
 403         MII_ANER_LP_NEXTPAGABLE = 0x0008,
 404         MII_ANER_NETXTPAGABLE = 0x0004,
 405         MII_ANER_PAGE_RECEIVED = 0x0002,
 406         MII_ANER_LP_NEGOTIABLE = 0x0001,
 407 };
 408
 409 /* MASTER-SLAVE Control Register */
 410 typedef union t_MII_MSCR {
 411         u16 image;
 412         struct {
 413                 u16 _bit_7_0:8; // bit 7:0
 414                 u16 media_1000BT_HD:1;  // bit 8
 415                 u16 media_1000BT_FD:1;  // bit 9
 416                 u16 port_type:1;        // bit 10
 417                 u16 cfg_value:1;        // bit 11
 418                 u16 cfg_enable:1;       // bit 12
 419                 u16 test_mode:3;        // bit 15:13
 420         } bits;
 421 } MSCR_t, *PMSCR_t;
 422
 423 enum _mii_mscr {
 424         MII_MSCR_TEST_MODE = 0xe000,
 425         MII_MSCR_CFG_ENABLE = 0x1000,
 426         MII_MSCR_CFG_VALUE = 0x0800,
 427         MII_MSCR_PORT_VALUE = 0x0400,
 428         MII_MSCR_1000BT_FD = 0x0200,
 429         MII_MSCR_1000BT_HD = 0X0100,
 430 };
 431
 432 /* MASTER-SLAVE Status Register */
 433 typedef union t_MII_MSSR {
 434         u16 image;
 435         struct {
 436                 u16 idle_err_count:8;   // bit 7:0
 437                 u16 _bit_9_8:2; // bit 9:8
 438                 u16 lp_1000BT_HD:1;     // bit 10
 439                 u16 lp_1000BT_FD:1;     // bit 11
 440                 u16 remote_rcv_status:1;        // bit 12
 441                 u16 local_rcv_status:1; // bit 13
 442                 u16 cfg_resolution:1;   // bit 14
 443                 u16 cfg_fault:1;        // bit 15
 444         } bits;
 445 } MSSR_t, *PMSSR_t;
 446
 447 enum _mii_mssr {
 448         MII_MSSR_CFG_FAULT = 0x8000,
 449         MII_MSSR_CFG_RES = 0x4000,
 450         MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
 451         MII_MSSR_REMOTE_RCVR = 0x1000,
 452         MII_MSSR_LP_1000BT_HD = 0x0800,
 453         MII_MSSR_LP_1000BT_FD = 0x0400,
 454         MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
 455 };
 456
 457 /* IEEE Extened Status Register */
 458 typedef union t_MII_ESR {
 459         u16 image;
 460         struct {
 461                 u16 _bit_11_0:12;       // bit 11:0
 462                 u16 media_1000BT_HD:2;  // bit 12
 463                 u16 media_1000BT_FD:1;  // bit 13
 464                 u16 media_1000BX_HD:1;  // bit 14
 465                 u16 media_1000BX_FD:1;  // bit 15
 466         } bits;
 467 } ESR_t, *PESR_t;
 468
 469 enum _mii_esr {
 470         MII_ESR_1000BX_FD = 0x8000,
 471         MII_ESR_1000BX_HD = 0x4000,
 472         MII_ESR_1000BT_FD = 0x2000,
 473         MII_ESR_1000BT_HD = 0x1000,
 474 };
 475 /* PHY Specific Control Register */
 476 typedef union t_MII_PHY_SCR {
 477         u16 image;
 478         struct {
 479                 u16 disable_jabber:1;   // bit 0
 480                 u16 polarity_reversal:1;        // bit 1
 481                 u16 SEQ_test:1; // bit 2
 482                 u16 _bit_3:1;   // bit 3
 483                 u16 disable_CLK125:1;   // bit 4
 484                 u16 mdi_crossover_mode:2;       // bit 6:5
 485                 u16 enable_ext_dist:1;  // bit 7
 486                 u16 _bit_8_9:2; // bit 9:8
 487                 u16 force_link:1;       // bit 10
 488                 u16 assert_CRS:1;       // bit 11
 489                 u16 rcv_fifo_depth:2;   // bit 13:12
 490                 u16 xmit_fifo_depth:2;  // bit 15:14
 491         } bits;
 492 } PHY_SCR_t, *PPHY_SCR_t;
 493
 494 typedef enum t_MII_ADMIN_STATUS {
 495         adm_reset,
 496         adm_operational,
 497         adm_loopback,
 498         adm_power_down,
 499         adm_isolate
 500 } MII_ADMIN_t, *PMII_ADMIN_t;
 501
 502 /* Physical Coding Sublayer Management (PCS) */
 503 /* PCS control and status registers bitmap as the same as MII */
 504 /* PCS Extended Status register bitmap as the same as MII */
 505 /* PCS ANAR */
 506 enum _pcs_anar {
 507         PCS_ANAR_NEXT_PAGE = 0x8000,
 508         PCS_ANAR_REMOTE_FAULT = 0x3000,
 509         PCS_ANAR_ASYMMETRIC = 0x0100,
 510         PCS_ANAR_PAUSE = 0x0080,
 511         PCS_ANAR_HALF_DUPLEX = 0x0040,
 512         PCS_ANAR_FULL_DUPLEX = 0x0020,
 513 };
 514 /* PCS ANLPAR */
 515 enum _pcs_anlpar {
 516         PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
 517         PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
 518         PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
 519         PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
 520         PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
 521         PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
 522 };
 523
 524 typedef struct t_SROM {
 525         u16 config_param;       /* 0x00 */
 526         u16 asic_ctrl;          /* 0x02 */
 527         u16 sub_vendor_id;      /* 0x04 */
 528         u16 sub_system_id;      /* 0x06 */
 529         u16 reserved1[12];      /* 0x08-0x1f */
 530         u8 mac_addr[6];         /* 0x20-0x25 */
 531         u8 reserved2[10];       /* 0x26-0x2f */
 532         u8 sib[204];            /* 0x30-0xfb */
 533         u32 crc;                /* 0xfc-0xff */
 534 } SROM_t, *PSROM_t;
 535
 536 /* Ioctl custom data */
 537 struct ioctl_data {
 538         char signature[10];
 539         int cmd;
 540         int len;
 541         char *data;
 542 };
 543
 544 struct mii_data {
 545         __u16 reserved;
 546         __u16 reg_num;
 547         __u16 in_value;
 548         __u16 out_value;
 549 };
 550
 551 /* The Rx and Tx buffer descriptors. */
 552 struct netdev_desc {
 553         __le64 next_desc;
 554         __le64 status;
 555         __le64 fraginfo;
 556 };
 557
 558 #define PRIV_ALIGN      15      /* Required alignment mask */
 559 /* Use  __attribute__((aligned (L1_CACHE_BYTES)))  to maintain alignment
 560    within the structure. */
 561 struct netdev_private {
 562         /* Descriptor rings first for alignment. */
 563         struct netdev_desc *rx_ring;
 564         struct netdev_desc *tx_ring;
 565         struct sk_buff *rx_skbuff[RX_RING_SIZE];
 566         struct sk_buff *tx_skbuff[TX_RING_SIZE];
 567         dma_addr_t tx_ring_dma;
 568         dma_addr_t rx_ring_dma;
 569         struct pci_dev *pdev;
 570         spinlock_t tx_lock;
 571         spinlock_t rx_lock;
 572         struct net_device_stats stats;
 573         unsigned int rx_buf_sz;         /* Based on MTU+slack. */
 574         unsigned int speed;             /* Operating speed */
 575         unsigned int vlan;              /* VLAN Id */
 576         unsigned int chip_id;           /* PCI table chip id */
 577         unsigned int rx_coalesce;       /* Maximum frames each RxDMAComplete intr */
 578         unsigned int rx_timeout;        /* Wait time between RxDMAComplete intr */
 579         unsigned int tx_coalesce;       /* Maximum frames each tx interrupt */
 580         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 581         unsigned int an_enable:2;       /* Auto-Negotiated Enable */
 582         unsigned int jumbo:1;           /* Jumbo frame enable */
 583         unsigned int coalesce:1;        /* Rx coalescing enable */
 584         unsigned int tx_flow:1;         /* Tx flow control enable */
 585         unsigned int rx_flow:1;         /* Rx flow control enable */
 586         unsigned int phy_media:1;       /* 1: fiber, 0: copper */
 587         unsigned int link_status:1;     /* Current link status */
 588         struct netdev_desc *last_tx;    /* Last Tx descriptor used. */
 589         unsigned long cur_rx, old_rx;   /* Producer/consumer ring indices */
 590         unsigned long cur_tx, old_tx;
 591         struct timer_list timer;
 592         int wake_polarity;
 593         char name[256];         /* net device description */
 594         u8 duplex_polarity;
 595         u16 mcast_filter[4];
 596         u16 advertising;        /* NWay media advertisement */
 597         u16 negotiate;          /* Negotiated media */
 598         int phy_addr;           /* PHY addresses. */
 599 };
 600
 601 /* The station address location in the EEPROM. */
 602 /* The struct pci_device_id consist of:
 603         vendor, device          Vendor and device ID to match (or PCI_ANY_ID)
 604         subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
 605         class                   Device class to match. The class_mask tells which bits
 606         class_mask              of the class are honored during the comparison.
 607         driver_data             Data private to the driver.
 608 */
 609
 610 static const struct pci_device_id rio_pci_tbl[] = {
 611         {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
 612         {0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
 613         { }
 614 };
 615 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
 616 #define TX_TIMEOUT  (4*HZ)
 617 #define PACKET_SIZE             1536
 618 #define MAX_JUMBO               8000
 619 #define RIO_IO_SIZE             340
 620 #define DEFAULT_RXC             5
 621 #define DEFAULT_RXT             750
 622 #define DEFAULT_TXC             1
 623 #define MAX_TXC                 8
 624 #endif                          /* __DL2K_H__ */