2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
26 #include <linux/ethtool.h>
27 #include <linux/if_bridge.h>
28 #include <linux/brcmphy.h>
29 #include <linux/etherdevice.h>
30 #include <net/switchdev.h>
33 #include "bcm_sf2_regs.h"
35 /* String, offset, and register size in bytes if different from 4 bytes */
36 static const struct bcm_sf2_hw_stats bcm_sf2_mib
[] = {
37 { "TxOctets", 0x000, 8 },
38 { "TxDropPkts", 0x020 },
39 { "TxQPKTQ0", 0x030 },
40 { "TxBroadcastPkts", 0x040 },
41 { "TxMulticastPkts", 0x050 },
42 { "TxUnicastPKts", 0x060 },
43 { "TxCollisions", 0x070 },
44 { "TxSingleCollision", 0x080 },
45 { "TxMultipleCollision", 0x090 },
46 { "TxDeferredCollision", 0x0a0 },
47 { "TxLateCollision", 0x0b0 },
48 { "TxExcessiveCollision", 0x0c0 },
49 { "TxFrameInDisc", 0x0d0 },
50 { "TxPausePkts", 0x0e0 },
51 { "TxQPKTQ1", 0x0f0 },
52 { "TxQPKTQ2", 0x100 },
53 { "TxQPKTQ3", 0x110 },
54 { "TxQPKTQ4", 0x120 },
55 { "TxQPKTQ5", 0x130 },
56 { "RxOctets", 0x140, 8 },
57 { "RxUndersizePkts", 0x160 },
58 { "RxPausePkts", 0x170 },
59 { "RxPkts64Octets", 0x180 },
60 { "RxPkts65to127Octets", 0x190 },
61 { "RxPkts128to255Octets", 0x1a0 },
62 { "RxPkts256to511Octets", 0x1b0 },
63 { "RxPkts512to1023Octets", 0x1c0 },
64 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
65 { "RxOversizePkts", 0x1e0 },
66 { "RxJabbers", 0x1f0 },
67 { "RxAlignmentErrors", 0x200 },
68 { "RxFCSErrors", 0x210 },
69 { "RxGoodOctets", 0x220, 8 },
70 { "RxDropPkts", 0x240 },
71 { "RxUnicastPkts", 0x250 },
72 { "RxMulticastPkts", 0x260 },
73 { "RxBroadcastPkts", 0x270 },
74 { "RxSAChanges", 0x280 },
75 { "RxFragments", 0x290 },
76 { "RxJumboPkt", 0x2a0 },
77 { "RxSymblErr", 0x2b0 },
78 { "InRangeErrCount", 0x2c0 },
79 { "OutRangeErrCount", 0x2d0 },
80 { "EEELpiEvent", 0x2e0 },
81 { "EEELpiDuration", 0x2f0 },
82 { "RxDiscard", 0x300, 8 },
83 { "TxQPKTQ6", 0x320 },
84 { "TxQPKTQ7", 0x330 },
85 { "TxPkts64Octets", 0x340 },
86 { "TxPkts65to127Octets", 0x350 },
87 { "TxPkts128to255Octets", 0x360 },
88 { "TxPkts256to511Ocets", 0x370 },
89 { "TxPkts512to1023Ocets", 0x380 },
90 { "TxPkts1024toMaxPktOcets", 0x390 },
93 #define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
95 static void bcm_sf2_sw_get_strings(struct dsa_switch
*ds
,
96 int port
, uint8_t *data
)
100 for (i
= 0; i
< BCM_SF2_STATS_SIZE
; i
++)
101 memcpy(data
+ i
* ETH_GSTRING_LEN
,
102 bcm_sf2_mib
[i
].string
, ETH_GSTRING_LEN
);
105 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch
*ds
,
106 int port
, uint64_t *data
)
108 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
109 const struct bcm_sf2_hw_stats
*s
;
114 mutex_lock(&priv
->stats_mutex
);
116 /* Now fetch the per-port counters */
117 for (i
= 0; i
< BCM_SF2_STATS_SIZE
; i
++) {
120 /* Do a latched 64-bit read if needed */
121 offset
= s
->reg
+ CORE_P_MIB_OFFSET(port
);
122 if (s
->sizeof_stat
== 8)
123 val
= core_readq(priv
, offset
);
125 val
= core_readl(priv
, offset
);
130 mutex_unlock(&priv
->stats_mutex
);
133 static int bcm_sf2_sw_get_sset_count(struct dsa_switch
*ds
)
135 return BCM_SF2_STATS_SIZE
;
138 static char *bcm_sf2_sw_drv_probe(struct device
*dsa_dev
,
139 struct device
*host_dev
,
140 int sw_addr
, void **_priv
)
142 struct bcm_sf2_priv
*priv
;
144 priv
= devm_kzalloc(dsa_dev
, sizeof(*priv
), GFP_KERNEL
);
149 return "Broadcom Starfighter 2";
152 static void bcm_sf2_imp_vlan_setup(struct dsa_switch
*ds
, int cpu_port
)
154 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
158 /* Enable the IMP Port to be in the same VLAN as the other ports
159 * on a per-port basis such that we only have Port i and IMP in
162 for (i
= 0; i
< priv
->hw_params
.num_ports
; i
++) {
163 if (!((1 << i
) & ds
->phys_port_mask
))
166 reg
= core_readl(priv
, CORE_PORT_VLAN_CTL_PORT(i
));
167 reg
|= (1 << cpu_port
);
168 core_writel(priv
, reg
, CORE_PORT_VLAN_CTL_PORT(i
));
172 static void bcm_sf2_imp_setup(struct dsa_switch
*ds
, int port
)
174 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
177 /* Enable the port memories */
178 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
179 reg
&= ~P_TXQ_PSM_VDD(port
);
180 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
182 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
183 reg
= core_readl(priv
, CORE_IMP_CTL
);
184 reg
|= (RX_BCST_EN
| RX_MCST_EN
| RX_UCST_EN
);
185 reg
&= ~(RX_DIS
| TX_DIS
);
186 core_writel(priv
, reg
, CORE_IMP_CTL
);
188 /* Enable forwarding */
189 core_writel(priv
, SW_FWDG_EN
, CORE_SWMODE
);
191 /* Enable IMP port in dumb mode */
192 reg
= core_readl(priv
, CORE_SWITCH_CTRL
);
193 reg
|= MII_DUMB_FWDG_EN
;
194 core_writel(priv
, reg
, CORE_SWITCH_CTRL
);
196 /* Resolve which bit controls the Broadcom tag */
199 val
= BRCM_HDR_EN_P8
;
202 val
= BRCM_HDR_EN_P7
;
205 val
= BRCM_HDR_EN_P5
;
212 /* Enable Broadcom tags for IMP port */
213 reg
= core_readl(priv
, CORE_BRCM_HDR_CTRL
);
215 core_writel(priv
, reg
, CORE_BRCM_HDR_CTRL
);
217 /* Enable reception Broadcom tag for CPU TX (switch RX) to
218 * allow us to tag outgoing frames
220 reg
= core_readl(priv
, CORE_BRCM_HDR_RX_DIS
);
222 core_writel(priv
, reg
, CORE_BRCM_HDR_RX_DIS
);
224 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
225 * allow delivering frames to the per-port net_devices
227 reg
= core_readl(priv
, CORE_BRCM_HDR_TX_DIS
);
229 core_writel(priv
, reg
, CORE_BRCM_HDR_TX_DIS
);
231 /* Force link status for IMP port */
232 reg
= core_readl(priv
, CORE_STS_OVERRIDE_IMP
);
233 reg
|= (MII_SW_OR
| LINK_STS
);
234 core_writel(priv
, reg
, CORE_STS_OVERRIDE_IMP
);
237 static void bcm_sf2_eee_enable_set(struct dsa_switch
*ds
, int port
, bool enable
)
239 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
242 reg
= core_readl(priv
, CORE_EEE_EN_CTRL
);
247 core_writel(priv
, reg
, CORE_EEE_EN_CTRL
);
250 static void bcm_sf2_gphy_enable_set(struct dsa_switch
*ds
, bool enable
)
252 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
255 reg
= reg_readl(priv
, REG_SPHY_CNTRL
);
258 reg
&= ~(EXT_PWR_DOWN
| IDDQ_BIAS
| CK25_DIS
);
259 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
261 reg
= reg_readl(priv
, REG_SPHY_CNTRL
);
264 reg
|= EXT_PWR_DOWN
| IDDQ_BIAS
| PHY_RESET
;
265 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
269 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
271 /* Use PHY-driven LED signaling */
273 reg
= reg_readl(priv
, REG_LED_CNTRL(0));
274 reg
|= SPDLNK_SRC_SEL
;
275 reg_writel(priv
, reg
, REG_LED_CNTRL(0));
279 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv
*priv
,
289 /* Port 0 interrupts are located on the first bank */
290 intrl2_0_mask_clear(priv
, P_IRQ_MASK(P0_IRQ_OFF
));
293 off
= P_IRQ_OFF(port
);
297 intrl2_1_mask_clear(priv
, P_IRQ_MASK(off
));
300 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv
*priv
,
310 /* Port 0 interrupts are located on the first bank */
311 intrl2_0_mask_set(priv
, P_IRQ_MASK(P0_IRQ_OFF
));
312 intrl2_0_writel(priv
, P_IRQ_MASK(P0_IRQ_OFF
), INTRL2_CPU_CLEAR
);
315 off
= P_IRQ_OFF(port
);
319 intrl2_1_mask_set(priv
, P_IRQ_MASK(off
));
320 intrl2_1_writel(priv
, P_IRQ_MASK(off
), INTRL2_CPU_CLEAR
);
323 static int bcm_sf2_port_setup(struct dsa_switch
*ds
, int port
,
324 struct phy_device
*phy
)
326 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
327 s8 cpu_port
= ds
->dst
[ds
->index
].cpu_port
;
330 /* Clear the memory power down */
331 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
332 reg
&= ~P_TXQ_PSM_VDD(port
);
333 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
335 /* Clear the Rx and Tx disable bits and set to no spanning tree */
336 core_writel(priv
, 0, CORE_G_PCTL_PORT(port
));
338 /* Re-enable the GPHY and re-apply workarounds */
339 if (priv
->int_phy_mask
& 1 << port
&& priv
->hw_params
.num_gphy
== 1) {
340 bcm_sf2_gphy_enable_set(ds
, true);
342 /* if phy_stop() has been called before, phy
343 * will be in halted state, and phy_start()
346 * the resume path does not configure back
347 * autoneg settings, and since we hard reset
348 * the phy manually here, we need to reset the
349 * state machine also.
351 phy
->state
= PHY_READY
;
356 /* Enable MoCA port interrupts to get notified */
357 if (port
== priv
->moca_port
)
358 bcm_sf2_port_intr_enable(priv
, port
);
360 /* Set this port, and only this one to be in the default VLAN,
361 * if member of a bridge, restore its membership prior to
362 * bringing down this port.
364 reg
= core_readl(priv
, CORE_PORT_VLAN_CTL_PORT(port
));
365 reg
&= ~PORT_VLAN_CTRL_MASK
;
367 reg
|= priv
->port_sts
[port
].vlan_ctl_mask
;
368 core_writel(priv
, reg
, CORE_PORT_VLAN_CTL_PORT(port
));
370 bcm_sf2_imp_vlan_setup(ds
, cpu_port
);
372 /* If EEE was enabled, restore it */
373 if (priv
->port_sts
[port
].eee
.eee_enabled
)
374 bcm_sf2_eee_enable_set(ds
, port
, true);
379 static void bcm_sf2_port_disable(struct dsa_switch
*ds
, int port
,
380 struct phy_device
*phy
)
382 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
385 if (priv
->wol_ports_mask
& (1 << port
))
388 if (port
== priv
->moca_port
)
389 bcm_sf2_port_intr_disable(priv
, port
);
391 if (priv
->int_phy_mask
& 1 << port
&& priv
->hw_params
.num_gphy
== 1)
392 bcm_sf2_gphy_enable_set(ds
, false);
394 if (dsa_is_cpu_port(ds
, port
))
397 off
= CORE_G_PCTL_PORT(port
);
399 reg
= core_readl(priv
, off
);
400 reg
|= RX_DIS
| TX_DIS
;
401 core_writel(priv
, reg
, off
);
403 /* Power down the port memory */
404 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
405 reg
|= P_TXQ_PSM_VDD(port
);
406 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
409 /* Returns 0 if EEE was not enabled, or 1 otherwise
411 static int bcm_sf2_eee_init(struct dsa_switch
*ds
, int port
,
412 struct phy_device
*phy
)
414 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
415 struct ethtool_eee
*p
= &priv
->port_sts
[port
].eee
;
418 p
->supported
= (SUPPORTED_1000baseT_Full
| SUPPORTED_100baseT_Full
);
420 ret
= phy_init_eee(phy
, 0);
424 bcm_sf2_eee_enable_set(ds
, port
, true);
429 static int bcm_sf2_sw_get_eee(struct dsa_switch
*ds
, int port
,
430 struct ethtool_eee
*e
)
432 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
433 struct ethtool_eee
*p
= &priv
->port_sts
[port
].eee
;
436 reg
= core_readl(priv
, CORE_EEE_LPI_INDICATE
);
437 e
->eee_enabled
= p
->eee_enabled
;
438 e
->eee_active
= !!(reg
& (1 << port
));
443 static int bcm_sf2_sw_set_eee(struct dsa_switch
*ds
, int port
,
444 struct phy_device
*phydev
,
445 struct ethtool_eee
*e
)
447 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
448 struct ethtool_eee
*p
= &priv
->port_sts
[port
].eee
;
450 p
->eee_enabled
= e
->eee_enabled
;
452 if (!p
->eee_enabled
) {
453 bcm_sf2_eee_enable_set(ds
, port
, false);
455 p
->eee_enabled
= bcm_sf2_eee_init(ds
, port
, phydev
);
463 /* Fast-ageing of ARL entries for a given port, equivalent to an ARL
464 * flush for that port.
466 static int bcm_sf2_sw_fast_age_port(struct dsa_switch
*ds
, int port
)
468 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
469 unsigned int timeout
= 1000;
472 core_writel(priv
, port
, CORE_FAST_AGE_PORT
);
474 reg
= core_readl(priv
, CORE_FAST_AGE_CTRL
);
475 reg
|= EN_AGE_PORT
| EN_AGE_DYNAMIC
| FAST_AGE_STR_DONE
;
476 core_writel(priv
, reg
, CORE_FAST_AGE_CTRL
);
479 reg
= core_readl(priv
, CORE_FAST_AGE_CTRL
);
480 if (!(reg
& FAST_AGE_STR_DONE
))
489 core_writel(priv
, 0, CORE_FAST_AGE_CTRL
);
494 static int bcm_sf2_sw_br_join(struct dsa_switch
*ds
, int port
,
495 struct net_device
*bridge
)
497 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
501 priv
->port_sts
[port
].bridge_dev
= bridge
;
502 p_ctl
= core_readl(priv
, CORE_PORT_VLAN_CTL_PORT(port
));
504 for (i
= 0; i
< priv
->hw_params
.num_ports
; i
++) {
505 if (priv
->port_sts
[i
].bridge_dev
!= bridge
)
508 /* Add this local port to the remote port VLAN control
509 * membership and update the remote port bitmask
511 reg
= core_readl(priv
, CORE_PORT_VLAN_CTL_PORT(i
));
513 core_writel(priv
, reg
, CORE_PORT_VLAN_CTL_PORT(i
));
514 priv
->port_sts
[i
].vlan_ctl_mask
= reg
;
519 /* Configure the local port VLAN control membership to include
520 * remote ports and update the local port bitmask
522 core_writel(priv
, p_ctl
, CORE_PORT_VLAN_CTL_PORT(port
));
523 priv
->port_sts
[port
].vlan_ctl_mask
= p_ctl
;
528 static void bcm_sf2_sw_br_leave(struct dsa_switch
*ds
, int port
)
530 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
531 struct net_device
*bridge
= priv
->port_sts
[port
].bridge_dev
;
535 p_ctl
= core_readl(priv
, CORE_PORT_VLAN_CTL_PORT(port
));
537 for (i
= 0; i
< priv
->hw_params
.num_ports
; i
++) {
538 /* Don't touch the remaining ports */
539 if (priv
->port_sts
[i
].bridge_dev
!= bridge
)
542 reg
= core_readl(priv
, CORE_PORT_VLAN_CTL_PORT(i
));
544 core_writel(priv
, reg
, CORE_PORT_VLAN_CTL_PORT(i
));
545 priv
->port_sts
[port
].vlan_ctl_mask
= reg
;
547 /* Prevent self removal to preserve isolation */
552 core_writel(priv
, p_ctl
, CORE_PORT_VLAN_CTL_PORT(port
));
553 priv
->port_sts
[port
].vlan_ctl_mask
= p_ctl
;
554 priv
->port_sts
[port
].bridge_dev
= NULL
;
557 static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch
*ds
, int port
,
560 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
561 u8 hw_state
, cur_hw_state
;
564 reg
= core_readl(priv
, CORE_G_PCTL_PORT(port
));
565 cur_hw_state
= reg
& (G_MISTP_STATE_MASK
<< G_MISTP_STATE_SHIFT
);
568 case BR_STATE_DISABLED
:
569 hw_state
= G_MISTP_DIS_STATE
;
571 case BR_STATE_LISTENING
:
572 hw_state
= G_MISTP_LISTEN_STATE
;
574 case BR_STATE_LEARNING
:
575 hw_state
= G_MISTP_LEARN_STATE
;
577 case BR_STATE_FORWARDING
:
578 hw_state
= G_MISTP_FWD_STATE
;
580 case BR_STATE_BLOCKING
:
581 hw_state
= G_MISTP_BLOCK_STATE
;
584 pr_err("%s: invalid STP state: %d\n", __func__
, state
);
588 /* Fast-age ARL entries if we are moving a port from Learning or
589 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
592 if (cur_hw_state
!= hw_state
) {
593 if (cur_hw_state
>= G_MISTP_LEARN_STATE
&&
594 hw_state
<= G_MISTP_LISTEN_STATE
) {
595 if (bcm_sf2_sw_fast_age_port(ds
, port
)) {
596 pr_err("%s: fast-ageing failed\n", __func__
);
602 reg
= core_readl(priv
, CORE_G_PCTL_PORT(port
));
603 reg
&= ~(G_MISTP_STATE_MASK
<< G_MISTP_STATE_SHIFT
);
605 core_writel(priv
, reg
, CORE_G_PCTL_PORT(port
));
608 /* Address Resolution Logic routines */
609 static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv
*priv
)
611 unsigned int timeout
= 10;
615 reg
= core_readl(priv
, CORE_ARLA_RWCTL
);
616 if (!(reg
& ARL_STRTDN
))
619 usleep_range(1000, 2000);
625 static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv
*priv
, unsigned int op
)
632 cmd
= core_readl(priv
, CORE_ARLA_RWCTL
);
633 cmd
&= ~IVL_SVL_SELECT
;
639 core_writel(priv
, cmd
, CORE_ARLA_RWCTL
);
641 return bcm_sf2_arl_op_wait(priv
);
644 static int bcm_sf2_arl_read(struct bcm_sf2_priv
*priv
, u64 mac
,
645 u16 vid
, struct bcm_sf2_arl_entry
*ent
, u8
*idx
,
651 ret
= bcm_sf2_arl_op_wait(priv
);
655 /* Read the 4 bins */
656 for (i
= 0; i
< 4; i
++) {
660 mac_vid
= core_readq(priv
, CORE_ARLA_MACVID_ENTRY(i
));
661 fwd_entry
= core_readl(priv
, CORE_ARLA_FWD_ENTRY(i
));
662 bcm_sf2_arl_to_entry(ent
, mac_vid
, fwd_entry
);
664 if (ent
->is_valid
&& is_valid
) {
669 /* This is the MAC we just deleted */
670 if (!is_valid
&& (mac_vid
& mac
))
677 static int bcm_sf2_arl_op(struct bcm_sf2_priv
*priv
, int op
, int port
,
678 const unsigned char *addr
, u16 vid
, bool is_valid
)
680 struct bcm_sf2_arl_entry ent
;
682 u64 mac
, mac_vid
= 0;
686 /* Convert the array into a 64-bit MAC */
687 mac
= bcm_sf2_mac_to_u64(addr
);
689 /* Perform a read for the given MAC and VID */
690 core_writeq(priv
, mac
, CORE_ARLA_MAC
);
691 core_writel(priv
, vid
, CORE_ARLA_VID
);
693 /* Issue a read operation for this MAC */
694 ret
= bcm_sf2_arl_rw_op(priv
, 1);
698 ret
= bcm_sf2_arl_read(priv
, mac
, vid
, &ent
, &idx
, is_valid
);
699 /* If this is a read, just finish now */
703 /* We could not find a matching MAC, so reset to a new entry */
709 memset(&ent
, 0, sizeof(ent
));
711 ent
.is_valid
= is_valid
;
713 ent
.is_static
= true;
714 memcpy(ent
.mac
, addr
, ETH_ALEN
);
715 bcm_sf2_arl_from_entry(&mac_vid
, &fwd_entry
, &ent
);
717 core_writeq(priv
, mac_vid
, CORE_ARLA_MACVID_ENTRY(idx
));
718 core_writel(priv
, fwd_entry
, CORE_ARLA_FWD_ENTRY(idx
));
720 ret
= bcm_sf2_arl_rw_op(priv
, 0);
724 /* Re-read the entry to check */
725 return bcm_sf2_arl_read(priv
, mac
, vid
, &ent
, &idx
, is_valid
);
728 static int bcm_sf2_sw_fdb_prepare(struct dsa_switch
*ds
, int port
,
729 const struct switchdev_obj_port_fdb
*fdb
,
730 struct switchdev_trans
*trans
)
732 /* We do not need to do anything specific here yet */
736 static void bcm_sf2_sw_fdb_add(struct dsa_switch
*ds
, int port
,
737 const struct switchdev_obj_port_fdb
*fdb
,
738 struct switchdev_trans
*trans
)
740 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
742 if (bcm_sf2_arl_op(priv
, 0, port
, fdb
->addr
, fdb
->vid
, true))
743 pr_err("%s: failed to add MAC address\n", __func__
);
746 static int bcm_sf2_sw_fdb_del(struct dsa_switch
*ds
, int port
,
747 const struct switchdev_obj_port_fdb
*fdb
)
749 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
751 return bcm_sf2_arl_op(priv
, 0, port
, fdb
->addr
, fdb
->vid
, false);
754 static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv
*priv
)
756 unsigned timeout
= 1000;
760 reg
= core_readl(priv
, CORE_ARLA_SRCH_CTL
);
761 if (!(reg
& ARLA_SRCH_STDN
))
764 if (reg
& ARLA_SRCH_VLID
)
767 usleep_range(1000, 2000);
773 static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv
*priv
, u8 idx
,
774 struct bcm_sf2_arl_entry
*ent
)
779 mac_vid
= core_readq(priv
, CORE_ARLA_SRCH_RSLT_MACVID(idx
));
780 fwd_entry
= core_readl(priv
, CORE_ARLA_SRCH_RSLT(idx
));
781 bcm_sf2_arl_to_entry(ent
, mac_vid
, fwd_entry
);
784 static int bcm_sf2_sw_fdb_copy(struct net_device
*dev
, int port
,
785 const struct bcm_sf2_arl_entry
*ent
,
786 struct switchdev_obj_port_fdb
*fdb
,
787 int (*cb
)(struct switchdev_obj
*obj
))
792 if (port
!= ent
->port
)
795 ether_addr_copy(fdb
->addr
, ent
->mac
);
797 fdb
->ndm_state
= ent
->is_static
? NUD_NOARP
: NUD_REACHABLE
;
799 return cb(&fdb
->obj
);
802 static int bcm_sf2_sw_fdb_dump(struct dsa_switch
*ds
, int port
,
803 struct switchdev_obj_port_fdb
*fdb
,
804 int (*cb
)(struct switchdev_obj
*obj
))
806 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
807 struct net_device
*dev
= ds
->ports
[port
];
808 struct bcm_sf2_arl_entry results
[2];
809 unsigned int count
= 0;
812 /* Start search operation */
813 core_writel(priv
, ARLA_SRCH_STDN
, CORE_ARLA_SRCH_CTL
);
816 ret
= bcm_sf2_arl_search_wait(priv
);
820 /* Read both entries, then return their values back */
821 bcm_sf2_arl_search_rd(priv
, 0, &results
[0]);
822 ret
= bcm_sf2_sw_fdb_copy(dev
, port
, &results
[0], fdb
, cb
);
826 bcm_sf2_arl_search_rd(priv
, 1, &results
[1]);
827 ret
= bcm_sf2_sw_fdb_copy(dev
, port
, &results
[1], fdb
, cb
);
831 if (!results
[0].is_valid
&& !results
[1].is_valid
)
834 } while (count
++ < CORE_ARLA_NUM_ENTRIES
);
839 static irqreturn_t
bcm_sf2_switch_0_isr(int irq
, void *dev_id
)
841 struct bcm_sf2_priv
*priv
= dev_id
;
843 priv
->irq0_stat
= intrl2_0_readl(priv
, INTRL2_CPU_STATUS
) &
845 intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
850 static irqreturn_t
bcm_sf2_switch_1_isr(int irq
, void *dev_id
)
852 struct bcm_sf2_priv
*priv
= dev_id
;
854 priv
->irq1_stat
= intrl2_1_readl(priv
, INTRL2_CPU_STATUS
) &
856 intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
858 if (priv
->irq1_stat
& P_LINK_UP_IRQ(P7_IRQ_OFF
))
859 priv
->port_sts
[7].link
= 1;
860 if (priv
->irq1_stat
& P_LINK_DOWN_IRQ(P7_IRQ_OFF
))
861 priv
->port_sts
[7].link
= 0;
866 static int bcm_sf2_sw_rst(struct bcm_sf2_priv
*priv
)
868 unsigned int timeout
= 1000;
871 reg
= core_readl(priv
, CORE_WATCHDOG_CTRL
);
872 reg
|= SOFTWARE_RESET
| EN_CHIP_RST
| EN_SW_RESET
;
873 core_writel(priv
, reg
, CORE_WATCHDOG_CTRL
);
876 reg
= core_readl(priv
, CORE_WATCHDOG_CTRL
);
877 if (!(reg
& SOFTWARE_RESET
))
880 usleep_range(1000, 2000);
881 } while (timeout
-- > 0);
889 static void bcm_sf2_intr_disable(struct bcm_sf2_priv
*priv
)
891 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_MASK_SET
);
892 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
893 intrl2_0_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
894 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_MASK_SET
);
895 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
896 intrl2_1_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
899 static void bcm_sf2_identify_ports(struct bcm_sf2_priv
*priv
,
900 struct device_node
*dn
)
902 struct device_node
*port
;
903 const char *phy_mode_str
;
905 unsigned int port_num
;
908 priv
->moca_port
= -1;
910 for_each_available_child_of_node(dn
, port
) {
911 if (of_property_read_u32(port
, "reg", &port_num
))
914 /* Internal PHYs get assigned a specific 'phy-mode' property
915 * value: "internal" to help flag them before MDIO probing
916 * has completed, since they might be turned off at that
919 mode
= of_get_phy_mode(port
);
921 ret
= of_property_read_string(port
, "phy-mode",
926 if (!strcasecmp(phy_mode_str
, "internal"))
927 priv
->int_phy_mask
|= 1 << port_num
;
930 if (mode
== PHY_INTERFACE_MODE_MOCA
)
931 priv
->moca_port
= port_num
;
935 static int bcm_sf2_sw_setup(struct dsa_switch
*ds
)
937 const char *reg_names
[BCM_SF2_REGS_NUM
] = BCM_SF2_REGS_NAME
;
938 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
939 struct device_node
*dn
;
946 spin_lock_init(&priv
->indir_lock
);
947 mutex_init(&priv
->stats_mutex
);
949 /* All the interesting properties are at the parent device_node
952 dn
= ds
->pd
->of_node
->parent
;
953 bcm_sf2_identify_ports(priv
, ds
->pd
->of_node
);
955 priv
->irq0
= irq_of_parse_and_map(dn
, 0);
956 priv
->irq1
= irq_of_parse_and_map(dn
, 1);
959 for (i
= 0; i
< BCM_SF2_REGS_NUM
; i
++) {
960 *base
= of_iomap(dn
, i
);
962 pr_err("unable to find register: %s\n", reg_names
[i
]);
969 ret
= bcm_sf2_sw_rst(priv
);
971 pr_err("unable to software reset switch: %d\n", ret
);
975 /* Disable all interrupts and request them */
976 bcm_sf2_intr_disable(priv
);
978 ret
= request_irq(priv
->irq0
, bcm_sf2_switch_0_isr
, 0,
981 pr_err("failed to request switch_0 IRQ\n");
985 ret
= request_irq(priv
->irq1
, bcm_sf2_switch_1_isr
, 0,
988 pr_err("failed to request switch_1 IRQ\n");
992 /* Reset the MIB counters */
993 reg
= core_readl(priv
, CORE_GMNCFGCFG
);
995 core_writel(priv
, reg
, CORE_GMNCFGCFG
);
997 core_writel(priv
, reg
, CORE_GMNCFGCFG
);
999 /* Get the maximum number of ports for this switch */
1000 priv
->hw_params
.num_ports
= core_readl(priv
, CORE_IMP0_PRT_ID
) + 1;
1001 if (priv
->hw_params
.num_ports
> DSA_MAX_PORTS
)
1002 priv
->hw_params
.num_ports
= DSA_MAX_PORTS
;
1004 /* Assume a single GPHY setup if we can't read that property */
1005 if (of_property_read_u32(dn
, "brcm,num-gphy",
1006 &priv
->hw_params
.num_gphy
))
1007 priv
->hw_params
.num_gphy
= 1;
1009 /* Enable all valid ports and disable those unused */
1010 for (port
= 0; port
< priv
->hw_params
.num_ports
; port
++) {
1011 /* IMP port receives special treatment */
1012 if ((1 << port
) & ds
->phys_port_mask
)
1013 bcm_sf2_port_setup(ds
, port
, NULL
);
1014 else if (dsa_is_cpu_port(ds
, port
))
1015 bcm_sf2_imp_setup(ds
, port
);
1017 bcm_sf2_port_disable(ds
, port
, NULL
);
1020 /* Include the pseudo-PHY address and the broadcast PHY address to
1021 * divert reads towards our workaround. This is only required for
1022 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
1023 * that we can use the regular SWITCH_MDIO master controller instead.
1025 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
1026 * to have a 1:1 mapping between Port address and PHY address in order
1027 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
1028 * not what we want here, so we initialize phys_mii_mask 0 to always
1029 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
1031 if (of_machine_is_compatible("brcm,bcm7445d0"))
1032 ds
->phys_mii_mask
|= ((1 << BRCM_PSEUDO_PHY_ADDR
) | (1 << 0));
1034 ds
->phys_mii_mask
= 0;
1036 rev
= reg_readl(priv
, REG_SWITCH_REVISION
);
1037 priv
->hw_params
.top_rev
= (rev
>> SWITCH_TOP_REV_SHIFT
) &
1038 SWITCH_TOP_REV_MASK
;
1039 priv
->hw_params
.core_rev
= (rev
& SF2_REV_MASK
);
1041 rev
= reg_readl(priv
, REG_PHY_REVISION
);
1042 priv
->hw_params
.gphy_rev
= rev
& PHY_REVISION_MASK
;
1044 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1045 priv
->hw_params
.top_rev
>> 8, priv
->hw_params
.top_rev
& 0xff,
1046 priv
->hw_params
.core_rev
>> 8, priv
->hw_params
.core_rev
& 0xff,
1047 priv
->core
, priv
->irq0
, priv
->irq1
);
1052 free_irq(priv
->irq0
, priv
);
1055 for (i
= 0; i
< BCM_SF2_REGS_NUM
; i
++) {
1063 static int bcm_sf2_sw_set_addr(struct dsa_switch
*ds
, u8
*addr
)
1068 static u32
bcm_sf2_sw_get_phy_flags(struct dsa_switch
*ds
, int port
)
1070 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1072 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
1073 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
1074 * the REG_PHY_REVISION register layout is.
1077 return priv
->hw_params
.gphy_rev
;
1080 static int bcm_sf2_sw_indir_rw(struct dsa_switch
*ds
, int op
, int addr
,
1081 int regnum
, u16 val
)
1083 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1087 reg
= reg_readl(priv
, REG_SWITCH_CNTRL
);
1088 reg
|= MDIO_MASTER_SEL
;
1089 reg_writel(priv
, reg
, REG_SWITCH_CNTRL
);
1091 /* Page << 8 | offset */
1094 core_writel(priv
, addr
, reg
);
1096 /* Page << 8 | offset */
1097 reg
= 0x80 << 8 | regnum
<< 1;
1101 ret
= core_readl(priv
, reg
);
1103 core_writel(priv
, val
, reg
);
1105 reg
= reg_readl(priv
, REG_SWITCH_CNTRL
);
1106 reg
&= ~MDIO_MASTER_SEL
;
1107 reg_writel(priv
, reg
, REG_SWITCH_CNTRL
);
1109 return ret
& 0xffff;
1112 static int bcm_sf2_sw_phy_read(struct dsa_switch
*ds
, int addr
, int regnum
)
1114 /* Intercept reads from the MDIO broadcast address or Broadcom
1115 * pseudo-PHY address
1119 case BRCM_PSEUDO_PHY_ADDR
:
1120 return bcm_sf2_sw_indir_rw(ds
, 1, addr
, regnum
, 0);
1126 static int bcm_sf2_sw_phy_write(struct dsa_switch
*ds
, int addr
, int regnum
,
1129 /* Intercept writes to the MDIO broadcast address or Broadcom
1130 * pseudo-PHY address
1134 case BRCM_PSEUDO_PHY_ADDR
:
1135 bcm_sf2_sw_indir_rw(ds
, 0, addr
, regnum
, val
);
1142 static void bcm_sf2_sw_adjust_link(struct dsa_switch
*ds
, int port
,
1143 struct phy_device
*phydev
)
1145 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1146 u32 id_mode_dis
= 0, port_mode
;
1147 const char *str
= NULL
;
1150 switch (phydev
->interface
) {
1151 case PHY_INTERFACE_MODE_RGMII
:
1152 str
= "RGMII (no delay)";
1154 case PHY_INTERFACE_MODE_RGMII_TXID
:
1156 str
= "RGMII (TX delay)";
1157 port_mode
= EXT_GPHY
;
1159 case PHY_INTERFACE_MODE_MII
:
1161 port_mode
= EXT_EPHY
;
1163 case PHY_INTERFACE_MODE_REVMII
:
1164 str
= "Reverse MII";
1165 port_mode
= EXT_REVMII
;
1168 /* All other PHYs: internal and MoCA */
1172 /* If the link is down, just disable the interface to conserve power */
1173 if (!phydev
->link
) {
1174 reg
= reg_readl(priv
, REG_RGMII_CNTRL_P(port
));
1175 reg
&= ~RGMII_MODE_EN
;
1176 reg_writel(priv
, reg
, REG_RGMII_CNTRL_P(port
));
1180 /* Clear id_mode_dis bit, and the existing port mode, but
1181 * make sure we enable the RGMII block for data to pass
1183 reg
= reg_readl(priv
, REG_RGMII_CNTRL_P(port
));
1184 reg
&= ~ID_MODE_DIS
;
1185 reg
&= ~(PORT_MODE_MASK
<< PORT_MODE_SHIFT
);
1186 reg
&= ~(RX_PAUSE_EN
| TX_PAUSE_EN
);
1188 reg
|= port_mode
| RGMII_MODE_EN
;
1192 if (phydev
->pause
) {
1193 if (phydev
->asym_pause
)
1198 reg_writel(priv
, reg
, REG_RGMII_CNTRL_P(port
));
1200 pr_info("Port %d configured for %s\n", port
, str
);
1203 /* Force link settings detected from the PHY */
1205 switch (phydev
->speed
) {
1207 reg
|= SPDSTS_1000
<< SPEED_SHIFT
;
1210 reg
|= SPDSTS_100
<< SPEED_SHIFT
;
1216 if (phydev
->duplex
== DUPLEX_FULL
)
1219 core_writel(priv
, reg
, CORE_STS_OVERRIDE_GMIIP_PORT(port
));
1222 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch
*ds
, int port
,
1223 struct fixed_phy_status
*status
)
1225 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1229 duplex
= core_readl(priv
, CORE_DUPSTS
);
1230 pause
= core_readl(priv
, CORE_PAUSESTS
);
1234 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
1235 * which means that we need to force the link at the port override
1236 * level to get the data to flow. We do use what the interrupt handler
1237 * did determine before.
1239 * For the other ports, we just force the link status, since this is
1240 * a fixed PHY device.
1242 if (port
== priv
->moca_port
) {
1243 status
->link
= priv
->port_sts
[port
].link
;
1244 /* For MoCA interfaces, also force a link down notification
1245 * since some version of the user-space daemon (mocad) use
1246 * cmd->autoneg to force the link, which messes up the PHY
1247 * state machine and make it go in PHY_FORCING state instead.
1250 netif_carrier_off(ds
->ports
[port
]);
1254 status
->duplex
= !!(duplex
& (1 << port
));
1257 reg
= core_readl(priv
, CORE_STS_OVERRIDE_GMIIP_PORT(port
));
1263 core_writel(priv
, reg
, CORE_STS_OVERRIDE_GMIIP_PORT(port
));
1265 if ((pause
& (1 << port
)) &&
1266 (pause
& (1 << (port
+ PAUSESTS_TX_PAUSE_SHIFT
)))) {
1267 status
->asym_pause
= 1;
1271 if (pause
& (1 << port
))
1275 static int bcm_sf2_sw_suspend(struct dsa_switch
*ds
)
1277 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1280 bcm_sf2_intr_disable(priv
);
1282 /* Disable all ports physically present including the IMP
1283 * port, the other ones have already been disabled during
1286 for (port
= 0; port
< DSA_MAX_PORTS
; port
++) {
1287 if ((1 << port
) & ds
->phys_port_mask
||
1288 dsa_is_cpu_port(ds
, port
))
1289 bcm_sf2_port_disable(ds
, port
, NULL
);
1295 static int bcm_sf2_sw_resume(struct dsa_switch
*ds
)
1297 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1301 ret
= bcm_sf2_sw_rst(priv
);
1303 pr_err("%s: failed to software reset switch\n", __func__
);
1307 if (priv
->hw_params
.num_gphy
== 1)
1308 bcm_sf2_gphy_enable_set(ds
, true);
1310 for (port
= 0; port
< DSA_MAX_PORTS
; port
++) {
1311 if ((1 << port
) & ds
->phys_port_mask
)
1312 bcm_sf2_port_setup(ds
, port
, NULL
);
1313 else if (dsa_is_cpu_port(ds
, port
))
1314 bcm_sf2_imp_setup(ds
, port
);
1320 static void bcm_sf2_sw_get_wol(struct dsa_switch
*ds
, int port
,
1321 struct ethtool_wolinfo
*wol
)
1323 struct net_device
*p
= ds
->dst
[ds
->index
].master_netdev
;
1324 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1325 struct ethtool_wolinfo pwol
;
1327 /* Get the parent device WoL settings */
1328 p
->ethtool_ops
->get_wol(p
, &pwol
);
1330 /* Advertise the parent device supported settings */
1331 wol
->supported
= pwol
.supported
;
1332 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1334 if (pwol
.wolopts
& WAKE_MAGICSECURE
)
1335 memcpy(&wol
->sopass
, pwol
.sopass
, sizeof(wol
->sopass
));
1337 if (priv
->wol_ports_mask
& (1 << port
))
1338 wol
->wolopts
= pwol
.wolopts
;
1343 static int bcm_sf2_sw_set_wol(struct dsa_switch
*ds
, int port
,
1344 struct ethtool_wolinfo
*wol
)
1346 struct net_device
*p
= ds
->dst
[ds
->index
].master_netdev
;
1347 struct bcm_sf2_priv
*priv
= ds_to_priv(ds
);
1348 s8 cpu_port
= ds
->dst
[ds
->index
].cpu_port
;
1349 struct ethtool_wolinfo pwol
;
1351 p
->ethtool_ops
->get_wol(p
, &pwol
);
1352 if (wol
->wolopts
& ~pwol
.supported
)
1356 priv
->wol_ports_mask
|= (1 << port
);
1358 priv
->wol_ports_mask
&= ~(1 << port
);
1360 /* If we have at least one port enabled, make sure the CPU port
1361 * is also enabled. If the CPU port is the last one enabled, we disable
1362 * it since this configuration does not make sense.
1364 if (priv
->wol_ports_mask
&& priv
->wol_ports_mask
!= (1 << cpu_port
))
1365 priv
->wol_ports_mask
|= (1 << cpu_port
);
1367 priv
->wol_ports_mask
&= ~(1 << cpu_port
);
1369 return p
->ethtool_ops
->set_wol(p
, wol
);
1372 static struct dsa_switch_driver bcm_sf2_switch_driver
= {
1373 .tag_protocol
= DSA_TAG_PROTO_BRCM
,
1374 .probe
= bcm_sf2_sw_drv_probe
,
1375 .setup
= bcm_sf2_sw_setup
,
1376 .set_addr
= bcm_sf2_sw_set_addr
,
1377 .get_phy_flags
= bcm_sf2_sw_get_phy_flags
,
1378 .phy_read
= bcm_sf2_sw_phy_read
,
1379 .phy_write
= bcm_sf2_sw_phy_write
,
1380 .get_strings
= bcm_sf2_sw_get_strings
,
1381 .get_ethtool_stats
= bcm_sf2_sw_get_ethtool_stats
,
1382 .get_sset_count
= bcm_sf2_sw_get_sset_count
,
1383 .adjust_link
= bcm_sf2_sw_adjust_link
,
1384 .fixed_link_update
= bcm_sf2_sw_fixed_link_update
,
1385 .suspend
= bcm_sf2_sw_suspend
,
1386 .resume
= bcm_sf2_sw_resume
,
1387 .get_wol
= bcm_sf2_sw_get_wol
,
1388 .set_wol
= bcm_sf2_sw_set_wol
,
1389 .port_enable
= bcm_sf2_port_setup
,
1390 .port_disable
= bcm_sf2_port_disable
,
1391 .get_eee
= bcm_sf2_sw_get_eee
,
1392 .set_eee
= bcm_sf2_sw_set_eee
,
1393 .port_bridge_join
= bcm_sf2_sw_br_join
,
1394 .port_bridge_leave
= bcm_sf2_sw_br_leave
,
1395 .port_stp_state_set
= bcm_sf2_sw_br_set_stp_state
,
1396 .port_fdb_prepare
= bcm_sf2_sw_fdb_prepare
,
1397 .port_fdb_add
= bcm_sf2_sw_fdb_add
,
1398 .port_fdb_del
= bcm_sf2_sw_fdb_del
,
1399 .port_fdb_dump
= bcm_sf2_sw_fdb_dump
,
1402 static int __init
bcm_sf2_init(void)
1404 register_switch_driver(&bcm_sf2_switch_driver
);
1408 module_init(bcm_sf2_init
);
1410 static void __exit
bcm_sf2_exit(void)
1412 unregister_switch_driver(&bcm_sf2_switch_driver
);
1414 module_exit(bcm_sf2_exit
);
1416 MODULE_AUTHOR("Broadcom Corporation");
1417 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1418 MODULE_LICENSE("GPL");
1419 MODULE_ALIAS("platform:brcm-sf2");