drivers/net/dsa/mv88e6060.c

   1 /*
   2  * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6060.h"
  19
  20 static int reg_read(struct dsa_switch *ds, int addr, int reg)
  21 {
  22         struct mv88e6060_priv *priv = ds_to_priv(ds);
  23
  24         return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
  25 }
  26
  27 #define REG_READ(addr, reg)                                     \
  28         ({                                                      \
  29                 int __ret;                                      \
  30                                                                 \
  31                 __ret = reg_read(ds, addr, reg);                \
  32                 if (__ret < 0)                                  \
  33                         return __ret;                           \
  34                 __ret;                                          \
  35         })
  36
  37
  38 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  39 {
  40         struct mv88e6060_priv *priv = ds_to_priv(ds);
  41
  42         return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
  43 }
  44
  45 #define REG_WRITE(addr, reg, val)                               \
  46         ({                                                      \
  47                 int __ret;                                      \
  48                                                                 \
  49                 __ret = reg_write(ds, addr, reg, val);          \
  50                 if (__ret < 0)                                  \
  51                         return __ret;                           \
  52         })
  53
  54 static char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
  55 {
  56         int ret;
  57
  58         ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
  59         if (ret >= 0) {
  60                 if (ret == PORT_SWITCH_ID_6060)
  61                         return "Marvell 88E6060 (A0)";
  62                 if (ret == PORT_SWITCH_ID_6060_R1 ||
  63                     ret == PORT_SWITCH_ID_6060_R2)
  64                         return "Marvell 88E6060 (B0)";
  65                 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
  66                         return "Marvell 88E6060";
  67         }
  68
  69         return NULL;
  70 }
  71
  72 static char *mv88e6060_probe(struct device *dsa_dev, struct device *host_dev,
  73                              int sw_addr, void **_priv)
  74 {
  75         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  76         struct mv88e6060_priv *priv;
  77         char *name;
  78
  79         name = mv88e6060_get_name(bus, sw_addr);
  80         if (name) {
  81                 priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
  82                 if (!priv)
  83                         return NULL;
  84                 *_priv = priv;
  85                 priv->bus = bus;
  86                 priv->sw_addr = sw_addr;
  87         }
  88
  89         return name;
  90 }
  91
  92 static int mv88e6060_switch_reset(struct dsa_switch *ds)
  93 {
  94         int i;
  95         int ret;
  96         unsigned long timeout;
  97
  98         /* Set all ports to the disabled state. */
  99         for (i = 0; i < MV88E6060_PORTS; i++) {
 100                 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
 101                 REG_WRITE(REG_PORT(i), PORT_CONTROL,
 102                           ret & ~PORT_CONTROL_STATE_MASK);
 103         }
 104
 105         /* Wait for transmit queues to drain. */
 106         usleep_range(2000, 4000);
 107
 108         /* Reset the switch. */
 109         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
 110                   GLOBAL_ATU_CONTROL_SWRESET |
 111                   GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
 112                   GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
 113
 114         /* Wait up to one second for reset to complete. */
 115         timeout = jiffies + 1 * HZ;
 116         while (time_before(jiffies, timeout)) {
 117                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 118                 if (ret & GLOBAL_STATUS_INIT_READY)
 119                         break;
 120
 121                 usleep_range(1000, 2000);
 122         }
 123         if (time_after(jiffies, timeout))
 124                 return -ETIMEDOUT;
 125
 126         return 0;
 127 }
 128
 129 static int mv88e6060_setup_global(struct dsa_switch *ds)
 130 {
 131         /* Disable discarding of frames with excessive collisions,
 132          * set the maximum frame size to 1536 bytes, and mask all
 133          * interrupt sources.
 134          */
 135         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
 136
 137         /* Enable automatic address learning, set the address
 138          * database size to 1024 entries, and set the default aging
 139          * time to 5 minutes.
 140          */
 141         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
 142                   GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
 143                   GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
 144
 145         return 0;
 146 }
 147
 148 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
 149 {
 150         int addr = REG_PORT(p);
 151
 152         /* Do not force flow control, disable Ingress and Egress
 153          * Header tagging, disable VLAN tunneling, and set the port
 154          * state to Forwarding.  Additionally, if this is the CPU
 155          * port, enable Ingress and Egress Trailer tagging mode.
 156          */
 157         REG_WRITE(addr, PORT_CONTROL,
 158                   dsa_is_cpu_port(ds, p) ?
 159                         PORT_CONTROL_TRAILER |
 160                         PORT_CONTROL_INGRESS_MODE |
 161                         PORT_CONTROL_STATE_FORWARDING :
 162                         PORT_CONTROL_STATE_FORWARDING);
 163
 164         /* Port based VLAN map: give each port its own address
 165          * database, allow the CPU port to talk to each of the 'real'
 166          * ports, and allow each of the 'real' ports to only talk to
 167          * the CPU port.
 168          */
 169         REG_WRITE(addr, PORT_VLAN_MAP,
 170                   ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
 171                    (dsa_is_cpu_port(ds, p) ?
 172                         ds->phys_port_mask :
 173                         BIT(ds->dst->cpu_port)));
 174
 175         /* Port Association Vector: when learning source addresses
 176          * of packets, add the address to the address database using
 177          * a port bitmap that has only the bit for this port set and
 178          * the other bits clear.
 179          */
 180         REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
 181
 182         return 0;
 183 }
 184
 185 static int mv88e6060_setup(struct dsa_switch *ds)
 186 {
 187         int ret;
 188         int i;
 189
 190         ret = mv88e6060_switch_reset(ds);
 191         if (ret < 0)
 192                 return ret;
 193
 194         /* @@@ initialise atu */
 195
 196         ret = mv88e6060_setup_global(ds);
 197         if (ret < 0)
 198                 return ret;
 199
 200         for (i = 0; i < MV88E6060_PORTS; i++) {
 201                 ret = mv88e6060_setup_port(ds, i);
 202                 if (ret < 0)
 203                         return ret;
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
 210 {
 211         /* Use the same MAC Address as FD Pause frames for all ports */
 212         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
 213         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
 214         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6060_port_to_phy_addr(int port)
 220 {
 221         if (port >= 0 && port < MV88E6060_PORTS)
 222                 return port;
 223         return -1;
 224 }
 225
 226 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
 227 {
 228         int addr;
 229
 230         addr = mv88e6060_port_to_phy_addr(port);
 231         if (addr == -1)
 232                 return 0xffff;
 233
 234         return reg_read(ds, addr, regnum);
 235 }
 236
 237 static int
 238 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
 239 {
 240         int addr;
 241
 242         addr = mv88e6060_port_to_phy_addr(port);
 243         if (addr == -1)
 244                 return 0xffff;
 245
 246         return reg_write(ds, addr, regnum, val);
 247 }
 248
 249 static struct dsa_switch_driver mv88e6060_switch_driver = {
 250         .tag_protocol   = DSA_TAG_PROTO_TRAILER,
 251         .probe          = mv88e6060_probe,
 252         .setup          = mv88e6060_setup,
 253         .set_addr       = mv88e6060_set_addr,
 254         .phy_read       = mv88e6060_phy_read,
 255         .phy_write      = mv88e6060_phy_write,
 256 };
 257
 258 static int __init mv88e6060_init(void)
 259 {
 260         register_switch_driver(&mv88e6060_switch_driver);
 261         return 0;
 262 }
 263 module_init(mv88e6060_init);
 264
 265 static void __exit mv88e6060_cleanup(void)
 266 {
 267         unregister_switch_driver(&mv88e6060_switch_driver);
 268 }
 269 module_exit(mv88e6060_cleanup);
 270
 271 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
 272 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
 273 MODULE_LICENSE("GPL");
 274 MODULE_ALIAS("platform:mv88e6060");