drivers/net/dsa/mv88e6060.c

   1 /*
   2  * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6060.h"
  19
  20 static int reg_read(struct dsa_switch *ds, int addr, int reg)
  21 {
  22         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  23
  24         if (bus == NULL)
  25                 return -EINVAL;
  26
  27         return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
  28 }
  29
  30 #define REG_READ(addr, reg)                                     \
  31         ({                                                      \
  32                 int __ret;                                      \
  33                                                                 \
  34                 __ret = reg_read(ds, addr, reg);                \
  35                 if (__ret < 0)                                  \
  36                         return __ret;                           \
  37                 __ret;                                          \
  38         })
  39
  40
  41 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  42 {
  43         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  44
  45         if (bus == NULL)
  46                 return -EINVAL;
  47
  48         return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
  49 }
  50
  51 #define REG_WRITE(addr, reg, val)                               \
  52         ({                                                      \
  53                 int __ret;                                      \
  54                                                                 \
  55                 __ret = reg_write(ds, addr, reg, val);          \
  56                 if (__ret < 0)                                  \
  57                         return __ret;                           \
  58         })
  59
  60 static char *mv88e6060_probe(struct device *dsa_dev, struct device *host_dev,
  61                              int sw_addr, void **priv)
  62 {
  63         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  64         int ret;
  65
  66         *priv = NULL;
  67         if (bus == NULL)
  68                 return NULL;
  69
  70         ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
  71         if (ret >= 0) {
  72                 if (ret == PORT_SWITCH_ID_6060)
  73                         return "Marvell 88E6060 (A0)";
  74                 if (ret == PORT_SWITCH_ID_6060_R1 ||
  75                     ret == PORT_SWITCH_ID_6060_R2)
  76                         return "Marvell 88E6060 (B0)";
  77                 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
  78                         return "Marvell 88E6060";
  79         }
  80
  81         return NULL;
  82 }
  83
  84 static int mv88e6060_switch_reset(struct dsa_switch *ds)
  85 {
  86         int i;
  87         int ret;
  88         unsigned long timeout;
  89
  90         /* Set all ports to the disabled state. */
  91         for (i = 0; i < MV88E6060_PORTS; i++) {
  92                 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
  93                 REG_WRITE(REG_PORT(i), PORT_CONTROL,
  94                           ret & ~PORT_CONTROL_STATE_MASK);
  95         }
  96
  97         /* Wait for transmit queues to drain. */
  98         usleep_range(2000, 4000);
  99
 100         /* Reset the switch. */
 101         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
 102                   GLOBAL_ATU_CONTROL_SWRESET |
 103                   GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
 104                   GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
 105
 106         /* Wait up to one second for reset to complete. */
 107         timeout = jiffies + 1 * HZ;
 108         while (time_before(jiffies, timeout)) {
 109                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 110                 if (ret & GLOBAL_STATUS_INIT_READY)
 111                         break;
 112
 113                 usleep_range(1000, 2000);
 114         }
 115         if (time_after(jiffies, timeout))
 116                 return -ETIMEDOUT;
 117
 118         return 0;
 119 }
 120
 121 static int mv88e6060_setup_global(struct dsa_switch *ds)
 122 {
 123         /* Disable discarding of frames with excessive collisions,
 124          * set the maximum frame size to 1536 bytes, and mask all
 125          * interrupt sources.
 126          */
 127         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
 128
 129         /* Enable automatic address learning, set the address
 130          * database size to 1024 entries, and set the default aging
 131          * time to 5 minutes.
 132          */
 133         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
 134                   GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
 135                   GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
 136
 137         return 0;
 138 }
 139
 140 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
 141 {
 142         int addr = REG_PORT(p);
 143
 144         /* Do not force flow control, disable Ingress and Egress
 145          * Header tagging, disable VLAN tunneling, and set the port
 146          * state to Forwarding.  Additionally, if this is the CPU
 147          * port, enable Ingress and Egress Trailer tagging mode.
 148          */
 149         REG_WRITE(addr, PORT_CONTROL,
 150                   dsa_is_cpu_port(ds, p) ?
 151                         PORT_CONTROL_TRAILER |
 152                         PORT_CONTROL_INGRESS_MODE |
 153                         PORT_CONTROL_STATE_FORWARDING :
 154                         PORT_CONTROL_STATE_FORWARDING);
 155
 156         /* Port based VLAN map: give each port its own address
 157          * database, allow the CPU port to talk to each of the 'real'
 158          * ports, and allow each of the 'real' ports to only talk to
 159          * the CPU port.
 160          */
 161         REG_WRITE(addr, PORT_VLAN_MAP,
 162                   ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
 163                    (dsa_is_cpu_port(ds, p) ?
 164                         ds->phys_port_mask :
 165                         BIT(ds->dst->cpu_port)));
 166
 167         /* Port Association Vector: when learning source addresses
 168          * of packets, add the address to the address database using
 169          * a port bitmap that has only the bit for this port set and
 170          * the other bits clear.
 171          */
 172         REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
 173
 174         return 0;
 175 }
 176
 177 static int mv88e6060_setup(struct dsa_switch *ds)
 178 {
 179         int i;
 180         int ret;
 181
 182         ret = mv88e6060_switch_reset(ds);
 183         if (ret < 0)
 184                 return ret;
 185
 186         /* @@@ initialise atu */
 187
 188         ret = mv88e6060_setup_global(ds);
 189         if (ret < 0)
 190                 return ret;
 191
 192         for (i = 0; i < MV88E6060_PORTS; i++) {
 193                 ret = mv88e6060_setup_port(ds, i);
 194                 if (ret < 0)
 195                         return ret;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
 202 {
 203         /* Use the same MAC Address as FD Pause frames for all ports */
 204         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
 205         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
 206         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
 207
 208         return 0;
 209 }
 210
 211 static int mv88e6060_port_to_phy_addr(int port)
 212 {
 213         if (port >= 0 && port < MV88E6060_PORTS)
 214                 return port;
 215         return -1;
 216 }
 217
 218 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
 219 {
 220         int addr;
 221
 222         addr = mv88e6060_port_to_phy_addr(port);
 223         if (addr == -1)
 224                 return 0xffff;
 225
 226         return reg_read(ds, addr, regnum);
 227 }
 228
 229 static int
 230 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
 231 {
 232         int addr;
 233
 234         addr = mv88e6060_port_to_phy_addr(port);
 235         if (addr == -1)
 236                 return 0xffff;
 237
 238         return reg_write(ds, addr, regnum, val);
 239 }
 240
 241 static struct dsa_switch_driver mv88e6060_switch_driver = {
 242         .tag_protocol   = DSA_TAG_PROTO_TRAILER,
 243         .probe          = mv88e6060_probe,
 244         .setup          = mv88e6060_setup,
 245         .set_addr       = mv88e6060_set_addr,
 246         .phy_read       = mv88e6060_phy_read,
 247         .phy_write      = mv88e6060_phy_write,
 248 };
 249
 250 static int __init mv88e6060_init(void)
 251 {
 252         register_switch_driver(&mv88e6060_switch_driver);
 253         return 0;
 254 }
 255 module_init(mv88e6060_init);
 256
 257 static void __exit mv88e6060_cleanup(void)
 258 {
 259         unregister_switch_driver(&mv88e6060_switch_driver);
 260 }
 261 module_exit(mv88e6060_cleanup);
 262
 263 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
 264 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
 265 MODULE_LICENSE("GPL");
 266 MODULE_ALIAS("platform:mv88e6060");