drivers/net/dsa/mv88e6060.c

   1 /*
   2  * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6060.h"
  19
  20 static int reg_read(struct dsa_switch *ds, int addr, int reg)
  21 {
  22         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  23
  24         if (bus == NULL)
  25                 return -EINVAL;
  26
  27         return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
  28 }
  29
  30 #define REG_READ(addr, reg)                                     \
  31         ({                                                      \
  32                 int __ret;                                      \
  33                                                                 \
  34                 __ret = reg_read(ds, addr, reg);                \
  35                 if (__ret < 0)                                  \
  36                         return __ret;                           \
  37                 __ret;                                          \
  38         })
  39
  40
  41 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  42 {
  43         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  44
  45         if (bus == NULL)
  46                 return -EINVAL;
  47
  48         return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
  49 }
  50
  51 #define REG_WRITE(addr, reg, val)                               \
  52         ({                                                      \
  53                 int __ret;                                      \
  54                                                                 \
  55                 __ret = reg_write(ds, addr, reg, val);          \
  56                 if (__ret < 0)                                  \
  57                         return __ret;                           \
  58         })
  59
  60 static char *mv88e6060_probe(struct device *dsa_dev, struct device *host_dev,
  61                              int sw_addr)
  62 {
  63         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  64         int ret;
  65
  66         if (bus == NULL)
  67                 return NULL;
  68
  69         ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
  70         if (ret >= 0) {
  71                 if (ret == PORT_SWITCH_ID_6060)
  72                         return "Marvell 88E6060 (A0)";
  73                 if (ret == PORT_SWITCH_ID_6060_R1 ||
  74                     ret == PORT_SWITCH_ID_6060_R2)
  75                         return "Marvell 88E6060 (B0)";
  76                 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
  77                         return "Marvell 88E6060";
  78         }
  79
  80         return NULL;
  81 }
  82
  83 static int mv88e6060_switch_reset(struct dsa_switch *ds)
  84 {
  85         int i;
  86         int ret;
  87         unsigned long timeout;
  88
  89         /* Set all ports to the disabled state. */
  90         for (i = 0; i < MV88E6060_PORTS; i++) {
  91                 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
  92                 REG_WRITE(REG_PORT(i), PORT_CONTROL,
  93                           ret & ~PORT_CONTROL_STATE_MASK);
  94         }
  95
  96         /* Wait for transmit queues to drain. */
  97         usleep_range(2000, 4000);
  98
  99         /* Reset the switch. */
 100         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
 101                   GLOBAL_ATU_CONTROL_SWRESET |
 102                   GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
 103                   GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
 104
 105         /* Wait up to one second for reset to complete. */
 106         timeout = jiffies + 1 * HZ;
 107         while (time_before(jiffies, timeout)) {
 108                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 109                 if (ret & GLOBAL_STATUS_INIT_READY)
 110                         break;
 111
 112                 usleep_range(1000, 2000);
 113         }
 114         if (time_after(jiffies, timeout))
 115                 return -ETIMEDOUT;
 116
 117         return 0;
 118 }
 119
 120 static int mv88e6060_setup_global(struct dsa_switch *ds)
 121 {
 122         /* Disable discarding of frames with excessive collisions,
 123          * set the maximum frame size to 1536 bytes, and mask all
 124          * interrupt sources.
 125          */
 126         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
 127
 128         /* Enable automatic address learning, set the address
 129          * database size to 1024 entries, and set the default aging
 130          * time to 5 minutes.
 131          */
 132         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
 133                   GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
 134                   GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
 135
 136         return 0;
 137 }
 138
 139 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
 140 {
 141         int addr = REG_PORT(p);
 142
 143         /* Do not force flow control, disable Ingress and Egress
 144          * Header tagging, disable VLAN tunneling, and set the port
 145          * state to Forwarding.  Additionally, if this is the CPU
 146          * port, enable Ingress and Egress Trailer tagging mode.
 147          */
 148         REG_WRITE(addr, PORT_CONTROL,
 149                   dsa_is_cpu_port(ds, p) ?
 150                         PORT_CONTROL_TRAILER |
 151                         PORT_CONTROL_INGRESS_MODE |
 152                         PORT_CONTROL_STATE_FORWARDING :
 153                         PORT_CONTROL_STATE_FORWARDING);
 154
 155         /* Port based VLAN map: give each port its own address
 156          * database, allow the CPU port to talk to each of the 'real'
 157          * ports, and allow each of the 'real' ports to only talk to
 158          * the CPU port.
 159          */
 160         REG_WRITE(addr, PORT_VLAN_MAP,
 161                   ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
 162                    (dsa_is_cpu_port(ds, p) ?
 163                         ds->phys_port_mask :
 164                         BIT(ds->dst->cpu_port)));
 165
 166         /* Port Association Vector: when learning source addresses
 167          * of packets, add the address to the address database using
 168          * a port bitmap that has only the bit for this port set and
 169          * the other bits clear.
 170          */
 171         REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
 172
 173         return 0;
 174 }
 175
 176 static int mv88e6060_setup(struct dsa_switch *ds)
 177 {
 178         int i;
 179         int ret;
 180
 181         ret = mv88e6060_switch_reset(ds);
 182         if (ret < 0)
 183                 return ret;
 184
 185         /* @@@ initialise atu */
 186
 187         ret = mv88e6060_setup_global(ds);
 188         if (ret < 0)
 189                 return ret;
 190
 191         for (i = 0; i < MV88E6060_PORTS; i++) {
 192                 ret = mv88e6060_setup_port(ds, i);
 193                 if (ret < 0)
 194                         return ret;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
 201 {
 202         /* Use the same MAC Address as FD Pause frames for all ports */
 203         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
 204         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
 205         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
 206
 207         return 0;
 208 }
 209
 210 static int mv88e6060_port_to_phy_addr(int port)
 211 {
 212         if (port >= 0 && port < MV88E6060_PORTS)
 213                 return port;
 214         return -1;
 215 }
 216
 217 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
 218 {
 219         int addr;
 220
 221         addr = mv88e6060_port_to_phy_addr(port);
 222         if (addr == -1)
 223                 return 0xffff;
 224
 225         return reg_read(ds, addr, regnum);
 226 }
 227
 228 static int
 229 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
 230 {
 231         int addr;
 232
 233         addr = mv88e6060_port_to_phy_addr(port);
 234         if (addr == -1)
 235                 return 0xffff;
 236
 237         return reg_write(ds, addr, regnum, val);
 238 }
 239
 240 static struct dsa_switch_driver mv88e6060_switch_driver = {
 241         .tag_protocol   = DSA_TAG_PROTO_TRAILER,
 242         .probe          = mv88e6060_probe,
 243         .setup          = mv88e6060_setup,
 244         .set_addr       = mv88e6060_set_addr,
 245         .phy_read       = mv88e6060_phy_read,
 246         .phy_write      = mv88e6060_phy_write,
 247 };
 248
 249 static int __init mv88e6060_init(void)
 250 {
 251         register_switch_driver(&mv88e6060_switch_driver);
 252         return 0;
 253 }
 254 module_init(mv88e6060_init);
 255
 256 static void __exit mv88e6060_cleanup(void)
 257 {
 258         unregister_switch_driver(&mv88e6060_switch_driver);
 259 }
 260 module_exit(mv88e6060_cleanup);
 261
 262 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
 263 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
 264 MODULE_LICENSE("GPL");
 265 MODULE_ALIAS("platform:mv88e6060");