drivers/net/dsa/mv88e6131.c

   1 /*
   2  * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 static const struct mv88e6xxx_switch_id mv88e6131_table[] = {
  21         { PORT_SWITCH_ID_6085, "Marvell 88E6085" },
  22         { PORT_SWITCH_ID_6095, "Marvell 88E6095/88E6095F" },
  23         { PORT_SWITCH_ID_6131, "Marvell 88E6131" },
  24         { PORT_SWITCH_ID_6131_B2, "Marvell 88E6131 (B2)" },
  25         { PORT_SWITCH_ID_6185, "Marvell 88E6185" },
  26 };
  27
  28 static char *mv88e6131_drv_probe(struct device *dsa_dev,
  29                                  struct device *host_dev,
  30                                  int sw_addr, void **priv)
  31 {
  32         return mv88e6xxx_drv_probe(dsa_dev, host_dev, sw_addr, priv,
  33                                    mv88e6131_table,
  34                                    ARRAY_SIZE(mv88e6131_table));
  35 }
  36
  37 static int mv88e6131_setup_global(struct dsa_switch *ds)
  38 {
  39         u32 upstream_port = dsa_upstream_port(ds);
  40         int ret;
  41         u32 reg;
  42
  43         ret = mv88e6xxx_setup_global(ds);
  44         if (ret)
  45                 return ret;
  46
  47         /* Enable the PHY polling unit, don't discard packets with
  48          * excessive collisions, use a weighted fair queueing scheme
  49          * to arbitrate between packet queues, set the maximum frame
  50          * size to 1632, and mask all interrupt sources.
  51          */
  52         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
  53                   GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632);
  54
  55         /* Set the VLAN ethertype to 0x8100. */
  56         REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
  57
  58         /* Disable ARP mirroring, and configure the upstream port as
  59          * the port to which ingress and egress monitor frames are to
  60          * be sent.
  61          */
  62         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
  63                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
  64                 GLOBAL_MONITOR_CONTROL_ARP_DISABLED;
  65         REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
  66
  67         /* Disable cascade port functionality unless this device
  68          * is used in a cascade configuration, and set the switch's
  69          * DSA device number.
  70          */
  71         if (ds->dst->pd->nr_chips > 1)
  72                 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
  73                           GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
  74                           (ds->index & 0x1f));
  75         else
  76                 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
  77                           GLOBAL_CONTROL_2_NO_CASCADE |
  78                           (ds->index & 0x1f));
  79
  80         /* Force the priority of IGMP/MLD snoop frames and ARP frames
  81          * to the highest setting.
  82          */
  83         REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
  84                   GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |
  85                   7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |
  86                   GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |
  87                   7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);
  88
  89         return 0;
  90 }
  91
  92 static int mv88e6131_setup(struct dsa_switch *ds)
  93 {
  94         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  95         int ret;
  96
  97         ps->ds = ds;
  98
  99         ret = mv88e6xxx_setup_common(ds);
 100         if (ret < 0)
 101                 return ret;
 102
 103         mv88e6xxx_ppu_state_init(ds);
 104
 105         switch (ps->id) {
 106         case PORT_SWITCH_ID_6085:
 107         case PORT_SWITCH_ID_6185:
 108                 ps->num_ports = 10;
 109                 break;
 110         case PORT_SWITCH_ID_6095:
 111                 ps->num_ports = 11;
 112                 break;
 113         case PORT_SWITCH_ID_6131:
 114         case PORT_SWITCH_ID_6131_B2:
 115                 ps->num_ports = 8;
 116                 break;
 117         default:
 118                 return -ENODEV;
 119         }
 120
 121         ret = mv88e6xxx_switch_reset(ds, false);
 122         if (ret < 0)
 123                 return ret;
 124
 125         ret = mv88e6131_setup_global(ds);
 126         if (ret < 0)
 127                 return ret;
 128
 129         return mv88e6xxx_setup_ports(ds);
 130 }
 131
 132 static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port)
 133 {
 134         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 135
 136         if (port >= 0 && port < ps->num_ports)
 137                 return port;
 138
 139         return -EINVAL;
 140 }
 141
 142 static int
 143 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
 144 {
 145         int addr = mv88e6131_port_to_phy_addr(ds, port);
 146
 147         if (addr < 0)
 148                 return addr;
 149
 150         return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
 151 }
 152
 153 static int
 154 mv88e6131_phy_write(struct dsa_switch *ds,
 155                               int port, int regnum, u16 val)
 156 {
 157         int addr = mv88e6131_port_to_phy_addr(ds, port);
 158
 159         if (addr < 0)
 160                 return addr;
 161
 162         return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
 163 }
 164
 165 struct dsa_switch_driver mv88e6131_switch_driver = {
 166         .tag_protocol           = DSA_TAG_PROTO_DSA,
 167         .probe                  = mv88e6131_drv_probe,
 168         .setup                  = mv88e6131_setup,
 169         .set_addr               = mv88e6xxx_set_addr_direct,
 170         .phy_read               = mv88e6131_phy_read,
 171         .phy_write              = mv88e6131_phy_write,
 172         .get_strings            = mv88e6xxx_get_strings,
 173         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
 174         .get_sset_count         = mv88e6xxx_get_sset_count,
 175         .adjust_link            = mv88e6xxx_adjust_link,
 176         .port_bridge_join       = mv88e6xxx_port_bridge_join,
 177         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
 178         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
 179         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
 180         .port_vlan_add          = mv88e6xxx_port_vlan_add,
 181         .port_vlan_del          = mv88e6xxx_port_vlan_del,
 182         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
 183         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
 184         .port_fdb_add           = mv88e6xxx_port_fdb_add,
 185         .port_fdb_del           = mv88e6xxx_port_fdb_del,
 186         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
 187 };
 188
 189 MODULE_ALIAS("platform:mv88e6085");
 190 MODULE_ALIAS("platform:mv88e6095");
 191 MODULE_ALIAS("platform:mv88e6095f");
 192 MODULE_ALIAS("platform:mv88e6131");