drivers/net/dsa/mv88e6171.c

   1 /* net/dsa/mv88e6171.c - Marvell 88e6171 switch chip support
   2  * Copyright (c) 2008-2009 Marvell Semiconductor
   3  * Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 static char *mv88e6171_probe(struct device *host_dev, int sw_addr)
  21 {
  22         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  23         int ret;
  24
  25         if (bus == NULL)
  26                 return NULL;
  27
  28         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
  29         if (ret >= 0) {
  30                 if ((ret & 0xfff0) == 0x1710)
  31                         return "Marvell 88E6171";
  32         }
  33
  34         return NULL;
  35 }
  36
  37 static int mv88e6171_switch_reset(struct dsa_switch *ds)
  38 {
  39         int i;
  40         int ret;
  41         unsigned long timeout;
  42
  43         /* Set all ports to the disabled state. */
  44         for (i = 0; i < 8; i++) {
  45                 ret = REG_READ(REG_PORT(i), 0x04);
  46                 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  47         }
  48
  49         /* Wait for transmit queues to drain. */
  50         usleep_range(2000, 4000);
  51
  52         /* Reset the switch. */
  53         REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
  54
  55         /* Wait up to one second for reset to complete. */
  56         timeout = jiffies + 1 * HZ;
  57         while (time_before(jiffies, timeout)) {
  58                 ret = REG_READ(REG_GLOBAL, 0x00);
  59                 if ((ret & 0xc800) == 0xc800)
  60                         break;
  61
  62                 usleep_range(1000, 2000);
  63         }
  64         if (time_after(jiffies, timeout))
  65                 return -ETIMEDOUT;
  66
  67         /* Enable ports not under DSA, e.g. WAN port */
  68         for (i = 0; i < 8; i++) {
  69                 if (dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i))
  70                         continue;
  71
  72                 ret = REG_READ(REG_PORT(i), 0x04);
  73                 REG_WRITE(REG_PORT(i), 0x04, ret | 0x03);
  74         }
  75
  76         return 0;
  77 }
  78
  79 static int mv88e6171_setup_global(struct dsa_switch *ds)
  80 {
  81         int ret;
  82         int i;
  83
  84         /* Disable the PHY polling unit (since there won't be any
  85          * external PHYs to poll), don't discard packets with
  86          * excessive collisions, and mask all interrupt sources.
  87          */
  88         REG_WRITE(REG_GLOBAL, 0x04, 0x0000);
  89
  90         /* Set the default address aging time to 5 minutes, and
  91          * enable address learn messages to be sent to all message
  92          * ports.
  93          */
  94         REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
  95
  96         /* Configure the priority mapping registers. */
  97         ret = mv88e6xxx_config_prio(ds);
  98         if (ret < 0)
  99                 return ret;
 100
 101         /* Configure the upstream port, and configure the upstream
 102          * port as the port to which ingress and egress monitor frames
 103          * are to be sent.
 104          */
 105         if (REG_READ(REG_PORT(0), 0x03) == 0x1710)
 106                 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111));
 107         else
 108                 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
 109
 110         /* Disable remote management for now, and set the switch's
 111          * DSA device number.
 112          */
 113         REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
 114
 115         /* Send all frames with destination addresses matching
 116          * 01:80:c2:00:00:2x to the CPU port.
 117          */
 118         REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
 119
 120         /* Send all frames with destination addresses matching
 121          * 01:80:c2:00:00:0x to the CPU port.
 122          */
 123         REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
 124
 125         /* Disable the loopback filter, disable flow control
 126          * messages, disable flood broadcast override, disable
 127          * removing of provider tags, disable ATU age violation
 128          * interrupts, disable tag flow control, force flow
 129          * control priority to the highest, and send all special
 130          * multicast frames to the CPU at the highest priority.
 131          */
 132         REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
 133
 134         /* Program the DSA routing table. */
 135         for (i = 0; i < 32; i++) {
 136                 int nexthop;
 137
 138                 nexthop = 0x1f;
 139                 if (i != ds->index && i < ds->dst->pd->nr_chips)
 140                         nexthop = ds->pd->rtable[i] & 0x1f;
 141
 142                 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
 143         }
 144
 145         /* Clear all trunk masks. */
 146         for (i = 0; i < 8; i++)
 147                 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);
 148
 149         /* Clear all trunk mappings. */
 150         for (i = 0; i < 16; i++)
 151                 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
 152
 153         /* Disable ingress rate limiting by resetting all ingress
 154          * rate limit registers to their initial state.
 155          */
 156         for (i = 0; i < 6; i++)
 157                 REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
 158
 159         /* Initialise cross-chip port VLAN table to reset defaults. */
 160         REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
 161
 162         /* Clear the priority override table. */
 163         for (i = 0; i < 16; i++)
 164                 REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
 165
 166         /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
 167
 168         return 0;
 169 }
 170
 171 static int mv88e6171_setup_port(struct dsa_switch *ds, int p)
 172 {
 173         int addr = REG_PORT(p);
 174         u16 val;
 175
 176         /* MAC Forcing register: don't force link, speed, duplex
 177          * or flow control state to any particular values on physical
 178          * ports, but force the CPU port and all DSA ports to 1000 Mb/s
 179          * full duplex.
 180          */
 181         val = REG_READ(addr, 0x01);
 182         if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
 183                 REG_WRITE(addr, 0x01, val | 0x003e);
 184         else
 185                 REG_WRITE(addr, 0x01, val | 0x0003);
 186
 187         /* Do not limit the period of time that this port can be
 188          * paused for by the remote end or the period of time that
 189          * this port can pause the remote end.
 190          */
 191         REG_WRITE(addr, 0x02, 0x0000);
 192
 193         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
 194          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
 195          * tunneling, determine priority by looking at 802.1p and IP
 196          * priority fields (IP prio has precedence), and set STP state
 197          * to Forwarding.
 198          *
 199          * If this is the CPU link, use DSA or EDSA tagging depending
 200          * on which tagging mode was configured.
 201          *
 202          * If this is a link to another switch, use DSA tagging mode.
 203          *
 204          * If this is the upstream port for this switch, enable
 205          * forwarding of unknown unicasts and multicasts.
 206          */
 207         val = 0x0433;
 208         if (dsa_is_cpu_port(ds, p)) {
 209                 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
 210                         val |= 0x3300;
 211                 else
 212                         val |= 0x0100;
 213         }
 214         if (ds->dsa_port_mask & (1 << p))
 215                 val |= 0x0100;
 216         if (p == dsa_upstream_port(ds))
 217                 val |= 0x000c;
 218         REG_WRITE(addr, 0x04, val);
 219
 220         /* Port Control 1: disable trunking.  Also, if this is the
 221          * CPU port, enable learn messages to be sent to this port.
 222          */
 223         REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
 224
 225         /* Port based VLAN map: give each port its own address
 226          * database, allow the CPU port to talk to each of the 'real'
 227          * ports, and allow each of the 'real' ports to only talk to
 228          * the upstream port.
 229          */
 230         val = (p & 0xf) << 12;
 231         if (dsa_is_cpu_port(ds, p))
 232                 val |= ds->phys_port_mask;
 233         else
 234                 val |= 1 << dsa_upstream_port(ds);
 235         REG_WRITE(addr, 0x06, val);
 236
 237         /* Default VLAN ID and priority: don't set a default VLAN
 238          * ID, and set the default packet priority to zero.
 239          */
 240         REG_WRITE(addr, 0x07, 0x0000);
 241
 242         /* Port Control 2: don't force a good FCS, set the maximum
 243          * frame size to 10240 bytes, don't let the switch add or
 244          * strip 802.1q tags, don't discard tagged or untagged frames
 245          * on this port, do a destination address lookup on all
 246          * received packets as usual, disable ARP mirroring and don't
 247          * send a copy of all transmitted/received frames on this port
 248          * to the CPU.
 249          */
 250         REG_WRITE(addr, 0x08, 0x2080);
 251
 252         /* Egress rate control: disable egress rate control. */
 253         REG_WRITE(addr, 0x09, 0x0001);
 254
 255         /* Egress rate control 2: disable egress rate control. */
 256         REG_WRITE(addr, 0x0a, 0x0000);
 257
 258         /* Port Association Vector: when learning source addresses
 259          * of packets, add the address to the address database using
 260          * a port bitmap that has only the bit for this port set and
 261          * the other bits clear.
 262          */
 263         REG_WRITE(addr, 0x0b, 1 << p);
 264
 265         /* Port ATU control: disable limiting the number of address
 266          * database entries that this port is allowed to use.
 267          */
 268         REG_WRITE(addr, 0x0c, 0x0000);
 269
 270         /* Priority Override: disable DA, SA and VTU priority override. */
 271         REG_WRITE(addr, 0x0d, 0x0000);
 272
 273         /* Port Ethertype: use the Ethertype DSA Ethertype value. */
 274         REG_WRITE(addr, 0x0f, ETH_P_EDSA);
 275
 276         /* Tag Remap: use an identity 802.1p prio -> switch prio
 277          * mapping.
 278          */
 279         REG_WRITE(addr, 0x18, 0x3210);
 280
 281         /* Tag Remap 2: use an identity 802.1p prio -> switch prio
 282          * mapping.
 283          */
 284         REG_WRITE(addr, 0x19, 0x7654);
 285
 286         return 0;
 287 }
 288
 289 static int mv88e6171_setup(struct dsa_switch *ds)
 290 {
 291         struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
 292         int i;
 293         int ret;
 294
 295         mutex_init(&ps->smi_mutex);
 296         mutex_init(&ps->stats_mutex);
 297
 298         ret = mv88e6171_switch_reset(ds);
 299         if (ret < 0)
 300                 return ret;
 301
 302         /* @@@ initialise vtu and atu */
 303
 304         ret = mv88e6171_setup_global(ds);
 305         if (ret < 0)
 306                 return ret;
 307
 308         for (i = 0; i < 8; i++) {
 309                 if (!(dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i)))
 310                         continue;
 311
 312                 ret = mv88e6171_setup_port(ds, i);
 313                 if (ret < 0)
 314                         return ret;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int mv88e6171_port_to_phy_addr(int port)
 321 {
 322         if (port >= 0 && port <= 4)
 323                 return port;
 324         return -1;
 325 }
 326
 327 static int
 328 mv88e6171_phy_read(struct dsa_switch *ds, int port, int regnum)
 329 {
 330         int addr = mv88e6171_port_to_phy_addr(port);
 331
 332         return mv88e6xxx_phy_read(ds, addr, regnum);
 333 }
 334
 335 static int
 336 mv88e6171_phy_write(struct dsa_switch *ds,
 337                     int port, int regnum, u16 val)
 338 {
 339         int addr = mv88e6171_port_to_phy_addr(port);
 340
 341         return mv88e6xxx_phy_write(ds, addr, regnum, val);
 342 }
 343
 344 static struct mv88e6xxx_hw_stat mv88e6171_hw_stats[] = {
 345         { "in_good_octets", 8, 0x00, },
 346         { "in_bad_octets", 4, 0x02, },
 347         { "in_unicast", 4, 0x04, },
 348         { "in_broadcasts", 4, 0x06, },
 349         { "in_multicasts", 4, 0x07, },
 350         { "in_pause", 4, 0x16, },
 351         { "in_undersize", 4, 0x18, },
 352         { "in_fragments", 4, 0x19, },
 353         { "in_oversize", 4, 0x1a, },
 354         { "in_jabber", 4, 0x1b, },
 355         { "in_rx_error", 4, 0x1c, },
 356         { "in_fcs_error", 4, 0x1d, },
 357         { "out_octets", 8, 0x0e, },
 358         { "out_unicast", 4, 0x10, },
 359         { "out_broadcasts", 4, 0x13, },
 360         { "out_multicasts", 4, 0x12, },
 361         { "out_pause", 4, 0x15, },
 362         { "excessive", 4, 0x11, },
 363         { "collisions", 4, 0x1e, },
 364         { "deferred", 4, 0x05, },
 365         { "single", 4, 0x14, },
 366         { "multiple", 4, 0x17, },
 367         { "out_fcs_error", 4, 0x03, },
 368         { "late", 4, 0x1f, },
 369         { "hist_64bytes", 4, 0x08, },
 370         { "hist_65_127bytes", 4, 0x09, },
 371         { "hist_128_255bytes", 4, 0x0a, },
 372         { "hist_256_511bytes", 4, 0x0b, },
 373         { "hist_512_1023bytes", 4, 0x0c, },
 374         { "hist_1024_max_bytes", 4, 0x0d, },
 375 };
 376
 377 static void
 378 mv88e6171_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 379 {
 380         mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6171_hw_stats),
 381                               mv88e6171_hw_stats, port, data);
 382 }
 383
 384 static void
 385 mv88e6171_get_ethtool_stats(struct dsa_switch *ds,
 386                             int port, uint64_t *data)
 387 {
 388         mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6171_hw_stats),
 389                                     mv88e6171_hw_stats, port, data);
 390 }
 391
 392 static int mv88e6171_get_sset_count(struct dsa_switch *ds)
 393 {
 394         return ARRAY_SIZE(mv88e6171_hw_stats);
 395 }
 396
 397 struct dsa_switch_driver mv88e6171_switch_driver = {
 398         .tag_protocol           = DSA_TAG_PROTO_DSA,
 399         .priv_size              = sizeof(struct mv88e6xxx_priv_state),
 400         .probe                  = mv88e6171_probe,
 401         .setup                  = mv88e6171_setup,
 402         .set_addr               = mv88e6xxx_set_addr_indirect,
 403         .phy_read               = mv88e6171_phy_read,
 404         .phy_write              = mv88e6171_phy_write,
 405         .poll_link              = mv88e6xxx_poll_link,
 406         .get_strings            = mv88e6171_get_strings,
 407         .get_ethtool_stats      = mv88e6171_get_ethtool_stats,
 408         .get_sset_count         = mv88e6171_get_sset_count,
 409 };
 410
 411 MODULE_ALIAS("platform:mv88e6171");