drivers/net/dsa/mv88e6xxx.c

   1 /*
   2  * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/if_bridge.h>
  14 #include <linux/jiffies.h>
  15 #include <linux/list.h>
  16 #include <linux/module.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/phy.h>
  19 #include <net/dsa.h>
  20 #include "mv88e6xxx.h"
  21
  22 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
  23  * use all 32 SMI bus addresses on its SMI bus, and all switch registers
  24  * will be directly accessible on some {device address,register address}
  25  * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
  26  * will only respond to SMI transactions to that specific address, and
  27  * an indirect addressing mechanism needs to be used to access its
  28  * registers.
  29  */
  30 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
  31 {
  32         int ret;
  33         int i;
  34
  35         for (i = 0; i < 16; i++) {
  36                 ret = mdiobus_read(bus, sw_addr, SMI_CMD);
  37                 if (ret < 0)
  38                         return ret;
  39
  40                 if ((ret & SMI_CMD_BUSY) == 0)
  41                         return 0;
  42         }
  43
  44         return -ETIMEDOUT;
  45 }
  46
  47 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
  48 {
  49         int ret;
  50
  51         if (sw_addr == 0)
  52                 return mdiobus_read(bus, addr, reg);
  53
  54         /* Wait for the bus to become free. */
  55         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  56         if (ret < 0)
  57                 return ret;
  58
  59         /* Transmit the read command. */
  60         ret = mdiobus_write(bus, sw_addr, SMI_CMD,
  61                             SMI_CMD_OP_22_READ | (addr << 5) | reg);
  62         if (ret < 0)
  63                 return ret;
  64
  65         /* Wait for the read command to complete. */
  66         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  67         if (ret < 0)
  68                 return ret;
  69
  70         /* Read the data. */
  71         ret = mdiobus_read(bus, sw_addr, SMI_DATA);
  72         if (ret < 0)
  73                 return ret;
  74
  75         return ret & 0xffff;
  76 }
  77
  78 /* Must be called with SMI mutex held */
  79 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  80 {
  81         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  82         int ret;
  83
  84         if (bus == NULL)
  85                 return -EINVAL;
  86
  87         ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
  88         if (ret < 0)
  89                 return ret;
  90
  91         dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  92                 addr, reg, ret);
  93
  94         return ret;
  95 }
  96
  97 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  98 {
  99         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 100         int ret;
 101
 102         mutex_lock(&ps->smi_mutex);
 103         ret = _mv88e6xxx_reg_read(ds, addr, reg);
 104         mutex_unlock(&ps->smi_mutex);
 105
 106         return ret;
 107 }
 108
 109 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
 110                           int reg, u16 val)
 111 {
 112         int ret;
 113
 114         if (sw_addr == 0)
 115                 return mdiobus_write(bus, addr, reg, val);
 116
 117         /* Wait for the bus to become free. */
 118         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 119         if (ret < 0)
 120                 return ret;
 121
 122         /* Transmit the data to write. */
 123         ret = mdiobus_write(bus, sw_addr, SMI_DATA, val);
 124         if (ret < 0)
 125                 return ret;
 126
 127         /* Transmit the write command. */
 128         ret = mdiobus_write(bus, sw_addr, SMI_CMD,
 129                             SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 130         if (ret < 0)
 131                 return ret;
 132
 133         /* Wait for the write command to complete. */
 134         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 135         if (ret < 0)
 136                 return ret;
 137
 138         return 0;
 139 }
 140
 141 /* Must be called with SMI mutex held */
 142 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
 143                                 u16 val)
 144 {
 145         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
 146
 147         if (bus == NULL)
 148                 return -EINVAL;
 149
 150         dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 151                 addr, reg, val);
 152
 153         return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
 154 }
 155
 156 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 157 {
 158         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 159         int ret;
 160
 161         mutex_lock(&ps->smi_mutex);
 162         ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
 163         mutex_unlock(&ps->smi_mutex);
 164
 165         return ret;
 166 }
 167
 168 int mv88e6xxx_config_prio(struct dsa_switch *ds)
 169 {
 170         /* Configure the IP ToS mapping registers. */
 171         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
 172         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
 173         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
 174         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
 175         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
 176         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
 177         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
 178         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
 179
 180         /* Configure the IEEE 802.1p priority mapping register. */
 181         REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
 182
 183         return 0;
 184 }
 185
 186 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 187 {
 188         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
 189         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
 190         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
 191
 192         return 0;
 193 }
 194
 195 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 196 {
 197         int i;
 198         int ret;
 199
 200         for (i = 0; i < 6; i++) {
 201                 int j;
 202
 203                 /* Write the MAC address byte. */
 204                 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
 205                           GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
 206
 207                 /* Wait for the write to complete. */
 208                 for (j = 0; j < 16; j++) {
 209                         ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
 210                         if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
 211                                 break;
 212                 }
 213                 if (j == 16)
 214                         return -ETIMEDOUT;
 215         }
 216
 217         return 0;
 218 }
 219
 220 /* Must be called with phy mutex held */
 221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
 222 {
 223         if (addr >= 0)
 224                 return mv88e6xxx_reg_read(ds, addr, regnum);
 225         return 0xffff;
 226 }
 227
 228 /* Must be called with phy mutex held */
 229 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
 230                                 u16 val)
 231 {
 232         if (addr >= 0)
 233                 return mv88e6xxx_reg_write(ds, addr, regnum, val);
 234         return 0;
 235 }
 236
 237 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
 238 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
 239 {
 240         int ret;
 241         unsigned long timeout;
 242
 243         ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
 244         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
 245                   ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 246
 247         timeout = jiffies + 1 * HZ;
 248         while (time_before(jiffies, timeout)) {
 249                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 250                 usleep_range(1000, 2000);
 251                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 252                     GLOBAL_STATUS_PPU_POLLING)
 253                         return 0;
 254         }
 255
 256         return -ETIMEDOUT;
 257 }
 258
 259 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
 260 {
 261         int ret;
 262         unsigned long timeout;
 263
 264         ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
 265         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
 266
 267         timeout = jiffies + 1 * HZ;
 268         while (time_before(jiffies, timeout)) {
 269                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 270                 usleep_range(1000, 2000);
 271                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 272                     GLOBAL_STATUS_PPU_POLLING)
 273                         return 0;
 274         }
 275
 276         return -ETIMEDOUT;
 277 }
 278
 279 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 280 {
 281         struct mv88e6xxx_priv_state *ps;
 282
 283         ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
 284         if (mutex_trylock(&ps->ppu_mutex)) {
 285                 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
 286
 287                 if (mv88e6xxx_ppu_enable(ds) == 0)
 288                         ps->ppu_disabled = 0;
 289                 mutex_unlock(&ps->ppu_mutex);
 290         }
 291 }
 292
 293 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 294 {
 295         struct mv88e6xxx_priv_state *ps = (void *)_ps;
 296
 297         schedule_work(&ps->ppu_work);
 298 }
 299
 300 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
 301 {
 302         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 303         int ret;
 304
 305         mutex_lock(&ps->ppu_mutex);
 306
 307         /* If the PHY polling unit is enabled, disable it so that
 308          * we can access the PHY registers.  If it was already
 309          * disabled, cancel the timer that is going to re-enable
 310          * it.
 311          */
 312         if (!ps->ppu_disabled) {
 313                 ret = mv88e6xxx_ppu_disable(ds);
 314                 if (ret < 0) {
 315                         mutex_unlock(&ps->ppu_mutex);
 316                         return ret;
 317                 }
 318                 ps->ppu_disabled = 1;
 319         } else {
 320                 del_timer(&ps->ppu_timer);
 321                 ret = 0;
 322         }
 323
 324         return ret;
 325 }
 326
 327 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
 328 {
 329         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 330
 331         /* Schedule a timer to re-enable the PHY polling unit. */
 332         mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
 333         mutex_unlock(&ps->ppu_mutex);
 334 }
 335
 336 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
 337 {
 338         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 339
 340         mutex_init(&ps->ppu_mutex);
 341         INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
 342         init_timer(&ps->ppu_timer);
 343         ps->ppu_timer.data = (unsigned long)ps;
 344         ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 345 }
 346
 347 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
 348 {
 349         int ret;
 350
 351         ret = mv88e6xxx_ppu_access_get(ds);
 352         if (ret >= 0) {
 353                 ret = mv88e6xxx_reg_read(ds, addr, regnum);
 354                 mv88e6xxx_ppu_access_put(ds);
 355         }
 356
 357         return ret;
 358 }
 359
 360 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
 361                             int regnum, u16 val)
 362 {
 363         int ret;
 364
 365         ret = mv88e6xxx_ppu_access_get(ds);
 366         if (ret >= 0) {
 367                 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
 368                 mv88e6xxx_ppu_access_put(ds);
 369         }
 370
 371         return ret;
 372 }
 373 #endif
 374
 375 void mv88e6xxx_poll_link(struct dsa_switch *ds)
 376 {
 377         int i;
 378
 379         for (i = 0; i < DSA_MAX_PORTS; i++) {
 380                 struct net_device *dev;
 381                 int uninitialized_var(port_status);
 382                 int link;
 383                 int speed;
 384                 int duplex;
 385                 int fc;
 386
 387                 dev = ds->ports[i];
 388                 if (dev == NULL)
 389                         continue;
 390
 391                 link = 0;
 392                 if (dev->flags & IFF_UP) {
 393                         port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
 394                                                          PORT_STATUS);
 395                         if (port_status < 0)
 396                                 continue;
 397
 398                         link = !!(port_status & PORT_STATUS_LINK);
 399                 }
 400
 401                 if (!link) {
 402                         if (netif_carrier_ok(dev)) {
 403                                 netdev_info(dev, "link down\n");
 404                                 netif_carrier_off(dev);
 405                         }
 406                         continue;
 407                 }
 408
 409                 switch (port_status & PORT_STATUS_SPEED_MASK) {
 410                 case PORT_STATUS_SPEED_10:
 411                         speed = 10;
 412                         break;
 413                 case PORT_STATUS_SPEED_100:
 414                         speed = 100;
 415                         break;
 416                 case PORT_STATUS_SPEED_1000:
 417                         speed = 1000;
 418                         break;
 419                 default:
 420                         speed = -1;
 421                         break;
 422                 }
 423                 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
 424                 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
 425
 426                 if (!netif_carrier_ok(dev)) {
 427                         netdev_info(dev,
 428                                     "link up, %d Mb/s, %s duplex, flow control %sabled\n",
 429                                     speed,
 430                                     duplex ? "full" : "half",
 431                                     fc ? "en" : "dis");
 432                         netif_carrier_on(dev);
 433                 }
 434         }
 435 }
 436
 437 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
 438 {
 439         int ret;
 440         int i;
 441
 442         for (i = 0; i < 10; i++) {
 443                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP);
 444                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 445                         return 0;
 446         }
 447
 448         return -ETIMEDOUT;
 449 }
 450
 451 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
 452 {
 453         int ret;
 454
 455         /* Snapshot the hardware statistics counters for this port. */
 456         REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP,
 457                   GLOBAL_STATS_OP_CAPTURE_PORT |
 458                   GLOBAL_STATS_OP_HIST_RX_TX | port);
 459
 460         /* Wait for the snapshotting to complete. */
 461         ret = mv88e6xxx_stats_wait(ds);
 462         if (ret < 0)
 463                 return ret;
 464
 465         return 0;
 466 }
 467
 468 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
 469 {
 470         u32 _val;
 471         int ret;
 472
 473         *val = 0;
 474
 475         ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
 476                                   GLOBAL_STATS_OP_READ_CAPTURED |
 477                                   GLOBAL_STATS_OP_HIST_RX_TX | stat);
 478         if (ret < 0)
 479                 return;
 480
 481         ret = mv88e6xxx_stats_wait(ds);
 482         if (ret < 0)
 483                 return;
 484
 485         ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 486         if (ret < 0)
 487                 return;
 488
 489         _val = ret << 16;
 490
 491         ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 492         if (ret < 0)
 493                 return;
 494
 495         *val = _val | ret;
 496 }
 497
 498 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 499         { "in_good_octets", 8, 0x00, },
 500         { "in_bad_octets", 4, 0x02, },
 501         { "in_unicast", 4, 0x04, },
 502         { "in_broadcasts", 4, 0x06, },
 503         { "in_multicasts", 4, 0x07, },
 504         { "in_pause", 4, 0x16, },
 505         { "in_undersize", 4, 0x18, },
 506         { "in_fragments", 4, 0x19, },
 507         { "in_oversize", 4, 0x1a, },
 508         { "in_jabber", 4, 0x1b, },
 509         { "in_rx_error", 4, 0x1c, },
 510         { "in_fcs_error", 4, 0x1d, },
 511         { "out_octets", 8, 0x0e, },
 512         { "out_unicast", 4, 0x10, },
 513         { "out_broadcasts", 4, 0x13, },
 514         { "out_multicasts", 4, 0x12, },
 515         { "out_pause", 4, 0x15, },
 516         { "excessive", 4, 0x11, },
 517         { "collisions", 4, 0x1e, },
 518         { "deferred", 4, 0x05, },
 519         { "single", 4, 0x14, },
 520         { "multiple", 4, 0x17, },
 521         { "out_fcs_error", 4, 0x03, },
 522         { "late", 4, 0x1f, },
 523         { "hist_64bytes", 4, 0x08, },
 524         { "hist_65_127bytes", 4, 0x09, },
 525         { "hist_128_255bytes", 4, 0x0a, },
 526         { "hist_256_511bytes", 4, 0x0b, },
 527         { "hist_512_1023bytes", 4, 0x0c, },
 528         { "hist_1024_max_bytes", 4, 0x0d, },
 529         /* Not all devices have the following counters */
 530         { "sw_in_discards", 4, 0x110, },
 531         { "sw_in_filtered", 2, 0x112, },
 532         { "sw_out_filtered", 2, 0x113, },
 533
 534 };
 535
 536 static bool have_sw_in_discards(struct dsa_switch *ds)
 537 {
 538         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 539
 540         switch (ps->id) {
 541         case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
 542         case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
 543         case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
 544         case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
 545         case PORT_SWITCH_ID_6352:
 546                 return true;
 547         default:
 548                 return false;
 549         }
 550 }
 551
 552 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
 553                                    int nr_stats,
 554                                    struct mv88e6xxx_hw_stat *stats,
 555                                    int port, uint8_t *data)
 556 {
 557         int i;
 558
 559         for (i = 0; i < nr_stats; i++) {
 560                 memcpy(data + i * ETH_GSTRING_LEN,
 561                        stats[i].string, ETH_GSTRING_LEN);
 562         }
 563 }
 564
 565 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 566                                          int nr_stats,
 567                                          struct mv88e6xxx_hw_stat *stats,
 568                                          int port, uint64_t *data)
 569 {
 570         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 571         int ret;
 572         int i;
 573
 574         mutex_lock(&ps->stats_mutex);
 575
 576         ret = mv88e6xxx_stats_snapshot(ds, port);
 577         if (ret < 0) {
 578                 mutex_unlock(&ps->stats_mutex);
 579                 return;
 580         }
 581
 582         /* Read each of the counters. */
 583         for (i = 0; i < nr_stats; i++) {
 584                 struct mv88e6xxx_hw_stat *s = stats + i;
 585                 u32 low;
 586                 u32 high = 0;
 587
 588                 if (s->reg >= 0x100) {
 589                         int ret;
 590
 591                         ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
 592                                                  s->reg - 0x100);
 593                         if (ret < 0)
 594                                 goto error;
 595                         low = ret;
 596                         if (s->sizeof_stat == 4) {
 597                                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
 598                                                          s->reg - 0x100 + 1);
 599                                 if (ret < 0)
 600                                         goto error;
 601                                 high = ret;
 602                         }
 603                         data[i] = (((u64)high) << 16) | low;
 604                         continue;
 605                 }
 606                 mv88e6xxx_stats_read(ds, s->reg, &low);
 607                 if (s->sizeof_stat == 8)
 608                         mv88e6xxx_stats_read(ds, s->reg + 1, &high);
 609
 610                 data[i] = (((u64)high) << 32) | low;
 611         }
 612 error:
 613         mutex_unlock(&ps->stats_mutex);
 614 }
 615
 616 /* All the statistics in the table */
 617 void
 618 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 619 {
 620         if (have_sw_in_discards(ds))
 621                 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
 622                                        mv88e6xxx_hw_stats, port, data);
 623         else
 624                 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
 625                                        mv88e6xxx_hw_stats, port, data);
 626 }
 627
 628 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 629 {
 630         if (have_sw_in_discards(ds))
 631                 return ARRAY_SIZE(mv88e6xxx_hw_stats);
 632         return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
 633 }
 634
 635 void
 636 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 637                             int port, uint64_t *data)
 638 {
 639         if (have_sw_in_discards(ds))
 640                 _mv88e6xxx_get_ethtool_stats(
 641                         ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
 642                         mv88e6xxx_hw_stats, port, data);
 643         else
 644                 _mv88e6xxx_get_ethtool_stats(
 645                         ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
 646                         mv88e6xxx_hw_stats, port, data);
 647 }
 648
 649 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 650 {
 651         return 32 * sizeof(u16);
 652 }
 653
 654 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 655                         struct ethtool_regs *regs, void *_p)
 656 {
 657         u16 *p = _p;
 658         int i;
 659
 660         regs->version = 0;
 661
 662         memset(p, 0xff, 32 * sizeof(u16));
 663
 664         for (i = 0; i < 32; i++) {
 665                 int ret;
 666
 667                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
 668                 if (ret >= 0)
 669                         p[i] = ret;
 670         }
 671 }
 672
 673 #ifdef CONFIG_NET_DSA_HWMON
 674
 675 int  mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
 676 {
 677         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 678         int ret;
 679         int val;
 680
 681         *temp = 0;
 682
 683         mutex_lock(&ps->phy_mutex);
 684
 685         ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
 686         if (ret < 0)
 687                 goto error;
 688
 689         /* Enable temperature sensor */
 690         ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
 691         if (ret < 0)
 692                 goto error;
 693
 694         ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
 695         if (ret < 0)
 696                 goto error;
 697
 698         /* Wait for temperature to stabilize */
 699         usleep_range(10000, 12000);
 700
 701         val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
 702         if (val < 0) {
 703                 ret = val;
 704                 goto error;
 705         }
 706
 707         /* Disable temperature sensor */
 708         ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
 709         if (ret < 0)
 710                 goto error;
 711
 712         *temp = ((val & 0x1f) - 5) * 5;
 713
 714 error:
 715         _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
 716         mutex_unlock(&ps->phy_mutex);
 717         return ret;
 718 }
 719 #endif /* CONFIG_NET_DSA_HWMON */
 720
 721 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 722 {
 723         unsigned long timeout = jiffies + HZ / 10;
 724
 725         while (time_before(jiffies, timeout)) {
 726                 int ret;
 727
 728                 ret = REG_READ(reg, offset);
 729                 if (!(ret & mask))
 730                         return 0;
 731
 732                 usleep_range(1000, 2000);
 733         }
 734         return -ETIMEDOUT;
 735 }
 736
 737 int mv88e6xxx_phy_wait(struct dsa_switch *ds)
 738 {
 739         return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
 740                               GLOBAL2_SMI_OP_BUSY);
 741 }
 742
 743 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 744 {
 745         return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 746                               GLOBAL2_EEPROM_OP_LOAD);
 747 }
 748
 749 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 750 {
 751         return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 752                               GLOBAL2_EEPROM_OP_BUSY);
 753 }
 754
 755 /* Must be called with SMI lock held */
 756 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 757 {
 758         unsigned long timeout = jiffies + HZ / 10;
 759
 760         while (time_before(jiffies, timeout)) {
 761                 int ret;
 762
 763                 ret = _mv88e6xxx_reg_read(ds, reg, offset);
 764                 if (ret < 0)
 765                         return ret;
 766                 if (!(ret & mask))
 767                         return 0;
 768
 769                 usleep_range(1000, 2000);
 770         }
 771         return -ETIMEDOUT;
 772 }
 773
 774 /* Must be called with SMI lock held */
 775 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
 776 {
 777         return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
 778                                GLOBAL_ATU_OP_BUSY);
 779 }
 780
 781 /* Must be called with phy mutex held */
 782 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
 783                                         int regnum)
 784 {
 785         int ret;
 786
 787         REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_OP,
 788                   GLOBAL2_SMI_OP_22_READ | (addr << 5) | regnum);
 789
 790         ret = mv88e6xxx_phy_wait(ds);
 791         if (ret < 0)
 792                 return ret;
 793
 794         return REG_READ(REG_GLOBAL2, GLOBAL2_SMI_DATA);
 795 }
 796
 797 /* Must be called with phy mutex held */
 798 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
 799                                          int regnum, u16 val)
 800 {
 801         REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
 802         REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_OP,
 803                   GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | regnum);
 804
 805         return mv88e6xxx_phy_wait(ds);
 806 }
 807
 808 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
 809 {
 810         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 811         int reg;
 812
 813         mutex_lock(&ps->phy_mutex);
 814
 815         reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
 816         if (reg < 0)
 817                 goto out;
 818
 819         e->eee_enabled = !!(reg & 0x0200);
 820         e->tx_lpi_enabled = !!(reg & 0x0100);
 821
 822         reg = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
 823         if (reg < 0)
 824                 goto out;
 825
 826         e->eee_active = !!(reg & PORT_STATUS_EEE);
 827         reg = 0;
 828
 829 out:
 830         mutex_unlock(&ps->phy_mutex);
 831         return reg;
 832 }
 833
 834 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 835                       struct phy_device *phydev, struct ethtool_eee *e)
 836 {
 837         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 838         int reg;
 839         int ret;
 840
 841         mutex_lock(&ps->phy_mutex);
 842
 843         ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
 844         if (ret < 0)
 845                 goto out;
 846
 847         reg = ret & ~0x0300;
 848         if (e->eee_enabled)
 849                 reg |= 0x0200;
 850         if (e->tx_lpi_enabled)
 851                 reg |= 0x0100;
 852
 853         ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
 854 out:
 855         mutex_unlock(&ps->phy_mutex);
 856
 857         return ret;
 858 }
 859
 860 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
 861 {
 862         int ret;
 863
 864         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
 865         if (ret < 0)
 866                 return ret;
 867
 868         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
 869         if (ret < 0)
 870                 return ret;
 871
 872         return _mv88e6xxx_atu_wait(ds);
 873 }
 874
 875 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
 876 {
 877         int ret;
 878
 879         ret = _mv88e6xxx_atu_wait(ds);
 880         if (ret < 0)
 881                 return ret;
 882
 883         return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
 884 }
 885
 886 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
 887 {
 888         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 889         int reg, ret;
 890         u8 oldstate;
 891
 892         mutex_lock(&ps->smi_mutex);
 893
 894         reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
 895         if (reg < 0)
 896                 goto abort;
 897
 898         oldstate = reg & PORT_CONTROL_STATE_MASK;
 899         if (oldstate != state) {
 900                 /* Flush forwarding database if we're moving a port
 901                  * from Learning or Forwarding state to Disabled or
 902                  * Blocking or Listening state.
 903                  */
 904                 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
 905                     state <= PORT_CONTROL_STATE_BLOCKING) {
 906                         ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
 907                         if (ret)
 908                                 goto abort;
 909                 }
 910                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
 911                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
 912                                            reg);
 913         }
 914
 915 abort:
 916         mutex_unlock(&ps->smi_mutex);
 917         return ret;
 918 }
 919
 920 /* Must be called with smi lock held */
 921 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
 922 {
 923         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 924         u8 fid = ps->fid[port];
 925         u16 reg = fid << 12;
 926
 927         if (dsa_is_cpu_port(ds, port))
 928                 reg |= ds->phys_port_mask;
 929         else
 930                 reg |= (ps->bridge_mask[fid] |
 931                        (1 << dsa_upstream_port(ds))) & ~(1 << port);
 932
 933         return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
 934 }
 935
 936 /* Must be called with smi lock held */
 937 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
 938 {
 939         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 940         int port;
 941         u32 mask;
 942         int ret;
 943
 944         mask = ds->phys_port_mask;
 945         while (mask) {
 946                 port = __ffs(mask);
 947                 mask &= ~(1 << port);
 948                 if (ps->fid[port] != fid)
 949                         continue;
 950
 951                 ret = _mv88e6xxx_update_port_config(ds, port);
 952                 if (ret)
 953                         return ret;
 954         }
 955
 956         return _mv88e6xxx_flush_fid(ds, fid);
 957 }
 958
 959 /* Bridge handling functions */
 960
 961 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
 962 {
 963         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 964         int ret = 0;
 965         u32 nmask;
 966         int fid;
 967
 968         /* If the bridge group is not empty, join that group.
 969          * Otherwise create a new group.
 970          */
 971         fid = ps->fid[port];
 972         nmask = br_port_mask & ~(1 << port);
 973         if (nmask)
 974                 fid = ps->fid[__ffs(nmask)];
 975
 976         nmask = ps->bridge_mask[fid] | (1 << port);
 977         if (nmask != br_port_mask) {
 978                 netdev_err(ds->ports[port],
 979                            "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
 980                            fid, br_port_mask, nmask);
 981                 return -EINVAL;
 982         }
 983
 984         mutex_lock(&ps->smi_mutex);
 985
 986         ps->bridge_mask[fid] = br_port_mask;
 987
 988         if (fid != ps->fid[port]) {
 989                 ps->fid_mask |= 1 << ps->fid[port];
 990                 ps->fid[port] = fid;
 991                 ret = _mv88e6xxx_update_bridge_config(ds, fid);
 992         }
 993
 994         mutex_unlock(&ps->smi_mutex);
 995
 996         return ret;
 997 }
 998
 999 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1000 {
1001         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1002         u8 fid, newfid;
1003         int ret;
1004
1005         fid = ps->fid[port];
1006
1007         if (ps->bridge_mask[fid] != br_port_mask) {
1008                 netdev_err(ds->ports[port],
1009                            "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1010                            fid, br_port_mask, ps->bridge_mask[fid]);
1011                 return -EINVAL;
1012         }
1013
1014         /* If the port was the last port of a bridge, we are done.
1015          * Otherwise assign a new fid to the port, and fix up
1016          * the bridge configuration.
1017          */
1018         if (br_port_mask == (1 << port))
1019                 return 0;
1020
1021         mutex_lock(&ps->smi_mutex);
1022
1023         newfid = __ffs(ps->fid_mask);
1024         ps->fid[port] = newfid;
1025         ps->fid_mask &= (1 << newfid);
1026         ps->bridge_mask[fid] &= ~(1 << port);
1027         ps->bridge_mask[newfid] = 1 << port;
1028
1029         ret = _mv88e6xxx_update_bridge_config(ds, fid);
1030         if (!ret)
1031                 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1032
1033         mutex_unlock(&ps->smi_mutex);
1034
1035         return ret;
1036 }
1037
1038 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1039 {
1040         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1041         int stp_state;
1042
1043         switch (state) {
1044         case BR_STATE_DISABLED:
1045                 stp_state = PORT_CONTROL_STATE_DISABLED;
1046                 break;
1047         case BR_STATE_BLOCKING:
1048         case BR_STATE_LISTENING:
1049                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1050                 break;
1051         case BR_STATE_LEARNING:
1052                 stp_state = PORT_CONTROL_STATE_LEARNING;
1053                 break;
1054         case BR_STATE_FORWARDING:
1055         default:
1056                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1057                 break;
1058         }
1059
1060         netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1061
1062         /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1063          * so we can not update the port state directly but need to schedule it.
1064          */
1065         ps->port_state[port] = stp_state;
1066         set_bit(port, &ps->port_state_update_mask);
1067         schedule_work(&ps->bridge_work);
1068
1069         return 0;
1070 }
1071
1072 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
1073                                   const unsigned char *addr)
1074 {
1075         int i, ret;
1076
1077         for (i = 0; i < 3; i++) {
1078                 ret = _mv88e6xxx_reg_write(
1079                         ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1080                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
1081                 if (ret < 0)
1082                         return ret;
1083         }
1084
1085         return 0;
1086 }
1087
1088 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
1089 {
1090         int i, ret;
1091
1092         for (i = 0; i < 3; i++) {
1093                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1094                                           GLOBAL_ATU_MAC_01 + i);
1095                 if (ret < 0)
1096                         return ret;
1097                 addr[i * 2] = ret >> 8;
1098                 addr[i * 2 + 1] = ret & 0xff;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
1105                                     const unsigned char *addr, int state)
1106 {
1107         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1108         u8 fid = ps->fid[port];
1109         int ret;
1110
1111         ret = _mv88e6xxx_atu_wait(ds);
1112         if (ret < 0)
1113                 return ret;
1114
1115         ret = __mv88e6xxx_write_addr(ds, addr);
1116         if (ret < 0)
1117                 return ret;
1118
1119         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
1120                                    (0x10 << port) | state);
1121         if (ret)
1122                 return ret;
1123
1124         ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
1125
1126         return ret;
1127 }
1128
1129 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1130                            const unsigned char *addr, u16 vid)
1131 {
1132         int state = is_multicast_ether_addr(addr) ?
1133                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1134                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1135         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1136         int ret;
1137
1138         mutex_lock(&ps->smi_mutex);
1139         ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1140         mutex_unlock(&ps->smi_mutex);
1141
1142         return ret;
1143 }
1144
1145 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1146                            const unsigned char *addr, u16 vid)
1147 {
1148         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1149         int ret;
1150
1151         mutex_lock(&ps->smi_mutex);
1152         ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
1153                                        GLOBAL_ATU_DATA_STATE_UNUSED);
1154         mutex_unlock(&ps->smi_mutex);
1155
1156         return ret;
1157 }
1158
1159 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1160                                     unsigned char *addr, bool *is_static)
1161 {
1162         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1163         u8 fid = ps->fid[port];
1164         int ret, state;
1165
1166         ret = _mv88e6xxx_atu_wait(ds);
1167         if (ret < 0)
1168                 return ret;
1169
1170         ret = __mv88e6xxx_write_addr(ds, addr);
1171         if (ret < 0)
1172                 return ret;
1173
1174         do {
1175                 ret = _mv88e6xxx_atu_cmd(ds, fid,  GLOBAL_ATU_OP_GET_NEXT_DB);
1176                 if (ret < 0)
1177                         return ret;
1178
1179                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1180                 if (ret < 0)
1181                         return ret;
1182                 state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1183                 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1184                         return -ENOENT;
1185         } while (!(((ret >> 4) & 0xff) & (1 << port)));
1186
1187         ret = __mv88e6xxx_read_addr(ds, addr);
1188         if (ret < 0)
1189                 return ret;
1190
1191         *is_static = state == (is_multicast_ether_addr(addr) ?
1192                                GLOBAL_ATU_DATA_STATE_MC_STATIC :
1193                                GLOBAL_ATU_DATA_STATE_UC_STATIC);
1194
1195         return 0;
1196 }
1197
1198 /* get next entry for port */
1199 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1200                                unsigned char *addr, bool *is_static)
1201 {
1202         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1203         int ret;
1204
1205         mutex_lock(&ps->smi_mutex);
1206         ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1207         mutex_unlock(&ps->smi_mutex);
1208
1209         return ret;
1210 }
1211
1212 static void mv88e6xxx_bridge_work(struct work_struct *work)
1213 {
1214         struct mv88e6xxx_priv_state *ps;
1215         struct dsa_switch *ds;
1216         int port;
1217
1218         ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1219         ds = ((struct dsa_switch *)ps) - 1;
1220
1221         while (ps->port_state_update_mask) {
1222                 port = __ffs(ps->port_state_update_mask);
1223                 clear_bit(port, &ps->port_state_update_mask);
1224                 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1225         }
1226 }
1227
1228 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
1229 {
1230         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1231         int ret, fid;
1232
1233         mutex_lock(&ps->smi_mutex);
1234
1235         /* Port Control 1: disable trunking, disable sending
1236          * learning messages to this port.
1237          */
1238         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1239                                    0x0000);
1240         if (ret)
1241                 goto abort;
1242
1243         /* Port based VLAN map: give each port its own address
1244          * database, allow the CPU port to talk to each of the 'real'
1245          * ports, and allow each of the 'real' ports to only talk to
1246          * the upstream port.
1247          */
1248         fid = __ffs(ps->fid_mask);
1249         ps->fid[port] = fid;
1250         ps->fid_mask &= ~(1 << fid);
1251
1252         if (!dsa_is_cpu_port(ds, port))
1253                 ps->bridge_mask[fid] = 1 << port;
1254
1255         ret = _mv88e6xxx_update_port_config(ds, port);
1256         if (ret)
1257                 goto abort;
1258
1259         /* Default VLAN ID and priority: don't set a default VLAN
1260          * ID, and set the default packet priority to zero.
1261          */
1262         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
1263 abort:
1264         mutex_unlock(&ps->smi_mutex);
1265         return ret;
1266 }
1267
1268 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1269 {
1270         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1271
1272         mutex_init(&ps->smi_mutex);
1273         mutex_init(&ps->stats_mutex);
1274         mutex_init(&ps->phy_mutex);
1275
1276         ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1277
1278         ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1279
1280         INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1281
1282         return 0;
1283 }
1284
1285 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
1286 {
1287         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1288         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
1289         unsigned long timeout;
1290         int ret;
1291         int i;
1292
1293         /* Set all ports to the disabled state. */
1294         for (i = 0; i < ps->num_ports; i++) {
1295                 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
1296                 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
1297         }
1298
1299         /* Wait for transmit queues to drain. */
1300         usleep_range(2000, 4000);
1301
1302         /* Reset the switch. Keep the PPU active if requested. The PPU
1303          * needs to be active to support indirect phy register access
1304          * through global registers 0x18 and 0x19.
1305          */
1306         if (ppu_active)
1307                 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
1308         else
1309                 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
1310
1311         /* Wait up to one second for reset to complete. */
1312         timeout = jiffies + 1 * HZ;
1313         while (time_before(jiffies, timeout)) {
1314                 ret = REG_READ(REG_GLOBAL, 0x00);
1315                 if ((ret & is_reset) == is_reset)
1316                         break;
1317                 usleep_range(1000, 2000);
1318         }
1319         if (time_after(jiffies, timeout))
1320                 return -ETIMEDOUT;
1321
1322         return 0;
1323 }
1324
1325 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
1326 {
1327         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1328         int ret;
1329
1330         mutex_lock(&ps->phy_mutex);
1331         ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
1332         if (ret < 0)
1333                 goto error;
1334         ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
1335 error:
1336         _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
1337         mutex_unlock(&ps->phy_mutex);
1338         return ret;
1339 }
1340
1341 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
1342                              int reg, int val)
1343 {
1344         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1345         int ret;
1346
1347         mutex_lock(&ps->phy_mutex);
1348         ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
1349         if (ret < 0)
1350                 goto error;
1351
1352         ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
1353 error:
1354         _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
1355         mutex_unlock(&ps->phy_mutex);
1356         return ret;
1357 }
1358
1359 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
1360 {
1361         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1362
1363         if (port >= 0 && port < ps->num_ports)
1364                 return port;
1365         return -EINVAL;
1366 }
1367
1368 int
1369 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
1370 {
1371         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1372         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1373         int ret;
1374
1375         if (addr < 0)
1376                 return addr;
1377
1378         mutex_lock(&ps->phy_mutex);
1379         ret = _mv88e6xxx_phy_read(ds, addr, regnum);
1380         mutex_unlock(&ps->phy_mutex);
1381         return ret;
1382 }
1383
1384 int
1385 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
1386 {
1387         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1388         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1389         int ret;
1390
1391         if (addr < 0)
1392                 return addr;
1393
1394         mutex_lock(&ps->phy_mutex);
1395         ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
1396         mutex_unlock(&ps->phy_mutex);
1397         return ret;
1398 }
1399
1400 int
1401 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
1402 {
1403         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1404         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1405         int ret;
1406
1407         if (addr < 0)
1408                 return addr;
1409
1410         mutex_lock(&ps->phy_mutex);
1411         ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
1412         mutex_unlock(&ps->phy_mutex);
1413         return ret;
1414 }
1415
1416 int
1417 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
1418                              u16 val)
1419 {
1420         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1421         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1422         int ret;
1423
1424         if (addr < 0)
1425                 return addr;
1426
1427         mutex_lock(&ps->phy_mutex);
1428         ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
1429         mutex_unlock(&ps->phy_mutex);
1430         return ret;
1431 }
1432
1433 static int __init mv88e6xxx_init(void)
1434 {
1435 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1436         register_switch_driver(&mv88e6131_switch_driver);
1437 #endif
1438 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1439         register_switch_driver(&mv88e6123_61_65_switch_driver);
1440 #endif
1441 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1442         register_switch_driver(&mv88e6352_switch_driver);
1443 #endif
1444 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1445         register_switch_driver(&mv88e6171_switch_driver);
1446 #endif
1447         return 0;
1448 }
1449 module_init(mv88e6xxx_init);
1450
1451 static void __exit mv88e6xxx_cleanup(void)
1452 {
1453 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1454         unregister_switch_driver(&mv88e6171_switch_driver);
1455 #endif
1456 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1457         unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1458 #endif
1459 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1460         unregister_switch_driver(&mv88e6131_switch_driver);
1461 #endif
1462 }
1463 module_exit(mv88e6xxx_cleanup);
1464
1465 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1466 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1467 MODULE_LICENSE("GPL");