projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branches 'work.lookups', 'work.misc' and 'work.preadv2' into for-next
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
1 /*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
24 #include <net/dsa.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
27
28 static void assert_smi_lock(struct dsa_switch *ds)
29 {
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
31
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
34 dump_stack();
35 }
36 }
37
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
44 * registers.
45 */
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
47 {
48 int ret;
49 int i;
50
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
53 if (ret < 0)
54 return ret;
55
56 if ((ret & SMI_CMD_BUSY) == 0)
57 return 0;
58 }
59
60 return -ETIMEDOUT;
61 }
62
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
64 int reg)
65 {
66 int ret;
67
68 if (sw_addr == 0)
69 return mdiobus_read_nested(bus, addr, reg);
70
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
73 if (ret < 0)
74 return ret;
75
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
79 if (ret < 0)
80 return ret;
81
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
84 if (ret < 0)
85 return ret;
86
87 /* Read the data. */
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
89 if (ret < 0)
90 return ret;
91
92 return ret & 0xffff;
93 }
94
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
96 {
97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
98 int ret;
99
100 assert_smi_lock(ds);
101
102 if (bus == NULL)
103 return -EINVAL;
104
105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
106 if (ret < 0)
107 return ret;
108
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
110 addr, reg, ret);
111
112 return ret;
113 }
114
115 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
116 {
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
118 int ret;
119
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
123
124 return ret;
125 }
126
127 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
128 int reg, u16 val)
129 {
130 int ret;
131
132 if (sw_addr == 0)
133 return mdiobus_write_nested(bus, addr, reg, val);
134
135 /* Wait for the bus to become free. */
136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 if (ret < 0)
138 return ret;
139
140 /* Transmit the data to write. */
141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
142 if (ret < 0)
143 return ret;
144
145 /* Transmit the write command. */
146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
148 if (ret < 0)
149 return ret;
150
151 /* Wait for the write command to complete. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
153 if (ret < 0)
154 return ret;
155
156 return 0;
157 }
158
159 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
160 u16 val)
161 {
162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
163
164 assert_smi_lock(ds);
165
166 if (bus == NULL)
167 return -EINVAL;
168
169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
170 addr, reg, val);
171
172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
173 }
174
175 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
176 {
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
178 int ret;
179
180 mutex_lock(&ps->smi_mutex);
181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
182 mutex_unlock(&ps->smi_mutex);
183
184 return ret;
185 }
186
187 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
188 {
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
192
193 return 0;
194 }
195
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
197 {
198 int i;
199 int ret;
200
201 for (i = 0; i < 6; i++) {
202 int j;
203
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
207
208 /* Wait for the write to complete. */
209 for (j = 0; j < 16; j++) {
210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
212 break;
213 }
214 if (j == 16)
215 return -ETIMEDOUT;
216 }
217
218 return 0;
219 }
220
221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
222 {
223 if (addr >= 0)
224 return _mv88e6xxx_reg_read(ds, addr, regnum);
225 return 0xffff;
226 }
227
228 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
229 u16 val)
230 {
231 if (addr >= 0)
232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
233 return 0;
234 }
235
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
238 {
239 int ret;
240 unsigned long timeout;
241
242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
245
246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
249 usleep_range(1000, 2000);
250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
252 return 0;
253 }
254
255 return -ETIMEDOUT;
256 }
257
258 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
259 {
260 int ret;
261 unsigned long timeout;
262
263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
265
266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
269 usleep_range(1000, 2000);
270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
272 return 0;
273 }
274
275 return -ETIMEDOUT;
276 }
277
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
279 {
280 struct mv88e6xxx_priv_state *ps;
281
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
285
286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
289 }
290 }
291
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
293 {
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
295
296 schedule_work(&ps->ppu_work);
297 }
298
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
300 {
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
302 int ret;
303
304 mutex_lock(&ps->ppu_mutex);
305
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
309 * it.
310 */
311 if (!ps->ppu_disabled) {
312 ret = mv88e6xxx_ppu_disable(ds);
313 if (ret < 0) {
314 mutex_unlock(&ps->ppu_mutex);
315 return ret;
316 }
317 ps->ppu_disabled = 1;
318 } else {
319 del_timer(&ps->ppu_timer);
320 ret = 0;
321 }
322
323 return ret;
324 }
325
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
327 {
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
329
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
333 }
334
335 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
336 {
337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
338
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
344 }
345
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
347 {
348 int ret;
349
350 ret = mv88e6xxx_ppu_access_get(ds);
351 if (ret >= 0) {
352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
354 }
355
356 return ret;
357 }
358
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
360 int regnum, u16 val)
361 {
362 int ret;
363
364 ret = mv88e6xxx_ppu_access_get(ds);
365 if (ret >= 0) {
366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
368 }
369
370 return ret;
371 }
372 #endif
373
374 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
375 {
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
377
378 switch (ps->id) {
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
383 return true;
384 }
385 return false;
386 }
387
388 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
389 {
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
391
392 switch (ps->id) {
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
395 return true;
396 }
397 return false;
398 }
399
400 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
401 {
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
403
404 switch (ps->id) {
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
409 return true;
410 }
411 return false;
412 }
413
414 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
415 {
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
417
418 switch (ps->id) {
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
422 return true;
423 }
424 return false;
425 }
426
427 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
428 {
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
430
431 switch (ps->id) {
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
440 return true;
441 }
442 return false;
443 }
444
445 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
446 {
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448
449 switch (ps->id) {
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
452 return true;
453 }
454 return false;
455 }
456
457 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
458 {
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
460
461 switch (ps->id) {
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
466 return true;
467 }
468 return false;
469 }
470
471 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
472 {
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
474
475 switch (ps->id) {
476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
480 return true;
481 }
482 return false;
483 }
484
485 /* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
488 */
489 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
491 {
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
493 u32 reg;
494 int ret;
495
496 if (!phy_is_pseudo_fixed_link(phydev))
497 return;
498
499 mutex_lock(&ps->smi_mutex);
500
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
502 if (ret < 0)
503 goto out;
504
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
510
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
512 if (phydev->link)
513 reg |= PORT_PCS_CTRL_LINK_UP;
514
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
516 goto out;
517
518 switch (phydev->speed) {
519 case SPEED_1000:
520 reg |= PORT_PCS_CTRL_1000;
521 break;
522 case SPEED_100:
523 reg |= PORT_PCS_CTRL_100;
524 break;
525 case SPEED_10:
526 reg |= PORT_PCS_CTRL_10;
527 break;
528 default:
529 pr_info("Unknown speed");
530 goto out;
531 }
532
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
536
537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
546 }
547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
548
549 out:
550 mutex_unlock(&ps->smi_mutex);
551 }
552
553 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
554 {
555 int ret;
556 int i;
557
558 for (i = 0; i < 10; i++) {
559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
561 return 0;
562 }
563
564 return -ETIMEDOUT;
565 }
566
567 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
568 {
569 int ret;
570
571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
572 port = (port + 1) << 5;
573
574 /* Snapshot the hardware statistics counters for this port. */
575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
578 if (ret < 0)
579 return ret;
580
581 /* Wait for the snapshotting to complete. */
582 ret = _mv88e6xxx_stats_wait(ds);
583 if (ret < 0)
584 return ret;
585
586 return 0;
587 }
588
589 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
590 {
591 u32 _val;
592 int ret;
593
594 *val = 0;
595
596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
599 if (ret < 0)
600 return;
601
602 ret = _mv88e6xxx_stats_wait(ds);
603 if (ret < 0)
604 return;
605
606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
607 if (ret < 0)
608 return;
609
610 _val = ret << 16;
611
612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
613 if (ret < 0)
614 return;
615
616 *val = _val | ret;
617 }
618
619 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 };
680
681 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
683 {
684 switch (stat->type) {
685 case BANK0:
686 return true;
687 case BANK1:
688 return mv88e6xxx_6320_family(ds);
689 case PORT:
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
696 }
697 return false;
698 }
699
700 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
701 struct mv88e6xxx_hw_stat *s,
702 int port)
703 {
704 u32 low;
705 u32 high = 0;
706 int ret;
707 u64 value;
708
709 switch (s->type) {
710 case PORT:
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
712 if (ret < 0)
713 return UINT64_MAX;
714
715 low = ret;
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
718 s->reg + 1);
719 if (ret < 0)
720 return UINT64_MAX;
721 high = ret;
722 }
723 break;
724 case BANK0:
725 case BANK1:
726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
729 }
730 value = (((u64)high) << 16) | low;
731 return value;
732 }
733
734 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
735 {
736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
738
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
743 ETH_GSTRING_LEN);
744 j++;
745 }
746 }
747 }
748
749 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
750 {
751 struct mv88e6xxx_hw_stat *stat;
752 int i, j;
753
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
757 j++;
758 }
759 return j;
760 }
761
762 void
763 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
765 {
766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
768 int ret;
769 int i, j;
770
771 mutex_lock(&ps->smi_mutex);
772
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
774 if (ret < 0) {
775 mutex_unlock(&ps->smi_mutex);
776 return;
777 }
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
782 j++;
783 }
784 }
785
786 mutex_unlock(&ps->smi_mutex);
787 }
788
789 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
790 {
791 return 32 * sizeof(u16);
792 }
793
794 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
796 {
797 u16 *p = _p;
798 int i;
799
800 regs->version = 0;
801
802 memset(p, 0xff, 32 * sizeof(u16));
803
804 for (i = 0; i < 32; i++) {
805 int ret;
806
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
808 if (ret >= 0)
809 p[i] = ret;
810 }
811 }
812
813 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
814 u16 mask)
815 {
816 unsigned long timeout = jiffies + HZ / 10;
817
818 while (time_before(jiffies, timeout)) {
819 int ret;
820
821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
822 if (ret < 0)
823 return ret;
824 if (!(ret & mask))
825 return 0;
826
827 usleep_range(1000, 2000);
828 }
829 return -ETIMEDOUT;
830 }
831
832 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833 {
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
835 int ret;
836
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
840
841 return ret;
842 }
843
844 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
845 {
846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
848 }
849
850 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851 {
852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
854 }
855
856 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857 {
858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
860 }
861
862 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
863 {
864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
865 GLOBAL_ATU_OP_BUSY);
866 }
867
868 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
869 int regnum)
870 {
871 int ret;
872
873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
875 regnum);
876 if (ret < 0)
877 return ret;
878
879 ret = _mv88e6xxx_phy_wait(ds);
880 if (ret < 0)
881 return ret;
882
883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
884 }
885
886 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
887 int regnum, u16 val)
888 {
889 int ret;
890
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
892 if (ret < 0)
893 return ret;
894
895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
897 regnum);
898
899 return _mv88e6xxx_phy_wait(ds);
900 }
901
902 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
903 {
904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
905 int reg;
906
907 mutex_lock(&ps->smi_mutex);
908
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
910 if (reg < 0)
911 goto out;
912
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
915
916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
917 if (reg < 0)
918 goto out;
919
920 e->eee_active = !!(reg & PORT_STATUS_EEE);
921 reg = 0;
922
923 out:
924 mutex_unlock(&ps->smi_mutex);
925 return reg;
926 }
927
928 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
930 {
931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
932 int reg;
933 int ret;
934
935 mutex_lock(&ps->smi_mutex);
936
937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
938 if (ret < 0)
939 goto out;
940
941 reg = ret & ~0x0300;
942 if (e->eee_enabled)
943 reg |= 0x0200;
944 if (e->tx_lpi_enabled)
945 reg |= 0x0100;
946
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
948 out:
949 mutex_unlock(&ps->smi_mutex);
950
951 return ret;
952 }
953
954 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
955 {
956 int ret;
957
958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
959 if (ret < 0)
960 return ret;
961
962 return _mv88e6xxx_atu_wait(ds);
963 }
964
965 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
967 {
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
969
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
972
973 if (entry->trunk) {
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
977 } else {
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
980 }
981
982 data |= (entry->portv_trunkid << shift) & mask;
983 }
984
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
986 }
987
988 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
990 bool static_too)
991 {
992 int op;
993 int err;
994
995 err = _mv88e6xxx_atu_wait(ds);
996 if (err)
997 return err;
998
999 err = _mv88e6xxx_atu_data_write(ds, entry);
1000 if (err)
1001 return err;
1002
1003 if (entry->fid) {
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1005 entry->fid);
1006 if (err)
1007 return err;
1008
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1011 } else {
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1014 }
1015
1016 return _mv88e6xxx_atu_cmd(ds, op);
1017 }
1018
1019 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1020 {
1021 struct mv88e6xxx_atu_entry entry = {
1022 .fid = fid,
1023 .state = 0, /* EntryState bits must be 0 */
1024 };
1025
1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1027 }
1028
1029 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1031 {
1032 struct mv88e6xxx_atu_entry entry = {
1033 .trunk = false,
1034 .fid = fid,
1035 };
1036
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1039
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1043
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1045 }
1046
1047 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1048 bool static_too)
1049 {
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1052 }
1053
1054 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1055 {
1056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1057 int reg, ret = 0;
1058 u8 oldstate;
1059
1060 mutex_lock(&ps->smi_mutex);
1061
1062 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1063 if (reg < 0) {
1064 ret = reg;
1065 goto abort;
1066 }
1067
1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
1069 if (oldstate != state) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1073 */
1074 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1075 state <= PORT_CONTROL_STATE_BLOCKING) {
1076 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1077 if (ret)
1078 goto abort;
1079 }
1080 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1081 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1082 reg);
1083 }
1084
1085 abort:
1086 mutex_unlock(&ps->smi_mutex);
1087 return ret;
1088 }
1089
1090 static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1091 u16 output_ports)
1092 {
1093 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1094 const u16 mask = (1 << ps->num_ports) - 1;
1095 int reg;
1096
1097 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1098 if (reg < 0)
1099 return reg;
1100
1101 reg &= ~mask;
1102 reg |= output_ports & mask;
1103
1104 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1105 }
1106
1107 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1108 {
1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1110 int stp_state;
1111
1112 switch (state) {
1113 case BR_STATE_DISABLED:
1114 stp_state = PORT_CONTROL_STATE_DISABLED;
1115 break;
1116 case BR_STATE_BLOCKING:
1117 case BR_STATE_LISTENING:
1118 stp_state = PORT_CONTROL_STATE_BLOCKING;
1119 break;
1120 case BR_STATE_LEARNING:
1121 stp_state = PORT_CONTROL_STATE_LEARNING;
1122 break;
1123 case BR_STATE_FORWARDING:
1124 default:
1125 stp_state = PORT_CONTROL_STATE_FORWARDING;
1126 break;
1127 }
1128
1129 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1130
1131 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1132 * so we can not update the port state directly but need to schedule it.
1133 */
1134 ps->port_state[port] = stp_state;
1135 set_bit(port, &ps->port_state_update_mask);
1136 schedule_work(&ps->bridge_work);
1137
1138 return 0;
1139 }
1140
1141 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1142 {
1143 int ret;
1144
1145 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1146 if (ret < 0)
1147 return ret;
1148
1149 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1150
1151 return 0;
1152 }
1153
1154 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1155 {
1156 int ret;
1157
1158 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1159 if (ret < 0)
1160 return ret;
1161
1162 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1163
1164 return 0;
1165 }
1166
1167 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1168 {
1169 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1170 pvid & PORT_DEFAULT_VLAN_MASK);
1171 }
1172
1173 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1174 {
1175 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1176 GLOBAL_VTU_OP_BUSY);
1177 }
1178
1179 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1180 {
1181 int ret;
1182
1183 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1184 if (ret < 0)
1185 return ret;
1186
1187 return _mv88e6xxx_vtu_wait(ds);
1188 }
1189
1190 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1191 {
1192 int ret;
1193
1194 ret = _mv88e6xxx_vtu_wait(ds);
1195 if (ret < 0)
1196 return ret;
1197
1198 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1199 }
1200
1201 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1202 struct mv88e6xxx_vtu_stu_entry *entry,
1203 unsigned int nibble_offset)
1204 {
1205 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1206 u16 regs[3];
1207 int i;
1208 int ret;
1209
1210 for (i = 0; i < 3; ++i) {
1211 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1212 GLOBAL_VTU_DATA_0_3 + i);
1213 if (ret < 0)
1214 return ret;
1215
1216 regs[i] = ret;
1217 }
1218
1219 for (i = 0; i < ps->num_ports; ++i) {
1220 unsigned int shift = (i % 4) * 4 + nibble_offset;
1221 u16 reg = regs[i / 4];
1222
1223 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1224 }
1225
1226 return 0;
1227 }
1228
1229 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1230 struct mv88e6xxx_vtu_stu_entry *entry,
1231 unsigned int nibble_offset)
1232 {
1233 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1234 u16 regs[3] = { 0 };
1235 int i;
1236 int ret;
1237
1238 for (i = 0; i < ps->num_ports; ++i) {
1239 unsigned int shift = (i % 4) * 4 + nibble_offset;
1240 u8 data = entry->data[i];
1241
1242 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1243 }
1244
1245 for (i = 0; i < 3; ++i) {
1246 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1247 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1248 if (ret < 0)
1249 return ret;
1250 }
1251
1252 return 0;
1253 }
1254
1255 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1256 {
1257 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1258 vid & GLOBAL_VTU_VID_MASK);
1259 }
1260
1261 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1262 struct mv88e6xxx_vtu_stu_entry *entry)
1263 {
1264 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1265 int ret;
1266
1267 ret = _mv88e6xxx_vtu_wait(ds);
1268 if (ret < 0)
1269 return ret;
1270
1271 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1272 if (ret < 0)
1273 return ret;
1274
1275 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1276 if (ret < 0)
1277 return ret;
1278
1279 next.vid = ret & GLOBAL_VTU_VID_MASK;
1280 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1281
1282 if (next.valid) {
1283 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1284 if (ret < 0)
1285 return ret;
1286
1287 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1288 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1289 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1290 GLOBAL_VTU_FID);
1291 if (ret < 0)
1292 return ret;
1293
1294 next.fid = ret & GLOBAL_VTU_FID_MASK;
1295
1296 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1297 GLOBAL_VTU_SID);
1298 if (ret < 0)
1299 return ret;
1300
1301 next.sid = ret & GLOBAL_VTU_SID_MASK;
1302 }
1303 }
1304
1305 *entry = next;
1306 return 0;
1307 }
1308
1309 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1310 struct mv88e6xxx_vtu_stu_entry *entry)
1311 {
1312 u16 reg = 0;
1313 int ret;
1314
1315 ret = _mv88e6xxx_vtu_wait(ds);
1316 if (ret < 0)
1317 return ret;
1318
1319 if (!entry->valid)
1320 goto loadpurge;
1321
1322 /* Write port member tags */
1323 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1324 if (ret < 0)
1325 return ret;
1326
1327 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1328 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1329 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1330 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1331 if (ret < 0)
1332 return ret;
1333
1334 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1335 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1336 if (ret < 0)
1337 return ret;
1338 }
1339
1340 reg = GLOBAL_VTU_VID_VALID;
1341 loadpurge:
1342 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1343 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1344 if (ret < 0)
1345 return ret;
1346
1347 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1348 }
1349
1350 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1351 struct mv88e6xxx_vtu_stu_entry *entry)
1352 {
1353 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1354 int ret;
1355
1356 ret = _mv88e6xxx_vtu_wait(ds);
1357 if (ret < 0)
1358 return ret;
1359
1360 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1361 sid & GLOBAL_VTU_SID_MASK);
1362 if (ret < 0)
1363 return ret;
1364
1365 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1366 if (ret < 0)
1367 return ret;
1368
1369 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1370 if (ret < 0)
1371 return ret;
1372
1373 next.sid = ret & GLOBAL_VTU_SID_MASK;
1374
1375 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1376 if (ret < 0)
1377 return ret;
1378
1379 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1380
1381 if (next.valid) {
1382 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1383 if (ret < 0)
1384 return ret;
1385 }
1386
1387 *entry = next;
1388 return 0;
1389 }
1390
1391 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1392 struct mv88e6xxx_vtu_stu_entry *entry)
1393 {
1394 u16 reg = 0;
1395 int ret;
1396
1397 ret = _mv88e6xxx_vtu_wait(ds);
1398 if (ret < 0)
1399 return ret;
1400
1401 if (!entry->valid)
1402 goto loadpurge;
1403
1404 /* Write port states */
1405 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1406 if (ret < 0)
1407 return ret;
1408
1409 reg = GLOBAL_VTU_VID_VALID;
1410 loadpurge:
1411 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1412 if (ret < 0)
1413 return ret;
1414
1415 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1416 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1417 if (ret < 0)
1418 return ret;
1419
1420 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1421 }
1422
1423 static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1424 struct mv88e6xxx_vtu_stu_entry *entry)
1425 {
1426 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1427 struct mv88e6xxx_vtu_stu_entry vlan = {
1428 .valid = true,
1429 .vid = vid,
1430 .fid = vid, /* We use one FID per VLAN */
1431 };
1432 int i;
1433
1434 /* exclude all ports except the CPU and DSA ports */
1435 for (i = 0; i < ps->num_ports; ++i)
1436 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1437 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1438 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1439
1440 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1441 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1442 struct mv88e6xxx_vtu_stu_entry vstp;
1443 int err;
1444
1445 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1446 * implemented, only one STU entry is needed to cover all VTU
1447 * entries. Thus, validate the SID 0.
1448 */
1449 vlan.sid = 0;
1450 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1451 if (err)
1452 return err;
1453
1454 if (vstp.sid != vlan.sid || !vstp.valid) {
1455 memset(&vstp, 0, sizeof(vstp));
1456 vstp.valid = true;
1457 vstp.sid = vlan.sid;
1458
1459 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1460 if (err)
1461 return err;
1462 }
1463
1464 /* Clear all MAC addresses from the new database */
1465 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
1466 if (err)
1467 return err;
1468 }
1469
1470 *entry = vlan;
1471 return 0;
1472 }
1473
1474 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1475 const struct switchdev_obj_port_vlan *vlan,
1476 struct switchdev_trans *trans)
1477 {
1478 /* We reserve a few VLANs to isolate unbridged ports */
1479 if (vlan->vid_end >= 4000)
1480 return -EOPNOTSUPP;
1481
1482 /* We don't need any dynamic resource from the kernel (yet),
1483 * so skip the prepare phase.
1484 */
1485 return 0;
1486 }
1487
1488 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1489 bool untagged)
1490 {
1491 struct mv88e6xxx_vtu_stu_entry vlan;
1492 int err;
1493
1494 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1495 if (err)
1496 return err;
1497
1498 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1499 if (err)
1500 return err;
1501
1502 if (vlan.vid != vid || !vlan.valid) {
1503 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1504 if (err)
1505 return err;
1506 }
1507
1508 vlan.data[port] = untagged ?
1509 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1510 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1511
1512 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1513 }
1514
1515 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1516 const struct switchdev_obj_port_vlan *vlan,
1517 struct switchdev_trans *trans)
1518 {
1519 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1520 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1521 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1522 u16 vid;
1523 int err = 0;
1524
1525 mutex_lock(&ps->smi_mutex);
1526
1527 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1528 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1529 if (err)
1530 goto unlock;
1531 }
1532
1533 /* no PVID with ranges, otherwise it's a bug */
1534 if (pvid)
1535 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
1536 unlock:
1537 mutex_unlock(&ps->smi_mutex);
1538
1539 return err;
1540 }
1541
1542 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1543 {
1544 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1545 struct mv88e6xxx_vtu_stu_entry vlan;
1546 int i, err;
1547
1548 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1549 if (err)
1550 return err;
1551
1552 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1553 if (err)
1554 return err;
1555
1556 if (vlan.vid != vid || !vlan.valid ||
1557 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1558 return -ENOENT;
1559
1560 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1561
1562 /* keep the VLAN unless all ports are excluded */
1563 vlan.valid = false;
1564 for (i = 0; i < ps->num_ports; ++i) {
1565 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1566 continue;
1567
1568 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1569 vlan.valid = true;
1570 break;
1571 }
1572 }
1573
1574 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1575 if (err)
1576 return err;
1577
1578 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1579 }
1580
1581 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1582 const struct switchdev_obj_port_vlan *vlan)
1583 {
1584 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1585 u16 pvid, vid;
1586 int err = 0;
1587
1588 mutex_lock(&ps->smi_mutex);
1589
1590 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1591 if (err)
1592 goto unlock;
1593
1594 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1595 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1596 if (err)
1597 goto unlock;
1598
1599 if (vid == pvid) {
1600 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1601 if (err)
1602 goto unlock;
1603 }
1604 }
1605
1606 unlock:
1607 mutex_unlock(&ps->smi_mutex);
1608
1609 return err;
1610 }
1611
1612 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1613 unsigned long *ports, unsigned long *untagged)
1614 {
1615 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1616 struct mv88e6xxx_vtu_stu_entry next;
1617 int port;
1618 int err;
1619
1620 if (*vid == 4095)
1621 return -ENOENT;
1622
1623 mutex_lock(&ps->smi_mutex);
1624 err = _mv88e6xxx_vtu_vid_write(ds, *vid);
1625 if (err)
1626 goto unlock;
1627
1628 err = _mv88e6xxx_vtu_getnext(ds, &next);
1629 unlock:
1630 mutex_unlock(&ps->smi_mutex);
1631
1632 if (err)
1633 return err;
1634
1635 if (!next.valid)
1636 return -ENOENT;
1637
1638 *vid = next.vid;
1639
1640 for (port = 0; port < ps->num_ports; ++port) {
1641 clear_bit(port, ports);
1642 clear_bit(port, untagged);
1643
1644 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1645 continue;
1646
1647 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1648 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1649 set_bit(port, ports);
1650
1651 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1652 set_bit(port, untagged);
1653 }
1654
1655 return 0;
1656 }
1657
1658 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1659 const unsigned char *addr)
1660 {
1661 int i, ret;
1662
1663 for (i = 0; i < 3; i++) {
1664 ret = _mv88e6xxx_reg_write(
1665 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1666 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1667 if (ret < 0)
1668 return ret;
1669 }
1670
1671 return 0;
1672 }
1673
1674 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1675 {
1676 int i, ret;
1677
1678 for (i = 0; i < 3; i++) {
1679 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1680 GLOBAL_ATU_MAC_01 + i);
1681 if (ret < 0)
1682 return ret;
1683 addr[i * 2] = ret >> 8;
1684 addr[i * 2 + 1] = ret & 0xff;
1685 }
1686
1687 return 0;
1688 }
1689
1690 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1691 struct mv88e6xxx_atu_entry *entry)
1692 {
1693 int ret;
1694
1695 ret = _mv88e6xxx_atu_wait(ds);
1696 if (ret < 0)
1697 return ret;
1698
1699 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1700 if (ret < 0)
1701 return ret;
1702
1703 ret = _mv88e6xxx_atu_data_write(ds, entry);
1704 if (ret < 0)
1705 return ret;
1706
1707 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1708 if (ret < 0)
1709 return ret;
1710
1711 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1712 }
1713
1714 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1715 const unsigned char *addr, u16 vid,
1716 u8 state)
1717 {
1718 struct mv88e6xxx_atu_entry entry = { 0 };
1719
1720 entry.fid = vid; /* We use one FID per VLAN */
1721 entry.state = state;
1722 ether_addr_copy(entry.mac, addr);
1723 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1724 entry.trunk = false;
1725 entry.portv_trunkid = BIT(port);
1726 }
1727
1728 return _mv88e6xxx_atu_load(ds, &entry);
1729 }
1730
1731 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1732 const struct switchdev_obj_port_fdb *fdb,
1733 struct switchdev_trans *trans)
1734 {
1735 /* We don't use per-port FDB */
1736 if (fdb->vid == 0)
1737 return -EOPNOTSUPP;
1738
1739 /* We don't need any dynamic resource from the kernel (yet),
1740 * so skip the prepare phase.
1741 */
1742 return 0;
1743 }
1744
1745 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1746 const struct switchdev_obj_port_fdb *fdb,
1747 struct switchdev_trans *trans)
1748 {
1749 int state = is_multicast_ether_addr(fdb->addr) ?
1750 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1751 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1752 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1753 int ret;
1754
1755 mutex_lock(&ps->smi_mutex);
1756 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
1757 mutex_unlock(&ps->smi_mutex);
1758
1759 return ret;
1760 }
1761
1762 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1763 const struct switchdev_obj_port_fdb *fdb)
1764 {
1765 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1766 int ret;
1767
1768 mutex_lock(&ps->smi_mutex);
1769 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
1770 GLOBAL_ATU_DATA_STATE_UNUSED);
1771 mutex_unlock(&ps->smi_mutex);
1772
1773 return ret;
1774 }
1775
1776 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1777 struct mv88e6xxx_atu_entry *entry)
1778 {
1779 struct mv88e6xxx_atu_entry next = { 0 };
1780 int ret;
1781
1782 next.fid = fid;
1783
1784 ret = _mv88e6xxx_atu_wait(ds);
1785 if (ret < 0)
1786 return ret;
1787
1788 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1789 if (ret < 0)
1790 return ret;
1791
1792 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1793 if (ret < 0)
1794 return ret;
1795
1796 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1797 if (ret < 0)
1798 return ret;
1799
1800 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1801 if (ret < 0)
1802 return ret;
1803
1804 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1805 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1806 unsigned int mask, shift;
1807
1808 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1809 next.trunk = true;
1810 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1811 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1812 } else {
1813 next.trunk = false;
1814 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1815 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1816 }
1817
1818 next.portv_trunkid = (ret & mask) >> shift;
1819 }
1820
1821 *entry = next;
1822 return 0;
1823 }
1824
1825 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1826 struct switchdev_obj_port_fdb *fdb,
1827 int (*cb)(struct switchdev_obj *obj))
1828 {
1829 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1830 struct mv88e6xxx_vtu_stu_entry vlan = {
1831 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
1832 };
1833 int err;
1834
1835 mutex_lock(&ps->smi_mutex);
1836
1837 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
1838 if (err)
1839 goto unlock;
1840
1841 do {
1842 struct mv88e6xxx_atu_entry addr = {
1843 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1844 };
1845
1846 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1847 if (err)
1848 goto unlock;
1849
1850 if (!vlan.valid)
1851 break;
1852
1853 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
1854 if (err)
1855 goto unlock;
1856
1857 do {
1858 err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr);
1859 if (err)
1860 goto unlock;
1861
1862 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1863 break;
1864
1865 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
1866 bool is_static = addr.state ==
1867 (is_multicast_ether_addr(addr.mac) ?
1868 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1869 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1870
1871 fdb->vid = vlan.vid;
1872 ether_addr_copy(fdb->addr, addr.mac);
1873 fdb->ndm_state = is_static ? NUD_NOARP :
1874 NUD_REACHABLE;
1875
1876 err = cb(&fdb->obj);
1877 if (err)
1878 goto unlock;
1879 }
1880 } while (!is_broadcast_ether_addr(addr.mac));
1881
1882 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1883
1884 unlock:
1885 mutex_unlock(&ps->smi_mutex);
1886
1887 return err;
1888 }
1889
1890 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, u32 members)
1891 {
1892 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1893 const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1894 int err;
1895
1896 /* The port joined a bridge, so leave its reserved VLAN */
1897 mutex_lock(&ps->smi_mutex);
1898 err = _mv88e6xxx_port_vlan_del(ds, port, pvid);
1899 if (!err)
1900 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1901 mutex_unlock(&ps->smi_mutex);
1902 return err;
1903 }
1904
1905 int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, u32 members)
1906 {
1907 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1908 const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1909 int err;
1910
1911 /* The port left the bridge, so join its reserved VLAN */
1912 mutex_lock(&ps->smi_mutex);
1913 err = _mv88e6xxx_port_vlan_add(ds, port, pvid, true);
1914 if (!err)
1915 err = _mv88e6xxx_port_pvid_set(ds, port, pvid);
1916 mutex_unlock(&ps->smi_mutex);
1917 return err;
1918 }
1919
1920 static void mv88e6xxx_bridge_work(struct work_struct *work)
1921 {
1922 struct mv88e6xxx_priv_state *ps;
1923 struct dsa_switch *ds;
1924 int port;
1925
1926 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1927 ds = ((struct dsa_switch *)ps) - 1;
1928
1929 while (ps->port_state_update_mask) {
1930 port = __ffs(ps->port_state_update_mask);
1931 clear_bit(port, &ps->port_state_update_mask);
1932 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1933 }
1934 }
1935
1936 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1937 {
1938 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1939 int ret;
1940 u16 reg;
1941
1942 mutex_lock(&ps->smi_mutex);
1943
1944 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1945 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1946 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1947 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1948 /* MAC Forcing register: don't force link, speed,
1949 * duplex or flow control state to any particular
1950 * values on physical ports, but force the CPU port
1951 * and all DSA ports to their maximum bandwidth and
1952 * full duplex.
1953 */
1954 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1955 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1956 reg &= ~PORT_PCS_CTRL_UNFORCED;
1957 reg |= PORT_PCS_CTRL_FORCE_LINK |
1958 PORT_PCS_CTRL_LINK_UP |
1959 PORT_PCS_CTRL_DUPLEX_FULL |
1960 PORT_PCS_CTRL_FORCE_DUPLEX;
1961 if (mv88e6xxx_6065_family(ds))
1962 reg |= PORT_PCS_CTRL_100;
1963 else
1964 reg |= PORT_PCS_CTRL_1000;
1965 } else {
1966 reg |= PORT_PCS_CTRL_UNFORCED;
1967 }
1968
1969 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1970 PORT_PCS_CTRL, reg);
1971 if (ret)
1972 goto abort;
1973 }
1974
1975 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1976 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1977 * tunneling, determine priority by looking at 802.1p and IP
1978 * priority fields (IP prio has precedence), and set STP state
1979 * to Forwarding.
1980 *
1981 * If this is the CPU link, use DSA or EDSA tagging depending
1982 * on which tagging mode was configured.
1983 *
1984 * If this is a link to another switch, use DSA tagging mode.
1985 *
1986 * If this is the upstream port for this switch, enable
1987 * forwarding of unknown unicasts and multicasts.
1988 */
1989 reg = 0;
1990 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1991 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1992 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1993 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1994 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1995 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1996 PORT_CONTROL_STATE_FORWARDING;
1997 if (dsa_is_cpu_port(ds, port)) {
1998 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1999 reg |= PORT_CONTROL_DSA_TAG;
2000 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2001 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2002 mv88e6xxx_6320_family(ds)) {
2003 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2004 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2005 else
2006 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2007 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2008 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2009 }
2010
2011 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2012 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2013 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2014 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2015 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2016 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2017 }
2018 }
2019 if (dsa_is_dsa_port(ds, port)) {
2020 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2021 reg |= PORT_CONTROL_DSA_TAG;
2022 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2023 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2024 mv88e6xxx_6320_family(ds)) {
2025 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2026 }
2027
2028 if (port == dsa_upstream_port(ds))
2029 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2030 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2031 }
2032 if (reg) {
2033 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2034 PORT_CONTROL, reg);
2035 if (ret)
2036 goto abort;
2037 }
2038
2039 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2040 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2041 * untagged frames on this port, do a destination address lookup on all
2042 * received packets as usual, disable ARP mirroring and don't send a
2043 * copy of all transmitted/received frames on this port to the CPU.
2044 */
2045 reg = 0;
2046 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2047 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2048 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2049 reg = PORT_CONTROL_2_MAP_DA;
2050
2051 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2052 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2053 reg |= PORT_CONTROL_2_JUMBO_10240;
2054
2055 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2056 /* Set the upstream port this port should use */
2057 reg |= dsa_upstream_port(ds);
2058 /* enable forwarding of unknown multicast addresses to
2059 * the upstream port
2060 */
2061 if (port == dsa_upstream_port(ds))
2062 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2063 }
2064
2065 reg |= PORT_CONTROL_2_8021Q_SECURE;
2066
2067 if (reg) {
2068 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2069 PORT_CONTROL_2, reg);
2070 if (ret)
2071 goto abort;
2072 }
2073
2074 /* Port Association Vector: when learning source addresses
2075 * of packets, add the address to the address database using
2076 * a port bitmap that has only the bit for this port set and
2077 * the other bits clear.
2078 */
2079 reg = 1 << port;
2080 /* Disable learning for DSA and CPU ports */
2081 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2082 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2083
2084 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2085 if (ret)
2086 goto abort;
2087
2088 /* Egress rate control 2: disable egress rate control. */
2089 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2090 0x0000);
2091 if (ret)
2092 goto abort;
2093
2094 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2095 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2096 mv88e6xxx_6320_family(ds)) {
2097 /* Do not limit the period of time that this port can
2098 * be paused for by the remote end or the period of
2099 * time that this port can pause the remote end.
2100 */
2101 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2102 PORT_PAUSE_CTRL, 0x0000);
2103 if (ret)
2104 goto abort;
2105
2106 /* Port ATU control: disable limiting the number of
2107 * address database entries that this port is allowed
2108 * to use.
2109 */
2110 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2111 PORT_ATU_CONTROL, 0x0000);
2112 /* Priority Override: disable DA, SA and VTU priority
2113 * override.
2114 */
2115 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2116 PORT_PRI_OVERRIDE, 0x0000);
2117 if (ret)
2118 goto abort;
2119
2120 /* Port Ethertype: use the Ethertype DSA Ethertype
2121 * value.
2122 */
2123 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2124 PORT_ETH_TYPE, ETH_P_EDSA);
2125 if (ret)
2126 goto abort;
2127 /* Tag Remap: use an identity 802.1p prio -> switch
2128 * prio mapping.
2129 */
2130 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2131 PORT_TAG_REGMAP_0123, 0x3210);
2132 if (ret)
2133 goto abort;
2134
2135 /* Tag Remap 2: use an identity 802.1p prio -> switch
2136 * prio mapping.
2137 */
2138 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2139 PORT_TAG_REGMAP_4567, 0x7654);
2140 if (ret)
2141 goto abort;
2142 }
2143
2144 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2145 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2146 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2147 mv88e6xxx_6320_family(ds)) {
2148 /* Rate Control: disable ingress rate limiting. */
2149 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2150 PORT_RATE_CONTROL, 0x0001);
2151 if (ret)
2152 goto abort;
2153 }
2154
2155 /* Port Control 1: disable trunking, disable sending
2156 * learning messages to this port.
2157 */
2158 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2159 if (ret)
2160 goto abort;
2161
2162 /* Port based VLAN map: do not give each port its own address
2163 * database, and allow every port to egress frames on all other ports.
2164 */
2165 reg = BIT(ps->num_ports) - 1; /* all ports */
2166 reg &= ~BIT(port); /* except itself */
2167 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg);
2168 if (ret)
2169 goto abort;
2170
2171 /* Default VLAN ID and priority: don't set a default VLAN
2172 * ID, and set the default packet priority to zero.
2173 */
2174 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2175 0x0000);
2176 abort:
2177 mutex_unlock(&ps->smi_mutex);
2178 return ret;
2179 }
2180
2181 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2182 {
2183 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2184 int ret;
2185 int i;
2186
2187 for (i = 0; i < ps->num_ports; i++) {
2188 ret = mv88e6xxx_setup_port(ds, i);
2189 if (ret < 0)
2190 return ret;
2191
2192 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2193 continue;
2194
2195 /* setup the unbridged state */
2196 ret = mv88e6xxx_port_bridge_leave(ds, i, 0);
2197 if (ret < 0)
2198 return ret;
2199 }
2200 return 0;
2201 }
2202
2203 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2204 {
2205 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2206
2207 mutex_init(&ps->smi_mutex);
2208
2209 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2210
2211 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2212
2213 return 0;
2214 }
2215
2216 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2217 {
2218 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2219 int ret;
2220 int i;
2221
2222 /* Set the default address aging time to 5 minutes, and
2223 * enable address learn messages to be sent to all message
2224 * ports.
2225 */
2226 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2227 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2228
2229 /* Configure the IP ToS mapping registers. */
2230 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2231 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2232 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2233 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2234 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2235 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2236 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2237 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2238
2239 /* Configure the IEEE 802.1p priority mapping register. */
2240 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2241
2242 /* Send all frames with destination addresses matching
2243 * 01:80:c2:00:00:0x to the CPU port.
2244 */
2245 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2246
2247 /* Ignore removed tag data on doubly tagged packets, disable
2248 * flow control messages, force flow control priority to the
2249 * highest, and send all special multicast frames to the CPU
2250 * port at the highest priority.
2251 */
2252 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2253 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2254 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2255
2256 /* Program the DSA routing table. */
2257 for (i = 0; i < 32; i++) {
2258 int nexthop = 0x1f;
2259
2260 if (ds->pd->rtable &&
2261 i != ds->index && i < ds->dst->pd->nr_chips)
2262 nexthop = ds->pd->rtable[i] & 0x1f;
2263
2264 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2265 GLOBAL2_DEVICE_MAPPING_UPDATE |
2266 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2267 nexthop);
2268 }
2269
2270 /* Clear all trunk masks. */
2271 for (i = 0; i < 8; i++)
2272 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2273 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2274 ((1 << ps->num_ports) - 1));
2275
2276 /* Clear all trunk mappings. */
2277 for (i = 0; i < 16; i++)
2278 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2279 GLOBAL2_TRUNK_MAPPING_UPDATE |
2280 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2281
2282 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2283 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2284 mv88e6xxx_6320_family(ds)) {
2285 /* Send all frames with destination addresses matching
2286 * 01:80:c2:00:00:2x to the CPU port.
2287 */
2288 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2289
2290 /* Initialise cross-chip port VLAN table to reset
2291 * defaults.
2292 */
2293 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2294
2295 /* Clear the priority override table. */
2296 for (i = 0; i < 16; i++)
2297 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2298 0x8000 | (i << 8));
2299 }
2300
2301 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2302 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2303 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2304 mv88e6xxx_6320_family(ds)) {
2305 /* Disable ingress rate limiting by resetting all
2306 * ingress rate limit registers to their initial
2307 * state.
2308 */
2309 for (i = 0; i < ps->num_ports; i++)
2310 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2311 0x9000 | (i << 8));
2312 }
2313
2314 /* Clear the statistics counters for all ports */
2315 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2316
2317 /* Wait for the flush to complete. */
2318 mutex_lock(&ps->smi_mutex);
2319 ret = _mv88e6xxx_stats_wait(ds);
2320 if (ret < 0)
2321 goto unlock;
2322
2323 /* Clear all ATU entries */
2324 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2325 if (ret < 0)
2326 goto unlock;
2327
2328 /* Clear all the VTU and STU entries */
2329 ret = _mv88e6xxx_vtu_stu_flush(ds);
2330 unlock:
2331 mutex_unlock(&ps->smi_mutex);
2332
2333 return ret;
2334 }
2335
2336 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2337 {
2338 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2339 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2340 struct gpio_desc *gpiod = ds->pd->reset;
2341 unsigned long timeout;
2342 int ret;
2343 int i;
2344
2345 /* Set all ports to the disabled state. */
2346 for (i = 0; i < ps->num_ports; i++) {
2347 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2348 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2349 }
2350
2351 /* Wait for transmit queues to drain. */
2352 usleep_range(2000, 4000);
2353
2354 /* If there is a gpio connected to the reset pin, toggle it */
2355 if (gpiod) {
2356 gpiod_set_value_cansleep(gpiod, 1);
2357 usleep_range(10000, 20000);
2358 gpiod_set_value_cansleep(gpiod, 0);
2359 usleep_range(10000, 20000);
2360 }
2361
2362 /* Reset the switch. Keep the PPU active if requested. The PPU
2363 * needs to be active to support indirect phy register access
2364 * through global registers 0x18 and 0x19.
2365 */
2366 if (ppu_active)
2367 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2368 else
2369 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2370
2371 /* Wait up to one second for reset to complete. */
2372 timeout = jiffies + 1 * HZ;
2373 while (time_before(jiffies, timeout)) {
2374 ret = REG_READ(REG_GLOBAL, 0x00);
2375 if ((ret & is_reset) == is_reset)
2376 break;
2377 usleep_range(1000, 2000);
2378 }
2379 if (time_after(jiffies, timeout))
2380 return -ETIMEDOUT;
2381
2382 return 0;
2383 }
2384
2385 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2386 {
2387 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2388 int ret;
2389
2390 mutex_lock(&ps->smi_mutex);
2391 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2392 if (ret < 0)
2393 goto error;
2394 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2395 error:
2396 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2397 mutex_unlock(&ps->smi_mutex);
2398 return ret;
2399 }
2400
2401 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2402 int reg, int val)
2403 {
2404 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2405 int ret;
2406
2407 mutex_lock(&ps->smi_mutex);
2408 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2409 if (ret < 0)
2410 goto error;
2411
2412 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2413 error:
2414 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2415 mutex_unlock(&ps->smi_mutex);
2416 return ret;
2417 }
2418
2419 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2420 {
2421 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2422
2423 if (port >= 0 && port < ps->num_ports)
2424 return port;
2425 return -EINVAL;
2426 }
2427
2428 int
2429 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2430 {
2431 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2432 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2433 int ret;
2434
2435 if (addr < 0)
2436 return addr;
2437
2438 mutex_lock(&ps->smi_mutex);
2439 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2440 mutex_unlock(&ps->smi_mutex);
2441 return ret;
2442 }
2443
2444 int
2445 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2446 {
2447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2448 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2449 int ret;
2450
2451 if (addr < 0)
2452 return addr;
2453
2454 mutex_lock(&ps->smi_mutex);
2455 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2456 mutex_unlock(&ps->smi_mutex);
2457 return ret;
2458 }
2459
2460 int
2461 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2462 {
2463 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2464 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2465 int ret;
2466
2467 if (addr < 0)
2468 return addr;
2469
2470 mutex_lock(&ps->smi_mutex);
2471 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2472 mutex_unlock(&ps->smi_mutex);
2473 return ret;
2474 }
2475
2476 int
2477 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2478 u16 val)
2479 {
2480 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2481 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2482 int ret;
2483
2484 if (addr < 0)
2485 return addr;
2486
2487 mutex_lock(&ps->smi_mutex);
2488 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2489 mutex_unlock(&ps->smi_mutex);
2490 return ret;
2491 }
2492
2493 #ifdef CONFIG_NET_DSA_HWMON
2494
2495 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2496 {
2497 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2498 int ret;
2499 int val;
2500
2501 *temp = 0;
2502
2503 mutex_lock(&ps->smi_mutex);
2504
2505 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2506 if (ret < 0)
2507 goto error;
2508
2509 /* Enable temperature sensor */
2510 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2511 if (ret < 0)
2512 goto error;
2513
2514 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2515 if (ret < 0)
2516 goto error;
2517
2518 /* Wait for temperature to stabilize */
2519 usleep_range(10000, 12000);
2520
2521 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2522 if (val < 0) {
2523 ret = val;
2524 goto error;
2525 }
2526
2527 /* Disable temperature sensor */
2528 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2529 if (ret < 0)
2530 goto error;
2531
2532 *temp = ((val & 0x1f) - 5) * 5;
2533
2534 error:
2535 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2536 mutex_unlock(&ps->smi_mutex);
2537 return ret;
2538 }
2539
2540 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2541 {
2542 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2543 int ret;
2544
2545 *temp = 0;
2546
2547 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2548 if (ret < 0)
2549 return ret;
2550
2551 *temp = (ret & 0xff) - 25;
2552
2553 return 0;
2554 }
2555
2556 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2557 {
2558 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2559 return mv88e63xx_get_temp(ds, temp);
2560
2561 return mv88e61xx_get_temp(ds, temp);
2562 }
2563
2564 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2565 {
2566 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2567 int ret;
2568
2569 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2570 return -EOPNOTSUPP;
2571
2572 *temp = 0;
2573
2574 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2575 if (ret < 0)
2576 return ret;
2577
2578 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2579
2580 return 0;
2581 }
2582
2583 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2584 {
2585 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2586 int ret;
2587
2588 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2589 return -EOPNOTSUPP;
2590
2591 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2592 if (ret < 0)
2593 return ret;
2594 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2595 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2596 (ret & 0xe0ff) | (temp << 8));
2597 }
2598
2599 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2600 {
2601 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2602 int ret;
2603
2604 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2605 return -EOPNOTSUPP;
2606
2607 *alarm = false;
2608
2609 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2610 if (ret < 0)
2611 return ret;
2612
2613 *alarm = !!(ret & 0x40);
2614
2615 return 0;
2616 }
2617 #endif /* CONFIG_NET_DSA_HWMON */
2618
2619 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2620 const struct mv88e6xxx_switch_id *table,
2621 unsigned int num)
2622 {
2623 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2624 int i, ret;
2625
2626 if (!bus)
2627 return NULL;
2628
2629 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2630 if (ret < 0)
2631 return NULL;
2632
2633 /* Look up the exact switch ID */
2634 for (i = 0; i < num; ++i)
2635 if (table[i].id == ret)
2636 return table[i].name;
2637
2638 /* Look up only the product number */
2639 for (i = 0; i < num; ++i) {
2640 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2641 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2642 ret & PORT_SWITCH_ID_REV_MASK,
2643 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2644 return table[i].name;
2645 }
2646 }
2647
2648 return NULL;
2649 }
2650
2651 static int __init mv88e6xxx_init(void)
2652 {
2653 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2654 register_switch_driver(&mv88e6131_switch_driver);
2655 #endif
2656 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2657 register_switch_driver(&mv88e6123_61_65_switch_driver);
2658 #endif
2659 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2660 register_switch_driver(&mv88e6352_switch_driver);
2661 #endif
2662 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2663 register_switch_driver(&mv88e6171_switch_driver);
2664 #endif
2665 return 0;
2666 }
2667 module_init(mv88e6xxx_init);
2668
2669 static void __exit mv88e6xxx_cleanup(void)
2670 {
2671 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2672 unregister_switch_driver(&mv88e6171_switch_driver);
2673 #endif
2674 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2675 unregister_switch_driver(&mv88e6352_switch_driver);
2676 #endif
2677 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2678 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2679 #endif
2680 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2681 unregister_switch_driver(&mv88e6131_switch_driver);
2682 #endif
2683 }
2684 module_exit(mv88e6xxx_cleanup);
2685
2686 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2687 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2688 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.136521 seconds and 6 git commands to generate.