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[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 */
28
29 /* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33 #include "e1000.h"
34
35 static s32 e1000_check_downshift(struct e1000_hw *hw);
36 static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39 static void e1000_clear_vfta(struct e1000_hw *hw);
40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
41 bool link_up);
42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46 u16 *max_length);
47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48 static s32 e1000_id_led_init(struct e1000_hw *hw);
49 static void e1000_init_rx_addrs(struct e1000_hw *hw);
50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57 static s32 e1000_set_phy_type(struct e1000_hw *hw);
58 static void e1000_phy_init_script(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
70 u16 words, u16 *data);
71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
78 u16 phy_data);
79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
80 u16 *phy_data);
81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83 static void e1000_release_eeprom(struct e1000_hw *hw);
84 static void e1000_standby_eeprom(struct e1000_hw *hw);
85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89 u16 *data);
90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91 u16 *data);
92
93 /* IGP cable length table */
94 static const
95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106 120, 120
107 };
108
109 static DEFINE_SPINLOCK(e1000_eeprom_lock);
110
111 /**
112 * e1000_set_phy_type - Set the phy type member in the hw struct.
113 * @hw: Struct containing variables accessed by shared code
114 */
115 static s32 e1000_set_phy_type(struct e1000_hw *hw)
116 {
117 e_dbg("e1000_set_phy_type");
118
119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
121
122 switch (hw->phy_id) {
123 case M88E1000_E_PHY_ID:
124 case M88E1000_I_PHY_ID:
125 case M88E1011_I_PHY_ID:
126 case M88E1111_I_PHY_ID:
127 case M88E1118_E_PHY_ID:
128 hw->phy_type = e1000_phy_m88;
129 break;
130 case IGP01E1000_I_PHY_ID:
131 if (hw->mac_type == e1000_82541 ||
132 hw->mac_type == e1000_82541_rev_2 ||
133 hw->mac_type == e1000_82547 ||
134 hw->mac_type == e1000_82547_rev_2)
135 hw->phy_type = e1000_phy_igp;
136 break;
137 case RTL8211B_PHY_ID:
138 hw->phy_type = e1000_phy_8211;
139 break;
140 case RTL8201N_PHY_ID:
141 hw->phy_type = e1000_phy_8201;
142 break;
143 default:
144 /* Should never have loaded on this device */
145 hw->phy_type = e1000_phy_undefined;
146 return -E1000_ERR_PHY_TYPE;
147 }
148
149 return E1000_SUCCESS;
150 }
151
152 /**
153 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
154 * @hw: Struct containing variables accessed by shared code
155 */
156 static void e1000_phy_init_script(struct e1000_hw *hw)
157 {
158 u32 ret_val;
159 u16 phy_saved_data;
160
161 e_dbg("e1000_phy_init_script");
162
163 if (hw->phy_init_script) {
164 msleep(20);
165
166 /* Save off the current value of register 0x2F5B to be restored at
167 * the end of this routine. */
168 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
169
170 /* Disabled the PHY transmitter */
171 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
172 msleep(20);
173
174 e1000_write_phy_reg(hw, 0x0000, 0x0140);
175 msleep(5);
176
177 switch (hw->mac_type) {
178 case e1000_82541:
179 case e1000_82547:
180 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
181 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
182 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
183 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
184 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
185 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
186 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
187 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
188 e1000_write_phy_reg(hw, 0x2010, 0x0008);
189 break;
190
191 case e1000_82541_rev_2:
192 case e1000_82547_rev_2:
193 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
194 break;
195 default:
196 break;
197 }
198
199 e1000_write_phy_reg(hw, 0x0000, 0x3300);
200 msleep(20);
201
202 /* Now enable the transmitter */
203 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
204
205 if (hw->mac_type == e1000_82547) {
206 u16 fused, fine, coarse;
207
208 /* Move to analog registers page */
209 e1000_read_phy_reg(hw,
210 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
211 &fused);
212
213 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
214 e1000_read_phy_reg(hw,
215 IGP01E1000_ANALOG_FUSE_STATUS,
216 &fused);
217
218 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
219 coarse =
220 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
221
222 if (coarse >
223 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
224 coarse -=
225 IGP01E1000_ANALOG_FUSE_COARSE_10;
226 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
227 } else if (coarse ==
228 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
229 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
230
231 fused =
232 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
233 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
234 (coarse &
235 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
236
237 e1000_write_phy_reg(hw,
238 IGP01E1000_ANALOG_FUSE_CONTROL,
239 fused);
240 e1000_write_phy_reg(hw,
241 IGP01E1000_ANALOG_FUSE_BYPASS,
242 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
243 }
244 }
245 }
246 }
247
248 /**
249 * e1000_set_mac_type - Set the mac type member in the hw struct.
250 * @hw: Struct containing variables accessed by shared code
251 */
252 s32 e1000_set_mac_type(struct e1000_hw *hw)
253 {
254 e_dbg("e1000_set_mac_type");
255
256 switch (hw->device_id) {
257 case E1000_DEV_ID_82542:
258 switch (hw->revision_id) {
259 case E1000_82542_2_0_REV_ID:
260 hw->mac_type = e1000_82542_rev2_0;
261 break;
262 case E1000_82542_2_1_REV_ID:
263 hw->mac_type = e1000_82542_rev2_1;
264 break;
265 default:
266 /* Invalid 82542 revision ID */
267 return -E1000_ERR_MAC_TYPE;
268 }
269 break;
270 case E1000_DEV_ID_82543GC_FIBER:
271 case E1000_DEV_ID_82543GC_COPPER:
272 hw->mac_type = e1000_82543;
273 break;
274 case E1000_DEV_ID_82544EI_COPPER:
275 case E1000_DEV_ID_82544EI_FIBER:
276 case E1000_DEV_ID_82544GC_COPPER:
277 case E1000_DEV_ID_82544GC_LOM:
278 hw->mac_type = e1000_82544;
279 break;
280 case E1000_DEV_ID_82540EM:
281 case E1000_DEV_ID_82540EM_LOM:
282 case E1000_DEV_ID_82540EP:
283 case E1000_DEV_ID_82540EP_LOM:
284 case E1000_DEV_ID_82540EP_LP:
285 hw->mac_type = e1000_82540;
286 break;
287 case E1000_DEV_ID_82545EM_COPPER:
288 case E1000_DEV_ID_82545EM_FIBER:
289 hw->mac_type = e1000_82545;
290 break;
291 case E1000_DEV_ID_82545GM_COPPER:
292 case E1000_DEV_ID_82545GM_FIBER:
293 case E1000_DEV_ID_82545GM_SERDES:
294 hw->mac_type = e1000_82545_rev_3;
295 break;
296 case E1000_DEV_ID_82546EB_COPPER:
297 case E1000_DEV_ID_82546EB_FIBER:
298 case E1000_DEV_ID_82546EB_QUAD_COPPER:
299 hw->mac_type = e1000_82546;
300 break;
301 case E1000_DEV_ID_82546GB_COPPER:
302 case E1000_DEV_ID_82546GB_FIBER:
303 case E1000_DEV_ID_82546GB_SERDES:
304 case E1000_DEV_ID_82546GB_PCIE:
305 case E1000_DEV_ID_82546GB_QUAD_COPPER:
306 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
307 hw->mac_type = e1000_82546_rev_3;
308 break;
309 case E1000_DEV_ID_82541EI:
310 case E1000_DEV_ID_82541EI_MOBILE:
311 case E1000_DEV_ID_82541ER_LOM:
312 hw->mac_type = e1000_82541;
313 break;
314 case E1000_DEV_ID_82541ER:
315 case E1000_DEV_ID_82541GI:
316 case E1000_DEV_ID_82541GI_LF:
317 case E1000_DEV_ID_82541GI_MOBILE:
318 hw->mac_type = e1000_82541_rev_2;
319 break;
320 case E1000_DEV_ID_82547EI:
321 case E1000_DEV_ID_82547EI_MOBILE:
322 hw->mac_type = e1000_82547;
323 break;
324 case E1000_DEV_ID_82547GI:
325 hw->mac_type = e1000_82547_rev_2;
326 break;
327 case E1000_DEV_ID_INTEL_CE4100_GBE:
328 hw->mac_type = e1000_ce4100;
329 break;
330 default:
331 /* Should never have loaded on this device */
332 return -E1000_ERR_MAC_TYPE;
333 }
334
335 switch (hw->mac_type) {
336 case e1000_82541:
337 case e1000_82547:
338 case e1000_82541_rev_2:
339 case e1000_82547_rev_2:
340 hw->asf_firmware_present = true;
341 break;
342 default:
343 break;
344 }
345
346 /* The 82543 chip does not count tx_carrier_errors properly in
347 * FD mode
348 */
349 if (hw->mac_type == e1000_82543)
350 hw->bad_tx_carr_stats_fd = true;
351
352 if (hw->mac_type > e1000_82544)
353 hw->has_smbus = true;
354
355 return E1000_SUCCESS;
356 }
357
358 /**
359 * e1000_set_media_type - Set media type and TBI compatibility.
360 * @hw: Struct containing variables accessed by shared code
361 */
362 void e1000_set_media_type(struct e1000_hw *hw)
363 {
364 u32 status;
365
366 e_dbg("e1000_set_media_type");
367
368 if (hw->mac_type != e1000_82543) {
369 /* tbi_compatibility is only valid on 82543 */
370 hw->tbi_compatibility_en = false;
371 }
372
373 switch (hw->device_id) {
374 case E1000_DEV_ID_82545GM_SERDES:
375 case E1000_DEV_ID_82546GB_SERDES:
376 hw->media_type = e1000_media_type_internal_serdes;
377 break;
378 default:
379 switch (hw->mac_type) {
380 case e1000_82542_rev2_0:
381 case e1000_82542_rev2_1:
382 hw->media_type = e1000_media_type_fiber;
383 break;
384 case e1000_ce4100:
385 hw->media_type = e1000_media_type_copper;
386 break;
387 default:
388 status = er32(STATUS);
389 if (status & E1000_STATUS_TBIMODE) {
390 hw->media_type = e1000_media_type_fiber;
391 /* tbi_compatibility not valid on fiber */
392 hw->tbi_compatibility_en = false;
393 } else {
394 hw->media_type = e1000_media_type_copper;
395 }
396 break;
397 }
398 }
399 }
400
401 /**
402 * e1000_reset_hw: reset the hardware completely
403 * @hw: Struct containing variables accessed by shared code
404 *
405 * Reset the transmit and receive units; mask and clear all interrupts.
406 */
407 s32 e1000_reset_hw(struct e1000_hw *hw)
408 {
409 u32 ctrl;
410 u32 ctrl_ext;
411 u32 icr;
412 u32 manc;
413 u32 led_ctrl;
414 s32 ret_val;
415
416 e_dbg("e1000_reset_hw");
417
418 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
419 if (hw->mac_type == e1000_82542_rev2_0) {
420 e_dbg("Disabling MWI on 82542 rev 2.0\n");
421 e1000_pci_clear_mwi(hw);
422 }
423
424 /* Clear interrupt mask to stop board from generating interrupts */
425 e_dbg("Masking off all interrupts\n");
426 ew32(IMC, 0xffffffff);
427
428 /* Disable the Transmit and Receive units. Then delay to allow
429 * any pending transactions to complete before we hit the MAC with
430 * the global reset.
431 */
432 ew32(RCTL, 0);
433 ew32(TCTL, E1000_TCTL_PSP);
434 E1000_WRITE_FLUSH();
435
436 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
437 hw->tbi_compatibility_on = false;
438
439 /* Delay to allow any outstanding PCI transactions to complete before
440 * resetting the device
441 */
442 msleep(10);
443
444 ctrl = er32(CTRL);
445
446 /* Must reset the PHY before resetting the MAC */
447 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
448 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
449 msleep(5);
450 }
451
452 /* Issue a global reset to the MAC. This will reset the chip's
453 * transmit, receive, DMA, and link units. It will not effect
454 * the current PCI configuration. The global reset bit is self-
455 * clearing, and should clear within a microsecond.
456 */
457 e_dbg("Issuing a global reset to MAC\n");
458
459 switch (hw->mac_type) {
460 case e1000_82544:
461 case e1000_82540:
462 case e1000_82545:
463 case e1000_82546:
464 case e1000_82541:
465 case e1000_82541_rev_2:
466 /* These controllers can't ack the 64-bit write when issuing the
467 * reset, so use IO-mapping as a workaround to issue the reset */
468 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
469 break;
470 case e1000_82545_rev_3:
471 case e1000_82546_rev_3:
472 /* Reset is performed on a shadow of the control register */
473 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
474 break;
475 case e1000_ce4100:
476 default:
477 ew32(CTRL, (ctrl | E1000_CTRL_RST));
478 break;
479 }
480
481 /* After MAC reset, force reload of EEPROM to restore power-on settings to
482 * device. Later controllers reload the EEPROM automatically, so just wait
483 * for reload to complete.
484 */
485 switch (hw->mac_type) {
486 case e1000_82542_rev2_0:
487 case e1000_82542_rev2_1:
488 case e1000_82543:
489 case e1000_82544:
490 /* Wait for reset to complete */
491 udelay(10);
492 ctrl_ext = er32(CTRL_EXT);
493 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
494 ew32(CTRL_EXT, ctrl_ext);
495 E1000_WRITE_FLUSH();
496 /* Wait for EEPROM reload */
497 msleep(2);
498 break;
499 case e1000_82541:
500 case e1000_82541_rev_2:
501 case e1000_82547:
502 case e1000_82547_rev_2:
503 /* Wait for EEPROM reload */
504 msleep(20);
505 break;
506 default:
507 /* Auto read done will delay 5ms or poll based on mac type */
508 ret_val = e1000_get_auto_rd_done(hw);
509 if (ret_val)
510 return ret_val;
511 break;
512 }
513
514 /* Disable HW ARPs on ASF enabled adapters */
515 if (hw->mac_type >= e1000_82540) {
516 manc = er32(MANC);
517 manc &= ~(E1000_MANC_ARP_EN);
518 ew32(MANC, manc);
519 }
520
521 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
522 e1000_phy_init_script(hw);
523
524 /* Configure activity LED after PHY reset */
525 led_ctrl = er32(LEDCTL);
526 led_ctrl &= IGP_ACTIVITY_LED_MASK;
527 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
528 ew32(LEDCTL, led_ctrl);
529 }
530
531 /* Clear interrupt mask to stop board from generating interrupts */
532 e_dbg("Masking off all interrupts\n");
533 ew32(IMC, 0xffffffff);
534
535 /* Clear any pending interrupt events. */
536 icr = er32(ICR);
537
538 /* If MWI was previously enabled, reenable it. */
539 if (hw->mac_type == e1000_82542_rev2_0) {
540 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
541 e1000_pci_set_mwi(hw);
542 }
543
544 return E1000_SUCCESS;
545 }
546
547 /**
548 * e1000_init_hw: Performs basic configuration of the adapter.
549 * @hw: Struct containing variables accessed by shared code
550 *
551 * Assumes that the controller has previously been reset and is in a
552 * post-reset uninitialized state. Initializes the receive address registers,
553 * multicast table, and VLAN filter table. Calls routines to setup link
554 * configuration and flow control settings. Clears all on-chip counters. Leaves
555 * the transmit and receive units disabled and uninitialized.
556 */
557 s32 e1000_init_hw(struct e1000_hw *hw)
558 {
559 u32 ctrl;
560 u32 i;
561 s32 ret_val;
562 u32 mta_size;
563 u32 ctrl_ext;
564
565 e_dbg("e1000_init_hw");
566
567 /* Initialize Identification LED */
568 ret_val = e1000_id_led_init(hw);
569 if (ret_val) {
570 e_dbg("Error Initializing Identification LED\n");
571 return ret_val;
572 }
573
574 /* Set the media type and TBI compatibility */
575 e1000_set_media_type(hw);
576
577 /* Disabling VLAN filtering. */
578 e_dbg("Initializing the IEEE VLAN\n");
579 if (hw->mac_type < e1000_82545_rev_3)
580 ew32(VET, 0);
581 e1000_clear_vfta(hw);
582
583 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
584 if (hw->mac_type == e1000_82542_rev2_0) {
585 e_dbg("Disabling MWI on 82542 rev 2.0\n");
586 e1000_pci_clear_mwi(hw);
587 ew32(RCTL, E1000_RCTL_RST);
588 E1000_WRITE_FLUSH();
589 msleep(5);
590 }
591
592 /* Setup the receive address. This involves initializing all of the Receive
593 * Address Registers (RARs 0 - 15).
594 */
595 e1000_init_rx_addrs(hw);
596
597 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
598 if (hw->mac_type == e1000_82542_rev2_0) {
599 ew32(RCTL, 0);
600 E1000_WRITE_FLUSH();
601 msleep(1);
602 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
603 e1000_pci_set_mwi(hw);
604 }
605
606 /* Zero out the Multicast HASH table */
607 e_dbg("Zeroing the MTA\n");
608 mta_size = E1000_MC_TBL_SIZE;
609 for (i = 0; i < mta_size; i++) {
610 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
611 /* use write flush to prevent Memory Write Block (MWB) from
612 * occurring when accessing our register space */
613 E1000_WRITE_FLUSH();
614 }
615
616 /* Set the PCI priority bit correctly in the CTRL register. This
617 * determines if the adapter gives priority to receives, or if it
618 * gives equal priority to transmits and receives. Valid only on
619 * 82542 and 82543 silicon.
620 */
621 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
622 ctrl = er32(CTRL);
623 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
624 }
625
626 switch (hw->mac_type) {
627 case e1000_82545_rev_3:
628 case e1000_82546_rev_3:
629 break;
630 default:
631 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
632 if (hw->bus_type == e1000_bus_type_pcix
633 && e1000_pcix_get_mmrbc(hw) > 2048)
634 e1000_pcix_set_mmrbc(hw, 2048);
635 break;
636 }
637
638 /* Call a subroutine to configure the link and setup flow control. */
639 ret_val = e1000_setup_link(hw);
640
641 /* Set the transmit descriptor write-back policy */
642 if (hw->mac_type > e1000_82544) {
643 ctrl = er32(TXDCTL);
644 ctrl =
645 (ctrl & ~E1000_TXDCTL_WTHRESH) |
646 E1000_TXDCTL_FULL_TX_DESC_WB;
647 ew32(TXDCTL, ctrl);
648 }
649
650 /* Clear all of the statistics registers (clear on read). It is
651 * important that we do this after we have tried to establish link
652 * because the symbol error count will increment wildly if there
653 * is no link.
654 */
655 e1000_clear_hw_cntrs(hw);
656
657 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
658 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
659 ctrl_ext = er32(CTRL_EXT);
660 /* Relaxed ordering must be disabled to avoid a parity
661 * error crash in a PCI slot. */
662 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
663 ew32(CTRL_EXT, ctrl_ext);
664 }
665
666 return ret_val;
667 }
668
669 /**
670 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
671 * @hw: Struct containing variables accessed by shared code.
672 */
673 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
674 {
675 u16 eeprom_data;
676 s32 ret_val;
677
678 e_dbg("e1000_adjust_serdes_amplitude");
679
680 if (hw->media_type != e1000_media_type_internal_serdes)
681 return E1000_SUCCESS;
682
683 switch (hw->mac_type) {
684 case e1000_82545_rev_3:
685 case e1000_82546_rev_3:
686 break;
687 default:
688 return E1000_SUCCESS;
689 }
690
691 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
692 &eeprom_data);
693 if (ret_val) {
694 return ret_val;
695 }
696
697 if (eeprom_data != EEPROM_RESERVED_WORD) {
698 /* Adjust SERDES output amplitude only. */
699 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
700 ret_val =
701 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
702 if (ret_val)
703 return ret_val;
704 }
705
706 return E1000_SUCCESS;
707 }
708
709 /**
710 * e1000_setup_link - Configures flow control and link settings.
711 * @hw: Struct containing variables accessed by shared code
712 *
713 * Determines which flow control settings to use. Calls the appropriate media-
714 * specific link configuration function. Configures the flow control settings.
715 * Assuming the adapter has a valid link partner, a valid link should be
716 * established. Assumes the hardware has previously been reset and the
717 * transmitter and receiver are not enabled.
718 */
719 s32 e1000_setup_link(struct e1000_hw *hw)
720 {
721 u32 ctrl_ext;
722 s32 ret_val;
723 u16 eeprom_data;
724
725 e_dbg("e1000_setup_link");
726
727 /* Read and store word 0x0F of the EEPROM. This word contains bits
728 * that determine the hardware's default PAUSE (flow control) mode,
729 * a bit that determines whether the HW defaults to enabling or
730 * disabling auto-negotiation, and the direction of the
731 * SW defined pins. If there is no SW over-ride of the flow
732 * control setting, then the variable hw->fc will
733 * be initialized based on a value in the EEPROM.
734 */
735 if (hw->fc == E1000_FC_DEFAULT) {
736 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
737 1, &eeprom_data);
738 if (ret_val) {
739 e_dbg("EEPROM Read Error\n");
740 return -E1000_ERR_EEPROM;
741 }
742 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
743 hw->fc = E1000_FC_NONE;
744 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
745 EEPROM_WORD0F_ASM_DIR)
746 hw->fc = E1000_FC_TX_PAUSE;
747 else
748 hw->fc = E1000_FC_FULL;
749 }
750
751 /* We want to save off the original Flow Control configuration just
752 * in case we get disconnected and then reconnected into a different
753 * hub or switch with different Flow Control capabilities.
754 */
755 if (hw->mac_type == e1000_82542_rev2_0)
756 hw->fc &= (~E1000_FC_TX_PAUSE);
757
758 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
759 hw->fc &= (~E1000_FC_RX_PAUSE);
760
761 hw->original_fc = hw->fc;
762
763 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
764
765 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
766 * polarity value for the SW controlled pins, and setup the
767 * Extended Device Control reg with that info.
768 * This is needed because one of the SW controlled pins is used for
769 * signal detection. So this should be done before e1000_setup_pcs_link()
770 * or e1000_phy_setup() is called.
771 */
772 if (hw->mac_type == e1000_82543) {
773 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
774 1, &eeprom_data);
775 if (ret_val) {
776 e_dbg("EEPROM Read Error\n");
777 return -E1000_ERR_EEPROM;
778 }
779 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
780 SWDPIO__EXT_SHIFT);
781 ew32(CTRL_EXT, ctrl_ext);
782 }
783
784 /* Call the necessary subroutine to configure the link. */
785 ret_val = (hw->media_type == e1000_media_type_copper) ?
786 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
787
788 /* Initialize the flow control address, type, and PAUSE timer
789 * registers to their default values. This is done even if flow
790 * control is disabled, because it does not hurt anything to
791 * initialize these registers.
792 */
793 e_dbg("Initializing the Flow Control address, type and timer regs\n");
794
795 ew32(FCT, FLOW_CONTROL_TYPE);
796 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
797 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
798
799 ew32(FCTTV, hw->fc_pause_time);
800
801 /* Set the flow control receive threshold registers. Normally,
802 * these registers will be set to a default threshold that may be
803 * adjusted later by the driver's runtime code. However, if the
804 * ability to transmit pause frames in not enabled, then these
805 * registers will be set to 0.
806 */
807 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
808 ew32(FCRTL, 0);
809 ew32(FCRTH, 0);
810 } else {
811 /* We need to set up the Receive Threshold high and low water marks
812 * as well as (optionally) enabling the transmission of XON frames.
813 */
814 if (hw->fc_send_xon) {
815 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
816 ew32(FCRTH, hw->fc_high_water);
817 } else {
818 ew32(FCRTL, hw->fc_low_water);
819 ew32(FCRTH, hw->fc_high_water);
820 }
821 }
822 return ret_val;
823 }
824
825 /**
826 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
827 * @hw: Struct containing variables accessed by shared code
828 *
829 * Manipulates Physical Coding Sublayer functions in order to configure
830 * link. Assumes the hardware has been previously reset and the transmitter
831 * and receiver are not enabled.
832 */
833 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
834 {
835 u32 ctrl;
836 u32 status;
837 u32 txcw = 0;
838 u32 i;
839 u32 signal = 0;
840 s32 ret_val;
841
842 e_dbg("e1000_setup_fiber_serdes_link");
843
844 /* On adapters with a MAC newer than 82544, SWDP 1 will be
845 * set when the optics detect a signal. On older adapters, it will be
846 * cleared when there is a signal. This applies to fiber media only.
847 * If we're on serdes media, adjust the output amplitude to value
848 * set in the EEPROM.
849 */
850 ctrl = er32(CTRL);
851 if (hw->media_type == e1000_media_type_fiber)
852 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
853
854 ret_val = e1000_adjust_serdes_amplitude(hw);
855 if (ret_val)
856 return ret_val;
857
858 /* Take the link out of reset */
859 ctrl &= ~(E1000_CTRL_LRST);
860
861 /* Adjust VCO speed to improve BER performance */
862 ret_val = e1000_set_vco_speed(hw);
863 if (ret_val)
864 return ret_val;
865
866 e1000_config_collision_dist(hw);
867
868 /* Check for a software override of the flow control settings, and setup
869 * the device accordingly. If auto-negotiation is enabled, then software
870 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
871 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
872 * auto-negotiation is disabled, then software will have to manually
873 * configure the two flow control enable bits in the CTRL register.
874 *
875 * The possible values of the "fc" parameter are:
876 * 0: Flow control is completely disabled
877 * 1: Rx flow control is enabled (we can receive pause frames, but
878 * not send pause frames).
879 * 2: Tx flow control is enabled (we can send pause frames but we do
880 * not support receiving pause frames).
881 * 3: Both Rx and TX flow control (symmetric) are enabled.
882 */
883 switch (hw->fc) {
884 case E1000_FC_NONE:
885 /* Flow control is completely disabled by a software over-ride. */
886 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
887 break;
888 case E1000_FC_RX_PAUSE:
889 /* RX Flow control is enabled and TX Flow control is disabled by a
890 * software over-ride. Since there really isn't a way to advertise
891 * that we are capable of RX Pause ONLY, we will advertise that we
892 * support both symmetric and asymmetric RX PAUSE. Later, we will
893 * disable the adapter's ability to send PAUSE frames.
894 */
895 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
896 break;
897 case E1000_FC_TX_PAUSE:
898 /* TX Flow control is enabled, and RX Flow control is disabled, by a
899 * software over-ride.
900 */
901 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
902 break;
903 case E1000_FC_FULL:
904 /* Flow control (both RX and TX) is enabled by a software over-ride. */
905 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
906 break;
907 default:
908 e_dbg("Flow control param set incorrectly\n");
909 return -E1000_ERR_CONFIG;
910 break;
911 }
912
913 /* Since auto-negotiation is enabled, take the link out of reset (the link
914 * will be in reset, because we previously reset the chip). This will
915 * restart auto-negotiation. If auto-negotiation is successful then the
916 * link-up status bit will be set and the flow control enable bits (RFCE
917 * and TFCE) will be set according to their negotiated value.
918 */
919 e_dbg("Auto-negotiation enabled\n");
920
921 ew32(TXCW, txcw);
922 ew32(CTRL, ctrl);
923 E1000_WRITE_FLUSH();
924
925 hw->txcw = txcw;
926 msleep(1);
927
928 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
929 * indication in the Device Status Register. Time-out if a link isn't
930 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
931 * less than 500 milliseconds even if the other end is doing it in SW).
932 * For internal serdes, we just assume a signal is present, then poll.
933 */
934 if (hw->media_type == e1000_media_type_internal_serdes ||
935 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
936 e_dbg("Looking for Link\n");
937 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
938 msleep(10);
939 status = er32(STATUS);
940 if (status & E1000_STATUS_LU)
941 break;
942 }
943 if (i == (LINK_UP_TIMEOUT / 10)) {
944 e_dbg("Never got a valid link from auto-neg!!!\n");
945 hw->autoneg_failed = 1;
946 /* AutoNeg failed to achieve a link, so we'll call
947 * e1000_check_for_link. This routine will force the link up if
948 * we detect a signal. This will allow us to communicate with
949 * non-autonegotiating link partners.
950 */
951 ret_val = e1000_check_for_link(hw);
952 if (ret_val) {
953 e_dbg("Error while checking for link\n");
954 return ret_val;
955 }
956 hw->autoneg_failed = 0;
957 } else {
958 hw->autoneg_failed = 0;
959 e_dbg("Valid Link Found\n");
960 }
961 } else {
962 e_dbg("No Signal Detected\n");
963 }
964 return E1000_SUCCESS;
965 }
966
967 /**
968 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
969 * @hw: Struct containing variables accessed by shared code
970 *
971 * Commits changes to PHY configuration by calling e1000_phy_reset().
972 */
973 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
974 {
975 s32 ret_val;
976
977 /* SW reset the PHY so all changes take effect */
978 ret_val = e1000_phy_reset(hw);
979 if (ret_val) {
980 e_dbg("Error Resetting the PHY\n");
981 return ret_val;
982 }
983
984 return E1000_SUCCESS;
985 }
986
987 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
988 {
989 s32 ret_val;
990 u32 ctrl_aux;
991
992 switch (hw->phy_type) {
993 case e1000_phy_8211:
994 ret_val = e1000_copper_link_rtl_setup(hw);
995 if (ret_val) {
996 e_dbg("e1000_copper_link_rtl_setup failed!\n");
997 return ret_val;
998 }
999 break;
1000 case e1000_phy_8201:
1001 /* Set RMII mode */
1002 ctrl_aux = er32(CTL_AUX);
1003 ctrl_aux |= E1000_CTL_AUX_RMII;
1004 ew32(CTL_AUX, ctrl_aux);
1005 E1000_WRITE_FLUSH();
1006
1007 /* Disable the J/K bits required for receive */
1008 ctrl_aux = er32(CTL_AUX);
1009 ctrl_aux |= 0x4;
1010 ctrl_aux &= ~0x2;
1011 ew32(CTL_AUX, ctrl_aux);
1012 E1000_WRITE_FLUSH();
1013 ret_val = e1000_copper_link_rtl_setup(hw);
1014
1015 if (ret_val) {
1016 e_dbg("e1000_copper_link_rtl_setup failed!\n");
1017 return ret_val;
1018 }
1019 break;
1020 default:
1021 e_dbg("Error Resetting the PHY\n");
1022 return E1000_ERR_PHY_TYPE;
1023 }
1024
1025 return E1000_SUCCESS;
1026 }
1027
1028 /**
1029 * e1000_copper_link_preconfig - early configuration for copper
1030 * @hw: Struct containing variables accessed by shared code
1031 *
1032 * Make sure we have a valid PHY and change PHY mode before link setup.
1033 */
1034 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1035 {
1036 u32 ctrl;
1037 s32 ret_val;
1038 u16 phy_data;
1039
1040 e_dbg("e1000_copper_link_preconfig");
1041
1042 ctrl = er32(CTRL);
1043 /* With 82543, we need to force speed and duplex on the MAC equal to what
1044 * the PHY speed and duplex configuration is. In addition, we need to
1045 * perform a hardware reset on the PHY to take it out of reset.
1046 */
1047 if (hw->mac_type > e1000_82543) {
1048 ctrl |= E1000_CTRL_SLU;
1049 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1050 ew32(CTRL, ctrl);
1051 } else {
1052 ctrl |=
1053 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1054 ew32(CTRL, ctrl);
1055 ret_val = e1000_phy_hw_reset(hw);
1056 if (ret_val)
1057 return ret_val;
1058 }
1059
1060 /* Make sure we have a valid PHY */
1061 ret_val = e1000_detect_gig_phy(hw);
1062 if (ret_val) {
1063 e_dbg("Error, did not detect valid phy.\n");
1064 return ret_val;
1065 }
1066 e_dbg("Phy ID = %x\n", hw->phy_id);
1067
1068 /* Set PHY to class A mode (if necessary) */
1069 ret_val = e1000_set_phy_mode(hw);
1070 if (ret_val)
1071 return ret_val;
1072
1073 if ((hw->mac_type == e1000_82545_rev_3) ||
1074 (hw->mac_type == e1000_82546_rev_3)) {
1075 ret_val =
1076 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1077 phy_data |= 0x00000008;
1078 ret_val =
1079 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1080 }
1081
1082 if (hw->mac_type <= e1000_82543 ||
1083 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1084 hw->mac_type == e1000_82541_rev_2
1085 || hw->mac_type == e1000_82547_rev_2)
1086 hw->phy_reset_disable = false;
1087
1088 return E1000_SUCCESS;
1089 }
1090
1091 /**
1092 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1093 * @hw: Struct containing variables accessed by shared code
1094 */
1095 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1096 {
1097 u32 led_ctrl;
1098 s32 ret_val;
1099 u16 phy_data;
1100
1101 e_dbg("e1000_copper_link_igp_setup");
1102
1103 if (hw->phy_reset_disable)
1104 return E1000_SUCCESS;
1105
1106 ret_val = e1000_phy_reset(hw);
1107 if (ret_val) {
1108 e_dbg("Error Resetting the PHY\n");
1109 return ret_val;
1110 }
1111
1112 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1113 msleep(15);
1114 /* Configure activity LED after PHY reset */
1115 led_ctrl = er32(LEDCTL);
1116 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1117 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1118 ew32(LEDCTL, led_ctrl);
1119
1120 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1121 if (hw->phy_type == e1000_phy_igp) {
1122 /* disable lplu d3 during driver init */
1123 ret_val = e1000_set_d3_lplu_state(hw, false);
1124 if (ret_val) {
1125 e_dbg("Error Disabling LPLU D3\n");
1126 return ret_val;
1127 }
1128 }
1129
1130 /* Configure mdi-mdix settings */
1131 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1132 if (ret_val)
1133 return ret_val;
1134
1135 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1136 hw->dsp_config_state = e1000_dsp_config_disabled;
1137 /* Force MDI for earlier revs of the IGP PHY */
1138 phy_data &=
1139 ~(IGP01E1000_PSCR_AUTO_MDIX |
1140 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1141 hw->mdix = 1;
1142
1143 } else {
1144 hw->dsp_config_state = e1000_dsp_config_enabled;
1145 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1146
1147 switch (hw->mdix) {
1148 case 1:
1149 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1150 break;
1151 case 2:
1152 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1153 break;
1154 case 0:
1155 default:
1156 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1157 break;
1158 }
1159 }
1160 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1161 if (ret_val)
1162 return ret_val;
1163
1164 /* set auto-master slave resolution settings */
1165 if (hw->autoneg) {
1166 e1000_ms_type phy_ms_setting = hw->master_slave;
1167
1168 if (hw->ffe_config_state == e1000_ffe_config_active)
1169 hw->ffe_config_state = e1000_ffe_config_enabled;
1170
1171 if (hw->dsp_config_state == e1000_dsp_config_activated)
1172 hw->dsp_config_state = e1000_dsp_config_enabled;
1173
1174 /* when autonegotiation advertisement is only 1000Mbps then we
1175 * should disable SmartSpeed and enable Auto MasterSlave
1176 * resolution as hardware default. */
1177 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1178 /* Disable SmartSpeed */
1179 ret_val =
1180 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1181 &phy_data);
1182 if (ret_val)
1183 return ret_val;
1184 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1185 ret_val =
1186 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1187 phy_data);
1188 if (ret_val)
1189 return ret_val;
1190 /* Set auto Master/Slave resolution process */
1191 ret_val =
1192 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1193 if (ret_val)
1194 return ret_val;
1195 phy_data &= ~CR_1000T_MS_ENABLE;
1196 ret_val =
1197 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1198 if (ret_val)
1199 return ret_val;
1200 }
1201
1202 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1203 if (ret_val)
1204 return ret_val;
1205
1206 /* load defaults for future use */
1207 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1208 ((phy_data & CR_1000T_MS_VALUE) ?
1209 e1000_ms_force_master :
1210 e1000_ms_force_slave) : e1000_ms_auto;
1211
1212 switch (phy_ms_setting) {
1213 case e1000_ms_force_master:
1214 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1215 break;
1216 case e1000_ms_force_slave:
1217 phy_data |= CR_1000T_MS_ENABLE;
1218 phy_data &= ~(CR_1000T_MS_VALUE);
1219 break;
1220 case e1000_ms_auto:
1221 phy_data &= ~CR_1000T_MS_ENABLE;
1222 default:
1223 break;
1224 }
1225 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1226 if (ret_val)
1227 return ret_val;
1228 }
1229
1230 return E1000_SUCCESS;
1231 }
1232
1233 /**
1234 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1235 * @hw: Struct containing variables accessed by shared code
1236 */
1237 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1238 {
1239 s32 ret_val;
1240 u16 phy_data;
1241
1242 e_dbg("e1000_copper_link_mgp_setup");
1243
1244 if (hw->phy_reset_disable)
1245 return E1000_SUCCESS;
1246
1247 /* Enable CRS on TX. This must be set for half-duplex operation. */
1248 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1249 if (ret_val)
1250 return ret_val;
1251
1252 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1253
1254 /* Options:
1255 * MDI/MDI-X = 0 (default)
1256 * 0 - Auto for all speeds
1257 * 1 - MDI mode
1258 * 2 - MDI-X mode
1259 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1260 */
1261 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1262
1263 switch (hw->mdix) {
1264 case 1:
1265 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1266 break;
1267 case 2:
1268 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1269 break;
1270 case 3:
1271 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1272 break;
1273 case 0:
1274 default:
1275 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1276 break;
1277 }
1278
1279 /* Options:
1280 * disable_polarity_correction = 0 (default)
1281 * Automatic Correction for Reversed Cable Polarity
1282 * 0 - Disabled
1283 * 1 - Enabled
1284 */
1285 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1286 if (hw->disable_polarity_correction == 1)
1287 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1288 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1289 if (ret_val)
1290 return ret_val;
1291
1292 if (hw->phy_revision < M88E1011_I_REV_4) {
1293 /* Force TX_CLK in the Extended PHY Specific Control Register
1294 * to 25MHz clock.
1295 */
1296 ret_val =
1297 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1298 &phy_data);
1299 if (ret_val)
1300 return ret_val;
1301
1302 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1303
1304 if ((hw->phy_revision == E1000_REVISION_2) &&
1305 (hw->phy_id == M88E1111_I_PHY_ID)) {
1306 /* Vidalia Phy, set the downshift counter to 5x */
1307 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1308 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1309 ret_val = e1000_write_phy_reg(hw,
1310 M88E1000_EXT_PHY_SPEC_CTRL,
1311 phy_data);
1312 if (ret_val)
1313 return ret_val;
1314 } else {
1315 /* Configure Master and Slave downshift values */
1316 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1317 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1318 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1319 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1320 ret_val = e1000_write_phy_reg(hw,
1321 M88E1000_EXT_PHY_SPEC_CTRL,
1322 phy_data);
1323 if (ret_val)
1324 return ret_val;
1325 }
1326 }
1327
1328 /* SW Reset the PHY so all changes take effect */
1329 ret_val = e1000_phy_reset(hw);
1330 if (ret_val) {
1331 e_dbg("Error Resetting the PHY\n");
1332 return ret_val;
1333 }
1334
1335 return E1000_SUCCESS;
1336 }
1337
1338 /**
1339 * e1000_copper_link_autoneg - setup auto-neg
1340 * @hw: Struct containing variables accessed by shared code
1341 *
1342 * Setup auto-negotiation and flow control advertisements,
1343 * and then perform auto-negotiation.
1344 */
1345 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1346 {
1347 s32 ret_val;
1348 u16 phy_data;
1349
1350 e_dbg("e1000_copper_link_autoneg");
1351
1352 /* Perform some bounds checking on the hw->autoneg_advertised
1353 * parameter. If this variable is zero, then set it to the default.
1354 */
1355 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1356
1357 /* If autoneg_advertised is zero, we assume it was not defaulted
1358 * by the calling code so we set to advertise full capability.
1359 */
1360 if (hw->autoneg_advertised == 0)
1361 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1362
1363 /* IFE/RTL8201N PHY only supports 10/100 */
1364 if (hw->phy_type == e1000_phy_8201)
1365 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1366
1367 e_dbg("Reconfiguring auto-neg advertisement params\n");
1368 ret_val = e1000_phy_setup_autoneg(hw);
1369 if (ret_val) {
1370 e_dbg("Error Setting up Auto-Negotiation\n");
1371 return ret_val;
1372 }
1373 e_dbg("Restarting Auto-Neg\n");
1374
1375 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1376 * the Auto Neg Restart bit in the PHY control register.
1377 */
1378 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1379 if (ret_val)
1380 return ret_val;
1381
1382 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1383 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 /* Does the user want to wait for Auto-Neg to complete here, or
1388 * check at a later time (for example, callback routine).
1389 */
1390 if (hw->wait_autoneg_complete) {
1391 ret_val = e1000_wait_autoneg(hw);
1392 if (ret_val) {
1393 e_dbg
1394 ("Error while waiting for autoneg to complete\n");
1395 return ret_val;
1396 }
1397 }
1398
1399 hw->get_link_status = true;
1400
1401 return E1000_SUCCESS;
1402 }
1403
1404 /**
1405 * e1000_copper_link_postconfig - post link setup
1406 * @hw: Struct containing variables accessed by shared code
1407 *
1408 * Config the MAC and the PHY after link is up.
1409 * 1) Set up the MAC to the current PHY speed/duplex
1410 * if we are on 82543. If we
1411 * are on newer silicon, we only need to configure
1412 * collision distance in the Transmit Control Register.
1413 * 2) Set up flow control on the MAC to that established with
1414 * the link partner.
1415 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1416 */
1417 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1418 {
1419 s32 ret_val;
1420 e_dbg("e1000_copper_link_postconfig");
1421
1422 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1423 e1000_config_collision_dist(hw);
1424 } else {
1425 ret_val = e1000_config_mac_to_phy(hw);
1426 if (ret_val) {
1427 e_dbg("Error configuring MAC to PHY settings\n");
1428 return ret_val;
1429 }
1430 }
1431 ret_val = e1000_config_fc_after_link_up(hw);
1432 if (ret_val) {
1433 e_dbg("Error Configuring Flow Control\n");
1434 return ret_val;
1435 }
1436
1437 /* Config DSP to improve Giga link quality */
1438 if (hw->phy_type == e1000_phy_igp) {
1439 ret_val = e1000_config_dsp_after_link_change(hw, true);
1440 if (ret_val) {
1441 e_dbg("Error Configuring DSP after link up\n");
1442 return ret_val;
1443 }
1444 }
1445
1446 return E1000_SUCCESS;
1447 }
1448
1449 /**
1450 * e1000_setup_copper_link - phy/speed/duplex setting
1451 * @hw: Struct containing variables accessed by shared code
1452 *
1453 * Detects which PHY is present and sets up the speed and duplex
1454 */
1455 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1456 {
1457 s32 ret_val;
1458 u16 i;
1459 u16 phy_data;
1460
1461 e_dbg("e1000_setup_copper_link");
1462
1463 /* Check if it is a valid PHY and set PHY mode if necessary. */
1464 ret_val = e1000_copper_link_preconfig(hw);
1465 if (ret_val)
1466 return ret_val;
1467
1468 if (hw->phy_type == e1000_phy_igp) {
1469 ret_val = e1000_copper_link_igp_setup(hw);
1470 if (ret_val)
1471 return ret_val;
1472 } else if (hw->phy_type == e1000_phy_m88) {
1473 ret_val = e1000_copper_link_mgp_setup(hw);
1474 if (ret_val)
1475 return ret_val;
1476 } else {
1477 ret_val = gbe_dhg_phy_setup(hw);
1478 if (ret_val) {
1479 e_dbg("gbe_dhg_phy_setup failed!\n");
1480 return ret_val;
1481 }
1482 }
1483
1484 if (hw->autoneg) {
1485 /* Setup autoneg and flow control advertisement
1486 * and perform autonegotiation */
1487 ret_val = e1000_copper_link_autoneg(hw);
1488 if (ret_val)
1489 return ret_val;
1490 } else {
1491 /* PHY will be set to 10H, 10F, 100H,or 100F
1492 * depending on value from forced_speed_duplex. */
1493 e_dbg("Forcing speed and duplex\n");
1494 ret_val = e1000_phy_force_speed_duplex(hw);
1495 if (ret_val) {
1496 e_dbg("Error Forcing Speed and Duplex\n");
1497 return ret_val;
1498 }
1499 }
1500
1501 /* Check link status. Wait up to 100 microseconds for link to become
1502 * valid.
1503 */
1504 for (i = 0; i < 10; i++) {
1505 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1506 if (ret_val)
1507 return ret_val;
1508 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1509 if (ret_val)
1510 return ret_val;
1511
1512 if (phy_data & MII_SR_LINK_STATUS) {
1513 /* Config the MAC and PHY after link is up */
1514 ret_val = e1000_copper_link_postconfig(hw);
1515 if (ret_val)
1516 return ret_val;
1517
1518 e_dbg("Valid link established!!!\n");
1519 return E1000_SUCCESS;
1520 }
1521 udelay(10);
1522 }
1523
1524 e_dbg("Unable to establish link!!!\n");
1525 return E1000_SUCCESS;
1526 }
1527
1528 /**
1529 * e1000_phy_setup_autoneg - phy settings
1530 * @hw: Struct containing variables accessed by shared code
1531 *
1532 * Configures PHY autoneg and flow control advertisement settings
1533 */
1534 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1535 {
1536 s32 ret_val;
1537 u16 mii_autoneg_adv_reg;
1538 u16 mii_1000t_ctrl_reg;
1539
1540 e_dbg("e1000_phy_setup_autoneg");
1541
1542 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1543 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1544 if (ret_val)
1545 return ret_val;
1546
1547 /* Read the MII 1000Base-T Control Register (Address 9). */
1548 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1549 if (ret_val)
1550 return ret_val;
1551 else if (hw->phy_type == e1000_phy_8201)
1552 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1553
1554 /* Need to parse both autoneg_advertised and fc and set up
1555 * the appropriate PHY registers. First we will parse for
1556 * autoneg_advertised software override. Since we can advertise
1557 * a plethora of combinations, we need to check each bit
1558 * individually.
1559 */
1560
1561 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1562 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1563 * the 1000Base-T Control Register (Address 9).
1564 */
1565 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1566 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1567
1568 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1569
1570 /* Do we want to advertise 10 Mb Half Duplex? */
1571 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1572 e_dbg("Advertise 10mb Half duplex\n");
1573 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1574 }
1575
1576 /* Do we want to advertise 10 Mb Full Duplex? */
1577 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1578 e_dbg("Advertise 10mb Full duplex\n");
1579 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1580 }
1581
1582 /* Do we want to advertise 100 Mb Half Duplex? */
1583 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1584 e_dbg("Advertise 100mb Half duplex\n");
1585 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1586 }
1587
1588 /* Do we want to advertise 100 Mb Full Duplex? */
1589 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1590 e_dbg("Advertise 100mb Full duplex\n");
1591 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1592 }
1593
1594 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1595 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1596 e_dbg
1597 ("Advertise 1000mb Half duplex requested, request denied!\n");
1598 }
1599
1600 /* Do we want to advertise 1000 Mb Full Duplex? */
1601 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1602 e_dbg("Advertise 1000mb Full duplex\n");
1603 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1604 }
1605
1606 /* Check for a software override of the flow control settings, and
1607 * setup the PHY advertisement registers accordingly. If
1608 * auto-negotiation is enabled, then software will have to set the
1609 * "PAUSE" bits to the correct value in the Auto-Negotiation
1610 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1611 *
1612 * The possible values of the "fc" parameter are:
1613 * 0: Flow control is completely disabled
1614 * 1: Rx flow control is enabled (we can receive pause frames
1615 * but not send pause frames).
1616 * 2: Tx flow control is enabled (we can send pause frames
1617 * but we do not support receiving pause frames).
1618 * 3: Both Rx and TX flow control (symmetric) are enabled.
1619 * other: No software override. The flow control configuration
1620 * in the EEPROM is used.
1621 */
1622 switch (hw->fc) {
1623 case E1000_FC_NONE: /* 0 */
1624 /* Flow control (RX & TX) is completely disabled by a
1625 * software over-ride.
1626 */
1627 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1628 break;
1629 case E1000_FC_RX_PAUSE: /* 1 */
1630 /* RX Flow control is enabled, and TX Flow control is
1631 * disabled, by a software over-ride.
1632 */
1633 /* Since there really isn't a way to advertise that we are
1634 * capable of RX Pause ONLY, we will advertise that we
1635 * support both symmetric and asymmetric RX PAUSE. Later
1636 * (in e1000_config_fc_after_link_up) we will disable the
1637 *hw's ability to send PAUSE frames.
1638 */
1639 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1640 break;
1641 case E1000_FC_TX_PAUSE: /* 2 */
1642 /* TX Flow control is enabled, and RX Flow control is
1643 * disabled, by a software over-ride.
1644 */
1645 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1646 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1647 break;
1648 case E1000_FC_FULL: /* 3 */
1649 /* Flow control (both RX and TX) is enabled by a software
1650 * over-ride.
1651 */
1652 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1653 break;
1654 default:
1655 e_dbg("Flow control param set incorrectly\n");
1656 return -E1000_ERR_CONFIG;
1657 }
1658
1659 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1660 if (ret_val)
1661 return ret_val;
1662
1663 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1664
1665 if (hw->phy_type == e1000_phy_8201) {
1666 mii_1000t_ctrl_reg = 0;
1667 } else {
1668 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1669 mii_1000t_ctrl_reg);
1670 if (ret_val)
1671 return ret_val;
1672 }
1673
1674 return E1000_SUCCESS;
1675 }
1676
1677 /**
1678 * e1000_phy_force_speed_duplex - force link settings
1679 * @hw: Struct containing variables accessed by shared code
1680 *
1681 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1682 */
1683 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1684 {
1685 u32 ctrl;
1686 s32 ret_val;
1687 u16 mii_ctrl_reg;
1688 u16 mii_status_reg;
1689 u16 phy_data;
1690 u16 i;
1691
1692 e_dbg("e1000_phy_force_speed_duplex");
1693
1694 /* Turn off Flow control if we are forcing speed and duplex. */
1695 hw->fc = E1000_FC_NONE;
1696
1697 e_dbg("hw->fc = %d\n", hw->fc);
1698
1699 /* Read the Device Control Register. */
1700 ctrl = er32(CTRL);
1701
1702 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1703 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1704 ctrl &= ~(DEVICE_SPEED_MASK);
1705
1706 /* Clear the Auto Speed Detect Enable bit. */
1707 ctrl &= ~E1000_CTRL_ASDE;
1708
1709 /* Read the MII Control Register. */
1710 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1711 if (ret_val)
1712 return ret_val;
1713
1714 /* We need to disable autoneg in order to force link and duplex. */
1715
1716 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1717
1718 /* Are we forcing Full or Half Duplex? */
1719 if (hw->forced_speed_duplex == e1000_100_full ||
1720 hw->forced_speed_duplex == e1000_10_full) {
1721 /* We want to force full duplex so we SET the full duplex bits in the
1722 * Device and MII Control Registers.
1723 */
1724 ctrl |= E1000_CTRL_FD;
1725 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1726 e_dbg("Full Duplex\n");
1727 } else {
1728 /* We want to force half duplex so we CLEAR the full duplex bits in
1729 * the Device and MII Control Registers.
1730 */
1731 ctrl &= ~E1000_CTRL_FD;
1732 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1733 e_dbg("Half Duplex\n");
1734 }
1735
1736 /* Are we forcing 100Mbps??? */
1737 if (hw->forced_speed_duplex == e1000_100_full ||
1738 hw->forced_speed_duplex == e1000_100_half) {
1739 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1740 ctrl |= E1000_CTRL_SPD_100;
1741 mii_ctrl_reg |= MII_CR_SPEED_100;
1742 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1743 e_dbg("Forcing 100mb ");
1744 } else {
1745 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1746 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1747 mii_ctrl_reg |= MII_CR_SPEED_10;
1748 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1749 e_dbg("Forcing 10mb ");
1750 }
1751
1752 e1000_config_collision_dist(hw);
1753
1754 /* Write the configured values back to the Device Control Reg. */
1755 ew32(CTRL, ctrl);
1756
1757 if (hw->phy_type == e1000_phy_m88) {
1758 ret_val =
1759 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1760 if (ret_val)
1761 return ret_val;
1762
1763 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1764 * forced whenever speed are duplex are forced.
1765 */
1766 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1767 ret_val =
1768 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1769 if (ret_val)
1770 return ret_val;
1771
1772 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1773
1774 /* Need to reset the PHY or these changes will be ignored */
1775 mii_ctrl_reg |= MII_CR_RESET;
1776
1777 /* Disable MDI-X support for 10/100 */
1778 } else {
1779 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1780 * forced whenever speed or duplex are forced.
1781 */
1782 ret_val =
1783 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1784 if (ret_val)
1785 return ret_val;
1786
1787 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1788 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1789
1790 ret_val =
1791 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1792 if (ret_val)
1793 return ret_val;
1794 }
1795
1796 /* Write back the modified PHY MII control register. */
1797 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1798 if (ret_val)
1799 return ret_val;
1800
1801 udelay(1);
1802
1803 /* The wait_autoneg_complete flag may be a little misleading here.
1804 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1805 * But we do want to delay for a period while forcing only so we
1806 * don't generate false No Link messages. So we will wait here
1807 * only if the user has set wait_autoneg_complete to 1, which is
1808 * the default.
1809 */
1810 if (hw->wait_autoneg_complete) {
1811 /* We will wait for autoneg to complete. */
1812 e_dbg("Waiting for forced speed/duplex link.\n");
1813 mii_status_reg = 0;
1814
1815 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1816 for (i = PHY_FORCE_TIME; i > 0; i--) {
1817 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1818 * to be set.
1819 */
1820 ret_val =
1821 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1822 if (ret_val)
1823 return ret_val;
1824
1825 ret_val =
1826 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1827 if (ret_val)
1828 return ret_val;
1829
1830 if (mii_status_reg & MII_SR_LINK_STATUS)
1831 break;
1832 msleep(100);
1833 }
1834 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1835 /* We didn't get link. Reset the DSP and wait again for link. */
1836 ret_val = e1000_phy_reset_dsp(hw);
1837 if (ret_val) {
1838 e_dbg("Error Resetting PHY DSP\n");
1839 return ret_val;
1840 }
1841 }
1842 /* This loop will early-out if the link condition has been met. */
1843 for (i = PHY_FORCE_TIME; i > 0; i--) {
1844 if (mii_status_reg & MII_SR_LINK_STATUS)
1845 break;
1846 msleep(100);
1847 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1848 * to be set.
1849 */
1850 ret_val =
1851 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1852 if (ret_val)
1853 return ret_val;
1854
1855 ret_val =
1856 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1857 if (ret_val)
1858 return ret_val;
1859 }
1860 }
1861
1862 if (hw->phy_type == e1000_phy_m88) {
1863 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1864 * Extended PHY Specific Control Register to 25MHz clock. This value
1865 * defaults back to a 2.5MHz clock when the PHY is reset.
1866 */
1867 ret_val =
1868 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1869 &phy_data);
1870 if (ret_val)
1871 return ret_val;
1872
1873 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1874 ret_val =
1875 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1876 phy_data);
1877 if (ret_val)
1878 return ret_val;
1879
1880 /* In addition, because of the s/w reset above, we need to enable CRS on
1881 * TX. This must be set for both full and half duplex operation.
1882 */
1883 ret_val =
1884 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1885 if (ret_val)
1886 return ret_val;
1887
1888 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1889 ret_val =
1890 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1891 if (ret_val)
1892 return ret_val;
1893
1894 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1895 && (!hw->autoneg)
1896 && (hw->forced_speed_duplex == e1000_10_full
1897 || hw->forced_speed_duplex == e1000_10_half)) {
1898 ret_val = e1000_polarity_reversal_workaround(hw);
1899 if (ret_val)
1900 return ret_val;
1901 }
1902 }
1903 return E1000_SUCCESS;
1904 }
1905
1906 /**
1907 * e1000_config_collision_dist - set collision distance register
1908 * @hw: Struct containing variables accessed by shared code
1909 *
1910 * Sets the collision distance in the Transmit Control register.
1911 * Link should have been established previously. Reads the speed and duplex
1912 * information from the Device Status register.
1913 */
1914 void e1000_config_collision_dist(struct e1000_hw *hw)
1915 {
1916 u32 tctl, coll_dist;
1917
1918 e_dbg("e1000_config_collision_dist");
1919
1920 if (hw->mac_type < e1000_82543)
1921 coll_dist = E1000_COLLISION_DISTANCE_82542;
1922 else
1923 coll_dist = E1000_COLLISION_DISTANCE;
1924
1925 tctl = er32(TCTL);
1926
1927 tctl &= ~E1000_TCTL_COLD;
1928 tctl |= coll_dist << E1000_COLD_SHIFT;
1929
1930 ew32(TCTL, tctl);
1931 E1000_WRITE_FLUSH();
1932 }
1933
1934 /**
1935 * e1000_config_mac_to_phy - sync phy and mac settings
1936 * @hw: Struct containing variables accessed by shared code
1937 * @mii_reg: data to write to the MII control register
1938 *
1939 * Sets MAC speed and duplex settings to reflect the those in the PHY
1940 * The contents of the PHY register containing the needed information need to
1941 * be passed in.
1942 */
1943 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1944 {
1945 u32 ctrl;
1946 s32 ret_val;
1947 u16 phy_data;
1948
1949 e_dbg("e1000_config_mac_to_phy");
1950
1951 /* 82544 or newer MAC, Auto Speed Detection takes care of
1952 * MAC speed/duplex configuration.*/
1953 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1954 return E1000_SUCCESS;
1955
1956 /* Read the Device Control Register and set the bits to Force Speed
1957 * and Duplex.
1958 */
1959 ctrl = er32(CTRL);
1960 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1961 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1962
1963 switch (hw->phy_type) {
1964 case e1000_phy_8201:
1965 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1966 if (ret_val)
1967 return ret_val;
1968
1969 if (phy_data & RTL_PHY_CTRL_FD)
1970 ctrl |= E1000_CTRL_FD;
1971 else
1972 ctrl &= ~E1000_CTRL_FD;
1973
1974 if (phy_data & RTL_PHY_CTRL_SPD_100)
1975 ctrl |= E1000_CTRL_SPD_100;
1976 else
1977 ctrl |= E1000_CTRL_SPD_10;
1978
1979 e1000_config_collision_dist(hw);
1980 break;
1981 default:
1982 /* Set up duplex in the Device Control and Transmit Control
1983 * registers depending on negotiated values.
1984 */
1985 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1986 &phy_data);
1987 if (ret_val)
1988 return ret_val;
1989
1990 if (phy_data & M88E1000_PSSR_DPLX)
1991 ctrl |= E1000_CTRL_FD;
1992 else
1993 ctrl &= ~E1000_CTRL_FD;
1994
1995 e1000_config_collision_dist(hw);
1996
1997 /* Set up speed in the Device Control register depending on
1998 * negotiated values.
1999 */
2000 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2001 ctrl |= E1000_CTRL_SPD_1000;
2002 else if ((phy_data & M88E1000_PSSR_SPEED) ==
2003 M88E1000_PSSR_100MBS)
2004 ctrl |= E1000_CTRL_SPD_100;
2005 }
2006
2007 /* Write the configured values back to the Device Control Reg. */
2008 ew32(CTRL, ctrl);
2009 return E1000_SUCCESS;
2010 }
2011
2012 /**
2013 * e1000_force_mac_fc - force flow control settings
2014 * @hw: Struct containing variables accessed by shared code
2015 *
2016 * Forces the MAC's flow control settings.
2017 * Sets the TFCE and RFCE bits in the device control register to reflect
2018 * the adapter settings. TFCE and RFCE need to be explicitly set by
2019 * software when a Copper PHY is used because autonegotiation is managed
2020 * by the PHY rather than the MAC. Software must also configure these
2021 * bits when link is forced on a fiber connection.
2022 */
2023 s32 e1000_force_mac_fc(struct e1000_hw *hw)
2024 {
2025 u32 ctrl;
2026
2027 e_dbg("e1000_force_mac_fc");
2028
2029 /* Get the current configuration of the Device Control Register */
2030 ctrl = er32(CTRL);
2031
2032 /* Because we didn't get link via the internal auto-negotiation
2033 * mechanism (we either forced link or we got link via PHY
2034 * auto-neg), we have to manually enable/disable transmit an
2035 * receive flow control.
2036 *
2037 * The "Case" statement below enables/disable flow control
2038 * according to the "hw->fc" parameter.
2039 *
2040 * The possible values of the "fc" parameter are:
2041 * 0: Flow control is completely disabled
2042 * 1: Rx flow control is enabled (we can receive pause
2043 * frames but not send pause frames).
2044 * 2: Tx flow control is enabled (we can send pause frames
2045 * frames but we do not receive pause frames).
2046 * 3: Both Rx and TX flow control (symmetric) is enabled.
2047 * other: No other values should be possible at this point.
2048 */
2049
2050 switch (hw->fc) {
2051 case E1000_FC_NONE:
2052 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2053 break;
2054 case E1000_FC_RX_PAUSE:
2055 ctrl &= (~E1000_CTRL_TFCE);
2056 ctrl |= E1000_CTRL_RFCE;
2057 break;
2058 case E1000_FC_TX_PAUSE:
2059 ctrl &= (~E1000_CTRL_RFCE);
2060 ctrl |= E1000_CTRL_TFCE;
2061 break;
2062 case E1000_FC_FULL:
2063 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2064 break;
2065 default:
2066 e_dbg("Flow control param set incorrectly\n");
2067 return -E1000_ERR_CONFIG;
2068 }
2069
2070 /* Disable TX Flow Control for 82542 (rev 2.0) */
2071 if (hw->mac_type == e1000_82542_rev2_0)
2072 ctrl &= (~E1000_CTRL_TFCE);
2073
2074 ew32(CTRL, ctrl);
2075 return E1000_SUCCESS;
2076 }
2077
2078 /**
2079 * e1000_config_fc_after_link_up - configure flow control after autoneg
2080 * @hw: Struct containing variables accessed by shared code
2081 *
2082 * Configures flow control settings after link is established
2083 * Should be called immediately after a valid link has been established.
2084 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2085 * and autonegotiation is enabled, the MAC flow control settings will be set
2086 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2087 * and RFCE bits will be automatically set to the negotiated flow control mode.
2088 */
2089 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2090 {
2091 s32 ret_val;
2092 u16 mii_status_reg;
2093 u16 mii_nway_adv_reg;
2094 u16 mii_nway_lp_ability_reg;
2095 u16 speed;
2096 u16 duplex;
2097
2098 e_dbg("e1000_config_fc_after_link_up");
2099
2100 /* Check for the case where we have fiber media and auto-neg failed
2101 * so we had to force link. In this case, we need to force the
2102 * configuration of the MAC to match the "fc" parameter.
2103 */
2104 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
2105 || ((hw->media_type == e1000_media_type_internal_serdes)
2106 && (hw->autoneg_failed))
2107 || ((hw->media_type == e1000_media_type_copper)
2108 && (!hw->autoneg))) {
2109 ret_val = e1000_force_mac_fc(hw);
2110 if (ret_val) {
2111 e_dbg("Error forcing flow control settings\n");
2112 return ret_val;
2113 }
2114 }
2115
2116 /* Check for the case where we have copper media and auto-neg is
2117 * enabled. In this case, we need to check and see if Auto-Neg
2118 * has completed, and if so, how the PHY and link partner has
2119 * flow control configured.
2120 */
2121 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2122 /* Read the MII Status Register and check to see if AutoNeg
2123 * has completed. We read this twice because this reg has
2124 * some "sticky" (latched) bits.
2125 */
2126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2127 if (ret_val)
2128 return ret_val;
2129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2130 if (ret_val)
2131 return ret_val;
2132
2133 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2134 /* The AutoNeg process has completed, so we now need to
2135 * read both the Auto Negotiation Advertisement Register
2136 * (Address 4) and the Auto_Negotiation Base Page Ability
2137 * Register (Address 5) to determine how flow control was
2138 * negotiated.
2139 */
2140 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2141 &mii_nway_adv_reg);
2142 if (ret_val)
2143 return ret_val;
2144 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2145 &mii_nway_lp_ability_reg);
2146 if (ret_val)
2147 return ret_val;
2148
2149 /* Two bits in the Auto Negotiation Advertisement Register
2150 * (Address 4) and two bits in the Auto Negotiation Base
2151 * Page Ability Register (Address 5) determine flow control
2152 * for both the PHY and the link partner. The following
2153 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2154 * 1999, describes these PAUSE resolution bits and how flow
2155 * control is determined based upon these settings.
2156 * NOTE: DC = Don't Care
2157 *
2158 * LOCAL DEVICE | LINK PARTNER
2159 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2160 *-------|---------|-------|---------|--------------------
2161 * 0 | 0 | DC | DC | E1000_FC_NONE
2162 * 0 | 1 | 0 | DC | E1000_FC_NONE
2163 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2164 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2165 * 1 | 0 | 0 | DC | E1000_FC_NONE
2166 * 1 | DC | 1 | DC | E1000_FC_FULL
2167 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2168 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2169 *
2170 */
2171 /* Are both PAUSE bits set to 1? If so, this implies
2172 * Symmetric Flow Control is enabled at both ends. The
2173 * ASM_DIR bits are irrelevant per the spec.
2174 *
2175 * For Symmetric Flow Control:
2176 *
2177 * LOCAL DEVICE | LINK PARTNER
2178 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2179 *-------|---------|-------|---------|--------------------
2180 * 1 | DC | 1 | DC | E1000_FC_FULL
2181 *
2182 */
2183 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2184 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2185 /* Now we need to check if the user selected RX ONLY
2186 * of pause frames. In this case, we had to advertise
2187 * FULL flow control because we could not advertise RX
2188 * ONLY. Hence, we must now check to see if we need to
2189 * turn OFF the TRANSMISSION of PAUSE frames.
2190 */
2191 if (hw->original_fc == E1000_FC_FULL) {
2192 hw->fc = E1000_FC_FULL;
2193 e_dbg("Flow Control = FULL.\n");
2194 } else {
2195 hw->fc = E1000_FC_RX_PAUSE;
2196 e_dbg
2197 ("Flow Control = RX PAUSE frames only.\n");
2198 }
2199 }
2200 /* For receiving PAUSE frames ONLY.
2201 *
2202 * LOCAL DEVICE | LINK PARTNER
2203 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2204 *-------|---------|-------|---------|--------------------
2205 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2206 *
2207 */
2208 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2209 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2210 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2211 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2212 {
2213 hw->fc = E1000_FC_TX_PAUSE;
2214 e_dbg
2215 ("Flow Control = TX PAUSE frames only.\n");
2216 }
2217 /* For transmitting PAUSE frames ONLY.
2218 *
2219 * LOCAL DEVICE | LINK PARTNER
2220 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2221 *-------|---------|-------|---------|--------------------
2222 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2223 *
2224 */
2225 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2226 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2227 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2228 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2229 {
2230 hw->fc = E1000_FC_RX_PAUSE;
2231 e_dbg
2232 ("Flow Control = RX PAUSE frames only.\n");
2233 }
2234 /* Per the IEEE spec, at this point flow control should be
2235 * disabled. However, we want to consider that we could
2236 * be connected to a legacy switch that doesn't advertise
2237 * desired flow control, but can be forced on the link
2238 * partner. So if we advertised no flow control, that is
2239 * what we will resolve to. If we advertised some kind of
2240 * receive capability (Rx Pause Only or Full Flow Control)
2241 * and the link partner advertised none, we will configure
2242 * ourselves to enable Rx Flow Control only. We can do
2243 * this safely for two reasons: If the link partner really
2244 * didn't want flow control enabled, and we enable Rx, no
2245 * harm done since we won't be receiving any PAUSE frames
2246 * anyway. If the intent on the link partner was to have
2247 * flow control enabled, then by us enabling RX only, we
2248 * can at least receive pause frames and process them.
2249 * This is a good idea because in most cases, since we are
2250 * predominantly a server NIC, more times than not we will
2251 * be asked to delay transmission of packets than asking
2252 * our link partner to pause transmission of frames.
2253 */
2254 else if ((hw->original_fc == E1000_FC_NONE ||
2255 hw->original_fc == E1000_FC_TX_PAUSE) ||
2256 hw->fc_strict_ieee) {
2257 hw->fc = E1000_FC_NONE;
2258 e_dbg("Flow Control = NONE.\n");
2259 } else {
2260 hw->fc = E1000_FC_RX_PAUSE;
2261 e_dbg
2262 ("Flow Control = RX PAUSE frames only.\n");
2263 }
2264
2265 /* Now we need to do one last check... If we auto-
2266 * negotiated to HALF DUPLEX, flow control should not be
2267 * enabled per IEEE 802.3 spec.
2268 */
2269 ret_val =
2270 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2271 if (ret_val) {
2272 e_dbg
2273 ("Error getting link speed and duplex\n");
2274 return ret_val;
2275 }
2276
2277 if (duplex == HALF_DUPLEX)
2278 hw->fc = E1000_FC_NONE;
2279
2280 /* Now we call a subroutine to actually force the MAC
2281 * controller to use the correct flow control settings.
2282 */
2283 ret_val = e1000_force_mac_fc(hw);
2284 if (ret_val) {
2285 e_dbg
2286 ("Error forcing flow control settings\n");
2287 return ret_val;
2288 }
2289 } else {
2290 e_dbg
2291 ("Copper PHY and Auto Neg has not completed.\n");
2292 }
2293 }
2294 return E1000_SUCCESS;
2295 }
2296
2297 /**
2298 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2299 * @hw: pointer to the HW structure
2300 *
2301 * Checks for link up on the hardware. If link is not up and we have
2302 * a signal, then we need to force link up.
2303 */
2304 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2305 {
2306 u32 rxcw;
2307 u32 ctrl;
2308 u32 status;
2309 s32 ret_val = E1000_SUCCESS;
2310
2311 e_dbg("e1000_check_for_serdes_link_generic");
2312
2313 ctrl = er32(CTRL);
2314 status = er32(STATUS);
2315 rxcw = er32(RXCW);
2316
2317 /*
2318 * If we don't have link (auto-negotiation failed or link partner
2319 * cannot auto-negotiate), and our link partner is not trying to
2320 * auto-negotiate with us (we are receiving idles or data),
2321 * we need to force link up. We also need to give auto-negotiation
2322 * time to complete.
2323 */
2324 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2325 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2326 if (hw->autoneg_failed == 0) {
2327 hw->autoneg_failed = 1;
2328 goto out;
2329 }
2330 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2331
2332 /* Disable auto-negotiation in the TXCW register */
2333 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2334
2335 /* Force link-up and also force full-duplex. */
2336 ctrl = er32(CTRL);
2337 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2338 ew32(CTRL, ctrl);
2339
2340 /* Configure Flow Control after forcing link up. */
2341 ret_val = e1000_config_fc_after_link_up(hw);
2342 if (ret_val) {
2343 e_dbg("Error configuring flow control\n");
2344 goto out;
2345 }
2346 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2347 /*
2348 * If we are forcing link and we are receiving /C/ ordered
2349 * sets, re-enable auto-negotiation in the TXCW register
2350 * and disable forced link in the Device Control register
2351 * in an attempt to auto-negotiate with our link partner.
2352 */
2353 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2354 ew32(TXCW, hw->txcw);
2355 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2356
2357 hw->serdes_has_link = true;
2358 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2359 /*
2360 * If we force link for non-auto-negotiation switch, check
2361 * link status based on MAC synchronization for internal
2362 * serdes media type.
2363 */
2364 /* SYNCH bit and IV bit are sticky. */
2365 udelay(10);
2366 rxcw = er32(RXCW);
2367 if (rxcw & E1000_RXCW_SYNCH) {
2368 if (!(rxcw & E1000_RXCW_IV)) {
2369 hw->serdes_has_link = true;
2370 e_dbg("SERDES: Link up - forced.\n");
2371 }
2372 } else {
2373 hw->serdes_has_link = false;
2374 e_dbg("SERDES: Link down - force failed.\n");
2375 }
2376 }
2377
2378 if (E1000_TXCW_ANE & er32(TXCW)) {
2379 status = er32(STATUS);
2380 if (status & E1000_STATUS_LU) {
2381 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2382 udelay(10);
2383 rxcw = er32(RXCW);
2384 if (rxcw & E1000_RXCW_SYNCH) {
2385 if (!(rxcw & E1000_RXCW_IV)) {
2386 hw->serdes_has_link = true;
2387 e_dbg("SERDES: Link up - autoneg "
2388 "completed successfully.\n");
2389 } else {
2390 hw->serdes_has_link = false;
2391 e_dbg("SERDES: Link down - invalid"
2392 "codewords detected in autoneg.\n");
2393 }
2394 } else {
2395 hw->serdes_has_link = false;
2396 e_dbg("SERDES: Link down - no sync.\n");
2397 }
2398 } else {
2399 hw->serdes_has_link = false;
2400 e_dbg("SERDES: Link down - autoneg failed\n");
2401 }
2402 }
2403
2404 out:
2405 return ret_val;
2406 }
2407
2408 /**
2409 * e1000_check_for_link
2410 * @hw: Struct containing variables accessed by shared code
2411 *
2412 * Checks to see if the link status of the hardware has changed.
2413 * Called by any function that needs to check the link status of the adapter.
2414 */
2415 s32 e1000_check_for_link(struct e1000_hw *hw)
2416 {
2417 u32 rxcw = 0;
2418 u32 ctrl;
2419 u32 status;
2420 u32 rctl;
2421 u32 icr;
2422 u32 signal = 0;
2423 s32 ret_val;
2424 u16 phy_data;
2425
2426 e_dbg("e1000_check_for_link");
2427
2428 ctrl = er32(CTRL);
2429 status = er32(STATUS);
2430
2431 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2432 * set when the optics detect a signal. On older adapters, it will be
2433 * cleared when there is a signal. This applies to fiber media only.
2434 */
2435 if ((hw->media_type == e1000_media_type_fiber) ||
2436 (hw->media_type == e1000_media_type_internal_serdes)) {
2437 rxcw = er32(RXCW);
2438
2439 if (hw->media_type == e1000_media_type_fiber) {
2440 signal =
2441 (hw->mac_type >
2442 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2443 if (status & E1000_STATUS_LU)
2444 hw->get_link_status = false;
2445 }
2446 }
2447
2448 /* If we have a copper PHY then we only want to go out to the PHY
2449 * registers to see if Auto-Neg has completed and/or if our link
2450 * status has changed. The get_link_status flag will be set if we
2451 * receive a Link Status Change interrupt or we have Rx Sequence
2452 * Errors.
2453 */
2454 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2455 /* First we want to see if the MII Status Register reports
2456 * link. If so, then we want to get the current speed/duplex
2457 * of the PHY.
2458 * Read the register twice since the link bit is sticky.
2459 */
2460 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2461 if (ret_val)
2462 return ret_val;
2463 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2464 if (ret_val)
2465 return ret_val;
2466
2467 if (phy_data & MII_SR_LINK_STATUS) {
2468 hw->get_link_status = false;
2469 /* Check if there was DownShift, must be checked immediately after
2470 * link-up */
2471 e1000_check_downshift(hw);
2472
2473 /* If we are on 82544 or 82543 silicon and speed/duplex
2474 * are forced to 10H or 10F, then we will implement the polarity
2475 * reversal workaround. We disable interrupts first, and upon
2476 * returning, place the devices interrupt state to its previous
2477 * value except for the link status change interrupt which will
2478 * happen due to the execution of this workaround.
2479 */
2480
2481 if ((hw->mac_type == e1000_82544
2482 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2483 && (hw->forced_speed_duplex == e1000_10_full
2484 || hw->forced_speed_duplex == e1000_10_half)) {
2485 ew32(IMC, 0xffffffff);
2486 ret_val =
2487 e1000_polarity_reversal_workaround(hw);
2488 icr = er32(ICR);
2489 ew32(ICS, (icr & ~E1000_ICS_LSC));
2490 ew32(IMS, IMS_ENABLE_MASK);
2491 }
2492
2493 } else {
2494 /* No link detected */
2495 e1000_config_dsp_after_link_change(hw, false);
2496 return 0;
2497 }
2498
2499 /* If we are forcing speed/duplex, then we simply return since
2500 * we have already determined whether we have link or not.
2501 */
2502 if (!hw->autoneg)
2503 return -E1000_ERR_CONFIG;
2504
2505 /* optimize the dsp settings for the igp phy */
2506 e1000_config_dsp_after_link_change(hw, true);
2507
2508 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2509 * have Si on board that is 82544 or newer, Auto
2510 * Speed Detection takes care of MAC speed/duplex
2511 * configuration. So we only need to configure Collision
2512 * Distance in the MAC. Otherwise, we need to force
2513 * speed/duplex on the MAC to the current PHY speed/duplex
2514 * settings.
2515 */
2516 if ((hw->mac_type >= e1000_82544) &&
2517 (hw->mac_type != e1000_ce4100))
2518 e1000_config_collision_dist(hw);
2519 else {
2520 ret_val = e1000_config_mac_to_phy(hw);
2521 if (ret_val) {
2522 e_dbg
2523 ("Error configuring MAC to PHY settings\n");
2524 return ret_val;
2525 }
2526 }
2527
2528 /* Configure Flow Control now that Auto-Neg has completed. First, we
2529 * need to restore the desired flow control settings because we may
2530 * have had to re-autoneg with a different link partner.
2531 */
2532 ret_val = e1000_config_fc_after_link_up(hw);
2533 if (ret_val) {
2534 e_dbg("Error configuring flow control\n");
2535 return ret_val;
2536 }
2537
2538 /* At this point we know that we are on copper and we have
2539 * auto-negotiated link. These are conditions for checking the link
2540 * partner capability register. We use the link speed to determine if
2541 * TBI compatibility needs to be turned on or off. If the link is not
2542 * at gigabit speed, then TBI compatibility is not needed. If we are
2543 * at gigabit speed, we turn on TBI compatibility.
2544 */
2545 if (hw->tbi_compatibility_en) {
2546 u16 speed, duplex;
2547 ret_val =
2548 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2549 if (ret_val) {
2550 e_dbg
2551 ("Error getting link speed and duplex\n");
2552 return ret_val;
2553 }
2554 if (speed != SPEED_1000) {
2555 /* If link speed is not set to gigabit speed, we do not need
2556 * to enable TBI compatibility.
2557 */
2558 if (hw->tbi_compatibility_on) {
2559 /* If we previously were in the mode, turn it off. */
2560 rctl = er32(RCTL);
2561 rctl &= ~E1000_RCTL_SBP;
2562 ew32(RCTL, rctl);
2563 hw->tbi_compatibility_on = false;
2564 }
2565 } else {
2566 /* If TBI compatibility is was previously off, turn it on. For
2567 * compatibility with a TBI link partner, we will store bad
2568 * packets. Some frames have an additional byte on the end and
2569 * will look like CRC errors to to the hardware.
2570 */
2571 if (!hw->tbi_compatibility_on) {
2572 hw->tbi_compatibility_on = true;
2573 rctl = er32(RCTL);
2574 rctl |= E1000_RCTL_SBP;
2575 ew32(RCTL, rctl);
2576 }
2577 }
2578 }
2579 }
2580
2581 if ((hw->media_type == e1000_media_type_fiber) ||
2582 (hw->media_type == e1000_media_type_internal_serdes))
2583 e1000_check_for_serdes_link_generic(hw);
2584
2585 return E1000_SUCCESS;
2586 }
2587
2588 /**
2589 * e1000_get_speed_and_duplex
2590 * @hw: Struct containing variables accessed by shared code
2591 * @speed: Speed of the connection
2592 * @duplex: Duplex setting of the connection
2593
2594 * Detects the current speed and duplex settings of the hardware.
2595 */
2596 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2597 {
2598 u32 status;
2599 s32 ret_val;
2600 u16 phy_data;
2601
2602 e_dbg("e1000_get_speed_and_duplex");
2603
2604 if (hw->mac_type >= e1000_82543) {
2605 status = er32(STATUS);
2606 if (status & E1000_STATUS_SPEED_1000) {
2607 *speed = SPEED_1000;
2608 e_dbg("1000 Mbs, ");
2609 } else if (status & E1000_STATUS_SPEED_100) {
2610 *speed = SPEED_100;
2611 e_dbg("100 Mbs, ");
2612 } else {
2613 *speed = SPEED_10;
2614 e_dbg("10 Mbs, ");
2615 }
2616
2617 if (status & E1000_STATUS_FD) {
2618 *duplex = FULL_DUPLEX;
2619 e_dbg("Full Duplex\n");
2620 } else {
2621 *duplex = HALF_DUPLEX;
2622 e_dbg(" Half Duplex\n");
2623 }
2624 } else {
2625 e_dbg("1000 Mbs, Full Duplex\n");
2626 *speed = SPEED_1000;
2627 *duplex = FULL_DUPLEX;
2628 }
2629
2630 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2631 * if it is operating at half duplex. Here we set the duplex settings to
2632 * match the duplex in the link partner's capabilities.
2633 */
2634 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2635 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2636 if (ret_val)
2637 return ret_val;
2638
2639 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2640 *duplex = HALF_DUPLEX;
2641 else {
2642 ret_val =
2643 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2644 if (ret_val)
2645 return ret_val;
2646 if ((*speed == SPEED_100
2647 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2648 || (*speed == SPEED_10
2649 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2650 *duplex = HALF_DUPLEX;
2651 }
2652 }
2653
2654 return E1000_SUCCESS;
2655 }
2656
2657 /**
2658 * e1000_wait_autoneg
2659 * @hw: Struct containing variables accessed by shared code
2660 *
2661 * Blocks until autoneg completes or times out (~4.5 seconds)
2662 */
2663 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2664 {
2665 s32 ret_val;
2666 u16 i;
2667 u16 phy_data;
2668
2669 e_dbg("e1000_wait_autoneg");
2670 e_dbg("Waiting for Auto-Neg to complete.\n");
2671
2672 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2673 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2674 /* Read the MII Status Register and wait for Auto-Neg
2675 * Complete bit to be set.
2676 */
2677 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2678 if (ret_val)
2679 return ret_val;
2680 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2681 if (ret_val)
2682 return ret_val;
2683 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2684 return E1000_SUCCESS;
2685 }
2686 msleep(100);
2687 }
2688 return E1000_SUCCESS;
2689 }
2690
2691 /**
2692 * e1000_raise_mdi_clk - Raises the Management Data Clock
2693 * @hw: Struct containing variables accessed by shared code
2694 * @ctrl: Device control register's current value
2695 */
2696 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2697 {
2698 /* Raise the clock input to the Management Data Clock (by setting the MDC
2699 * bit), and then delay 10 microseconds.
2700 */
2701 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2702 E1000_WRITE_FLUSH();
2703 udelay(10);
2704 }
2705
2706 /**
2707 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2708 * @hw: Struct containing variables accessed by shared code
2709 * @ctrl: Device control register's current value
2710 */
2711 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2712 {
2713 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2714 * bit), and then delay 10 microseconds.
2715 */
2716 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2717 E1000_WRITE_FLUSH();
2718 udelay(10);
2719 }
2720
2721 /**
2722 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2723 * @hw: Struct containing variables accessed by shared code
2724 * @data: Data to send out to the PHY
2725 * @count: Number of bits to shift out
2726 *
2727 * Bits are shifted out in MSB to LSB order.
2728 */
2729 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2730 {
2731 u32 ctrl;
2732 u32 mask;
2733
2734 /* We need to shift "count" number of bits out to the PHY. So, the value
2735 * in the "data" parameter will be shifted out to the PHY one bit at a
2736 * time. In order to do this, "data" must be broken down into bits.
2737 */
2738 mask = 0x01;
2739 mask <<= (count - 1);
2740
2741 ctrl = er32(CTRL);
2742
2743 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2744 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2745
2746 while (mask) {
2747 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2748 * then raising and lowering the Management Data Clock. A "0" is
2749 * shifted out to the PHY by setting the MDIO bit to "0" and then
2750 * raising and lowering the clock.
2751 */
2752 if (data & mask)
2753 ctrl |= E1000_CTRL_MDIO;
2754 else
2755 ctrl &= ~E1000_CTRL_MDIO;
2756
2757 ew32(CTRL, ctrl);
2758 E1000_WRITE_FLUSH();
2759
2760 udelay(10);
2761
2762 e1000_raise_mdi_clk(hw, &ctrl);
2763 e1000_lower_mdi_clk(hw, &ctrl);
2764
2765 mask = mask >> 1;
2766 }
2767 }
2768
2769 /**
2770 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2771 * @hw: Struct containing variables accessed by shared code
2772 *
2773 * Bits are shifted in in MSB to LSB order.
2774 */
2775 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2776 {
2777 u32 ctrl;
2778 u16 data = 0;
2779 u8 i;
2780
2781 /* In order to read a register from the PHY, we need to shift in a total
2782 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2783 * to avoid contention on the MDIO pin when a read operation is performed.
2784 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2785 * by raising the input to the Management Data Clock (setting the MDC bit),
2786 * and then reading the value of the MDIO bit.
2787 */
2788 ctrl = er32(CTRL);
2789
2790 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2791 ctrl &= ~E1000_CTRL_MDIO_DIR;
2792 ctrl &= ~E1000_CTRL_MDIO;
2793
2794 ew32(CTRL, ctrl);
2795 E1000_WRITE_FLUSH();
2796
2797 /* Raise and Lower the clock before reading in the data. This accounts for
2798 * the turnaround bits. The first clock occurred when we clocked out the
2799 * last bit of the Register Address.
2800 */
2801 e1000_raise_mdi_clk(hw, &ctrl);
2802 e1000_lower_mdi_clk(hw, &ctrl);
2803
2804 for (data = 0, i = 0; i < 16; i++) {
2805 data = data << 1;
2806 e1000_raise_mdi_clk(hw, &ctrl);
2807 ctrl = er32(CTRL);
2808 /* Check to see if we shifted in a "1". */
2809 if (ctrl & E1000_CTRL_MDIO)
2810 data |= 1;
2811 e1000_lower_mdi_clk(hw, &ctrl);
2812 }
2813
2814 e1000_raise_mdi_clk(hw, &ctrl);
2815 e1000_lower_mdi_clk(hw, &ctrl);
2816
2817 return data;
2818 }
2819
2820
2821 /**
2822 * e1000_read_phy_reg - read a phy register
2823 * @hw: Struct containing variables accessed by shared code
2824 * @reg_addr: address of the PHY register to read
2825 *
2826 * Reads the value from a PHY register, if the value is on a specific non zero
2827 * page, sets the page first.
2828 */
2829 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2830 {
2831 u32 ret_val;
2832
2833 e_dbg("e1000_read_phy_reg");
2834
2835 if ((hw->phy_type == e1000_phy_igp) &&
2836 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2837 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2838 (u16) reg_addr);
2839 if (ret_val)
2840 return ret_val;
2841 }
2842
2843 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2844 phy_data);
2845
2846 return ret_val;
2847 }
2848
2849 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2850 u16 *phy_data)
2851 {
2852 u32 i;
2853 u32 mdic = 0;
2854 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2855
2856 e_dbg("e1000_read_phy_reg_ex");
2857
2858 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2859 e_dbg("PHY Address %d is out of range\n", reg_addr);
2860 return -E1000_ERR_PARAM;
2861 }
2862
2863 if (hw->mac_type > e1000_82543) {
2864 /* Set up Op-code, Phy Address, and register address in the MDI
2865 * Control register. The MAC will take care of interfacing with the
2866 * PHY to retrieve the desired data.
2867 */
2868 if (hw->mac_type == e1000_ce4100) {
2869 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2870 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2871 (INTEL_CE_GBE_MDIC_OP_READ) |
2872 (INTEL_CE_GBE_MDIC_GO));
2873
2874 writel(mdic, E1000_MDIO_CMD);
2875
2876 /* Poll the ready bit to see if the MDI read
2877 * completed
2878 */
2879 for (i = 0; i < 64; i++) {
2880 udelay(50);
2881 mdic = readl(E1000_MDIO_CMD);
2882 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2883 break;
2884 }
2885
2886 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2887 e_dbg("MDI Read did not complete\n");
2888 return -E1000_ERR_PHY;
2889 }
2890
2891 mdic = readl(E1000_MDIO_STS);
2892 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2893 e_dbg("MDI Read Error\n");
2894 return -E1000_ERR_PHY;
2895 }
2896 *phy_data = (u16) mdic;
2897 } else {
2898 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2899 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2900 (E1000_MDIC_OP_READ));
2901
2902 ew32(MDIC, mdic);
2903
2904 /* Poll the ready bit to see if the MDI read
2905 * completed
2906 */
2907 for (i = 0; i < 64; i++) {
2908 udelay(50);
2909 mdic = er32(MDIC);
2910 if (mdic & E1000_MDIC_READY)
2911 break;
2912 }
2913 if (!(mdic & E1000_MDIC_READY)) {
2914 e_dbg("MDI Read did not complete\n");
2915 return -E1000_ERR_PHY;
2916 }
2917 if (mdic & E1000_MDIC_ERROR) {
2918 e_dbg("MDI Error\n");
2919 return -E1000_ERR_PHY;
2920 }
2921 *phy_data = (u16) mdic;
2922 }
2923 } else {
2924 /* We must first send a preamble through the MDIO pin to signal the
2925 * beginning of an MII instruction. This is done by sending 32
2926 * consecutive "1" bits.
2927 */
2928 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2929
2930 /* Now combine the next few fields that are required for a read
2931 * operation. We use this method instead of calling the
2932 * e1000_shift_out_mdi_bits routine five different times. The format of
2933 * a MII read instruction consists of a shift out of 14 bits and is
2934 * defined as follows:
2935 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2936 * followed by a shift in of 18 bits. This first two bits shifted in
2937 * are TurnAround bits used to avoid contention on the MDIO pin when a
2938 * READ operation is performed. These two bits are thrown away
2939 * followed by a shift in of 16 bits which contains the desired data.
2940 */
2941 mdic = ((reg_addr) | (phy_addr << 5) |
2942 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2943
2944 e1000_shift_out_mdi_bits(hw, mdic, 14);
2945
2946 /* Now that we've shifted out the read command to the MII, we need to
2947 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2948 * register address.
2949 */
2950 *phy_data = e1000_shift_in_mdi_bits(hw);
2951 }
2952 return E1000_SUCCESS;
2953 }
2954
2955 /**
2956 * e1000_write_phy_reg - write a phy register
2957 *
2958 * @hw: Struct containing variables accessed by shared code
2959 * @reg_addr: address of the PHY register to write
2960 * @data: data to write to the PHY
2961
2962 * Writes a value to a PHY register
2963 */
2964 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2965 {
2966 u32 ret_val;
2967
2968 e_dbg("e1000_write_phy_reg");
2969
2970 if ((hw->phy_type == e1000_phy_igp) &&
2971 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2972 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2973 (u16) reg_addr);
2974 if (ret_val)
2975 return ret_val;
2976 }
2977
2978 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2979 phy_data);
2980
2981 return ret_val;
2982 }
2983
2984 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2985 u16 phy_data)
2986 {
2987 u32 i;
2988 u32 mdic = 0;
2989 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2990
2991 e_dbg("e1000_write_phy_reg_ex");
2992
2993 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2994 e_dbg("PHY Address %d is out of range\n", reg_addr);
2995 return -E1000_ERR_PARAM;
2996 }
2997
2998 if (hw->mac_type > e1000_82543) {
2999 /* Set up Op-code, Phy Address, register address, and data
3000 * intended for the PHY register in the MDI Control register.
3001 * The MAC will take care of interfacing with the PHY to send
3002 * the desired data.
3003 */
3004 if (hw->mac_type == e1000_ce4100) {
3005 mdic = (((u32) phy_data) |
3006 (reg_addr << E1000_MDIC_REG_SHIFT) |
3007 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3008 (INTEL_CE_GBE_MDIC_OP_WRITE) |
3009 (INTEL_CE_GBE_MDIC_GO));
3010
3011 writel(mdic, E1000_MDIO_CMD);
3012
3013 /* Poll the ready bit to see if the MDI read
3014 * completed
3015 */
3016 for (i = 0; i < 640; i++) {
3017 udelay(5);
3018 mdic = readl(E1000_MDIO_CMD);
3019 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
3020 break;
3021 }
3022 if (mdic & INTEL_CE_GBE_MDIC_GO) {
3023 e_dbg("MDI Write did not complete\n");
3024 return -E1000_ERR_PHY;
3025 }
3026 } else {
3027 mdic = (((u32) phy_data) |
3028 (reg_addr << E1000_MDIC_REG_SHIFT) |
3029 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3030 (E1000_MDIC_OP_WRITE));
3031
3032 ew32(MDIC, mdic);
3033
3034 /* Poll the ready bit to see if the MDI read
3035 * completed
3036 */
3037 for (i = 0; i < 641; i++) {
3038 udelay(5);
3039 mdic = er32(MDIC);
3040 if (mdic & E1000_MDIC_READY)
3041 break;
3042 }
3043 if (!(mdic & E1000_MDIC_READY)) {
3044 e_dbg("MDI Write did not complete\n");
3045 return -E1000_ERR_PHY;
3046 }
3047 }
3048 } else {
3049 /* We'll need to use the SW defined pins to shift the write command
3050 * out to the PHY. We first send a preamble to the PHY to signal the
3051 * beginning of the MII instruction. This is done by sending 32
3052 * consecutive "1" bits.
3053 */
3054 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3055
3056 /* Now combine the remaining required fields that will indicate a
3057 * write operation. We use this method instead of calling the
3058 * e1000_shift_out_mdi_bits routine for each field in the command. The
3059 * format of a MII write instruction is as follows:
3060 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3061 */
3062 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3063 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3064 mdic <<= 16;
3065 mdic |= (u32) phy_data;
3066
3067 e1000_shift_out_mdi_bits(hw, mdic, 32);
3068 }
3069
3070 return E1000_SUCCESS;
3071 }
3072
3073 /**
3074 * e1000_phy_hw_reset - reset the phy, hardware style
3075 * @hw: Struct containing variables accessed by shared code
3076 *
3077 * Returns the PHY to the power-on reset state
3078 */
3079 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3080 {
3081 u32 ctrl, ctrl_ext;
3082 u32 led_ctrl;
3083
3084 e_dbg("e1000_phy_hw_reset");
3085
3086 e_dbg("Resetting Phy...\n");
3087
3088 if (hw->mac_type > e1000_82543) {
3089 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3090 * bit. Then, take it out of reset.
3091 * For e1000 hardware, we delay for 10ms between the assert
3092 * and deassert.
3093 */
3094 ctrl = er32(CTRL);
3095 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3096 E1000_WRITE_FLUSH();
3097
3098 msleep(10);
3099
3100 ew32(CTRL, ctrl);
3101 E1000_WRITE_FLUSH();
3102
3103 } else {
3104 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3105 * bit to put the PHY into reset. Then, take it out of reset.
3106 */
3107 ctrl_ext = er32(CTRL_EXT);
3108 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3109 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3110 ew32(CTRL_EXT, ctrl_ext);
3111 E1000_WRITE_FLUSH();
3112 msleep(10);
3113 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3114 ew32(CTRL_EXT, ctrl_ext);
3115 E1000_WRITE_FLUSH();
3116 }
3117 udelay(150);
3118
3119 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3120 /* Configure activity LED after PHY reset */
3121 led_ctrl = er32(LEDCTL);
3122 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3123 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3124 ew32(LEDCTL, led_ctrl);
3125 }
3126
3127 /* Wait for FW to finish PHY configuration. */
3128 return e1000_get_phy_cfg_done(hw);
3129 }
3130
3131 /**
3132 * e1000_phy_reset - reset the phy to commit settings
3133 * @hw: Struct containing variables accessed by shared code
3134 *
3135 * Resets the PHY
3136 * Sets bit 15 of the MII Control register
3137 */
3138 s32 e1000_phy_reset(struct e1000_hw *hw)
3139 {
3140 s32 ret_val;
3141 u16 phy_data;
3142
3143 e_dbg("e1000_phy_reset");
3144
3145 switch (hw->phy_type) {
3146 case e1000_phy_igp:
3147 ret_val = e1000_phy_hw_reset(hw);
3148 if (ret_val)
3149 return ret_val;
3150 break;
3151 default:
3152 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3153 if (ret_val)
3154 return ret_val;
3155
3156 phy_data |= MII_CR_RESET;
3157 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3158 if (ret_val)
3159 return ret_val;
3160
3161 udelay(1);
3162 break;
3163 }
3164
3165 if (hw->phy_type == e1000_phy_igp)
3166 e1000_phy_init_script(hw);
3167
3168 return E1000_SUCCESS;
3169 }
3170
3171 /**
3172 * e1000_detect_gig_phy - check the phy type
3173 * @hw: Struct containing variables accessed by shared code
3174 *
3175 * Probes the expected PHY address for known PHY IDs
3176 */
3177 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3178 {
3179 s32 phy_init_status, ret_val;
3180 u16 phy_id_high, phy_id_low;
3181 bool match = false;
3182
3183 e_dbg("e1000_detect_gig_phy");
3184
3185 if (hw->phy_id != 0)
3186 return E1000_SUCCESS;
3187
3188 /* Read the PHY ID Registers to identify which PHY is onboard. */
3189 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3190 if (ret_val)
3191 return ret_val;
3192
3193 hw->phy_id = (u32) (phy_id_high << 16);
3194 udelay(20);
3195 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3196 if (ret_val)
3197 return ret_val;
3198
3199 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3200 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3201
3202 switch (hw->mac_type) {
3203 case e1000_82543:
3204 if (hw->phy_id == M88E1000_E_PHY_ID)
3205 match = true;
3206 break;
3207 case e1000_82544:
3208 if (hw->phy_id == M88E1000_I_PHY_ID)
3209 match = true;
3210 break;
3211 case e1000_82540:
3212 case e1000_82545:
3213 case e1000_82545_rev_3:
3214 case e1000_82546:
3215 case e1000_82546_rev_3:
3216 if (hw->phy_id == M88E1011_I_PHY_ID)
3217 match = true;
3218 break;
3219 case e1000_ce4100:
3220 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3221 (hw->phy_id == RTL8201N_PHY_ID) ||
3222 (hw->phy_id == M88E1118_E_PHY_ID))
3223 match = true;
3224 break;
3225 case e1000_82541:
3226 case e1000_82541_rev_2:
3227 case e1000_82547:
3228 case e1000_82547_rev_2:
3229 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3230 match = true;
3231 break;
3232 default:
3233 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3234 return -E1000_ERR_CONFIG;
3235 }
3236 phy_init_status = e1000_set_phy_type(hw);
3237
3238 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3239 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3240 return E1000_SUCCESS;
3241 }
3242 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3243 return -E1000_ERR_PHY;
3244 }
3245
3246 /**
3247 * e1000_phy_reset_dsp - reset DSP
3248 * @hw: Struct containing variables accessed by shared code
3249 *
3250 * Resets the PHY's DSP
3251 */
3252 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3253 {
3254 s32 ret_val;
3255 e_dbg("e1000_phy_reset_dsp");
3256
3257 do {
3258 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3259 if (ret_val)
3260 break;
3261 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3262 if (ret_val)
3263 break;
3264 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3265 if (ret_val)
3266 break;
3267 ret_val = E1000_SUCCESS;
3268 } while (0);
3269
3270 return ret_val;
3271 }
3272
3273 /**
3274 * e1000_phy_igp_get_info - get igp specific registers
3275 * @hw: Struct containing variables accessed by shared code
3276 * @phy_info: PHY information structure
3277 *
3278 * Get PHY information from various PHY registers for igp PHY only.
3279 */
3280 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3281 struct e1000_phy_info *phy_info)
3282 {
3283 s32 ret_val;
3284 u16 phy_data, min_length, max_length, average;
3285 e1000_rev_polarity polarity;
3286
3287 e_dbg("e1000_phy_igp_get_info");
3288
3289 /* The downshift status is checked only once, after link is established,
3290 * and it stored in the hw->speed_downgraded parameter. */
3291 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3292
3293 /* IGP01E1000 does not need to support it. */
3294 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3295
3296 /* IGP01E1000 always correct polarity reversal */
3297 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3298
3299 /* Check polarity status */
3300 ret_val = e1000_check_polarity(hw, &polarity);
3301 if (ret_val)
3302 return ret_val;
3303
3304 phy_info->cable_polarity = polarity;
3305
3306 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3307 if (ret_val)
3308 return ret_val;
3309
3310 phy_info->mdix_mode =
3311 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3312 IGP01E1000_PSSR_MDIX_SHIFT);
3313
3314 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3315 IGP01E1000_PSSR_SPEED_1000MBPS) {
3316 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3317 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3318 if (ret_val)
3319 return ret_val;
3320
3321 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3322 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3323 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3324 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3325 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3326 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3327
3328 /* Get cable length */
3329 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3330 if (ret_val)
3331 return ret_val;
3332
3333 /* Translate to old method */
3334 average = (max_length + min_length) / 2;
3335
3336 if (average <= e1000_igp_cable_length_50)
3337 phy_info->cable_length = e1000_cable_length_50;
3338 else if (average <= e1000_igp_cable_length_80)
3339 phy_info->cable_length = e1000_cable_length_50_80;
3340 else if (average <= e1000_igp_cable_length_110)
3341 phy_info->cable_length = e1000_cable_length_80_110;
3342 else if (average <= e1000_igp_cable_length_140)
3343 phy_info->cable_length = e1000_cable_length_110_140;
3344 else
3345 phy_info->cable_length = e1000_cable_length_140;
3346 }
3347
3348 return E1000_SUCCESS;
3349 }
3350
3351 /**
3352 * e1000_phy_m88_get_info - get m88 specific registers
3353 * @hw: Struct containing variables accessed by shared code
3354 * @phy_info: PHY information structure
3355 *
3356 * Get PHY information from various PHY registers for m88 PHY only.
3357 */
3358 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3359 struct e1000_phy_info *phy_info)
3360 {
3361 s32 ret_val;
3362 u16 phy_data;
3363 e1000_rev_polarity polarity;
3364
3365 e_dbg("e1000_phy_m88_get_info");
3366
3367 /* The downshift status is checked only once, after link is established,
3368 * and it stored in the hw->speed_downgraded parameter. */
3369 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3370
3371 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3372 if (ret_val)
3373 return ret_val;
3374
3375 phy_info->extended_10bt_distance =
3376 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3377 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3378 e1000_10bt_ext_dist_enable_lower :
3379 e1000_10bt_ext_dist_enable_normal;
3380
3381 phy_info->polarity_correction =
3382 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3383 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3384 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3385
3386 /* Check polarity status */
3387 ret_val = e1000_check_polarity(hw, &polarity);
3388 if (ret_val)
3389 return ret_val;
3390 phy_info->cable_polarity = polarity;
3391
3392 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3393 if (ret_val)
3394 return ret_val;
3395
3396 phy_info->mdix_mode =
3397 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3398 M88E1000_PSSR_MDIX_SHIFT);
3399
3400 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3401 /* Cable Length Estimation and Local/Remote Receiver Information
3402 * are only valid at 1000 Mbps.
3403 */
3404 phy_info->cable_length =
3405 (e1000_cable_length) ((phy_data &
3406 M88E1000_PSSR_CABLE_LENGTH) >>
3407 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3408
3409 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3410 if (ret_val)
3411 return ret_val;
3412
3413 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3414 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3415 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3416 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3417 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3418 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3419
3420 }
3421
3422 return E1000_SUCCESS;
3423 }
3424
3425 /**
3426 * e1000_phy_get_info - request phy info
3427 * @hw: Struct containing variables accessed by shared code
3428 * @phy_info: PHY information structure
3429 *
3430 * Get PHY information from various PHY registers
3431 */
3432 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3433 {
3434 s32 ret_val;
3435 u16 phy_data;
3436
3437 e_dbg("e1000_phy_get_info");
3438
3439 phy_info->cable_length = e1000_cable_length_undefined;
3440 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3441 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3442 phy_info->downshift = e1000_downshift_undefined;
3443 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3444 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3445 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3446 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3447
3448 if (hw->media_type != e1000_media_type_copper) {
3449 e_dbg("PHY info is only valid for copper media\n");
3450 return -E1000_ERR_CONFIG;
3451 }
3452
3453 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3454 if (ret_val)
3455 return ret_val;
3456
3457 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3458 if (ret_val)
3459 return ret_val;
3460
3461 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3462 e_dbg("PHY info is only valid if link is up\n");
3463 return -E1000_ERR_CONFIG;
3464 }
3465
3466 if (hw->phy_type == e1000_phy_igp)
3467 return e1000_phy_igp_get_info(hw, phy_info);
3468 else if ((hw->phy_type == e1000_phy_8211) ||
3469 (hw->phy_type == e1000_phy_8201))
3470 return E1000_SUCCESS;
3471 else
3472 return e1000_phy_m88_get_info(hw, phy_info);
3473 }
3474
3475 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3476 {
3477 e_dbg("e1000_validate_mdi_settings");
3478
3479 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3480 e_dbg("Invalid MDI setting detected\n");
3481 hw->mdix = 1;
3482 return -E1000_ERR_CONFIG;
3483 }
3484 return E1000_SUCCESS;
3485 }
3486
3487 /**
3488 * e1000_init_eeprom_params - initialize sw eeprom vars
3489 * @hw: Struct containing variables accessed by shared code
3490 *
3491 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3492 * is configured.
3493 */
3494 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3495 {
3496 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3497 u32 eecd = er32(EECD);
3498 s32 ret_val = E1000_SUCCESS;
3499 u16 eeprom_size;
3500
3501 e_dbg("e1000_init_eeprom_params");
3502
3503 switch (hw->mac_type) {
3504 case e1000_82542_rev2_0:
3505 case e1000_82542_rev2_1:
3506 case e1000_82543:
3507 case e1000_82544:
3508 eeprom->type = e1000_eeprom_microwire;
3509 eeprom->word_size = 64;
3510 eeprom->opcode_bits = 3;
3511 eeprom->address_bits = 6;
3512 eeprom->delay_usec = 50;
3513 break;
3514 case e1000_82540:
3515 case e1000_82545:
3516 case e1000_82545_rev_3:
3517 case e1000_82546:
3518 case e1000_82546_rev_3:
3519 eeprom->type = e1000_eeprom_microwire;
3520 eeprom->opcode_bits = 3;
3521 eeprom->delay_usec = 50;
3522 if (eecd & E1000_EECD_SIZE) {
3523 eeprom->word_size = 256;
3524 eeprom->address_bits = 8;
3525 } else {
3526 eeprom->word_size = 64;
3527 eeprom->address_bits = 6;
3528 }
3529 break;
3530 case e1000_82541:
3531 case e1000_82541_rev_2:
3532 case e1000_82547:
3533 case e1000_82547_rev_2:
3534 if (eecd & E1000_EECD_TYPE) {
3535 eeprom->type = e1000_eeprom_spi;
3536 eeprom->opcode_bits = 8;
3537 eeprom->delay_usec = 1;
3538 if (eecd & E1000_EECD_ADDR_BITS) {
3539 eeprom->page_size = 32;
3540 eeprom->address_bits = 16;
3541 } else {
3542 eeprom->page_size = 8;
3543 eeprom->address_bits = 8;
3544 }
3545 } else {
3546 eeprom->type = e1000_eeprom_microwire;
3547 eeprom->opcode_bits = 3;
3548 eeprom->delay_usec = 50;
3549 if (eecd & E1000_EECD_ADDR_BITS) {
3550 eeprom->word_size = 256;
3551 eeprom->address_bits = 8;
3552 } else {
3553 eeprom->word_size = 64;
3554 eeprom->address_bits = 6;
3555 }
3556 }
3557 break;
3558 default:
3559 break;
3560 }
3561
3562 if (eeprom->type == e1000_eeprom_spi) {
3563 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3564 * 32KB (incremented by powers of 2).
3565 */
3566 /* Set to default value for initial eeprom read. */
3567 eeprom->word_size = 64;
3568 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3569 if (ret_val)
3570 return ret_val;
3571 eeprom_size =
3572 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3573 /* 256B eeprom size was not supported in earlier hardware, so we
3574 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3575 * is never the result used in the shifting logic below. */
3576 if (eeprom_size)
3577 eeprom_size++;
3578
3579 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3580 }
3581 return ret_val;
3582 }
3583
3584 /**
3585 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3586 * @hw: Struct containing variables accessed by shared code
3587 * @eecd: EECD's current value
3588 */
3589 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3590 {
3591 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3592 * wait <delay> microseconds.
3593 */
3594 *eecd = *eecd | E1000_EECD_SK;
3595 ew32(EECD, *eecd);
3596 E1000_WRITE_FLUSH();
3597 udelay(hw->eeprom.delay_usec);
3598 }
3599
3600 /**
3601 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3602 * @hw: Struct containing variables accessed by shared code
3603 * @eecd: EECD's current value
3604 */
3605 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3606 {
3607 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3608 * wait 50 microseconds.
3609 */
3610 *eecd = *eecd & ~E1000_EECD_SK;
3611 ew32(EECD, *eecd);
3612 E1000_WRITE_FLUSH();
3613 udelay(hw->eeprom.delay_usec);
3614 }
3615
3616 /**
3617 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3618 * @hw: Struct containing variables accessed by shared code
3619 * @data: data to send to the EEPROM
3620 * @count: number of bits to shift out
3621 */
3622 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3623 {
3624 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3625 u32 eecd;
3626 u32 mask;
3627
3628 /* We need to shift "count" bits out to the EEPROM. So, value in the
3629 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3630 * In order to do this, "data" must be broken down into bits.
3631 */
3632 mask = 0x01 << (count - 1);
3633 eecd = er32(EECD);
3634 if (eeprom->type == e1000_eeprom_microwire) {
3635 eecd &= ~E1000_EECD_DO;
3636 } else if (eeprom->type == e1000_eeprom_spi) {
3637 eecd |= E1000_EECD_DO;
3638 }
3639 do {
3640 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3641 * and then raising and then lowering the clock (the SK bit controls
3642 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3643 * by setting "DI" to "0" and then raising and then lowering the clock.
3644 */
3645 eecd &= ~E1000_EECD_DI;
3646
3647 if (data & mask)
3648 eecd |= E1000_EECD_DI;
3649
3650 ew32(EECD, eecd);
3651 E1000_WRITE_FLUSH();
3652
3653 udelay(eeprom->delay_usec);
3654
3655 e1000_raise_ee_clk(hw, &eecd);
3656 e1000_lower_ee_clk(hw, &eecd);
3657
3658 mask = mask >> 1;
3659
3660 } while (mask);
3661
3662 /* We leave the "DI" bit set to "0" when we leave this routine. */
3663 eecd &= ~E1000_EECD_DI;
3664 ew32(EECD, eecd);
3665 }
3666
3667 /**
3668 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3669 * @hw: Struct containing variables accessed by shared code
3670 * @count: number of bits to shift in
3671 */
3672 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3673 {
3674 u32 eecd;
3675 u32 i;
3676 u16 data;
3677
3678 /* In order to read a register from the EEPROM, we need to shift 'count'
3679 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3680 * input to the EEPROM (setting the SK bit), and then reading the value of
3681 * the "DO" bit. During this "shifting in" process the "DI" bit should
3682 * always be clear.
3683 */
3684
3685 eecd = er32(EECD);
3686
3687 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3688 data = 0;
3689
3690 for (i = 0; i < count; i++) {
3691 data = data << 1;
3692 e1000_raise_ee_clk(hw, &eecd);
3693
3694 eecd = er32(EECD);
3695
3696 eecd &= ~(E1000_EECD_DI);
3697 if (eecd & E1000_EECD_DO)
3698 data |= 1;
3699
3700 e1000_lower_ee_clk(hw, &eecd);
3701 }
3702
3703 return data;
3704 }
3705
3706 /**
3707 * e1000_acquire_eeprom - Prepares EEPROM for access
3708 * @hw: Struct containing variables accessed by shared code
3709 *
3710 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3711 * function should be called before issuing a command to the EEPROM.
3712 */
3713 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3714 {
3715 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3716 u32 eecd, i = 0;
3717
3718 e_dbg("e1000_acquire_eeprom");
3719
3720 eecd = er32(EECD);
3721
3722 /* Request EEPROM Access */
3723 if (hw->mac_type > e1000_82544) {
3724 eecd |= E1000_EECD_REQ;
3725 ew32(EECD, eecd);
3726 eecd = er32(EECD);
3727 while ((!(eecd & E1000_EECD_GNT)) &&
3728 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3729 i++;
3730 udelay(5);
3731 eecd = er32(EECD);
3732 }
3733 if (!(eecd & E1000_EECD_GNT)) {
3734 eecd &= ~E1000_EECD_REQ;
3735 ew32(EECD, eecd);
3736 e_dbg("Could not acquire EEPROM grant\n");
3737 return -E1000_ERR_EEPROM;
3738 }
3739 }
3740
3741 /* Setup EEPROM for Read/Write */
3742
3743 if (eeprom->type == e1000_eeprom_microwire) {
3744 /* Clear SK and DI */
3745 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3746 ew32(EECD, eecd);
3747
3748 /* Set CS */
3749 eecd |= E1000_EECD_CS;
3750 ew32(EECD, eecd);
3751 } else if (eeprom->type == e1000_eeprom_spi) {
3752 /* Clear SK and CS */
3753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3754 ew32(EECD, eecd);
3755 udelay(1);
3756 }
3757
3758 return E1000_SUCCESS;
3759 }
3760
3761 /**
3762 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3763 * @hw: Struct containing variables accessed by shared code
3764 */
3765 static void e1000_standby_eeprom(struct e1000_hw *hw)
3766 {
3767 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3768 u32 eecd;
3769
3770 eecd = er32(EECD);
3771
3772 if (eeprom->type == e1000_eeprom_microwire) {
3773 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3774 ew32(EECD, eecd);
3775 E1000_WRITE_FLUSH();
3776 udelay(eeprom->delay_usec);
3777
3778 /* Clock high */
3779 eecd |= E1000_EECD_SK;
3780 ew32(EECD, eecd);
3781 E1000_WRITE_FLUSH();
3782 udelay(eeprom->delay_usec);
3783
3784 /* Select EEPROM */
3785 eecd |= E1000_EECD_CS;
3786 ew32(EECD, eecd);
3787 E1000_WRITE_FLUSH();
3788 udelay(eeprom->delay_usec);
3789
3790 /* Clock low */
3791 eecd &= ~E1000_EECD_SK;
3792 ew32(EECD, eecd);
3793 E1000_WRITE_FLUSH();
3794 udelay(eeprom->delay_usec);
3795 } else if (eeprom->type == e1000_eeprom_spi) {
3796 /* Toggle CS to flush commands */
3797 eecd |= E1000_EECD_CS;
3798 ew32(EECD, eecd);
3799 E1000_WRITE_FLUSH();
3800 udelay(eeprom->delay_usec);
3801 eecd &= ~E1000_EECD_CS;
3802 ew32(EECD, eecd);
3803 E1000_WRITE_FLUSH();
3804 udelay(eeprom->delay_usec);
3805 }
3806 }
3807
3808 /**
3809 * e1000_release_eeprom - drop chip select
3810 * @hw: Struct containing variables accessed by shared code
3811 *
3812 * Terminates a command by inverting the EEPROM's chip select pin
3813 */
3814 static void e1000_release_eeprom(struct e1000_hw *hw)
3815 {
3816 u32 eecd;
3817
3818 e_dbg("e1000_release_eeprom");
3819
3820 eecd = er32(EECD);
3821
3822 if (hw->eeprom.type == e1000_eeprom_spi) {
3823 eecd |= E1000_EECD_CS; /* Pull CS high */
3824 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3825
3826 ew32(EECD, eecd);
3827
3828 udelay(hw->eeprom.delay_usec);
3829 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3830 /* cleanup eeprom */
3831
3832 /* CS on Microwire is active-high */
3833 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3834
3835 ew32(EECD, eecd);
3836
3837 /* Rising edge of clock */
3838 eecd |= E1000_EECD_SK;
3839 ew32(EECD, eecd);
3840 E1000_WRITE_FLUSH();
3841 udelay(hw->eeprom.delay_usec);
3842
3843 /* Falling edge of clock */
3844 eecd &= ~E1000_EECD_SK;
3845 ew32(EECD, eecd);
3846 E1000_WRITE_FLUSH();
3847 udelay(hw->eeprom.delay_usec);
3848 }
3849
3850 /* Stop requesting EEPROM access */
3851 if (hw->mac_type > e1000_82544) {
3852 eecd &= ~E1000_EECD_REQ;
3853 ew32(EECD, eecd);
3854 }
3855 }
3856
3857 /**
3858 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3859 * @hw: Struct containing variables accessed by shared code
3860 */
3861 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3862 {
3863 u16 retry_count = 0;
3864 u8 spi_stat_reg;
3865
3866 e_dbg("e1000_spi_eeprom_ready");
3867
3868 /* Read "Status Register" repeatedly until the LSB is cleared. The
3869 * EEPROM will signal that the command has been completed by clearing
3870 * bit 0 of the internal status register. If it's not cleared within
3871 * 5 milliseconds, then error out.
3872 */
3873 retry_count = 0;
3874 do {
3875 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3876 hw->eeprom.opcode_bits);
3877 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3878 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3879 break;
3880
3881 udelay(5);
3882 retry_count += 5;
3883
3884 e1000_standby_eeprom(hw);
3885 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3886
3887 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3888 * only 0-5mSec on 5V devices)
3889 */
3890 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3891 e_dbg("SPI EEPROM Status error\n");
3892 return -E1000_ERR_EEPROM;
3893 }
3894
3895 return E1000_SUCCESS;
3896 }
3897
3898 /**
3899 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3900 * @hw: Struct containing variables accessed by shared code
3901 * @offset: offset of word in the EEPROM to read
3902 * @data: word read from the EEPROM
3903 * @words: number of words to read
3904 */
3905 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3906 {
3907 s32 ret;
3908 spin_lock(&e1000_eeprom_lock);
3909 ret = e1000_do_read_eeprom(hw, offset, words, data);
3910 spin_unlock(&e1000_eeprom_lock);
3911 return ret;
3912 }
3913
3914 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3915 u16 *data)
3916 {
3917 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3918 u32 i = 0;
3919
3920 e_dbg("e1000_read_eeprom");
3921
3922 if (hw->mac_type == e1000_ce4100) {
3923 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3924 data);
3925 return E1000_SUCCESS;
3926 }
3927
3928 /* If eeprom is not yet detected, do so now */
3929 if (eeprom->word_size == 0)
3930 e1000_init_eeprom_params(hw);
3931
3932 /* A check for invalid values: offset too large, too many words, and not
3933 * enough words.
3934 */
3935 if ((offset >= eeprom->word_size)
3936 || (words > eeprom->word_size - offset) || (words == 0)) {
3937 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3938 "size = %d\n", offset, eeprom->word_size);
3939 return -E1000_ERR_EEPROM;
3940 }
3941
3942 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3943 * directly. In this case, we need to acquire the EEPROM so that
3944 * FW or other port software does not interrupt.
3945 */
3946 /* Prepare the EEPROM for bit-bang reading */
3947 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3948 return -E1000_ERR_EEPROM;
3949
3950 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3951 * acquired the EEPROM at this point, so any returns should release it */
3952 if (eeprom->type == e1000_eeprom_spi) {
3953 u16 word_in;
3954 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3955
3956 if (e1000_spi_eeprom_ready(hw)) {
3957 e1000_release_eeprom(hw);
3958 return -E1000_ERR_EEPROM;
3959 }
3960
3961 e1000_standby_eeprom(hw);
3962
3963 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3964 if ((eeprom->address_bits == 8) && (offset >= 128))
3965 read_opcode |= EEPROM_A8_OPCODE_SPI;
3966
3967 /* Send the READ command (opcode + addr) */
3968 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3969 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3970 eeprom->address_bits);
3971
3972 /* Read the data. The address of the eeprom internally increments with
3973 * each byte (spi) being read, saving on the overhead of eeprom setup
3974 * and tear-down. The address counter will roll over if reading beyond
3975 * the size of the eeprom, thus allowing the entire memory to be read
3976 * starting from any offset. */
3977 for (i = 0; i < words; i++) {
3978 word_in = e1000_shift_in_ee_bits(hw, 16);
3979 data[i] = (word_in >> 8) | (word_in << 8);
3980 }
3981 } else if (eeprom->type == e1000_eeprom_microwire) {
3982 for (i = 0; i < words; i++) {
3983 /* Send the READ command (opcode + addr) */
3984 e1000_shift_out_ee_bits(hw,
3985 EEPROM_READ_OPCODE_MICROWIRE,
3986 eeprom->opcode_bits);
3987 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3988 eeprom->address_bits);
3989
3990 /* Read the data. For microwire, each word requires the overhead
3991 * of eeprom setup and tear-down. */
3992 data[i] = e1000_shift_in_ee_bits(hw, 16);
3993 e1000_standby_eeprom(hw);
3994 }
3995 }
3996
3997 /* End this read operation */
3998 e1000_release_eeprom(hw);
3999
4000 return E1000_SUCCESS;
4001 }
4002
4003 /**
4004 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
4005 * @hw: Struct containing variables accessed by shared code
4006 *
4007 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4008 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4009 * valid.
4010 */
4011 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4012 {
4013 u16 checksum = 0;
4014 u16 i, eeprom_data;
4015
4016 e_dbg("e1000_validate_eeprom_checksum");
4017
4018 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4019 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4020 e_dbg("EEPROM Read Error\n");
4021 return -E1000_ERR_EEPROM;
4022 }
4023 checksum += eeprom_data;
4024 }
4025
4026 if (checksum == (u16) EEPROM_SUM)
4027 return E1000_SUCCESS;
4028 else {
4029 e_dbg("EEPROM Checksum Invalid\n");
4030 return -E1000_ERR_EEPROM;
4031 }
4032 }
4033
4034 /**
4035 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
4036 * @hw: Struct containing variables accessed by shared code
4037 *
4038 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4039 * Writes the difference to word offset 63 of the EEPROM.
4040 */
4041 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4042 {
4043 u16 checksum = 0;
4044 u16 i, eeprom_data;
4045
4046 e_dbg("e1000_update_eeprom_checksum");
4047
4048 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4049 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4050 e_dbg("EEPROM Read Error\n");
4051 return -E1000_ERR_EEPROM;
4052 }
4053 checksum += eeprom_data;
4054 }
4055 checksum = (u16) EEPROM_SUM - checksum;
4056 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4057 e_dbg("EEPROM Write Error\n");
4058 return -E1000_ERR_EEPROM;
4059 }
4060 return E1000_SUCCESS;
4061 }
4062
4063 /**
4064 * e1000_write_eeprom - write words to the different EEPROM types.
4065 * @hw: Struct containing variables accessed by shared code
4066 * @offset: offset within the EEPROM to be written to
4067 * @words: number of words to write
4068 * @data: 16 bit word to be written to the EEPROM
4069 *
4070 * If e1000_update_eeprom_checksum is not called after this function, the
4071 * EEPROM will most likely contain an invalid checksum.
4072 */
4073 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4074 {
4075 s32 ret;
4076 spin_lock(&e1000_eeprom_lock);
4077 ret = e1000_do_write_eeprom(hw, offset, words, data);
4078 spin_unlock(&e1000_eeprom_lock);
4079 return ret;
4080 }
4081
4082 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4083 u16 *data)
4084 {
4085 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4086 s32 status = 0;
4087
4088 e_dbg("e1000_write_eeprom");
4089
4090 if (hw->mac_type == e1000_ce4100) {
4091 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4092 data);
4093 return E1000_SUCCESS;
4094 }
4095
4096 /* If eeprom is not yet detected, do so now */
4097 if (eeprom->word_size == 0)
4098 e1000_init_eeprom_params(hw);
4099
4100 /* A check for invalid values: offset too large, too many words, and not
4101 * enough words.
4102 */
4103 if ((offset >= eeprom->word_size)
4104 || (words > eeprom->word_size - offset) || (words == 0)) {
4105 e_dbg("\"words\" parameter out of bounds\n");
4106 return -E1000_ERR_EEPROM;
4107 }
4108
4109 /* Prepare the EEPROM for writing */
4110 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4111 return -E1000_ERR_EEPROM;
4112
4113 if (eeprom->type == e1000_eeprom_microwire) {
4114 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4115 } else {
4116 status = e1000_write_eeprom_spi(hw, offset, words, data);
4117 msleep(10);
4118 }
4119
4120 /* Done with writing */
4121 e1000_release_eeprom(hw);
4122
4123 return status;
4124 }
4125
4126 /**
4127 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4128 * @hw: Struct containing variables accessed by shared code
4129 * @offset: offset within the EEPROM to be written to
4130 * @words: number of words to write
4131 * @data: pointer to array of 8 bit words to be written to the EEPROM
4132 */
4133 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4134 u16 *data)
4135 {
4136 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4137 u16 widx = 0;
4138
4139 e_dbg("e1000_write_eeprom_spi");
4140
4141 while (widx < words) {
4142 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4143
4144 if (e1000_spi_eeprom_ready(hw))
4145 return -E1000_ERR_EEPROM;
4146
4147 e1000_standby_eeprom(hw);
4148
4149 /* Send the WRITE ENABLE command (8 bit opcode ) */
4150 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4151 eeprom->opcode_bits);
4152
4153 e1000_standby_eeprom(hw);
4154
4155 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4156 if ((eeprom->address_bits == 8) && (offset >= 128))
4157 write_opcode |= EEPROM_A8_OPCODE_SPI;
4158
4159 /* Send the Write command (8-bit opcode + addr) */
4160 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4161
4162 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
4163 eeprom->address_bits);
4164
4165 /* Send the data */
4166
4167 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4168 while (widx < words) {
4169 u16 word_out = data[widx];
4170 word_out = (word_out >> 8) | (word_out << 8);
4171 e1000_shift_out_ee_bits(hw, word_out, 16);
4172 widx++;
4173
4174 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4175 * operation, while the smaller eeproms are capable of an 8-byte
4176 * PAGE WRITE operation. Break the inner loop to pass new address
4177 */
4178 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4179 e1000_standby_eeprom(hw);
4180 break;
4181 }
4182 }
4183 }
4184
4185 return E1000_SUCCESS;
4186 }
4187
4188 /**
4189 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4190 * @hw: Struct containing variables accessed by shared code
4191 * @offset: offset within the EEPROM to be written to
4192 * @words: number of words to write
4193 * @data: pointer to array of 8 bit words to be written to the EEPROM
4194 */
4195 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4196 u16 words, u16 *data)
4197 {
4198 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4199 u32 eecd;
4200 u16 words_written = 0;
4201 u16 i = 0;
4202
4203 e_dbg("e1000_write_eeprom_microwire");
4204
4205 /* Send the write enable command to the EEPROM (3-bit opcode plus
4206 * 6/8-bit dummy address beginning with 11). It's less work to include
4207 * the 11 of the dummy address as part of the opcode than it is to shift
4208 * it over the correct number of bits for the address. This puts the
4209 * EEPROM into write/erase mode.
4210 */
4211 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4212 (u16) (eeprom->opcode_bits + 2));
4213
4214 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4215
4216 /* Prepare the EEPROM */
4217 e1000_standby_eeprom(hw);
4218
4219 while (words_written < words) {
4220 /* Send the Write command (3-bit opcode + addr) */
4221 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4222 eeprom->opcode_bits);
4223
4224 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4225 eeprom->address_bits);
4226
4227 /* Send the data */
4228 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4229
4230 /* Toggle the CS line. This in effect tells the EEPROM to execute
4231 * the previous command.
4232 */
4233 e1000_standby_eeprom(hw);
4234
4235 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4236 * signal that the command has been completed by raising the DO signal.
4237 * If DO does not go high in 10 milliseconds, then error out.
4238 */
4239 for (i = 0; i < 200; i++) {
4240 eecd = er32(EECD);
4241 if (eecd & E1000_EECD_DO)
4242 break;
4243 udelay(50);
4244 }
4245 if (i == 200) {
4246 e_dbg("EEPROM Write did not complete\n");
4247 return -E1000_ERR_EEPROM;
4248 }
4249
4250 /* Recover from write */
4251 e1000_standby_eeprom(hw);
4252
4253 words_written++;
4254 }
4255
4256 /* Send the write disable command to the EEPROM (3-bit opcode plus
4257 * 6/8-bit dummy address beginning with 10). It's less work to include
4258 * the 10 of the dummy address as part of the opcode than it is to shift
4259 * it over the correct number of bits for the address. This takes the
4260 * EEPROM out of write/erase mode.
4261 */
4262 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4263 (u16) (eeprom->opcode_bits + 2));
4264
4265 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4266
4267 return E1000_SUCCESS;
4268 }
4269
4270 /**
4271 * e1000_read_mac_addr - read the adapters MAC from eeprom
4272 * @hw: Struct containing variables accessed by shared code
4273 *
4274 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4275 * second function of dual function devices
4276 */
4277 s32 e1000_read_mac_addr(struct e1000_hw *hw)
4278 {
4279 u16 offset;
4280 u16 eeprom_data, i;
4281
4282 e_dbg("e1000_read_mac_addr");
4283
4284 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4285 offset = i >> 1;
4286 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4287 e_dbg("EEPROM Read Error\n");
4288 return -E1000_ERR_EEPROM;
4289 }
4290 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4291 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4292 }
4293
4294 switch (hw->mac_type) {
4295 default:
4296 break;
4297 case e1000_82546:
4298 case e1000_82546_rev_3:
4299 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4300 hw->perm_mac_addr[5] ^= 0x01;
4301 break;
4302 }
4303
4304 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4305 hw->mac_addr[i] = hw->perm_mac_addr[i];
4306 return E1000_SUCCESS;
4307 }
4308
4309 /**
4310 * e1000_init_rx_addrs - Initializes receive address filters.
4311 * @hw: Struct containing variables accessed by shared code
4312 *
4313 * Places the MAC address in receive address register 0 and clears the rest
4314 * of the receive address registers. Clears the multicast table. Assumes
4315 * the receiver is in reset when the routine is called.
4316 */
4317 static void e1000_init_rx_addrs(struct e1000_hw *hw)
4318 {
4319 u32 i;
4320 u32 rar_num;
4321
4322 e_dbg("e1000_init_rx_addrs");
4323
4324 /* Setup the receive address. */
4325 e_dbg("Programming MAC Address into RAR[0]\n");
4326
4327 e1000_rar_set(hw, hw->mac_addr, 0);
4328
4329 rar_num = E1000_RAR_ENTRIES;
4330
4331 /* Zero out the other 15 receive addresses. */
4332 e_dbg("Clearing RAR[1-15]\n");
4333 for (i = 1; i < rar_num; i++) {
4334 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4335 E1000_WRITE_FLUSH();
4336 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4337 E1000_WRITE_FLUSH();
4338 }
4339 }
4340
4341 /**
4342 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4343 * @hw: Struct containing variables accessed by shared code
4344 * @mc_addr: the multicast address to hash
4345 */
4346 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4347 {
4348 u32 hash_value = 0;
4349
4350 /* The portion of the address that is used for the hash table is
4351 * determined by the mc_filter_type setting.
4352 */
4353 switch (hw->mc_filter_type) {
4354 /* [0] [1] [2] [3] [4] [5]
4355 * 01 AA 00 12 34 56
4356 * LSB MSB
4357 */
4358 case 0:
4359 /* [47:36] i.e. 0x563 for above example address */
4360 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4361 break;
4362 case 1:
4363 /* [46:35] i.e. 0xAC6 for above example address */
4364 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4365 break;
4366 case 2:
4367 /* [45:34] i.e. 0x5D8 for above example address */
4368 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4369 break;
4370 case 3:
4371 /* [43:32] i.e. 0x634 for above example address */
4372 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4373 break;
4374 }
4375
4376 hash_value &= 0xFFF;
4377 return hash_value;
4378 }
4379
4380 /**
4381 * e1000_rar_set - Puts an ethernet address into a receive address register.
4382 * @hw: Struct containing variables accessed by shared code
4383 * @addr: Address to put into receive address register
4384 * @index: Receive address register to write
4385 */
4386 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4387 {
4388 u32 rar_low, rar_high;
4389
4390 /* HW expects these in little endian so we reverse the byte order
4391 * from network order (big endian) to little endian
4392 */
4393 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4394 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4395 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4396
4397 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4398 * unit hang.
4399 *
4400 * Description:
4401 * If there are any Rx frames queued up or otherwise present in the HW
4402 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4403 * hang. To work around this issue, we have to disable receives and
4404 * flush out all Rx frames before we enable RSS. To do so, we modify we
4405 * redirect all Rx traffic to manageability and then reset the HW.
4406 * This flushes away Rx frames, and (since the redirections to
4407 * manageability persists across resets) keeps new ones from coming in
4408 * while we work. Then, we clear the Address Valid AV bit for all MAC
4409 * addresses and undo the re-direction to manageability.
4410 * Now, frames are coming in again, but the MAC won't accept them, so
4411 * far so good. We now proceed to initialize RSS (if necessary) and
4412 * configure the Rx unit. Last, we re-enable the AV bits and continue
4413 * on our merry way.
4414 */
4415 switch (hw->mac_type) {
4416 default:
4417 /* Indicate to hardware the Address is Valid. */
4418 rar_high |= E1000_RAH_AV;
4419 break;
4420 }
4421
4422 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4423 E1000_WRITE_FLUSH();
4424 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4425 E1000_WRITE_FLUSH();
4426 }
4427
4428 /**
4429 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4430 * @hw: Struct containing variables accessed by shared code
4431 * @offset: Offset in VLAN filer table to write
4432 * @value: Value to write into VLAN filter table
4433 */
4434 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4435 {
4436 u32 temp;
4437
4438 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4439 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4440 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4441 E1000_WRITE_FLUSH();
4442 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4443 E1000_WRITE_FLUSH();
4444 } else {
4445 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4446 E1000_WRITE_FLUSH();
4447 }
4448 }
4449
4450 /**
4451 * e1000_clear_vfta - Clears the VLAN filer table
4452 * @hw: Struct containing variables accessed by shared code
4453 */
4454 static void e1000_clear_vfta(struct e1000_hw *hw)
4455 {
4456 u32 offset;
4457 u32 vfta_value = 0;
4458 u32 vfta_offset = 0;
4459 u32 vfta_bit_in_reg = 0;
4460
4461 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4462 /* If the offset we want to clear is the same offset of the
4463 * manageability VLAN ID, then clear all bits except that of the
4464 * manageability unit */
4465 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4466 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4467 E1000_WRITE_FLUSH();
4468 }
4469 }
4470
4471 static s32 e1000_id_led_init(struct e1000_hw *hw)
4472 {
4473 u32 ledctl;
4474 const u32 ledctl_mask = 0x000000FF;
4475 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4476 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4477 u16 eeprom_data, i, temp;
4478 const u16 led_mask = 0x0F;
4479
4480 e_dbg("e1000_id_led_init");
4481
4482 if (hw->mac_type < e1000_82540) {
4483 /* Nothing to do */
4484 return E1000_SUCCESS;
4485 }
4486
4487 ledctl = er32(LEDCTL);
4488 hw->ledctl_default = ledctl;
4489 hw->ledctl_mode1 = hw->ledctl_default;
4490 hw->ledctl_mode2 = hw->ledctl_default;
4491
4492 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4493 e_dbg("EEPROM Read Error\n");
4494 return -E1000_ERR_EEPROM;
4495 }
4496
4497 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4498 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4499 eeprom_data = ID_LED_DEFAULT;
4500 }
4501
4502 for (i = 0; i < 4; i++) {
4503 temp = (eeprom_data >> (i << 2)) & led_mask;
4504 switch (temp) {
4505 case ID_LED_ON1_DEF2:
4506 case ID_LED_ON1_ON2:
4507 case ID_LED_ON1_OFF2:
4508 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4509 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4510 break;
4511 case ID_LED_OFF1_DEF2:
4512 case ID_LED_OFF1_ON2:
4513 case ID_LED_OFF1_OFF2:
4514 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4515 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4516 break;
4517 default:
4518 /* Do nothing */
4519 break;
4520 }
4521 switch (temp) {
4522 case ID_LED_DEF1_ON2:
4523 case ID_LED_ON1_ON2:
4524 case ID_LED_OFF1_ON2:
4525 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4526 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4527 break;
4528 case ID_LED_DEF1_OFF2:
4529 case ID_LED_ON1_OFF2:
4530 case ID_LED_OFF1_OFF2:
4531 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4532 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4533 break;
4534 default:
4535 /* Do nothing */
4536 break;
4537 }
4538 }
4539 return E1000_SUCCESS;
4540 }
4541
4542 /**
4543 * e1000_setup_led
4544 * @hw: Struct containing variables accessed by shared code
4545 *
4546 * Prepares SW controlable LED for use and saves the current state of the LED.
4547 */
4548 s32 e1000_setup_led(struct e1000_hw *hw)
4549 {
4550 u32 ledctl;
4551 s32 ret_val = E1000_SUCCESS;
4552
4553 e_dbg("e1000_setup_led");
4554
4555 switch (hw->mac_type) {
4556 case e1000_82542_rev2_0:
4557 case e1000_82542_rev2_1:
4558 case e1000_82543:
4559 case e1000_82544:
4560 /* No setup necessary */
4561 break;
4562 case e1000_82541:
4563 case e1000_82547:
4564 case e1000_82541_rev_2:
4565 case e1000_82547_rev_2:
4566 /* Turn off PHY Smart Power Down (if enabled) */
4567 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4568 &hw->phy_spd_default);
4569 if (ret_val)
4570 return ret_val;
4571 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4572 (u16) (hw->phy_spd_default &
4573 ~IGP01E1000_GMII_SPD));
4574 if (ret_val)
4575 return ret_val;
4576 /* Fall Through */
4577 default:
4578 if (hw->media_type == e1000_media_type_fiber) {
4579 ledctl = er32(LEDCTL);
4580 /* Save current LEDCTL settings */
4581 hw->ledctl_default = ledctl;
4582 /* Turn off LED0 */
4583 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4584 E1000_LEDCTL_LED0_BLINK |
4585 E1000_LEDCTL_LED0_MODE_MASK);
4586 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4587 E1000_LEDCTL_LED0_MODE_SHIFT);
4588 ew32(LEDCTL, ledctl);
4589 } else if (hw->media_type == e1000_media_type_copper)
4590 ew32(LEDCTL, hw->ledctl_mode1);
4591 break;
4592 }
4593
4594 return E1000_SUCCESS;
4595 }
4596
4597 /**
4598 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4599 * @hw: Struct containing variables accessed by shared code
4600 */
4601 s32 e1000_cleanup_led(struct e1000_hw *hw)
4602 {
4603 s32 ret_val = E1000_SUCCESS;
4604
4605 e_dbg("e1000_cleanup_led");
4606
4607 switch (hw->mac_type) {
4608 case e1000_82542_rev2_0:
4609 case e1000_82542_rev2_1:
4610 case e1000_82543:
4611 case e1000_82544:
4612 /* No cleanup necessary */
4613 break;
4614 case e1000_82541:
4615 case e1000_82547:
4616 case e1000_82541_rev_2:
4617 case e1000_82547_rev_2:
4618 /* Turn on PHY Smart Power Down (if previously enabled) */
4619 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4620 hw->phy_spd_default);
4621 if (ret_val)
4622 return ret_val;
4623 /* Fall Through */
4624 default:
4625 /* Restore LEDCTL settings */
4626 ew32(LEDCTL, hw->ledctl_default);
4627 break;
4628 }
4629
4630 return E1000_SUCCESS;
4631 }
4632
4633 /**
4634 * e1000_led_on - Turns on the software controllable LED
4635 * @hw: Struct containing variables accessed by shared code
4636 */
4637 s32 e1000_led_on(struct e1000_hw *hw)
4638 {
4639 u32 ctrl = er32(CTRL);
4640
4641 e_dbg("e1000_led_on");
4642
4643 switch (hw->mac_type) {
4644 case e1000_82542_rev2_0:
4645 case e1000_82542_rev2_1:
4646 case e1000_82543:
4647 /* Set SW Defineable Pin 0 to turn on the LED */
4648 ctrl |= E1000_CTRL_SWDPIN0;
4649 ctrl |= E1000_CTRL_SWDPIO0;
4650 break;
4651 case e1000_82544:
4652 if (hw->media_type == e1000_media_type_fiber) {
4653 /* Set SW Defineable Pin 0 to turn on the LED */
4654 ctrl |= E1000_CTRL_SWDPIN0;
4655 ctrl |= E1000_CTRL_SWDPIO0;
4656 } else {
4657 /* Clear SW Defineable Pin 0 to turn on the LED */
4658 ctrl &= ~E1000_CTRL_SWDPIN0;
4659 ctrl |= E1000_CTRL_SWDPIO0;
4660 }
4661 break;
4662 default:
4663 if (hw->media_type == e1000_media_type_fiber) {
4664 /* Clear SW Defineable Pin 0 to turn on the LED */
4665 ctrl &= ~E1000_CTRL_SWDPIN0;
4666 ctrl |= E1000_CTRL_SWDPIO0;
4667 } else if (hw->media_type == e1000_media_type_copper) {
4668 ew32(LEDCTL, hw->ledctl_mode2);
4669 return E1000_SUCCESS;
4670 }
4671 break;
4672 }
4673
4674 ew32(CTRL, ctrl);
4675
4676 return E1000_SUCCESS;
4677 }
4678
4679 /**
4680 * e1000_led_off - Turns off the software controllable LED
4681 * @hw: Struct containing variables accessed by shared code
4682 */
4683 s32 e1000_led_off(struct e1000_hw *hw)
4684 {
4685 u32 ctrl = er32(CTRL);
4686
4687 e_dbg("e1000_led_off");
4688
4689 switch (hw->mac_type) {
4690 case e1000_82542_rev2_0:
4691 case e1000_82542_rev2_1:
4692 case e1000_82543:
4693 /* Clear SW Defineable Pin 0 to turn off the LED */
4694 ctrl &= ~E1000_CTRL_SWDPIN0;
4695 ctrl |= E1000_CTRL_SWDPIO0;
4696 break;
4697 case e1000_82544:
4698 if (hw->media_type == e1000_media_type_fiber) {
4699 /* Clear SW Defineable Pin 0 to turn off the LED */
4700 ctrl &= ~E1000_CTRL_SWDPIN0;
4701 ctrl |= E1000_CTRL_SWDPIO0;
4702 } else {
4703 /* Set SW Defineable Pin 0 to turn off the LED */
4704 ctrl |= E1000_CTRL_SWDPIN0;
4705 ctrl |= E1000_CTRL_SWDPIO0;
4706 }
4707 break;
4708 default:
4709 if (hw->media_type == e1000_media_type_fiber) {
4710 /* Set SW Defineable Pin 0 to turn off the LED */
4711 ctrl |= E1000_CTRL_SWDPIN0;
4712 ctrl |= E1000_CTRL_SWDPIO0;
4713 } else if (hw->media_type == e1000_media_type_copper) {
4714 ew32(LEDCTL, hw->ledctl_mode1);
4715 return E1000_SUCCESS;
4716 }
4717 break;
4718 }
4719
4720 ew32(CTRL, ctrl);
4721
4722 return E1000_SUCCESS;
4723 }
4724
4725 /**
4726 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4727 * @hw: Struct containing variables accessed by shared code
4728 */
4729 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4730 {
4731 volatile u32 temp;
4732
4733 temp = er32(CRCERRS);
4734 temp = er32(SYMERRS);
4735 temp = er32(MPC);
4736 temp = er32(SCC);
4737 temp = er32(ECOL);
4738 temp = er32(MCC);
4739 temp = er32(LATECOL);
4740 temp = er32(COLC);
4741 temp = er32(DC);
4742 temp = er32(SEC);
4743 temp = er32(RLEC);
4744 temp = er32(XONRXC);
4745 temp = er32(XONTXC);
4746 temp = er32(XOFFRXC);
4747 temp = er32(XOFFTXC);
4748 temp = er32(FCRUC);
4749
4750 temp = er32(PRC64);
4751 temp = er32(PRC127);
4752 temp = er32(PRC255);
4753 temp = er32(PRC511);
4754 temp = er32(PRC1023);
4755 temp = er32(PRC1522);
4756
4757 temp = er32(GPRC);
4758 temp = er32(BPRC);
4759 temp = er32(MPRC);
4760 temp = er32(GPTC);
4761 temp = er32(GORCL);
4762 temp = er32(GORCH);
4763 temp = er32(GOTCL);
4764 temp = er32(GOTCH);
4765 temp = er32(RNBC);
4766 temp = er32(RUC);
4767 temp = er32(RFC);
4768 temp = er32(ROC);
4769 temp = er32(RJC);
4770 temp = er32(TORL);
4771 temp = er32(TORH);
4772 temp = er32(TOTL);
4773 temp = er32(TOTH);
4774 temp = er32(TPR);
4775 temp = er32(TPT);
4776
4777 temp = er32(PTC64);
4778 temp = er32(PTC127);
4779 temp = er32(PTC255);
4780 temp = er32(PTC511);
4781 temp = er32(PTC1023);
4782 temp = er32(PTC1522);
4783
4784 temp = er32(MPTC);
4785 temp = er32(BPTC);
4786
4787 if (hw->mac_type < e1000_82543)
4788 return;
4789
4790 temp = er32(ALGNERRC);
4791 temp = er32(RXERRC);
4792 temp = er32(TNCRS);
4793 temp = er32(CEXTERR);
4794 temp = er32(TSCTC);
4795 temp = er32(TSCTFC);
4796
4797 if (hw->mac_type <= e1000_82544)
4798 return;
4799
4800 temp = er32(MGTPRC);
4801 temp = er32(MGTPDC);
4802 temp = er32(MGTPTC);
4803 }
4804
4805 /**
4806 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4807 * @hw: Struct containing variables accessed by shared code
4808 *
4809 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4810 * hw->ifs_params_forced to true. However, you must initialize hw->
4811 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4812 * before calling this function.
4813 */
4814 void e1000_reset_adaptive(struct e1000_hw *hw)
4815 {
4816 e_dbg("e1000_reset_adaptive");
4817
4818 if (hw->adaptive_ifs) {
4819 if (!hw->ifs_params_forced) {
4820 hw->current_ifs_val = 0;
4821 hw->ifs_min_val = IFS_MIN;
4822 hw->ifs_max_val = IFS_MAX;
4823 hw->ifs_step_size = IFS_STEP;
4824 hw->ifs_ratio = IFS_RATIO;
4825 }
4826 hw->in_ifs_mode = false;
4827 ew32(AIT, 0);
4828 } else {
4829 e_dbg("Not in Adaptive IFS mode!\n");
4830 }
4831 }
4832
4833 /**
4834 * e1000_update_adaptive - update adaptive IFS
4835 * @hw: Struct containing variables accessed by shared code
4836 * @tx_packets: Number of transmits since last callback
4837 * @total_collisions: Number of collisions since last callback
4838 *
4839 * Called during the callback/watchdog routine to update IFS value based on
4840 * the ratio of transmits to collisions.
4841 */
4842 void e1000_update_adaptive(struct e1000_hw *hw)
4843 {
4844 e_dbg("e1000_update_adaptive");
4845
4846 if (hw->adaptive_ifs) {
4847 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4848 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4849 hw->in_ifs_mode = true;
4850 if (hw->current_ifs_val < hw->ifs_max_val) {
4851 if (hw->current_ifs_val == 0)
4852 hw->current_ifs_val =
4853 hw->ifs_min_val;
4854 else
4855 hw->current_ifs_val +=
4856 hw->ifs_step_size;
4857 ew32(AIT, hw->current_ifs_val);
4858 }
4859 }
4860 } else {
4861 if (hw->in_ifs_mode
4862 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4863 hw->current_ifs_val = 0;
4864 hw->in_ifs_mode = false;
4865 ew32(AIT, 0);
4866 }
4867 }
4868 } else {
4869 e_dbg("Not in Adaptive IFS mode!\n");
4870 }
4871 }
4872
4873 /**
4874 * e1000_tbi_adjust_stats
4875 * @hw: Struct containing variables accessed by shared code
4876 * @frame_len: The length of the frame in question
4877 * @mac_addr: The Ethernet destination address of the frame in question
4878 *
4879 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4880 */
4881 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4882 u32 frame_len, u8 *mac_addr)
4883 {
4884 u64 carry_bit;
4885
4886 /* First adjust the frame length. */
4887 frame_len--;
4888 /* We need to adjust the statistics counters, since the hardware
4889 * counters overcount this packet as a CRC error and undercount
4890 * the packet as a good packet
4891 */
4892 /* This packet should not be counted as a CRC error. */
4893 stats->crcerrs--;
4894 /* This packet does count as a Good Packet Received. */
4895 stats->gprc++;
4896
4897 /* Adjust the Good Octets received counters */
4898 carry_bit = 0x80000000 & stats->gorcl;
4899 stats->gorcl += frame_len;
4900 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4901 * Received Count) was one before the addition,
4902 * AND it is zero after, then we lost the carry out,
4903 * need to add one to Gorch (Good Octets Received Count High).
4904 * This could be simplified if all environments supported
4905 * 64-bit integers.
4906 */
4907 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4908 stats->gorch++;
4909 /* Is this a broadcast or multicast? Check broadcast first,
4910 * since the test for a multicast frame will test positive on
4911 * a broadcast frame.
4912 */
4913 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4914 /* Broadcast packet */
4915 stats->bprc++;
4916 else if (*mac_addr & 0x01)
4917 /* Multicast packet */
4918 stats->mprc++;
4919
4920 if (frame_len == hw->max_frame_size) {
4921 /* In this case, the hardware has overcounted the number of
4922 * oversize frames.
4923 */
4924 if (stats->roc > 0)
4925 stats->roc--;
4926 }
4927
4928 /* Adjust the bin counters when the extra byte put the frame in the
4929 * wrong bin. Remember that the frame_len was adjusted above.
4930 */
4931 if (frame_len == 64) {
4932 stats->prc64++;
4933 stats->prc127--;
4934 } else if (frame_len == 127) {
4935 stats->prc127++;
4936 stats->prc255--;
4937 } else if (frame_len == 255) {
4938 stats->prc255++;
4939 stats->prc511--;
4940 } else if (frame_len == 511) {
4941 stats->prc511++;
4942 stats->prc1023--;
4943 } else if (frame_len == 1023) {
4944 stats->prc1023++;
4945 stats->prc1522--;
4946 } else if (frame_len == 1522) {
4947 stats->prc1522++;
4948 }
4949 }
4950
4951 /**
4952 * e1000_get_bus_info
4953 * @hw: Struct containing variables accessed by shared code
4954 *
4955 * Gets the current PCI bus type, speed, and width of the hardware
4956 */
4957 void e1000_get_bus_info(struct e1000_hw *hw)
4958 {
4959 u32 status;
4960
4961 switch (hw->mac_type) {
4962 case e1000_82542_rev2_0:
4963 case e1000_82542_rev2_1:
4964 hw->bus_type = e1000_bus_type_pci;
4965 hw->bus_speed = e1000_bus_speed_unknown;
4966 hw->bus_width = e1000_bus_width_unknown;
4967 break;
4968 default:
4969 status = er32(STATUS);
4970 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4971 e1000_bus_type_pcix : e1000_bus_type_pci;
4972
4973 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4974 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4975 e1000_bus_speed_66 : e1000_bus_speed_120;
4976 } else if (hw->bus_type == e1000_bus_type_pci) {
4977 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4978 e1000_bus_speed_66 : e1000_bus_speed_33;
4979 } else {
4980 switch (status & E1000_STATUS_PCIX_SPEED) {
4981 case E1000_STATUS_PCIX_SPEED_66:
4982 hw->bus_speed = e1000_bus_speed_66;
4983 break;
4984 case E1000_STATUS_PCIX_SPEED_100:
4985 hw->bus_speed = e1000_bus_speed_100;
4986 break;
4987 case E1000_STATUS_PCIX_SPEED_133:
4988 hw->bus_speed = e1000_bus_speed_133;
4989 break;
4990 default:
4991 hw->bus_speed = e1000_bus_speed_reserved;
4992 break;
4993 }
4994 }
4995 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4996 e1000_bus_width_64 : e1000_bus_width_32;
4997 break;
4998 }
4999 }
5000
5001 /**
5002 * e1000_write_reg_io
5003 * @hw: Struct containing variables accessed by shared code
5004 * @offset: offset to write to
5005 * @value: value to write
5006 *
5007 * Writes a value to one of the devices registers using port I/O (as opposed to
5008 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5009 */
5010 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
5011 {
5012 unsigned long io_addr = hw->io_base;
5013 unsigned long io_data = hw->io_base + 4;
5014
5015 e1000_io_write(hw, io_addr, offset);
5016 e1000_io_write(hw, io_data, value);
5017 }
5018
5019 /**
5020 * e1000_get_cable_length - Estimates the cable length.
5021 * @hw: Struct containing variables accessed by shared code
5022 * @min_length: The estimated minimum length
5023 * @max_length: The estimated maximum length
5024 *
5025 * returns: - E1000_ERR_XXX
5026 * E1000_SUCCESS
5027 *
5028 * This function always returns a ranged length (minimum & maximum).
5029 * So for M88 phy's, this function interprets the one value returned from the
5030 * register to the minimum and maximum range.
5031 * For IGP phy's, the function calculates the range by the AGC registers.
5032 */
5033 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
5034 u16 *max_length)
5035 {
5036 s32 ret_val;
5037 u16 agc_value = 0;
5038 u16 i, phy_data;
5039 u16 cable_length;
5040
5041 e_dbg("e1000_get_cable_length");
5042
5043 *min_length = *max_length = 0;
5044
5045 /* Use old method for Phy older than IGP */
5046 if (hw->phy_type == e1000_phy_m88) {
5047
5048 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5049 &phy_data);
5050 if (ret_val)
5051 return ret_val;
5052 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5053 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5054
5055 /* Convert the enum value to ranged values */
5056 switch (cable_length) {
5057 case e1000_cable_length_50:
5058 *min_length = 0;
5059 *max_length = e1000_igp_cable_length_50;
5060 break;
5061 case e1000_cable_length_50_80:
5062 *min_length = e1000_igp_cable_length_50;
5063 *max_length = e1000_igp_cable_length_80;
5064 break;
5065 case e1000_cable_length_80_110:
5066 *min_length = e1000_igp_cable_length_80;
5067 *max_length = e1000_igp_cable_length_110;
5068 break;
5069 case e1000_cable_length_110_140:
5070 *min_length = e1000_igp_cable_length_110;
5071 *max_length = e1000_igp_cable_length_140;
5072 break;
5073 case e1000_cable_length_140:
5074 *min_length = e1000_igp_cable_length_140;
5075 *max_length = e1000_igp_cable_length_170;
5076 break;
5077 default:
5078 return -E1000_ERR_PHY;
5079 break;
5080 }
5081 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5082 u16 cur_agc_value;
5083 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5084 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5085 IGP01E1000_PHY_AGC_A,
5086 IGP01E1000_PHY_AGC_B,
5087 IGP01E1000_PHY_AGC_C,
5088 IGP01E1000_PHY_AGC_D
5089 };
5090 /* Read the AGC registers for all channels */
5091 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5092
5093 ret_val =
5094 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5095 if (ret_val)
5096 return ret_val;
5097
5098 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5099
5100 /* Value bound check. */
5101 if ((cur_agc_value >=
5102 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
5103 || (cur_agc_value == 0))
5104 return -E1000_ERR_PHY;
5105
5106 agc_value += cur_agc_value;
5107
5108 /* Update minimal AGC value. */
5109 if (min_agc_value > cur_agc_value)
5110 min_agc_value = cur_agc_value;
5111 }
5112
5113 /* Remove the minimal AGC result for length < 50m */
5114 if (agc_value <
5115 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5116 agc_value -= min_agc_value;
5117
5118 /* Get the average length of the remaining 3 channels */
5119 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5120 } else {
5121 /* Get the average length of all the 4 channels. */
5122 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5123 }
5124
5125 /* Set the range of the calculated length. */
5126 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5127 IGP01E1000_AGC_RANGE) > 0) ?
5128 (e1000_igp_cable_length_table[agc_value] -
5129 IGP01E1000_AGC_RANGE) : 0;
5130 *max_length = e1000_igp_cable_length_table[agc_value] +
5131 IGP01E1000_AGC_RANGE;
5132 }
5133
5134 return E1000_SUCCESS;
5135 }
5136
5137 /**
5138 * e1000_check_polarity - Check the cable polarity
5139 * @hw: Struct containing variables accessed by shared code
5140 * @polarity: output parameter : 0 - Polarity is not reversed
5141 * 1 - Polarity is reversed.
5142 *
5143 * returns: - E1000_ERR_XXX
5144 * E1000_SUCCESS
5145 *
5146 * For phy's older than IGP, this function simply reads the polarity bit in the
5147 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5148 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5149 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5150 * IGP01E1000_PHY_PCS_INIT_REG.
5151 */
5152 static s32 e1000_check_polarity(struct e1000_hw *hw,
5153 e1000_rev_polarity *polarity)
5154 {
5155 s32 ret_val;
5156 u16 phy_data;
5157
5158 e_dbg("e1000_check_polarity");
5159
5160 if (hw->phy_type == e1000_phy_m88) {
5161 /* return the Polarity bit in the Status register. */
5162 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5163 &phy_data);
5164 if (ret_val)
5165 return ret_val;
5166 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5167 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5168 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5169
5170 } else if (hw->phy_type == e1000_phy_igp) {
5171 /* Read the Status register to check the speed */
5172 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5173 &phy_data);
5174 if (ret_val)
5175 return ret_val;
5176
5177 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5178 * find the polarity status */
5179 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5180 IGP01E1000_PSSR_SPEED_1000MBPS) {
5181
5182 /* Read the GIG initialization PCS register (0x00B4) */
5183 ret_val =
5184 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5185 &phy_data);
5186 if (ret_val)
5187 return ret_val;
5188
5189 /* Check the polarity bits */
5190 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5191 e1000_rev_polarity_reversed :
5192 e1000_rev_polarity_normal;
5193 } else {
5194 /* For 10 Mbps, read the polarity bit in the status register. (for
5195 * 100 Mbps this bit is always 0) */
5196 *polarity =
5197 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5198 e1000_rev_polarity_reversed :
5199 e1000_rev_polarity_normal;
5200 }
5201 }
5202 return E1000_SUCCESS;
5203 }
5204
5205 /**
5206 * e1000_check_downshift - Check if Downshift occurred
5207 * @hw: Struct containing variables accessed by shared code
5208 * @downshift: output parameter : 0 - No Downshift occurred.
5209 * 1 - Downshift occurred.
5210 *
5211 * returns: - E1000_ERR_XXX
5212 * E1000_SUCCESS
5213 *
5214 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5215 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5216 * Link Health register. In IGP this bit is latched high, so the driver must
5217 * read it immediately after link is established.
5218 */
5219 static s32 e1000_check_downshift(struct e1000_hw *hw)
5220 {
5221 s32 ret_val;
5222 u16 phy_data;
5223
5224 e_dbg("e1000_check_downshift");
5225
5226 if (hw->phy_type == e1000_phy_igp) {
5227 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5228 &phy_data);
5229 if (ret_val)
5230 return ret_val;
5231
5232 hw->speed_downgraded =
5233 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5234 } else if (hw->phy_type == e1000_phy_m88) {
5235 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5236 &phy_data);
5237 if (ret_val)
5238 return ret_val;
5239
5240 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5241 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5242 }
5243
5244 return E1000_SUCCESS;
5245 }
5246
5247 /**
5248 * e1000_config_dsp_after_link_change
5249 * @hw: Struct containing variables accessed by shared code
5250 * @link_up: was link up at the time this was called
5251 *
5252 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5253 * E1000_SUCCESS at any other case.
5254 *
5255 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5256 * gigabit link is achieved to improve link quality.
5257 */
5258
5259 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5260 {
5261 s32 ret_val;
5262 u16 phy_data, phy_saved_data, speed, duplex, i;
5263 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5264 IGP01E1000_PHY_AGC_PARAM_A,
5265 IGP01E1000_PHY_AGC_PARAM_B,
5266 IGP01E1000_PHY_AGC_PARAM_C,
5267 IGP01E1000_PHY_AGC_PARAM_D
5268 };
5269 u16 min_length, max_length;
5270
5271 e_dbg("e1000_config_dsp_after_link_change");
5272
5273 if (hw->phy_type != e1000_phy_igp)
5274 return E1000_SUCCESS;
5275
5276 if (link_up) {
5277 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5278 if (ret_val) {
5279 e_dbg("Error getting link speed and duplex\n");
5280 return ret_val;
5281 }
5282
5283 if (speed == SPEED_1000) {
5284
5285 ret_val =
5286 e1000_get_cable_length(hw, &min_length,
5287 &max_length);
5288 if (ret_val)
5289 return ret_val;
5290
5291 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5292 && min_length >= e1000_igp_cable_length_50) {
5293
5294 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5295 ret_val =
5296 e1000_read_phy_reg(hw,
5297 dsp_reg_array[i],
5298 &phy_data);
5299 if (ret_val)
5300 return ret_val;
5301
5302 phy_data &=
5303 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5304
5305 ret_val =
5306 e1000_write_phy_reg(hw,
5307 dsp_reg_array
5308 [i], phy_data);
5309 if (ret_val)
5310 return ret_val;
5311 }
5312 hw->dsp_config_state =
5313 e1000_dsp_config_activated;
5314 }
5315
5316 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5317 && (min_length < e1000_igp_cable_length_50)) {
5318
5319 u16 ffe_idle_err_timeout =
5320 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5321 u32 idle_errs = 0;
5322
5323 /* clear previous idle error counts */
5324 ret_val =
5325 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5326 &phy_data);
5327 if (ret_val)
5328 return ret_val;
5329
5330 for (i = 0; i < ffe_idle_err_timeout; i++) {
5331 udelay(1000);
5332 ret_val =
5333 e1000_read_phy_reg(hw,
5334 PHY_1000T_STATUS,
5335 &phy_data);
5336 if (ret_val)
5337 return ret_val;
5338
5339 idle_errs +=
5340 (phy_data &
5341 SR_1000T_IDLE_ERROR_CNT);
5342 if (idle_errs >
5343 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5344 {
5345 hw->ffe_config_state =
5346 e1000_ffe_config_active;
5347
5348 ret_val =
5349 e1000_write_phy_reg(hw,
5350 IGP01E1000_PHY_DSP_FFE,
5351 IGP01E1000_PHY_DSP_FFE_CM_CP);
5352 if (ret_val)
5353 return ret_val;
5354 break;
5355 }
5356
5357 if (idle_errs)
5358 ffe_idle_err_timeout =
5359 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5360 }
5361 }
5362 }
5363 } else {
5364 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5365 /* Save off the current value of register 0x2F5B to be restored at
5366 * the end of the routines. */
5367 ret_val =
5368 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5369
5370 if (ret_val)
5371 return ret_val;
5372
5373 /* Disable the PHY transmitter */
5374 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5375
5376 if (ret_val)
5377 return ret_val;
5378
5379 mdelay(20);
5380
5381 ret_val = e1000_write_phy_reg(hw, 0x0000,
5382 IGP01E1000_IEEE_FORCE_GIGA);
5383 if (ret_val)
5384 return ret_val;
5385 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5386 ret_val =
5387 e1000_read_phy_reg(hw, dsp_reg_array[i],
5388 &phy_data);
5389 if (ret_val)
5390 return ret_val;
5391
5392 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5393 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5394
5395 ret_val =
5396 e1000_write_phy_reg(hw, dsp_reg_array[i],
5397 phy_data);
5398 if (ret_val)
5399 return ret_val;
5400 }
5401
5402 ret_val = e1000_write_phy_reg(hw, 0x0000,
5403 IGP01E1000_IEEE_RESTART_AUTONEG);
5404 if (ret_val)
5405 return ret_val;
5406
5407 mdelay(20);
5408
5409 /* Now enable the transmitter */
5410 ret_val =
5411 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5412
5413 if (ret_val)
5414 return ret_val;
5415
5416 hw->dsp_config_state = e1000_dsp_config_enabled;
5417 }
5418
5419 if (hw->ffe_config_state == e1000_ffe_config_active) {
5420 /* Save off the current value of register 0x2F5B to be restored at
5421 * the end of the routines. */
5422 ret_val =
5423 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5424
5425 if (ret_val)
5426 return ret_val;
5427
5428 /* Disable the PHY transmitter */
5429 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5430
5431 if (ret_val)
5432 return ret_val;
5433
5434 mdelay(20);
5435
5436 ret_val = e1000_write_phy_reg(hw, 0x0000,
5437 IGP01E1000_IEEE_FORCE_GIGA);
5438 if (ret_val)
5439 return ret_val;
5440 ret_val =
5441 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5442 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5443 if (ret_val)
5444 return ret_val;
5445
5446 ret_val = e1000_write_phy_reg(hw, 0x0000,
5447 IGP01E1000_IEEE_RESTART_AUTONEG);
5448 if (ret_val)
5449 return ret_val;
5450
5451 mdelay(20);
5452
5453 /* Now enable the transmitter */
5454 ret_val =
5455 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5456
5457 if (ret_val)
5458 return ret_val;
5459
5460 hw->ffe_config_state = e1000_ffe_config_enabled;
5461 }
5462 }
5463 return E1000_SUCCESS;
5464 }
5465
5466 /**
5467 * e1000_set_phy_mode - Set PHY to class A mode
5468 * @hw: Struct containing variables accessed by shared code
5469 *
5470 * Assumes the following operations will follow to enable the new class mode.
5471 * 1. Do a PHY soft reset
5472 * 2. Restart auto-negotiation or force link.
5473 */
5474 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5475 {
5476 s32 ret_val;
5477 u16 eeprom_data;
5478
5479 e_dbg("e1000_set_phy_mode");
5480
5481 if ((hw->mac_type == e1000_82545_rev_3) &&
5482 (hw->media_type == e1000_media_type_copper)) {
5483 ret_val =
5484 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5485 &eeprom_data);
5486 if (ret_val) {
5487 return ret_val;
5488 }
5489
5490 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5491 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5492 ret_val =
5493 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5494 0x000B);
5495 if (ret_val)
5496 return ret_val;
5497 ret_val =
5498 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5499 0x8104);
5500 if (ret_val)
5501 return ret_val;
5502
5503 hw->phy_reset_disable = false;
5504 }
5505 }
5506
5507 return E1000_SUCCESS;
5508 }
5509
5510 /**
5511 * e1000_set_d3_lplu_state - set d3 link power state
5512 * @hw: Struct containing variables accessed by shared code
5513 * @active: true to enable lplu false to disable lplu.
5514 *
5515 * This function sets the lplu state according to the active flag. When
5516 * activating lplu this function also disables smart speed and vise versa.
5517 * lplu will not be activated unless the device autonegotiation advertisement
5518 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5519 *
5520 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5521 * E1000_SUCCESS at any other case.
5522 */
5523 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5524 {
5525 s32 ret_val;
5526 u16 phy_data;
5527 e_dbg("e1000_set_d3_lplu_state");
5528
5529 if (hw->phy_type != e1000_phy_igp)
5530 return E1000_SUCCESS;
5531
5532 /* During driver activity LPLU should not be used or it will attain link
5533 * from the lowest speeds starting from 10Mbps. The capability is used for
5534 * Dx transitions and states */
5535 if (hw->mac_type == e1000_82541_rev_2
5536 || hw->mac_type == e1000_82547_rev_2) {
5537 ret_val =
5538 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5539 if (ret_val)
5540 return ret_val;
5541 }
5542
5543 if (!active) {
5544 if (hw->mac_type == e1000_82541_rev_2 ||
5545 hw->mac_type == e1000_82547_rev_2) {
5546 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5547 ret_val =
5548 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5549 phy_data);
5550 if (ret_val)
5551 return ret_val;
5552 }
5553
5554 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5555 * Dx states where the power conservation is most important. During
5556 * driver activity we should enable SmartSpeed, so performance is
5557 * maintained. */
5558 if (hw->smart_speed == e1000_smart_speed_on) {
5559 ret_val =
5560 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5561 &phy_data);
5562 if (ret_val)
5563 return ret_val;
5564
5565 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5566 ret_val =
5567 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5568 phy_data);
5569 if (ret_val)
5570 return ret_val;
5571 } else if (hw->smart_speed == e1000_smart_speed_off) {
5572 ret_val =
5573 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5574 &phy_data);
5575 if (ret_val)
5576 return ret_val;
5577
5578 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5579 ret_val =
5580 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5581 phy_data);
5582 if (ret_val)
5583 return ret_val;
5584 }
5585 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5586 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5587 || (hw->autoneg_advertised ==
5588 AUTONEG_ADVERTISE_10_100_ALL)) {
5589
5590 if (hw->mac_type == e1000_82541_rev_2 ||
5591 hw->mac_type == e1000_82547_rev_2) {
5592 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5593 ret_val =
5594 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5595 phy_data);
5596 if (ret_val)
5597 return ret_val;
5598 }
5599
5600 /* When LPLU is enabled we should disable SmartSpeed */
5601 ret_val =
5602 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5603 &phy_data);
5604 if (ret_val)
5605 return ret_val;
5606
5607 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5608 ret_val =
5609 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5610 phy_data);
5611 if (ret_val)
5612 return ret_val;
5613
5614 }
5615 return E1000_SUCCESS;
5616 }
5617
5618 /**
5619 * e1000_set_vco_speed
5620 * @hw: Struct containing variables accessed by shared code
5621 *
5622 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5623 */
5624 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5625 {
5626 s32 ret_val;
5627 u16 default_page = 0;
5628 u16 phy_data;
5629
5630 e_dbg("e1000_set_vco_speed");
5631
5632 switch (hw->mac_type) {
5633 case e1000_82545_rev_3:
5634 case e1000_82546_rev_3:
5635 break;
5636 default:
5637 return E1000_SUCCESS;
5638 }
5639
5640 /* Set PHY register 30, page 5, bit 8 to 0 */
5641
5642 ret_val =
5643 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5644 if (ret_val)
5645 return ret_val;
5646
5647 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5648 if (ret_val)
5649 return ret_val;
5650
5651 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5652 if (ret_val)
5653 return ret_val;
5654
5655 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5656 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5657 if (ret_val)
5658 return ret_val;
5659
5660 /* Set PHY register 30, page 4, bit 11 to 1 */
5661
5662 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5663 if (ret_val)
5664 return ret_val;
5665
5666 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5667 if (ret_val)
5668 return ret_val;
5669
5670 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5671 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5672 if (ret_val)
5673 return ret_val;
5674
5675 ret_val =
5676 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5677 if (ret_val)
5678 return ret_val;
5679
5680 return E1000_SUCCESS;
5681 }
5682
5683
5684 /**
5685 * e1000_enable_mng_pass_thru - check for bmc pass through
5686 * @hw: Struct containing variables accessed by shared code
5687 *
5688 * Verifies the hardware needs to allow ARPs to be processed by the host
5689 * returns: - true/false
5690 */
5691 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5692 {
5693 u32 manc;
5694
5695 if (hw->asf_firmware_present) {
5696 manc = er32(MANC);
5697
5698 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5699 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5700 return false;
5701 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5702 return true;
5703 }
5704 return false;
5705 }
5706
5707 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5708 {
5709 s32 ret_val;
5710 u16 mii_status_reg;
5711 u16 i;
5712
5713 /* Polarity reversal workaround for forced 10F/10H links. */
5714
5715 /* Disable the transmitter on the PHY */
5716
5717 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5718 if (ret_val)
5719 return ret_val;
5720 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5721 if (ret_val)
5722 return ret_val;
5723
5724 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5725 if (ret_val)
5726 return ret_val;
5727
5728 /* This loop will early-out if the NO link condition has been met. */
5729 for (i = PHY_FORCE_TIME; i > 0; i--) {
5730 /* Read the MII Status Register and wait for Link Status bit
5731 * to be clear.
5732 */
5733
5734 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5735 if (ret_val)
5736 return ret_val;
5737
5738 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5739 if (ret_val)
5740 return ret_val;
5741
5742 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5743 break;
5744 mdelay(100);
5745 }
5746
5747 /* Recommended delay time after link has been lost */
5748 mdelay(1000);
5749
5750 /* Now we will re-enable th transmitter on the PHY */
5751
5752 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5753 if (ret_val)
5754 return ret_val;
5755 mdelay(50);
5756 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5757 if (ret_val)
5758 return ret_val;
5759 mdelay(50);
5760 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5761 if (ret_val)
5762 return ret_val;
5763 mdelay(50);
5764 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5765 if (ret_val)
5766 return ret_val;
5767
5768 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5769 if (ret_val)
5770 return ret_val;
5771
5772 /* This loop will early-out if the link condition has been met. */
5773 for (i = PHY_FORCE_TIME; i > 0; i--) {
5774 /* Read the MII Status Register and wait for Link Status bit
5775 * to be set.
5776 */
5777
5778 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5779 if (ret_val)
5780 return ret_val;
5781
5782 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5783 if (ret_val)
5784 return ret_val;
5785
5786 if (mii_status_reg & MII_SR_LINK_STATUS)
5787 break;
5788 mdelay(100);
5789 }
5790 return E1000_SUCCESS;
5791 }
5792
5793 /**
5794 * e1000_get_auto_rd_done
5795 * @hw: Struct containing variables accessed by shared code
5796 *
5797 * Check for EEPROM Auto Read bit done.
5798 * returns: - E1000_ERR_RESET if fail to reset MAC
5799 * E1000_SUCCESS at any other case.
5800 */
5801 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5802 {
5803 e_dbg("e1000_get_auto_rd_done");
5804 msleep(5);
5805 return E1000_SUCCESS;
5806 }
5807
5808 /**
5809 * e1000_get_phy_cfg_done
5810 * @hw: Struct containing variables accessed by shared code
5811 *
5812 * Checks if the PHY configuration is done
5813 * returns: - E1000_ERR_RESET if fail to reset MAC
5814 * E1000_SUCCESS at any other case.
5815 */
5816 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5817 {
5818 e_dbg("e1000_get_phy_cfg_done");
5819 mdelay(10);
5820 return E1000_SUCCESS;
5821 }
Linux kernel - Deliverables
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