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Merge branch 'r8169-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu...
[deliverable/linux.git] / drivers / net / e1000e / 82571.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Fiber)
32 * 82571EB Dual Port Gigabit Mezzanine Adapter
33 * 82571EB Quad Port Gigabit Mezzanine Adapter
34 * 82571PT Gigabit PT Quad Port Server ExpressModule
35 * 82572EI Gigabit Ethernet Controller (Copper)
36 * 82572EI Gigabit Ethernet Controller (Fiber)
37 * 82572EI Gigabit Ethernet Controller
38 * 82573V Gigabit Ethernet Controller (Copper)
39 * 82573E Gigabit Ethernet Controller (Copper)
40 * 82573L Gigabit Ethernet Controller
41 * 82574L Gigabit Network Connection
42 */
43
44 #include <linux/netdevice.h>
45 #include <linux/delay.h>
46 #include <linux/pci.h>
47
48 #include "e1000.h"
49
50 #define ID_LED_RESERVED_F746 0xF746
51 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
52 (ID_LED_OFF1_ON2 << 8) | \
53 (ID_LED_DEF1_DEF2 << 4) | \
54 (ID_LED_DEF1_DEF2))
55
56 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
57
58 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
59
60 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
61 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
62 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
63 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
64 u16 words, u16 *data);
65 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
66 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
71
72 /**
73 * e1000_init_phy_params_82571 - Init PHY func ptrs.
74 * @hw: pointer to the HW structure
75 *
76 * This is a function pointer entry point called by the api module.
77 **/
78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
79 {
80 struct e1000_phy_info *phy = &hw->phy;
81 s32 ret_val;
82
83 if (hw->phy.media_type != e1000_media_type_copper) {
84 phy->type = e1000_phy_none;
85 return 0;
86 }
87
88 phy->addr = 1;
89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
90 phy->reset_delay_us = 100;
91
92 switch (hw->mac.type) {
93 case e1000_82571:
94 case e1000_82572:
95 phy->type = e1000_phy_igp_2;
96 break;
97 case e1000_82573:
98 phy->type = e1000_phy_m88;
99 break;
100 case e1000_82574:
101 phy->type = e1000_phy_bm;
102 break;
103 default:
104 return -E1000_ERR_PHY;
105 break;
106 }
107
108 /* This can only be done after all function pointers are setup. */
109 ret_val = e1000_get_phy_id_82571(hw);
110
111 /* Verify phy id */
112 switch (hw->mac.type) {
113 case e1000_82571:
114 case e1000_82572:
115 if (phy->id != IGP01E1000_I_PHY_ID)
116 return -E1000_ERR_PHY;
117 break;
118 case e1000_82573:
119 if (phy->id != M88E1111_I_PHY_ID)
120 return -E1000_ERR_PHY;
121 break;
122 case e1000_82574:
123 if (phy->id != BME1000_E_PHY_ID_R2)
124 return -E1000_ERR_PHY;
125 break;
126 default:
127 return -E1000_ERR_PHY;
128 break;
129 }
130
131 return 0;
132 }
133
134 /**
135 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
136 * @hw: pointer to the HW structure
137 *
138 * This is a function pointer entry point called by the api module.
139 **/
140 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
141 {
142 struct e1000_nvm_info *nvm = &hw->nvm;
143 u32 eecd = er32(EECD);
144 u16 size;
145
146 nvm->opcode_bits = 8;
147 nvm->delay_usec = 1;
148 switch (nvm->override) {
149 case e1000_nvm_override_spi_large:
150 nvm->page_size = 32;
151 nvm->address_bits = 16;
152 break;
153 case e1000_nvm_override_spi_small:
154 nvm->page_size = 8;
155 nvm->address_bits = 8;
156 break;
157 default:
158 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
159 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
160 break;
161 }
162
163 switch (hw->mac.type) {
164 case e1000_82573:
165 case e1000_82574:
166 if (((eecd >> 15) & 0x3) == 0x3) {
167 nvm->type = e1000_nvm_flash_hw;
168 nvm->word_size = 2048;
169 /*
170 * Autonomous Flash update bit must be cleared due
171 * to Flash update issue.
172 */
173 eecd &= ~E1000_EECD_AUPDEN;
174 ew32(EECD, eecd);
175 break;
176 }
177 /* Fall Through */
178 default:
179 nvm->type = e1000_nvm_eeprom_spi;
180 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
181 E1000_EECD_SIZE_EX_SHIFT);
182 /*
183 * Added to a constant, "size" becomes the left-shift value
184 * for setting word_size.
185 */
186 size += NVM_WORD_SIZE_BASE_SHIFT;
187
188 /* EEPROM access above 16k is unsupported */
189 if (size > 14)
190 size = 14;
191 nvm->word_size = 1 << size;
192 break;
193 }
194
195 return 0;
196 }
197
198 /**
199 * e1000_init_mac_params_82571 - Init MAC func ptrs.
200 * @hw: pointer to the HW structure
201 *
202 * This is a function pointer entry point called by the api module.
203 **/
204 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
205 {
206 struct e1000_hw *hw = &adapter->hw;
207 struct e1000_mac_info *mac = &hw->mac;
208 struct e1000_mac_operations *func = &mac->ops;
209
210 /* Set media type */
211 switch (adapter->pdev->device) {
212 case E1000_DEV_ID_82571EB_FIBER:
213 case E1000_DEV_ID_82572EI_FIBER:
214 case E1000_DEV_ID_82571EB_QUAD_FIBER:
215 hw->phy.media_type = e1000_media_type_fiber;
216 break;
217 case E1000_DEV_ID_82571EB_SERDES:
218 case E1000_DEV_ID_82572EI_SERDES:
219 case E1000_DEV_ID_82571EB_SERDES_DUAL:
220 case E1000_DEV_ID_82571EB_SERDES_QUAD:
221 hw->phy.media_type = e1000_media_type_internal_serdes;
222 break;
223 default:
224 hw->phy.media_type = e1000_media_type_copper;
225 break;
226 }
227
228 /* Set mta register count */
229 mac->mta_reg_count = 128;
230 /* Set rar entry count */
231 mac->rar_entry_count = E1000_RAR_ENTRIES;
232 /* Set if manageability features are enabled. */
233 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
234
235 /* check for link */
236 switch (hw->phy.media_type) {
237 case e1000_media_type_copper:
238 func->setup_physical_interface = e1000_setup_copper_link_82571;
239 func->check_for_link = e1000e_check_for_copper_link;
240 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
241 break;
242 case e1000_media_type_fiber:
243 func->setup_physical_interface =
244 e1000_setup_fiber_serdes_link_82571;
245 func->check_for_link = e1000e_check_for_fiber_link;
246 func->get_link_up_info =
247 e1000e_get_speed_and_duplex_fiber_serdes;
248 break;
249 case e1000_media_type_internal_serdes:
250 func->setup_physical_interface =
251 e1000_setup_fiber_serdes_link_82571;
252 func->check_for_link = e1000e_check_for_serdes_link;
253 func->get_link_up_info =
254 e1000e_get_speed_and_duplex_fiber_serdes;
255 break;
256 default:
257 return -E1000_ERR_CONFIG;
258 break;
259 }
260
261 switch (hw->mac.type) {
262 case e1000_82574:
263 func->check_mng_mode = e1000_check_mng_mode_82574;
264 func->led_on = e1000_led_on_82574;
265 break;
266 default:
267 func->check_mng_mode = e1000e_check_mng_mode_generic;
268 func->led_on = e1000e_led_on_generic;
269 break;
270 }
271
272 return 0;
273 }
274
275 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
276 {
277 struct e1000_hw *hw = &adapter->hw;
278 static int global_quad_port_a; /* global port a indication */
279 struct pci_dev *pdev = adapter->pdev;
280 u16 eeprom_data = 0;
281 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
282 s32 rc;
283
284 rc = e1000_init_mac_params_82571(adapter);
285 if (rc)
286 return rc;
287
288 rc = e1000_init_nvm_params_82571(hw);
289 if (rc)
290 return rc;
291
292 rc = e1000_init_phy_params_82571(hw);
293 if (rc)
294 return rc;
295
296 /* tag quad port adapters first, it's used below */
297 switch (pdev->device) {
298 case E1000_DEV_ID_82571EB_QUAD_COPPER:
299 case E1000_DEV_ID_82571EB_QUAD_FIBER:
300 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
301 case E1000_DEV_ID_82571PT_QUAD_COPPER:
302 adapter->flags |= FLAG_IS_QUAD_PORT;
303 /* mark the first port */
304 if (global_quad_port_a == 0)
305 adapter->flags |= FLAG_IS_QUAD_PORT_A;
306 /* Reset for multiple quad port adapters */
307 global_quad_port_a++;
308 if (global_quad_port_a == 4)
309 global_quad_port_a = 0;
310 break;
311 default:
312 break;
313 }
314
315 switch (adapter->hw.mac.type) {
316 case e1000_82571:
317 /* these dual ports don't have WoL on port B at all */
318 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
319 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
320 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
321 (is_port_b))
322 adapter->flags &= ~FLAG_HAS_WOL;
323 /* quad ports only support WoL on port A */
324 if (adapter->flags & FLAG_IS_QUAD_PORT &&
325 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
326 adapter->flags &= ~FLAG_HAS_WOL;
327 /* Does not support WoL on any port */
328 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
329 adapter->flags &= ~FLAG_HAS_WOL;
330 break;
331
332 case e1000_82573:
333 if (pdev->device == E1000_DEV_ID_82573L) {
334 e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
335 &eeprom_data);
336 if (eeprom_data & NVM_WORD1A_ASPM_MASK)
337 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
338 }
339 break;
340 default:
341 break;
342 }
343
344 return 0;
345 }
346
347 /**
348 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
349 * @hw: pointer to the HW structure
350 *
351 * Reads the PHY registers and stores the PHY ID and possibly the PHY
352 * revision in the hardware structure.
353 **/
354 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
355 {
356 struct e1000_phy_info *phy = &hw->phy;
357 s32 ret_val;
358 u16 phy_id = 0;
359
360 switch (hw->mac.type) {
361 case e1000_82571:
362 case e1000_82572:
363 /*
364 * The 82571 firmware may still be configuring the PHY.
365 * In this case, we cannot access the PHY until the
366 * configuration is done. So we explicitly set the
367 * PHY ID.
368 */
369 phy->id = IGP01E1000_I_PHY_ID;
370 break;
371 case e1000_82573:
372 return e1000e_get_phy_id(hw);
373 break;
374 case e1000_82574:
375 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
376 if (ret_val)
377 return ret_val;
378
379 phy->id = (u32)(phy_id << 16);
380 udelay(20);
381 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
382 if (ret_val)
383 return ret_val;
384
385 phy->id |= (u32)(phy_id);
386 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
387 break;
388 default:
389 return -E1000_ERR_PHY;
390 break;
391 }
392
393 return 0;
394 }
395
396 /**
397 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
398 * @hw: pointer to the HW structure
399 *
400 * Acquire the HW semaphore to access the PHY or NVM
401 **/
402 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
403 {
404 u32 swsm;
405 s32 timeout = hw->nvm.word_size + 1;
406 s32 i = 0;
407
408 /* Get the FW semaphore. */
409 for (i = 0; i < timeout; i++) {
410 swsm = er32(SWSM);
411 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
412
413 /* Semaphore acquired if bit latched */
414 if (er32(SWSM) & E1000_SWSM_SWESMBI)
415 break;
416
417 udelay(50);
418 }
419
420 if (i == timeout) {
421 /* Release semaphores */
422 e1000e_put_hw_semaphore(hw);
423 hw_dbg(hw, "Driver can't access the NVM\n");
424 return -E1000_ERR_NVM;
425 }
426
427 return 0;
428 }
429
430 /**
431 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
432 * @hw: pointer to the HW structure
433 *
434 * Release hardware semaphore used to access the PHY or NVM
435 **/
436 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
437 {
438 u32 swsm;
439
440 swsm = er32(SWSM);
441
442 swsm &= ~E1000_SWSM_SWESMBI;
443
444 ew32(SWSM, swsm);
445 }
446
447 /**
448 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
449 * @hw: pointer to the HW structure
450 *
451 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
452 * Then for non-82573 hardware, set the EEPROM access request bit and wait
453 * for EEPROM access grant bit. If the access grant bit is not set, release
454 * hardware semaphore.
455 **/
456 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
457 {
458 s32 ret_val;
459
460 ret_val = e1000_get_hw_semaphore_82571(hw);
461 if (ret_val)
462 return ret_val;
463
464 if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
465 ret_val = e1000e_acquire_nvm(hw);
466
467 if (ret_val)
468 e1000_put_hw_semaphore_82571(hw);
469
470 return ret_val;
471 }
472
473 /**
474 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
475 * @hw: pointer to the HW structure
476 *
477 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
478 **/
479 static void e1000_release_nvm_82571(struct e1000_hw *hw)
480 {
481 e1000e_release_nvm(hw);
482 e1000_put_hw_semaphore_82571(hw);
483 }
484
485 /**
486 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
487 * @hw: pointer to the HW structure
488 * @offset: offset within the EEPROM to be written to
489 * @words: number of words to write
490 * @data: 16 bit word(s) to be written to the EEPROM
491 *
492 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
493 *
494 * If e1000e_update_nvm_checksum is not called after this function, the
495 * EEPROM will most likely contain an invalid checksum.
496 **/
497 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
498 u16 *data)
499 {
500 s32 ret_val;
501
502 switch (hw->mac.type) {
503 case e1000_82573:
504 case e1000_82574:
505 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
506 break;
507 case e1000_82571:
508 case e1000_82572:
509 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
510 break;
511 default:
512 ret_val = -E1000_ERR_NVM;
513 break;
514 }
515
516 return ret_val;
517 }
518
519 /**
520 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
521 * @hw: pointer to the HW structure
522 *
523 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
524 * up to the checksum. Then calculates the EEPROM checksum and writes the
525 * value to the EEPROM.
526 **/
527 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
528 {
529 u32 eecd;
530 s32 ret_val;
531 u16 i;
532
533 ret_val = e1000e_update_nvm_checksum_generic(hw);
534 if (ret_val)
535 return ret_val;
536
537 /*
538 * If our nvm is an EEPROM, then we're done
539 * otherwise, commit the checksum to the flash NVM.
540 */
541 if (hw->nvm.type != e1000_nvm_flash_hw)
542 return ret_val;
543
544 /* Check for pending operations. */
545 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
546 msleep(1);
547 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
548 break;
549 }
550
551 if (i == E1000_FLASH_UPDATES)
552 return -E1000_ERR_NVM;
553
554 /* Reset the firmware if using STM opcode. */
555 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
556 /*
557 * The enabling of and the actual reset must be done
558 * in two write cycles.
559 */
560 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
561 e1e_flush();
562 ew32(HICR, E1000_HICR_FW_RESET);
563 }
564
565 /* Commit the write to flash */
566 eecd = er32(EECD) | E1000_EECD_FLUPD;
567 ew32(EECD, eecd);
568
569 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
570 msleep(1);
571 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
572 break;
573 }
574
575 if (i == E1000_FLASH_UPDATES)
576 return -E1000_ERR_NVM;
577
578 return 0;
579 }
580
581 /**
582 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
583 * @hw: pointer to the HW structure
584 *
585 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
586 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
587 **/
588 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
589 {
590 if (hw->nvm.type == e1000_nvm_flash_hw)
591 e1000_fix_nvm_checksum_82571(hw);
592
593 return e1000e_validate_nvm_checksum_generic(hw);
594 }
595
596 /**
597 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
598 * @hw: pointer to the HW structure
599 * @offset: offset within the EEPROM to be written to
600 * @words: number of words to write
601 * @data: 16 bit word(s) to be written to the EEPROM
602 *
603 * After checking for invalid values, poll the EEPROM to ensure the previous
604 * command has completed before trying to write the next word. After write
605 * poll for completion.
606 *
607 * If e1000e_update_nvm_checksum is not called after this function, the
608 * EEPROM will most likely contain an invalid checksum.
609 **/
610 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
611 u16 words, u16 *data)
612 {
613 struct e1000_nvm_info *nvm = &hw->nvm;
614 u32 i;
615 u32 eewr = 0;
616 s32 ret_val = 0;
617
618 /*
619 * A check for invalid values: offset too large, too many words,
620 * and not enough words.
621 */
622 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
623 (words == 0)) {
624 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
625 return -E1000_ERR_NVM;
626 }
627
628 for (i = 0; i < words; i++) {
629 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
630 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
631 E1000_NVM_RW_REG_START;
632
633 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
634 if (ret_val)
635 break;
636
637 ew32(EEWR, eewr);
638
639 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
640 if (ret_val)
641 break;
642 }
643
644 return ret_val;
645 }
646
647 /**
648 * e1000_get_cfg_done_82571 - Poll for configuration done
649 * @hw: pointer to the HW structure
650 *
651 * Reads the management control register for the config done bit to be set.
652 **/
653 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
654 {
655 s32 timeout = PHY_CFG_TIMEOUT;
656
657 while (timeout) {
658 if (er32(EEMNGCTL) &
659 E1000_NVM_CFG_DONE_PORT_0)
660 break;
661 msleep(1);
662 timeout--;
663 }
664 if (!timeout) {
665 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
666 return -E1000_ERR_RESET;
667 }
668
669 return 0;
670 }
671
672 /**
673 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
674 * @hw: pointer to the HW structure
675 * @active: TRUE to enable LPLU, FALSE to disable
676 *
677 * Sets the LPLU D0 state according to the active flag. When activating LPLU
678 * this function also disables smart speed and vice versa. LPLU will not be
679 * activated unless the device autonegotiation advertisement meets standards
680 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
681 * pointer entry point only called by PHY setup routines.
682 **/
683 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
684 {
685 struct e1000_phy_info *phy = &hw->phy;
686 s32 ret_val;
687 u16 data;
688
689 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
690 if (ret_val)
691 return ret_val;
692
693 if (active) {
694 data |= IGP02E1000_PM_D0_LPLU;
695 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
696 if (ret_val)
697 return ret_val;
698
699 /* When LPLU is enabled, we should disable SmartSpeed */
700 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
701 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
702 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
703 if (ret_val)
704 return ret_val;
705 } else {
706 data &= ~IGP02E1000_PM_D0_LPLU;
707 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
708 /*
709 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
710 * during Dx states where the power conservation is most
711 * important. During driver activity we should enable
712 * SmartSpeed, so performance is maintained.
713 */
714 if (phy->smart_speed == e1000_smart_speed_on) {
715 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
716 &data);
717 if (ret_val)
718 return ret_val;
719
720 data |= IGP01E1000_PSCFR_SMART_SPEED;
721 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
722 data);
723 if (ret_val)
724 return ret_val;
725 } else if (phy->smart_speed == e1000_smart_speed_off) {
726 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
727 &data);
728 if (ret_val)
729 return ret_val;
730
731 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
732 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
733 data);
734 if (ret_val)
735 return ret_val;
736 }
737 }
738
739 return 0;
740 }
741
742 /**
743 * e1000_reset_hw_82571 - Reset hardware
744 * @hw: pointer to the HW structure
745 *
746 * This resets the hardware into a known state. This is a
747 * function pointer entry point called by the api module.
748 **/
749 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
750 {
751 u32 ctrl;
752 u32 extcnf_ctrl;
753 u32 ctrl_ext;
754 u32 icr;
755 s32 ret_val;
756 u16 i = 0;
757
758 /*
759 * Prevent the PCI-E bus from sticking if there is no TLP connection
760 * on the last TLP read/write transaction when MAC is reset.
761 */
762 ret_val = e1000e_disable_pcie_master(hw);
763 if (ret_val)
764 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
765
766 hw_dbg(hw, "Masking off all interrupts\n");
767 ew32(IMC, 0xffffffff);
768
769 ew32(RCTL, 0);
770 ew32(TCTL, E1000_TCTL_PSP);
771 e1e_flush();
772
773 msleep(10);
774
775 /*
776 * Must acquire the MDIO ownership before MAC reset.
777 * Ownership defaults to firmware after a reset.
778 */
779 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
780 extcnf_ctrl = er32(EXTCNF_CTRL);
781 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
782
783 do {
784 ew32(EXTCNF_CTRL, extcnf_ctrl);
785 extcnf_ctrl = er32(EXTCNF_CTRL);
786
787 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
788 break;
789
790 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
791
792 msleep(2);
793 i++;
794 } while (i < MDIO_OWNERSHIP_TIMEOUT);
795 }
796
797 ctrl = er32(CTRL);
798
799 hw_dbg(hw, "Issuing a global reset to MAC\n");
800 ew32(CTRL, ctrl | E1000_CTRL_RST);
801
802 if (hw->nvm.type == e1000_nvm_flash_hw) {
803 udelay(10);
804 ctrl_ext = er32(CTRL_EXT);
805 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
806 ew32(CTRL_EXT, ctrl_ext);
807 e1e_flush();
808 }
809
810 ret_val = e1000e_get_auto_rd_done(hw);
811 if (ret_val)
812 /* We don't want to continue accessing MAC registers. */
813 return ret_val;
814
815 /*
816 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
817 * Need to wait for Phy configuration completion before accessing
818 * NVM and Phy.
819 */
820 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
821 msleep(25);
822
823 /* Clear any pending interrupt events. */
824 ew32(IMC, 0xffffffff);
825 icr = er32(ICR);
826
827 if (hw->mac.type == e1000_82571 &&
828 hw->dev_spec.e82571.alt_mac_addr_is_present)
829 e1000e_set_laa_state_82571(hw, true);
830
831 return 0;
832 }
833
834 /**
835 * e1000_init_hw_82571 - Initialize hardware
836 * @hw: pointer to the HW structure
837 *
838 * This inits the hardware readying it for operation.
839 **/
840 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
841 {
842 struct e1000_mac_info *mac = &hw->mac;
843 u32 reg_data;
844 s32 ret_val;
845 u16 i;
846 u16 rar_count = mac->rar_entry_count;
847
848 e1000_initialize_hw_bits_82571(hw);
849
850 /* Initialize identification LED */
851 ret_val = e1000e_id_led_init(hw);
852 if (ret_val) {
853 hw_dbg(hw, "Error initializing identification LED\n");
854 return ret_val;
855 }
856
857 /* Disabling VLAN filtering */
858 hw_dbg(hw, "Initializing the IEEE VLAN\n");
859 e1000e_clear_vfta(hw);
860
861 /* Setup the receive address. */
862 /*
863 * If, however, a locally administered address was assigned to the
864 * 82571, we must reserve a RAR for it to work around an issue where
865 * resetting one port will reload the MAC on the other port.
866 */
867 if (e1000e_get_laa_state_82571(hw))
868 rar_count--;
869 e1000e_init_rx_addrs(hw, rar_count);
870
871 /* Zero out the Multicast HASH table */
872 hw_dbg(hw, "Zeroing the MTA\n");
873 for (i = 0; i < mac->mta_reg_count; i++)
874 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
875
876 /* Setup link and flow control */
877 ret_val = e1000_setup_link_82571(hw);
878
879 /* Set the transmit descriptor write-back policy */
880 reg_data = er32(TXDCTL(0));
881 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
882 E1000_TXDCTL_FULL_TX_DESC_WB |
883 E1000_TXDCTL_COUNT_DESC;
884 ew32(TXDCTL(0), reg_data);
885
886 /* ...for both queues. */
887 if (mac->type != e1000_82573 && mac->type != e1000_82574) {
888 reg_data = er32(TXDCTL(1));
889 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
890 E1000_TXDCTL_FULL_TX_DESC_WB |
891 E1000_TXDCTL_COUNT_DESC;
892 ew32(TXDCTL(1), reg_data);
893 } else {
894 e1000e_enable_tx_pkt_filtering(hw);
895 reg_data = er32(GCR);
896 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
897 ew32(GCR, reg_data);
898 }
899
900 /*
901 * Clear all of the statistics registers (clear on read). It is
902 * important that we do this after we have tried to establish link
903 * because the symbol error count will increment wildly if there
904 * is no link.
905 */
906 e1000_clear_hw_cntrs_82571(hw);
907
908 return ret_val;
909 }
910
911 /**
912 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
913 * @hw: pointer to the HW structure
914 *
915 * Initializes required hardware-dependent bits needed for normal operation.
916 **/
917 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
918 {
919 u32 reg;
920
921 /* Transmit Descriptor Control 0 */
922 reg = er32(TXDCTL(0));
923 reg |= (1 << 22);
924 ew32(TXDCTL(0), reg);
925
926 /* Transmit Descriptor Control 1 */
927 reg = er32(TXDCTL(1));
928 reg |= (1 << 22);
929 ew32(TXDCTL(1), reg);
930
931 /* Transmit Arbitration Control 0 */
932 reg = er32(TARC(0));
933 reg &= ~(0xF << 27); /* 30:27 */
934 switch (hw->mac.type) {
935 case e1000_82571:
936 case e1000_82572:
937 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
938 break;
939 default:
940 break;
941 }
942 ew32(TARC(0), reg);
943
944 /* Transmit Arbitration Control 1 */
945 reg = er32(TARC(1));
946 switch (hw->mac.type) {
947 case e1000_82571:
948 case e1000_82572:
949 reg &= ~((1 << 29) | (1 << 30));
950 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
951 if (er32(TCTL) & E1000_TCTL_MULR)
952 reg &= ~(1 << 28);
953 else
954 reg |= (1 << 28);
955 ew32(TARC(1), reg);
956 break;
957 default:
958 break;
959 }
960
961 /* Device Control */
962 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
963 reg = er32(CTRL);
964 reg &= ~(1 << 29);
965 ew32(CTRL, reg);
966 }
967
968 /* Extended Device Control */
969 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
970 reg = er32(CTRL_EXT);
971 reg &= ~(1 << 23);
972 reg |= (1 << 22);
973 ew32(CTRL_EXT, reg);
974 }
975
976 /* PCI-Ex Control Register */
977 if (hw->mac.type == e1000_82574) {
978 reg = er32(GCR);
979 reg |= (1 << 22);
980 ew32(GCR, reg);
981 }
982
983 return;
984 }
985
986 /**
987 * e1000e_clear_vfta - Clear VLAN filter table
988 * @hw: pointer to the HW structure
989 *
990 * Clears the register array which contains the VLAN filter table by
991 * setting all the values to 0.
992 **/
993 void e1000e_clear_vfta(struct e1000_hw *hw)
994 {
995 u32 offset;
996 u32 vfta_value = 0;
997 u32 vfta_offset = 0;
998 u32 vfta_bit_in_reg = 0;
999
1000 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1001 if (hw->mng_cookie.vlan_id != 0) {
1002 /*
1003 * The VFTA is a 4096b bit-field, each identifying
1004 * a single VLAN ID. The following operations
1005 * determine which 32b entry (i.e. offset) into the
1006 * array we want to set the VLAN ID (i.e. bit) of
1007 * the manageability unit.
1008 */
1009 vfta_offset = (hw->mng_cookie.vlan_id >>
1010 E1000_VFTA_ENTRY_SHIFT) &
1011 E1000_VFTA_ENTRY_MASK;
1012 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1013 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1014 }
1015 }
1016 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1017 /*
1018 * If the offset we want to clear is the same offset of the
1019 * manageability VLAN ID, then clear all bits except that of
1020 * the manageability unit.
1021 */
1022 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1023 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1024 e1e_flush();
1025 }
1026 }
1027
1028 /**
1029 * e1000_check_mng_mode_82574 - Check manageability is enabled
1030 * @hw: pointer to the HW structure
1031 *
1032 * Reads the NVM Initialization Control Word 2 and returns true
1033 * (>0) if any manageability is enabled, else false (0).
1034 **/
1035 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1036 {
1037 u16 data;
1038
1039 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1040 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1041 }
1042
1043 /**
1044 * e1000_led_on_82574 - Turn LED on
1045 * @hw: pointer to the HW structure
1046 *
1047 * Turn LED on.
1048 **/
1049 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1050 {
1051 u32 ctrl;
1052 u32 i;
1053
1054 ctrl = hw->mac.ledctl_mode2;
1055 if (!(E1000_STATUS_LU & er32(STATUS))) {
1056 /*
1057 * If no link, then turn LED on by setting the invert bit
1058 * for each LED that's "on" (0x0E) in ledctl_mode2.
1059 */
1060 for (i = 0; i < 4; i++)
1061 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1062 E1000_LEDCTL_MODE_LED_ON)
1063 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1064 }
1065 ew32(LEDCTL, ctrl);
1066
1067 return 0;
1068 }
1069
1070 /**
1071 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1072 * @hw: pointer to the HW structure
1073 * @mc_addr_list: array of multicast addresses to program
1074 * @mc_addr_count: number of multicast addresses to program
1075 * @rar_used_count: the first RAR register free to program
1076 * @rar_count: total number of supported Receive Address Registers
1077 *
1078 * Updates the Receive Address Registers and Multicast Table Array.
1079 * The caller must have a packed mc_addr_list of multicast addresses.
1080 * The parameter rar_count will usually be hw->mac.rar_entry_count
1081 * unless there are workarounds that change this.
1082 **/
1083 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1084 u8 *mc_addr_list,
1085 u32 mc_addr_count,
1086 u32 rar_used_count,
1087 u32 rar_count)
1088 {
1089 if (e1000e_get_laa_state_82571(hw))
1090 rar_count--;
1091
1092 e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1093 rar_used_count, rar_count);
1094 }
1095
1096 /**
1097 * e1000_setup_link_82571 - Setup flow control and link settings
1098 * @hw: pointer to the HW structure
1099 *
1100 * Determines which flow control settings to use, then configures flow
1101 * control. Calls the appropriate media-specific link configuration
1102 * function. Assuming the adapter has a valid link partner, a valid link
1103 * should be established. Assumes the hardware has previously been reset
1104 * and the transmitter and receiver are not enabled.
1105 **/
1106 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1107 {
1108 /*
1109 * 82573 does not have a word in the NVM to determine
1110 * the default flow control setting, so we explicitly
1111 * set it to full.
1112 */
1113 if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1114 hw->fc.type == e1000_fc_default)
1115 hw->fc.type = e1000_fc_full;
1116
1117 return e1000e_setup_link(hw);
1118 }
1119
1120 /**
1121 * e1000_setup_copper_link_82571 - Configure copper link settings
1122 * @hw: pointer to the HW structure
1123 *
1124 * Configures the link for auto-neg or forced speed and duplex. Then we check
1125 * for link, once link is established calls to configure collision distance
1126 * and flow control are called.
1127 **/
1128 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1129 {
1130 u32 ctrl;
1131 u32 led_ctrl;
1132 s32 ret_val;
1133
1134 ctrl = er32(CTRL);
1135 ctrl |= E1000_CTRL_SLU;
1136 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1137 ew32(CTRL, ctrl);
1138
1139 switch (hw->phy.type) {
1140 case e1000_phy_m88:
1141 case e1000_phy_bm:
1142 ret_val = e1000e_copper_link_setup_m88(hw);
1143 break;
1144 case e1000_phy_igp_2:
1145 ret_val = e1000e_copper_link_setup_igp(hw);
1146 /* Setup activity LED */
1147 led_ctrl = er32(LEDCTL);
1148 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1149 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1150 ew32(LEDCTL, led_ctrl);
1151 break;
1152 default:
1153 return -E1000_ERR_PHY;
1154 break;
1155 }
1156
1157 if (ret_val)
1158 return ret_val;
1159
1160 ret_val = e1000e_setup_copper_link(hw);
1161
1162 return ret_val;
1163 }
1164
1165 /**
1166 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1167 * @hw: pointer to the HW structure
1168 *
1169 * Configures collision distance and flow control for fiber and serdes links.
1170 * Upon successful setup, poll for link.
1171 **/
1172 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1173 {
1174 switch (hw->mac.type) {
1175 case e1000_82571:
1176 case e1000_82572:
1177 /*
1178 * If SerDes loopback mode is entered, there is no form
1179 * of reset to take the adapter out of that mode. So we
1180 * have to explicitly take the adapter out of loopback
1181 * mode. This prevents drivers from twiddling their thumbs
1182 * if another tool failed to take it out of loopback mode.
1183 */
1184 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1185 break;
1186 default:
1187 break;
1188 }
1189
1190 return e1000e_setup_fiber_serdes_link(hw);
1191 }
1192
1193 /**
1194 * e1000_valid_led_default_82571 - Verify a valid default LED config
1195 * @hw: pointer to the HW structure
1196 * @data: pointer to the NVM (EEPROM)
1197 *
1198 * Read the EEPROM for the current default LED configuration. If the
1199 * LED configuration is not valid, set to a valid LED configuration.
1200 **/
1201 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1202 {
1203 s32 ret_val;
1204
1205 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1206 if (ret_val) {
1207 hw_dbg(hw, "NVM Read Error\n");
1208 return ret_val;
1209 }
1210
1211 if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1212 *data == ID_LED_RESERVED_F746)
1213 *data = ID_LED_DEFAULT_82573;
1214 else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1215 *data = ID_LED_DEFAULT;
1216
1217 return 0;
1218 }
1219
1220 /**
1221 * e1000e_get_laa_state_82571 - Get locally administered address state
1222 * @hw: pointer to the HW structure
1223 *
1224 * Retrieve and return the current locally administered address state.
1225 **/
1226 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1227 {
1228 if (hw->mac.type != e1000_82571)
1229 return 0;
1230
1231 return hw->dev_spec.e82571.laa_is_present;
1232 }
1233
1234 /**
1235 * e1000e_set_laa_state_82571 - Set locally administered address state
1236 * @hw: pointer to the HW structure
1237 * @state: enable/disable locally administered address
1238 *
1239 * Enable/Disable the current locally administers address state.
1240 **/
1241 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1242 {
1243 if (hw->mac.type != e1000_82571)
1244 return;
1245
1246 hw->dev_spec.e82571.laa_is_present = state;
1247
1248 /* If workaround is activated... */
1249 if (state)
1250 /*
1251 * Hold a copy of the LAA in RAR[14] This is done so that
1252 * between the time RAR[0] gets clobbered and the time it
1253 * gets fixed, the actual LAA is in one of the RARs and no
1254 * incoming packets directed to this port are dropped.
1255 * Eventually the LAA will be in RAR[0] and RAR[14].
1256 */
1257 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1258 }
1259
1260 /**
1261 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1262 * @hw: pointer to the HW structure
1263 *
1264 * Verifies that the EEPROM has completed the update. After updating the
1265 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1266 * the checksum fix is not implemented, we need to set the bit and update
1267 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1268 * we need to return bad checksum.
1269 **/
1270 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1271 {
1272 struct e1000_nvm_info *nvm = &hw->nvm;
1273 s32 ret_val;
1274 u16 data;
1275
1276 if (nvm->type != e1000_nvm_flash_hw)
1277 return 0;
1278
1279 /*
1280 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1281 * 10h-12h. Checksum may need to be fixed.
1282 */
1283 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1284 if (ret_val)
1285 return ret_val;
1286
1287 if (!(data & 0x10)) {
1288 /*
1289 * Read 0x23 and check bit 15. This bit is a 1
1290 * when the checksum has already been fixed. If
1291 * the checksum is still wrong and this bit is a
1292 * 1, we need to return bad checksum. Otherwise,
1293 * we need to set this bit to a 1 and update the
1294 * checksum.
1295 */
1296 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1297 if (ret_val)
1298 return ret_val;
1299
1300 if (!(data & 0x8000)) {
1301 data |= 0x8000;
1302 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1303 if (ret_val)
1304 return ret_val;
1305 ret_val = e1000e_update_nvm_checksum(hw);
1306 }
1307 }
1308
1309 return 0;
1310 }
1311
1312 /**
1313 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1314 * @hw: pointer to the HW structure
1315 *
1316 * Clears the hardware counters by reading the counter registers.
1317 **/
1318 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1319 {
1320 u32 temp;
1321
1322 e1000e_clear_hw_cntrs_base(hw);
1323
1324 temp = er32(PRC64);
1325 temp = er32(PRC127);
1326 temp = er32(PRC255);
1327 temp = er32(PRC511);
1328 temp = er32(PRC1023);
1329 temp = er32(PRC1522);
1330 temp = er32(PTC64);
1331 temp = er32(PTC127);
1332 temp = er32(PTC255);
1333 temp = er32(PTC511);
1334 temp = er32(PTC1023);
1335 temp = er32(PTC1522);
1336
1337 temp = er32(ALGNERRC);
1338 temp = er32(RXERRC);
1339 temp = er32(TNCRS);
1340 temp = er32(CEXTERR);
1341 temp = er32(TSCTC);
1342 temp = er32(TSCTFC);
1343
1344 temp = er32(MGTPRC);
1345 temp = er32(MGTPDC);
1346 temp = er32(MGTPTC);
1347
1348 temp = er32(IAC);
1349 temp = er32(ICRXOC);
1350
1351 temp = er32(ICRXPTC);
1352 temp = er32(ICRXATC);
1353 temp = er32(ICTXPTC);
1354 temp = er32(ICTXATC);
1355 temp = er32(ICTXQEC);
1356 temp = er32(ICTXQMTC);
1357 temp = er32(ICRXDMTC);
1358 }
1359
1360 static struct e1000_mac_operations e82571_mac_ops = {
1361 /* .check_mng_mode: mac type dependent */
1362 /* .check_for_link: media type dependent */
1363 .cleanup_led = e1000e_cleanup_led_generic,
1364 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1365 .get_bus_info = e1000e_get_bus_info_pcie,
1366 /* .get_link_up_info: media type dependent */
1367 /* .led_on: mac type dependent */
1368 .led_off = e1000e_led_off_generic,
1369 .update_mc_addr_list = e1000_update_mc_addr_list_82571,
1370 .reset_hw = e1000_reset_hw_82571,
1371 .init_hw = e1000_init_hw_82571,
1372 .setup_link = e1000_setup_link_82571,
1373 /* .setup_physical_interface: media type dependent */
1374 };
1375
1376 static struct e1000_phy_operations e82_phy_ops_igp = {
1377 .acquire_phy = e1000_get_hw_semaphore_82571,
1378 .check_reset_block = e1000e_check_reset_block_generic,
1379 .commit_phy = NULL,
1380 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1381 .get_cfg_done = e1000_get_cfg_done_82571,
1382 .get_cable_length = e1000e_get_cable_length_igp_2,
1383 .get_phy_info = e1000e_get_phy_info_igp,
1384 .read_phy_reg = e1000e_read_phy_reg_igp,
1385 .release_phy = e1000_put_hw_semaphore_82571,
1386 .reset_phy = e1000e_phy_hw_reset_generic,
1387 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1388 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1389 .write_phy_reg = e1000e_write_phy_reg_igp,
1390 };
1391
1392 static struct e1000_phy_operations e82_phy_ops_m88 = {
1393 .acquire_phy = e1000_get_hw_semaphore_82571,
1394 .check_reset_block = e1000e_check_reset_block_generic,
1395 .commit_phy = e1000e_phy_sw_reset,
1396 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1397 .get_cfg_done = e1000e_get_cfg_done,
1398 .get_cable_length = e1000e_get_cable_length_m88,
1399 .get_phy_info = e1000e_get_phy_info_m88,
1400 .read_phy_reg = e1000e_read_phy_reg_m88,
1401 .release_phy = e1000_put_hw_semaphore_82571,
1402 .reset_phy = e1000e_phy_hw_reset_generic,
1403 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1404 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1405 .write_phy_reg = e1000e_write_phy_reg_m88,
1406 };
1407
1408 static struct e1000_phy_operations e82_phy_ops_bm = {
1409 .acquire_phy = e1000_get_hw_semaphore_82571,
1410 .check_reset_block = e1000e_check_reset_block_generic,
1411 .commit_phy = e1000e_phy_sw_reset,
1412 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1413 .get_cfg_done = e1000e_get_cfg_done,
1414 .get_cable_length = e1000e_get_cable_length_m88,
1415 .get_phy_info = e1000e_get_phy_info_m88,
1416 .read_phy_reg = e1000e_read_phy_reg_bm2,
1417 .release_phy = e1000_put_hw_semaphore_82571,
1418 .reset_phy = e1000e_phy_hw_reset_generic,
1419 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1420 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1421 .write_phy_reg = e1000e_write_phy_reg_bm2,
1422 };
1423
1424 static struct e1000_nvm_operations e82571_nvm_ops = {
1425 .acquire_nvm = e1000_acquire_nvm_82571,
1426 .read_nvm = e1000e_read_nvm_eerd,
1427 .release_nvm = e1000_release_nvm_82571,
1428 .update_nvm = e1000_update_nvm_checksum_82571,
1429 .valid_led_default = e1000_valid_led_default_82571,
1430 .validate_nvm = e1000_validate_nvm_checksum_82571,
1431 .write_nvm = e1000_write_nvm_82571,
1432 };
1433
1434 struct e1000_info e1000_82571_info = {
1435 .mac = e1000_82571,
1436 .flags = FLAG_HAS_HW_VLAN_FILTER
1437 | FLAG_HAS_JUMBO_FRAMES
1438 | FLAG_HAS_WOL
1439 | FLAG_APME_IN_CTRL3
1440 | FLAG_RX_CSUM_ENABLED
1441 | FLAG_HAS_CTRLEXT_ON_LOAD
1442 | FLAG_HAS_SMART_POWER_DOWN
1443 | FLAG_RESET_OVERWRITES_LAA /* errata */
1444 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1445 | FLAG_APME_CHECK_PORT_B,
1446 .pba = 38,
1447 .get_variants = e1000_get_variants_82571,
1448 .mac_ops = &e82571_mac_ops,
1449 .phy_ops = &e82_phy_ops_igp,
1450 .nvm_ops = &e82571_nvm_ops,
1451 };
1452
1453 struct e1000_info e1000_82572_info = {
1454 .mac = e1000_82572,
1455 .flags = FLAG_HAS_HW_VLAN_FILTER
1456 | FLAG_HAS_JUMBO_FRAMES
1457 | FLAG_HAS_WOL
1458 | FLAG_APME_IN_CTRL3
1459 | FLAG_RX_CSUM_ENABLED
1460 | FLAG_HAS_CTRLEXT_ON_LOAD
1461 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1462 .pba = 38,
1463 .get_variants = e1000_get_variants_82571,
1464 .mac_ops = &e82571_mac_ops,
1465 .phy_ops = &e82_phy_ops_igp,
1466 .nvm_ops = &e82571_nvm_ops,
1467 };
1468
1469 struct e1000_info e1000_82573_info = {
1470 .mac = e1000_82573,
1471 .flags = FLAG_HAS_HW_VLAN_FILTER
1472 | FLAG_HAS_JUMBO_FRAMES
1473 | FLAG_HAS_WOL
1474 | FLAG_APME_IN_CTRL3
1475 | FLAG_RX_CSUM_ENABLED
1476 | FLAG_HAS_SMART_POWER_DOWN
1477 | FLAG_HAS_AMT
1478 | FLAG_HAS_ERT
1479 | FLAG_HAS_SWSM_ON_LOAD,
1480 .pba = 20,
1481 .get_variants = e1000_get_variants_82571,
1482 .mac_ops = &e82571_mac_ops,
1483 .phy_ops = &e82_phy_ops_m88,
1484 .nvm_ops = &e82571_nvm_ops,
1485 };
1486
1487 struct e1000_info e1000_82574_info = {
1488 .mac = e1000_82574,
1489 .flags = FLAG_HAS_HW_VLAN_FILTER
1490 | FLAG_HAS_MSIX
1491 | FLAG_HAS_JUMBO_FRAMES
1492 | FLAG_HAS_WOL
1493 | FLAG_APME_IN_CTRL3
1494 | FLAG_RX_CSUM_ENABLED
1495 | FLAG_HAS_SMART_POWER_DOWN
1496 | FLAG_HAS_AMT
1497 | FLAG_HAS_CTRLEXT_ON_LOAD,
1498 .pba = 20,
1499 .get_variants = e1000_get_variants_82571,
1500 .mac_ops = &e82571_mac_ops,
1501 .phy_ops = &e82_phy_ops_bm,
1502 .nvm_ops = &e82571_nvm_ops,
1503 };
1504
Linux kernel - Deliverables
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