1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
58 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
);
59 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
);
60 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
);
61 static s32
e1000_check_for_serdes_link_82571(struct e1000_hw
*hw
);
62 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
63 u16 words
, u16
*data
);
64 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
);
66 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
);
68 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
);
69 static s32
e1000_led_on_82574(struct e1000_hw
*hw
);
70 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
);
73 * e1000_init_phy_params_82571 - Init PHY func ptrs.
74 * @hw: pointer to the HW structure
76 static s32
e1000_init_phy_params_82571(struct e1000_hw
*hw
)
78 struct e1000_phy_info
*phy
= &hw
->phy
;
81 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
82 phy
->type
= e1000_phy_none
;
87 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
88 phy
->reset_delay_us
= 100;
90 switch (hw
->mac
.type
) {
93 phy
->type
= e1000_phy_igp_2
;
96 phy
->type
= e1000_phy_m88
;
100 phy
->type
= e1000_phy_bm
;
103 return -E1000_ERR_PHY
;
107 /* This can only be done after all function pointers are setup. */
108 ret_val
= e1000_get_phy_id_82571(hw
);
111 switch (hw
->mac
.type
) {
114 if (phy
->id
!= IGP01E1000_I_PHY_ID
)
115 return -E1000_ERR_PHY
;
118 if (phy
->id
!= M88E1111_I_PHY_ID
)
119 return -E1000_ERR_PHY
;
123 if (phy
->id
!= BME1000_E_PHY_ID_R2
)
124 return -E1000_ERR_PHY
;
127 return -E1000_ERR_PHY
;
135 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
136 * @hw: pointer to the HW structure
138 static s32
e1000_init_nvm_params_82571(struct e1000_hw
*hw
)
140 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
141 u32 eecd
= er32(EECD
);
144 nvm
->opcode_bits
= 8;
146 switch (nvm
->override
) {
147 case e1000_nvm_override_spi_large
:
149 nvm
->address_bits
= 16;
151 case e1000_nvm_override_spi_small
:
153 nvm
->address_bits
= 8;
156 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
157 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
161 switch (hw
->mac
.type
) {
165 if (((eecd
>> 15) & 0x3) == 0x3) {
166 nvm
->type
= e1000_nvm_flash_hw
;
167 nvm
->word_size
= 2048;
169 * Autonomous Flash update bit must be cleared due
170 * to Flash update issue.
172 eecd
&= ~E1000_EECD_AUPDEN
;
178 nvm
->type
= e1000_nvm_eeprom_spi
;
179 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
180 E1000_EECD_SIZE_EX_SHIFT
);
182 * Added to a constant, "size" becomes the left-shift value
183 * for setting word_size.
185 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
187 /* EEPROM access above 16k is unsupported */
190 nvm
->word_size
= 1 << size
;
198 * e1000_init_mac_params_82571 - Init MAC func ptrs.
199 * @hw: pointer to the HW structure
201 static s32
e1000_init_mac_params_82571(struct e1000_adapter
*adapter
)
203 struct e1000_hw
*hw
= &adapter
->hw
;
204 struct e1000_mac_info
*mac
= &hw
->mac
;
205 struct e1000_mac_operations
*func
= &mac
->ops
;
208 bool force_clear_smbi
= false;
211 switch (adapter
->pdev
->device
) {
212 case E1000_DEV_ID_82571EB_FIBER
:
213 case E1000_DEV_ID_82572EI_FIBER
:
214 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
215 hw
->phy
.media_type
= e1000_media_type_fiber
;
217 case E1000_DEV_ID_82571EB_SERDES
:
218 case E1000_DEV_ID_82572EI_SERDES
:
219 case E1000_DEV_ID_82571EB_SERDES_DUAL
:
220 case E1000_DEV_ID_82571EB_SERDES_QUAD
:
221 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
224 hw
->phy
.media_type
= e1000_media_type_copper
;
228 /* Set mta register count */
229 mac
->mta_reg_count
= 128;
230 /* Set rar entry count */
231 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
232 /* Set if manageability features are enabled. */
233 mac
->arc_subsystem_valid
= (er32(FWSM
) & E1000_FWSM_MODE_MASK
) ? 1 : 0;
236 switch (hw
->phy
.media_type
) {
237 case e1000_media_type_copper
:
238 func
->setup_physical_interface
= e1000_setup_copper_link_82571
;
239 func
->check_for_link
= e1000e_check_for_copper_link
;
240 func
->get_link_up_info
= e1000e_get_speed_and_duplex_copper
;
242 case e1000_media_type_fiber
:
243 func
->setup_physical_interface
=
244 e1000_setup_fiber_serdes_link_82571
;
245 func
->check_for_link
= e1000e_check_for_fiber_link
;
246 func
->get_link_up_info
=
247 e1000e_get_speed_and_duplex_fiber_serdes
;
249 case e1000_media_type_internal_serdes
:
250 func
->setup_physical_interface
=
251 e1000_setup_fiber_serdes_link_82571
;
252 func
->check_for_link
= e1000_check_for_serdes_link_82571
;
253 func
->get_link_up_info
=
254 e1000e_get_speed_and_duplex_fiber_serdes
;
257 return -E1000_ERR_CONFIG
;
261 switch (hw
->mac
.type
) {
264 func
->check_mng_mode
= e1000_check_mng_mode_82574
;
265 func
->led_on
= e1000_led_on_82574
;
268 func
->check_mng_mode
= e1000e_check_mng_mode_generic
;
269 func
->led_on
= e1000e_led_on_generic
;
274 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
275 * first NVM or PHY acess. This should be done for single-port
276 * devices, and for one port only on dual-port devices so that
277 * for those devices we can still use the SMBI lock to synchronize
278 * inter-port accesses to the PHY & NVM.
280 switch (hw
->mac
.type
) {
285 if (!(swsm2
& E1000_SWSM2_LOCK
)) {
286 /* Only do this for the first interface on this card */
288 swsm2
| E1000_SWSM2_LOCK
);
289 force_clear_smbi
= true;
291 force_clear_smbi
= false;
294 force_clear_smbi
= true;
298 if (force_clear_smbi
) {
299 /* Make sure SWSM.SMBI is clear */
301 if (swsm
& E1000_SWSM_SMBI
) {
302 /* This bit should not be set on a first interface, and
303 * indicates that the bootagent or EFI code has
304 * improperly left this bit enabled
306 e_dbg("Please update your 82571 Bootagent\n");
308 ew32(SWSM
, swsm
& ~E1000_SWSM_SMBI
);
312 * Initialze device specific counter of SMBI acquisition
315 hw
->dev_spec
.e82571
.smb_counter
= 0;
320 static s32
e1000_get_variants_82571(struct e1000_adapter
*adapter
)
322 struct e1000_hw
*hw
= &adapter
->hw
;
323 static int global_quad_port_a
; /* global port a indication */
324 struct pci_dev
*pdev
= adapter
->pdev
;
326 int is_port_b
= er32(STATUS
) & E1000_STATUS_FUNC_1
;
329 rc
= e1000_init_mac_params_82571(adapter
);
333 rc
= e1000_init_nvm_params_82571(hw
);
337 rc
= e1000_init_phy_params_82571(hw
);
341 /* tag quad port adapters first, it's used below */
342 switch (pdev
->device
) {
343 case E1000_DEV_ID_82571EB_QUAD_COPPER
:
344 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
345 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP
:
346 case E1000_DEV_ID_82571PT_QUAD_COPPER
:
347 adapter
->flags
|= FLAG_IS_QUAD_PORT
;
348 /* mark the first port */
349 if (global_quad_port_a
== 0)
350 adapter
->flags
|= FLAG_IS_QUAD_PORT_A
;
351 /* Reset for multiple quad port adapters */
352 global_quad_port_a
++;
353 if (global_quad_port_a
== 4)
354 global_quad_port_a
= 0;
360 switch (adapter
->hw
.mac
.type
) {
362 /* these dual ports don't have WoL on port B at all */
363 if (((pdev
->device
== E1000_DEV_ID_82571EB_FIBER
) ||
364 (pdev
->device
== E1000_DEV_ID_82571EB_SERDES
) ||
365 (pdev
->device
== E1000_DEV_ID_82571EB_COPPER
)) &&
367 adapter
->flags
&= ~FLAG_HAS_WOL
;
368 /* quad ports only support WoL on port A */
369 if (adapter
->flags
& FLAG_IS_QUAD_PORT
&&
370 (!(adapter
->flags
& FLAG_IS_QUAD_PORT_A
)))
371 adapter
->flags
&= ~FLAG_HAS_WOL
;
372 /* Does not support WoL on any port */
373 if (pdev
->device
== E1000_DEV_ID_82571EB_SERDES_QUAD
)
374 adapter
->flags
&= ~FLAG_HAS_WOL
;
378 if (pdev
->device
== E1000_DEV_ID_82573L
) {
379 if (e1000_read_nvm(&adapter
->hw
, NVM_INIT_3GIO_3
, 1,
382 if (!(eeprom_data
& NVM_WORD1A_ASPM_MASK
)) {
383 adapter
->flags
|= FLAG_HAS_JUMBO_FRAMES
;
384 adapter
->max_hw_frame_size
= DEFAULT_JUMBO
;
396 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
397 * @hw: pointer to the HW structure
399 * Reads the PHY registers and stores the PHY ID and possibly the PHY
400 * revision in the hardware structure.
402 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
)
404 struct e1000_phy_info
*phy
= &hw
->phy
;
408 switch (hw
->mac
.type
) {
412 * The 82571 firmware may still be configuring the PHY.
413 * In this case, we cannot access the PHY until the
414 * configuration is done. So we explicitly set the
417 phy
->id
= IGP01E1000_I_PHY_ID
;
420 return e1000e_get_phy_id(hw
);
424 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
428 phy
->id
= (u32
)(phy_id
<< 16);
430 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
434 phy
->id
|= (u32
)(phy_id
);
435 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
438 return -E1000_ERR_PHY
;
446 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
447 * @hw: pointer to the HW structure
449 * Acquire the HW semaphore to access the PHY or NVM
451 static s32
e1000_get_hw_semaphore_82571(struct e1000_hw
*hw
)
454 s32 sw_timeout
= hw
->nvm
.word_size
+ 1;
455 s32 fw_timeout
= hw
->nvm
.word_size
+ 1;
459 * If we have timedout 3 times on trying to acquire
460 * the inter-port SMBI semaphore, there is old code
461 * operating on the other port, and it is not
462 * releasing SMBI. Modify the number of times that
463 * we try for the semaphore to interwork with this
466 if (hw
->dev_spec
.e82571
.smb_counter
> 2)
469 /* Get the SW semaphore */
470 while (i
< sw_timeout
) {
472 if (!(swsm
& E1000_SWSM_SMBI
))
479 if (i
== sw_timeout
) {
480 e_dbg("Driver can't access device - SMBI bit is set.\n");
481 hw
->dev_spec
.e82571
.smb_counter
++;
483 /* Get the FW semaphore. */
484 for (i
= 0; i
< fw_timeout
; i
++) {
486 ew32(SWSM
, swsm
| E1000_SWSM_SWESMBI
);
488 /* Semaphore acquired if bit latched */
489 if (er32(SWSM
) & E1000_SWSM_SWESMBI
)
495 if (i
== fw_timeout
) {
496 /* Release semaphores */
497 e1000_put_hw_semaphore_82571(hw
);
498 e_dbg("Driver can't access the NVM\n");
499 return -E1000_ERR_NVM
;
506 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
507 * @hw: pointer to the HW structure
509 * Release hardware semaphore used to access the PHY or NVM
511 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
)
516 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
521 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
522 * @hw: pointer to the HW structure
524 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
525 * Then for non-82573 hardware, set the EEPROM access request bit and wait
526 * for EEPROM access grant bit. If the access grant bit is not set, release
527 * hardware semaphore.
529 static s32
e1000_acquire_nvm_82571(struct e1000_hw
*hw
)
533 ret_val
= e1000_get_hw_semaphore_82571(hw
);
537 switch (hw
->mac
.type
) {
543 ret_val
= e1000e_acquire_nvm(hw
);
548 e1000_put_hw_semaphore_82571(hw
);
554 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
555 * @hw: pointer to the HW structure
557 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
559 static void e1000_release_nvm_82571(struct e1000_hw
*hw
)
561 e1000e_release_nvm(hw
);
562 e1000_put_hw_semaphore_82571(hw
);
566 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
567 * @hw: pointer to the HW structure
568 * @offset: offset within the EEPROM to be written to
569 * @words: number of words to write
570 * @data: 16 bit word(s) to be written to the EEPROM
572 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
574 * If e1000e_update_nvm_checksum is not called after this function, the
575 * EEPROM will most likely contain an invalid checksum.
577 static s32
e1000_write_nvm_82571(struct e1000_hw
*hw
, u16 offset
, u16 words
,
582 switch (hw
->mac
.type
) {
586 ret_val
= e1000_write_nvm_eewr_82571(hw
, offset
, words
, data
);
590 ret_val
= e1000e_write_nvm_spi(hw
, offset
, words
, data
);
593 ret_val
= -E1000_ERR_NVM
;
601 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
602 * @hw: pointer to the HW structure
604 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
605 * up to the checksum. Then calculates the EEPROM checksum and writes the
606 * value to the EEPROM.
608 static s32
e1000_update_nvm_checksum_82571(struct e1000_hw
*hw
)
614 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
619 * If our nvm is an EEPROM, then we're done
620 * otherwise, commit the checksum to the flash NVM.
622 if (hw
->nvm
.type
!= e1000_nvm_flash_hw
)
625 /* Check for pending operations. */
626 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
628 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
632 if (i
== E1000_FLASH_UPDATES
)
633 return -E1000_ERR_NVM
;
635 /* Reset the firmware if using STM opcode. */
636 if ((er32(FLOP
) & 0xFF00) == E1000_STM_OPCODE
) {
638 * The enabling of and the actual reset must be done
639 * in two write cycles.
641 ew32(HICR
, E1000_HICR_FW_RESET_ENABLE
);
643 ew32(HICR
, E1000_HICR_FW_RESET
);
646 /* Commit the write to flash */
647 eecd
= er32(EECD
) | E1000_EECD_FLUPD
;
650 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
652 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
656 if (i
== E1000_FLASH_UPDATES
)
657 return -E1000_ERR_NVM
;
663 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
664 * @hw: pointer to the HW structure
666 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
667 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
669 static s32
e1000_validate_nvm_checksum_82571(struct e1000_hw
*hw
)
671 if (hw
->nvm
.type
== e1000_nvm_flash_hw
)
672 e1000_fix_nvm_checksum_82571(hw
);
674 return e1000e_validate_nvm_checksum_generic(hw
);
678 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
679 * @hw: pointer to the HW structure
680 * @offset: offset within the EEPROM to be written to
681 * @words: number of words to write
682 * @data: 16 bit word(s) to be written to the EEPROM
684 * After checking for invalid values, poll the EEPROM to ensure the previous
685 * command has completed before trying to write the next word. After write
686 * poll for completion.
688 * If e1000e_update_nvm_checksum is not called after this function, the
689 * EEPROM will most likely contain an invalid checksum.
691 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
692 u16 words
, u16
*data
)
694 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
700 * A check for invalid values: offset too large, too many words,
701 * and not enough words.
703 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
705 e_dbg("nvm parameter(s) out of bounds\n");
706 return -E1000_ERR_NVM
;
709 for (i
= 0; i
< words
; i
++) {
710 eewr
= (data
[i
] << E1000_NVM_RW_REG_DATA
) |
711 ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
712 E1000_NVM_RW_REG_START
;
714 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
720 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
729 * e1000_get_cfg_done_82571 - Poll for configuration done
730 * @hw: pointer to the HW structure
732 * Reads the management control register for the config done bit to be set.
734 static s32
e1000_get_cfg_done_82571(struct e1000_hw
*hw
)
736 s32 timeout
= PHY_CFG_TIMEOUT
;
740 E1000_NVM_CFG_DONE_PORT_0
)
746 e_dbg("MNG configuration cycle has not completed.\n");
747 return -E1000_ERR_RESET
;
754 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
755 * @hw: pointer to the HW structure
756 * @active: TRUE to enable LPLU, FALSE to disable
758 * Sets the LPLU D0 state according to the active flag. When activating LPLU
759 * this function also disables smart speed and vice versa. LPLU will not be
760 * activated unless the device autonegotiation advertisement meets standards
761 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
762 * pointer entry point only called by PHY setup routines.
764 static s32
e1000_set_d0_lplu_state_82571(struct e1000_hw
*hw
, bool active
)
766 struct e1000_phy_info
*phy
= &hw
->phy
;
770 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
775 data
|= IGP02E1000_PM_D0_LPLU
;
776 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
780 /* When LPLU is enabled, we should disable SmartSpeed */
781 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
782 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
783 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
787 data
&= ~IGP02E1000_PM_D0_LPLU
;
788 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
790 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
791 * during Dx states where the power conservation is most
792 * important. During driver activity we should enable
793 * SmartSpeed, so performance is maintained.
795 if (phy
->smart_speed
== e1000_smart_speed_on
) {
796 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
801 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
802 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
806 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
807 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
812 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
813 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
824 * e1000_reset_hw_82571 - Reset hardware
825 * @hw: pointer to the HW structure
827 * This resets the hardware into a known state.
829 static s32
e1000_reset_hw_82571(struct e1000_hw
*hw
)
839 * Prevent the PCI-E bus from sticking if there is no TLP connection
840 * on the last TLP read/write transaction when MAC is reset.
842 ret_val
= e1000e_disable_pcie_master(hw
);
844 e_dbg("PCI-E Master disable polling has failed.\n");
846 e_dbg("Masking off all interrupts\n");
847 ew32(IMC
, 0xffffffff);
850 ew32(TCTL
, E1000_TCTL_PSP
);
856 * Must acquire the MDIO ownership before MAC reset.
857 * Ownership defaults to firmware after a reset.
859 switch (hw
->mac
.type
) {
863 extcnf_ctrl
= er32(EXTCNF_CTRL
);
864 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
867 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
868 extcnf_ctrl
= er32(EXTCNF_CTRL
);
870 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
873 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
877 } while (i
< MDIO_OWNERSHIP_TIMEOUT
);
885 e_dbg("Issuing a global reset to MAC\n");
886 ew32(CTRL
, ctrl
| E1000_CTRL_RST
);
888 if (hw
->nvm
.type
== e1000_nvm_flash_hw
) {
890 ctrl_ext
= er32(CTRL_EXT
);
891 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
892 ew32(CTRL_EXT
, ctrl_ext
);
896 ret_val
= e1000e_get_auto_rd_done(hw
);
898 /* We don't want to continue accessing MAC registers. */
902 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
903 * Need to wait for Phy configuration completion before accessing
907 switch (hw
->mac
.type
) {
917 /* Clear any pending interrupt events. */
918 ew32(IMC
, 0xffffffff);
921 if (hw
->mac
.type
== e1000_82571
&&
922 hw
->dev_spec
.e82571
.alt_mac_addr_is_present
)
923 e1000e_set_laa_state_82571(hw
, true);
925 /* Reinitialize the 82571 serdes link state machine */
926 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
927 hw
->mac
.serdes_link_state
= e1000_serdes_link_down
;
933 * e1000_init_hw_82571 - Initialize hardware
934 * @hw: pointer to the HW structure
936 * This inits the hardware readying it for operation.
938 static s32
e1000_init_hw_82571(struct e1000_hw
*hw
)
940 struct e1000_mac_info
*mac
= &hw
->mac
;
944 u16 rar_count
= mac
->rar_entry_count
;
946 e1000_initialize_hw_bits_82571(hw
);
948 /* Initialize identification LED */
949 ret_val
= e1000e_id_led_init(hw
);
951 e_dbg("Error initializing identification LED\n");
955 /* Disabling VLAN filtering */
956 e_dbg("Initializing the IEEE VLAN\n");
957 e1000e_clear_vfta(hw
);
959 /* Setup the receive address. */
961 * If, however, a locally administered address was assigned to the
962 * 82571, we must reserve a RAR for it to work around an issue where
963 * resetting one port will reload the MAC on the other port.
965 if (e1000e_get_laa_state_82571(hw
))
967 e1000e_init_rx_addrs(hw
, rar_count
);
969 /* Zero out the Multicast HASH table */
970 e_dbg("Zeroing the MTA\n");
971 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
972 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
974 /* Setup link and flow control */
975 ret_val
= e1000_setup_link_82571(hw
);
977 /* Set the transmit descriptor write-back policy */
978 reg_data
= er32(TXDCTL(0));
979 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
980 E1000_TXDCTL_FULL_TX_DESC_WB
|
981 E1000_TXDCTL_COUNT_DESC
;
982 ew32(TXDCTL(0), reg_data
);
984 /* ...for both queues. */
989 e1000e_enable_tx_pkt_filtering(hw
);
990 reg_data
= er32(GCR
);
991 reg_data
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
995 reg_data
= er32(TXDCTL(1));
996 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
997 E1000_TXDCTL_FULL_TX_DESC_WB
|
998 E1000_TXDCTL_COUNT_DESC
;
999 ew32(TXDCTL(1), reg_data
);
1004 * Clear all of the statistics registers (clear on read). It is
1005 * important that we do this after we have tried to establish link
1006 * because the symbol error count will increment wildly if there
1009 e1000_clear_hw_cntrs_82571(hw
);
1015 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1016 * @hw: pointer to the HW structure
1018 * Initializes required hardware-dependent bits needed for normal operation.
1020 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
)
1024 /* Transmit Descriptor Control 0 */
1025 reg
= er32(TXDCTL(0));
1027 ew32(TXDCTL(0), reg
);
1029 /* Transmit Descriptor Control 1 */
1030 reg
= er32(TXDCTL(1));
1032 ew32(TXDCTL(1), reg
);
1034 /* Transmit Arbitration Control 0 */
1035 reg
= er32(TARC(0));
1036 reg
&= ~(0xF << 27); /* 30:27 */
1037 switch (hw
->mac
.type
) {
1040 reg
|= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1047 /* Transmit Arbitration Control 1 */
1048 reg
= er32(TARC(1));
1049 switch (hw
->mac
.type
) {
1052 reg
&= ~((1 << 29) | (1 << 30));
1053 reg
|= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1054 if (er32(TCTL
) & E1000_TCTL_MULR
)
1064 /* Device Control */
1065 switch (hw
->mac
.type
) {
1077 /* Extended Device Control */
1078 switch (hw
->mac
.type
) {
1082 reg
= er32(CTRL_EXT
);
1085 ew32(CTRL_EXT
, reg
);
1091 if (hw
->mac
.type
== e1000_82571
) {
1092 reg
= er32(PBA_ECC
);
1093 reg
|= E1000_PBA_ECC_CORR_EN
;
1097 * Workaround for hardware errata.
1098 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1101 if ((hw
->mac
.type
== e1000_82571
) ||
1102 (hw
->mac
.type
== e1000_82572
)) {
1103 reg
= er32(CTRL_EXT
);
1104 reg
&= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN
;
1105 ew32(CTRL_EXT
, reg
);
1109 /* PCI-Ex Control Registers */
1110 switch (hw
->mac
.type
) {
1129 * e1000e_clear_vfta - Clear VLAN filter table
1130 * @hw: pointer to the HW structure
1132 * Clears the register array which contains the VLAN filter table by
1133 * setting all the values to 0.
1135 void e1000e_clear_vfta(struct e1000_hw
*hw
)
1139 u32 vfta_offset
= 0;
1140 u32 vfta_bit_in_reg
= 0;
1142 switch (hw
->mac
.type
) {
1146 if (hw
->mng_cookie
.vlan_id
!= 0) {
1148 * The VFTA is a 4096b bit-field, each identifying
1149 * a single VLAN ID. The following operations
1150 * determine which 32b entry (i.e. offset) into the
1151 * array we want to set the VLAN ID (i.e. bit) of
1152 * the manageability unit.
1154 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
1155 E1000_VFTA_ENTRY_SHIFT
) &
1156 E1000_VFTA_ENTRY_MASK
;
1157 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
1158 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
1164 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
1166 * If the offset we want to clear is the same offset of the
1167 * manageability VLAN ID, then clear all bits except that of
1168 * the manageability unit.
1170 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
1171 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, vfta_value
);
1177 * e1000_check_mng_mode_82574 - Check manageability is enabled
1178 * @hw: pointer to the HW structure
1180 * Reads the NVM Initialization Control Word 2 and returns true
1181 * (>0) if any manageability is enabled, else false (0).
1183 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
)
1187 e1000_read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1, &data
);
1188 return (data
& E1000_NVM_INIT_CTRL2_MNGM
) != 0;
1192 * e1000_led_on_82574 - Turn LED on
1193 * @hw: pointer to the HW structure
1197 static s32
e1000_led_on_82574(struct e1000_hw
*hw
)
1202 ctrl
= hw
->mac
.ledctl_mode2
;
1203 if (!(E1000_STATUS_LU
& er32(STATUS
))) {
1205 * If no link, then turn LED on by setting the invert bit
1206 * for each LED that's "on" (0x0E) in ledctl_mode2.
1208 for (i
= 0; i
< 4; i
++)
1209 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1210 E1000_LEDCTL_MODE_LED_ON
)
1211 ctrl
|= (E1000_LEDCTL_LED0_IVRT
<< (i
* 8));
1219 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1220 * @hw: pointer to the HW structure
1221 * @mc_addr_list: array of multicast addresses to program
1222 * @mc_addr_count: number of multicast addresses to program
1223 * @rar_used_count: the first RAR register free to program
1224 * @rar_count: total number of supported Receive Address Registers
1226 * Updates the Receive Address Registers and Multicast Table Array.
1227 * The caller must have a packed mc_addr_list of multicast addresses.
1228 * The parameter rar_count will usually be hw->mac.rar_entry_count
1229 * unless there are workarounds that change this.
1231 static void e1000_update_mc_addr_list_82571(struct e1000_hw
*hw
,
1237 if (e1000e_get_laa_state_82571(hw
))
1240 e1000e_update_mc_addr_list_generic(hw
, mc_addr_list
, mc_addr_count
,
1241 rar_used_count
, rar_count
);
1245 * e1000_setup_link_82571 - Setup flow control and link settings
1246 * @hw: pointer to the HW structure
1248 * Determines which flow control settings to use, then configures flow
1249 * control. Calls the appropriate media-specific link configuration
1250 * function. Assuming the adapter has a valid link partner, a valid link
1251 * should be established. Assumes the hardware has previously been reset
1252 * and the transmitter and receiver are not enabled.
1254 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
)
1257 * 82573 does not have a word in the NVM to determine
1258 * the default flow control setting, so we explicitly
1261 switch (hw
->mac
.type
) {
1265 if (hw
->fc
.requested_mode
== e1000_fc_default
)
1266 hw
->fc
.requested_mode
= e1000_fc_full
;
1272 return e1000e_setup_link(hw
);
1276 * e1000_setup_copper_link_82571 - Configure copper link settings
1277 * @hw: pointer to the HW structure
1279 * Configures the link for auto-neg or forced speed and duplex. Then we check
1280 * for link, once link is established calls to configure collision distance
1281 * and flow control are called.
1283 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
)
1290 ctrl
|= E1000_CTRL_SLU
;
1291 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1294 switch (hw
->phy
.type
) {
1297 ret_val
= e1000e_copper_link_setup_m88(hw
);
1299 case e1000_phy_igp_2
:
1300 ret_val
= e1000e_copper_link_setup_igp(hw
);
1301 /* Setup activity LED */
1302 led_ctrl
= er32(LEDCTL
);
1303 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1304 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1305 ew32(LEDCTL
, led_ctrl
);
1308 return -E1000_ERR_PHY
;
1315 ret_val
= e1000e_setup_copper_link(hw
);
1321 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1322 * @hw: pointer to the HW structure
1324 * Configures collision distance and flow control for fiber and serdes links.
1325 * Upon successful setup, poll for link.
1327 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
)
1329 switch (hw
->mac
.type
) {
1333 * If SerDes loopback mode is entered, there is no form
1334 * of reset to take the adapter out of that mode. So we
1335 * have to explicitly take the adapter out of loopback
1336 * mode. This prevents drivers from twiddling their thumbs
1337 * if another tool failed to take it out of loopback mode.
1339 ew32(SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1345 return e1000e_setup_fiber_serdes_link(hw
);
1349 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1350 * @hw: pointer to the HW structure
1352 * Checks for link up on the hardware. If link is not up and we have
1353 * a signal, then we need to force link up.
1355 static s32
e1000_check_for_serdes_link_82571(struct e1000_hw
*hw
)
1357 struct e1000_mac_info
*mac
= &hw
->mac
;
1364 status
= er32(STATUS
);
1367 if ((rxcw
& E1000_RXCW_SYNCH
) && !(rxcw
& E1000_RXCW_IV
)) {
1369 /* Receiver is synchronized with no invalid bits. */
1370 switch (mac
->serdes_link_state
) {
1371 case e1000_serdes_link_autoneg_complete
:
1372 if (!(status
& E1000_STATUS_LU
)) {
1374 * We have lost link, retry autoneg before
1375 * reporting link failure
1377 mac
->serdes_link_state
=
1378 e1000_serdes_link_autoneg_progress
;
1379 e_dbg("AN_UP -> AN_PROG\n");
1383 case e1000_serdes_link_forced_up
:
1385 * If we are receiving /C/ ordered sets, re-enable
1386 * auto-negotiation in the TXCW register and disable
1387 * forced link in the Device Control register in an
1388 * attempt to auto-negotiate with our link partner.
1390 if (rxcw
& E1000_RXCW_C
) {
1391 /* Enable autoneg, and unforce link up */
1392 ew32(TXCW
, mac
->txcw
);
1394 (ctrl
& ~E1000_CTRL_SLU
));
1395 mac
->serdes_link_state
=
1396 e1000_serdes_link_autoneg_progress
;
1397 e_dbg("FORCED_UP -> AN_PROG\n");
1401 case e1000_serdes_link_autoneg_progress
:
1403 * If the LU bit is set in the STATUS register,
1404 * autoneg has completed sucessfully. If not,
1405 * try foring the link because the far end may be
1406 * available but not capable of autonegotiation.
1408 if (status
& E1000_STATUS_LU
) {
1409 mac
->serdes_link_state
=
1410 e1000_serdes_link_autoneg_complete
;
1411 e_dbg("AN_PROG -> AN_UP\n");
1414 * Disable autoneg, force link up and
1415 * full duplex, and change state to forced
1418 (mac
->txcw
& ~E1000_TXCW_ANE
));
1419 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
1422 /* Configure Flow Control after link up. */
1424 e1000e_config_fc_after_link_up(hw
);
1426 e_dbg("Error config flow control\n");
1429 mac
->serdes_link_state
=
1430 e1000_serdes_link_forced_up
;
1431 e_dbg("AN_PROG -> FORCED_UP\n");
1433 mac
->serdes_has_link
= true;
1436 case e1000_serdes_link_down
:
1438 /* The link was down but the receiver has now gained
1439 * valid sync, so lets see if we can bring the link
1441 ew32(TXCW
, mac
->txcw
);
1443 (ctrl
& ~E1000_CTRL_SLU
));
1444 mac
->serdes_link_state
=
1445 e1000_serdes_link_autoneg_progress
;
1446 e_dbg("DOWN -> AN_PROG\n");
1450 if (!(rxcw
& E1000_RXCW_SYNCH
)) {
1451 mac
->serdes_has_link
= false;
1452 mac
->serdes_link_state
= e1000_serdes_link_down
;
1453 e_dbg("ANYSTATE -> DOWN\n");
1456 * We have sync, and can tolerate one
1457 * invalid (IV) codeword before declaring
1458 * link down, so reread to look again
1462 if (rxcw
& E1000_RXCW_IV
) {
1463 mac
->serdes_link_state
= e1000_serdes_link_down
;
1464 mac
->serdes_has_link
= false;
1465 e_dbg("ANYSTATE -> DOWN\n");
1474 * e1000_valid_led_default_82571 - Verify a valid default LED config
1475 * @hw: pointer to the HW structure
1476 * @data: pointer to the NVM (EEPROM)
1478 * Read the EEPROM for the current default LED configuration. If the
1479 * LED configuration is not valid, set to a valid LED configuration.
1481 static s32
e1000_valid_led_default_82571(struct e1000_hw
*hw
, u16
*data
)
1485 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1487 e_dbg("NVM Read Error\n");
1491 switch (hw
->mac
.type
) {
1495 if (*data
== ID_LED_RESERVED_F746
)
1496 *data
= ID_LED_DEFAULT_82573
;
1499 if (*data
== ID_LED_RESERVED_0000
||
1500 *data
== ID_LED_RESERVED_FFFF
)
1501 *data
= ID_LED_DEFAULT
;
1509 * e1000e_get_laa_state_82571 - Get locally administered address state
1510 * @hw: pointer to the HW structure
1512 * Retrieve and return the current locally administered address state.
1514 bool e1000e_get_laa_state_82571(struct e1000_hw
*hw
)
1516 if (hw
->mac
.type
!= e1000_82571
)
1519 return hw
->dev_spec
.e82571
.laa_is_present
;
1523 * e1000e_set_laa_state_82571 - Set locally administered address state
1524 * @hw: pointer to the HW structure
1525 * @state: enable/disable locally administered address
1527 * Enable/Disable the current locally administers address state.
1529 void e1000e_set_laa_state_82571(struct e1000_hw
*hw
, bool state
)
1531 if (hw
->mac
.type
!= e1000_82571
)
1534 hw
->dev_spec
.e82571
.laa_is_present
= state
;
1536 /* If workaround is activated... */
1539 * Hold a copy of the LAA in RAR[14] This is done so that
1540 * between the time RAR[0] gets clobbered and the time it
1541 * gets fixed, the actual LAA is in one of the RARs and no
1542 * incoming packets directed to this port are dropped.
1543 * Eventually the LAA will be in RAR[0] and RAR[14].
1545 e1000e_rar_set(hw
, hw
->mac
.addr
, hw
->mac
.rar_entry_count
- 1);
1549 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1550 * @hw: pointer to the HW structure
1552 * Verifies that the EEPROM has completed the update. After updating the
1553 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1554 * the checksum fix is not implemented, we need to set the bit and update
1555 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1556 * we need to return bad checksum.
1558 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
)
1560 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1564 if (nvm
->type
!= e1000_nvm_flash_hw
)
1568 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1569 * 10h-12h. Checksum may need to be fixed.
1571 ret_val
= e1000_read_nvm(hw
, 0x10, 1, &data
);
1575 if (!(data
& 0x10)) {
1577 * Read 0x23 and check bit 15. This bit is a 1
1578 * when the checksum has already been fixed. If
1579 * the checksum is still wrong and this bit is a
1580 * 1, we need to return bad checksum. Otherwise,
1581 * we need to set this bit to a 1 and update the
1584 ret_val
= e1000_read_nvm(hw
, 0x23, 1, &data
);
1588 if (!(data
& 0x8000)) {
1590 ret_val
= e1000_write_nvm(hw
, 0x23, 1, &data
);
1593 ret_val
= e1000e_update_nvm_checksum(hw
);
1601 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1602 * @hw: pointer to the HW structure
1604 * Clears the hardware counters by reading the counter registers.
1606 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
)
1610 e1000e_clear_hw_cntrs_base(hw
);
1613 temp
= er32(PRC127
);
1614 temp
= er32(PRC255
);
1615 temp
= er32(PRC511
);
1616 temp
= er32(PRC1023
);
1617 temp
= er32(PRC1522
);
1619 temp
= er32(PTC127
);
1620 temp
= er32(PTC255
);
1621 temp
= er32(PTC511
);
1622 temp
= er32(PTC1023
);
1623 temp
= er32(PTC1522
);
1625 temp
= er32(ALGNERRC
);
1626 temp
= er32(RXERRC
);
1628 temp
= er32(CEXTERR
);
1630 temp
= er32(TSCTFC
);
1632 temp
= er32(MGTPRC
);
1633 temp
= er32(MGTPDC
);
1634 temp
= er32(MGTPTC
);
1637 temp
= er32(ICRXOC
);
1639 temp
= er32(ICRXPTC
);
1640 temp
= er32(ICRXATC
);
1641 temp
= er32(ICTXPTC
);
1642 temp
= er32(ICTXATC
);
1643 temp
= er32(ICTXQEC
);
1644 temp
= er32(ICTXQMTC
);
1645 temp
= er32(ICRXDMTC
);
1648 static struct e1000_mac_operations e82571_mac_ops
= {
1649 /* .check_mng_mode: mac type dependent */
1650 /* .check_for_link: media type dependent */
1651 .id_led_init
= e1000e_id_led_init
,
1652 .cleanup_led
= e1000e_cleanup_led_generic
,
1653 .clear_hw_cntrs
= e1000_clear_hw_cntrs_82571
,
1654 .get_bus_info
= e1000e_get_bus_info_pcie
,
1655 /* .get_link_up_info: media type dependent */
1656 /* .led_on: mac type dependent */
1657 .led_off
= e1000e_led_off_generic
,
1658 .update_mc_addr_list
= e1000_update_mc_addr_list_82571
,
1659 .reset_hw
= e1000_reset_hw_82571
,
1660 .init_hw
= e1000_init_hw_82571
,
1661 .setup_link
= e1000_setup_link_82571
,
1662 /* .setup_physical_interface: media type dependent */
1663 .setup_led
= e1000e_setup_led_generic
,
1666 static struct e1000_phy_operations e82_phy_ops_igp
= {
1667 .acquire
= e1000_get_hw_semaphore_82571
,
1668 .check_reset_block
= e1000e_check_reset_block_generic
,
1670 .force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
,
1671 .get_cfg_done
= e1000_get_cfg_done_82571
,
1672 .get_cable_length
= e1000e_get_cable_length_igp_2
,
1673 .get_info
= e1000e_get_phy_info_igp
,
1674 .read_reg
= e1000e_read_phy_reg_igp
,
1675 .release
= e1000_put_hw_semaphore_82571
,
1676 .reset
= e1000e_phy_hw_reset_generic
,
1677 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1678 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1679 .write_reg
= e1000e_write_phy_reg_igp
,
1680 .cfg_on_link_up
= NULL
,
1683 static struct e1000_phy_operations e82_phy_ops_m88
= {
1684 .acquire
= e1000_get_hw_semaphore_82571
,
1685 .check_reset_block
= e1000e_check_reset_block_generic
,
1686 .commit
= e1000e_phy_sw_reset
,
1687 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1688 .get_cfg_done
= e1000e_get_cfg_done
,
1689 .get_cable_length
= e1000e_get_cable_length_m88
,
1690 .get_info
= e1000e_get_phy_info_m88
,
1691 .read_reg
= e1000e_read_phy_reg_m88
,
1692 .release
= e1000_put_hw_semaphore_82571
,
1693 .reset
= e1000e_phy_hw_reset_generic
,
1694 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1695 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1696 .write_reg
= e1000e_write_phy_reg_m88
,
1697 .cfg_on_link_up
= NULL
,
1700 static struct e1000_phy_operations e82_phy_ops_bm
= {
1701 .acquire
= e1000_get_hw_semaphore_82571
,
1702 .check_reset_block
= e1000e_check_reset_block_generic
,
1703 .commit
= e1000e_phy_sw_reset
,
1704 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1705 .get_cfg_done
= e1000e_get_cfg_done
,
1706 .get_cable_length
= e1000e_get_cable_length_m88
,
1707 .get_info
= e1000e_get_phy_info_m88
,
1708 .read_reg
= e1000e_read_phy_reg_bm2
,
1709 .release
= e1000_put_hw_semaphore_82571
,
1710 .reset
= e1000e_phy_hw_reset_generic
,
1711 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1712 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1713 .write_reg
= e1000e_write_phy_reg_bm2
,
1714 .cfg_on_link_up
= NULL
,
1717 static struct e1000_nvm_operations e82571_nvm_ops
= {
1718 .acquire
= e1000_acquire_nvm_82571
,
1719 .read
= e1000e_read_nvm_eerd
,
1720 .release
= e1000_release_nvm_82571
,
1721 .update
= e1000_update_nvm_checksum_82571
,
1722 .valid_led_default
= e1000_valid_led_default_82571
,
1723 .validate
= e1000_validate_nvm_checksum_82571
,
1724 .write
= e1000_write_nvm_82571
,
1727 struct e1000_info e1000_82571_info
= {
1729 .flags
= FLAG_HAS_HW_VLAN_FILTER
1730 | FLAG_HAS_JUMBO_FRAMES
1732 | FLAG_APME_IN_CTRL3
1733 | FLAG_RX_CSUM_ENABLED
1734 | FLAG_HAS_CTRLEXT_ON_LOAD
1735 | FLAG_HAS_SMART_POWER_DOWN
1736 | FLAG_RESET_OVERWRITES_LAA
/* errata */
1737 | FLAG_TARC_SPEED_MODE_BIT
/* errata */
1738 | FLAG_APME_CHECK_PORT_B
,
1740 .max_hw_frame_size
= DEFAULT_JUMBO
,
1741 .get_variants
= e1000_get_variants_82571
,
1742 .mac_ops
= &e82571_mac_ops
,
1743 .phy_ops
= &e82_phy_ops_igp
,
1744 .nvm_ops
= &e82571_nvm_ops
,
1747 struct e1000_info e1000_82572_info
= {
1749 .flags
= FLAG_HAS_HW_VLAN_FILTER
1750 | FLAG_HAS_JUMBO_FRAMES
1752 | FLAG_APME_IN_CTRL3
1753 | FLAG_RX_CSUM_ENABLED
1754 | FLAG_HAS_CTRLEXT_ON_LOAD
1755 | FLAG_TARC_SPEED_MODE_BIT
, /* errata */
1757 .max_hw_frame_size
= DEFAULT_JUMBO
,
1758 .get_variants
= e1000_get_variants_82571
,
1759 .mac_ops
= &e82571_mac_ops
,
1760 .phy_ops
= &e82_phy_ops_igp
,
1761 .nvm_ops
= &e82571_nvm_ops
,
1764 struct e1000_info e1000_82573_info
= {
1766 .flags
= FLAG_HAS_HW_VLAN_FILTER
1767 | FLAG_HAS_JUMBO_FRAMES
1769 | FLAG_APME_IN_CTRL3
1770 | FLAG_RX_CSUM_ENABLED
1771 | FLAG_HAS_SMART_POWER_DOWN
1774 | FLAG_HAS_SWSM_ON_LOAD
,
1776 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
1777 .get_variants
= e1000_get_variants_82571
,
1778 .mac_ops
= &e82571_mac_ops
,
1779 .phy_ops
= &e82_phy_ops_m88
,
1780 .nvm_ops
= &e82571_nvm_ops
,
1783 struct e1000_info e1000_82574_info
= {
1785 .flags
= FLAG_HAS_HW_VLAN_FILTER
1787 | FLAG_HAS_JUMBO_FRAMES
1789 | FLAG_APME_IN_CTRL3
1790 | FLAG_RX_CSUM_ENABLED
1791 | FLAG_HAS_SMART_POWER_DOWN
1793 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1795 .max_hw_frame_size
= DEFAULT_JUMBO
,
1796 .get_variants
= e1000_get_variants_82571
,
1797 .mac_ops
= &e82571_mac_ops
,
1798 .phy_ops
= &e82_phy_ops_bm
,
1799 .nvm_ops
= &e82571_nvm_ops
,
1802 struct e1000_info e1000_82583_info
= {
1804 .flags
= FLAG_HAS_HW_VLAN_FILTER
1806 | FLAG_APME_IN_CTRL3
1807 | FLAG_RX_CSUM_ENABLED
1808 | FLAG_HAS_SMART_POWER_DOWN
1810 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1812 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
1813 .get_variants
= e1000_get_variants_82571
,
1814 .mac_ops
= &e82571_mac_ops
,
1815 .phy_ops
= &e82_phy_ops_bm
,
1816 .nvm_ops
= &e82571_nvm_ops
,