1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
114 #define E1000_ICH_RAR_ENTRIES 7
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
143 /* Strapping Option Register - RO */
144 #define E1000_STRAP 0x0000C
145 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
146 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
148 /* OEM Bits Phy Register */
149 #define HV_OEM_BITS PHY_REG(768, 25)
150 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
151 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
152 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
154 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
155 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
157 /* KMRN Mode Control */
158 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
159 #define HV_KMRN_MDIO_SLOW 0x0400
161 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
162 /* Offset 04h HSFSTS */
163 union ich8_hws_flash_status
{
165 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
166 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
167 u16 dael
:1; /* bit 2 Direct Access error Log */
168 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
169 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
170 u16 reserved1
:2; /* bit 13:6 Reserved */
171 u16 reserved2
:6; /* bit 13:6 Reserved */
172 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
173 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
178 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
179 /* Offset 06h FLCTL */
180 union ich8_hws_flash_ctrl
{
181 struct ich8_hsflctl
{
182 u16 flcgo
:1; /* 0 Flash Cycle Go */
183 u16 flcycle
:2; /* 2:1 Flash Cycle */
184 u16 reserved
:5; /* 7:3 Reserved */
185 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
186 u16 flockdn
:6; /* 15:10 Reserved */
191 /* ICH Flash Region Access Permissions */
192 union ich8_hws_flash_regacc
{
194 u32 grra
:8; /* 0:7 GbE region Read Access */
195 u32 grwa
:8; /* 8:15 GbE region Write Access */
196 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
197 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
202 /* ICH Flash Protected Region */
203 union ich8_flash_protected_range
{
205 u32 base
:13; /* 0:12 Protected Range Base */
206 u32 reserved1
:2; /* 13:14 Reserved */
207 u32 rpe
:1; /* 15 Read Protection Enable */
208 u32 limit
:13; /* 16:28 Protected Range Limit */
209 u32 reserved2
:2; /* 29:30 Reserved */
210 u32 wpe
:1; /* 31 Write Protection Enable */
215 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
218 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
219 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
220 u32 offset
, u8 byte
);
221 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
223 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
225 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
227 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
228 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
229 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
230 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
231 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
232 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
233 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
234 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
235 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
236 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
237 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
238 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
240 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
241 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
242 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
);
243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
);
244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
);
245 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
);
246 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
);
248 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
250 return readw(hw
->flash_address
+ reg
);
253 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
255 return readl(hw
->flash_address
+ reg
);
258 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
260 writew(val
, hw
->flash_address
+ reg
);
263 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
265 writel(val
, hw
->flash_address
+ reg
);
268 #define er16flash(reg) __er16flash(hw, (reg))
269 #define er32flash(reg) __er32flash(hw, (reg))
270 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
271 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
274 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
275 * @hw: pointer to the HW structure
277 * Initialize family-specific PHY parameters and function pointers.
279 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
281 struct e1000_phy_info
*phy
= &hw
->phy
;
286 phy
->reset_delay_us
= 100;
288 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
289 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
290 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
291 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
292 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
293 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
294 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
295 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
296 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
299 * The MAC-PHY interconnect may still be in SMBus mode
300 * after Sx->S0. If the manageability engine (ME) is
301 * disabled, then toggle the LANPHYPC Value bit to force
302 * the interconnect to PCIe mode.
305 if (!(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
307 ctrl
|= E1000_CTRL_LANPHYPC_OVERRIDE
;
308 ctrl
&= ~E1000_CTRL_LANPHYPC_VALUE
;
311 ctrl
&= ~E1000_CTRL_LANPHYPC_OVERRIDE
;
316 * Gate automatic PHY configuration by hardware on
319 if (hw
->mac
.type
== e1000_pch2lan
)
320 e1000_gate_hw_phy_config_ich8lan(hw
, true);
324 * Reset the PHY before any access to it. Doing so, ensures that
325 * the PHY is in a known good state before we read/write PHY registers.
326 * The generic reset is sufficient here, because we haven't determined
329 ret_val
= e1000e_phy_hw_reset_generic(hw
);
333 /* Ungate automatic PHY configuration on non-managed 82579 */
334 if ((hw
->mac
.type
== e1000_pch2lan
) &&
335 !(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
337 e1000_gate_hw_phy_config_ich8lan(hw
, false);
340 phy
->id
= e1000_phy_unknown
;
341 ret_val
= e1000e_get_phy_id(hw
);
344 if ((phy
->id
== 0) || (phy
->id
== PHY_REVISION_MASK
)) {
346 * In case the PHY needs to be in mdio slow mode (eg. 82577),
347 * set slow mode and try to get the PHY id again.
349 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
352 ret_val
= e1000e_get_phy_id(hw
);
356 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
359 case e1000_phy_82577
:
360 case e1000_phy_82579
:
361 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
362 phy
->ops
.force_speed_duplex
=
363 e1000_phy_force_speed_duplex_82577
;
364 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
365 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
366 phy
->ops
.commit
= e1000e_phy_sw_reset
;
368 case e1000_phy_82578
:
369 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
370 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
371 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
372 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
375 ret_val
= -E1000_ERR_PHY
;
384 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
385 * @hw: pointer to the HW structure
387 * Initialize family-specific PHY parameters and function pointers.
389 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
391 struct e1000_phy_info
*phy
= &hw
->phy
;
396 phy
->reset_delay_us
= 100;
398 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
399 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
402 * We may need to do this twice - once for IGP and if that fails,
403 * we'll set BM func pointers and try again
405 ret_val
= e1000e_determine_phy_address(hw
);
407 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
408 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
409 ret_val
= e1000e_determine_phy_address(hw
);
411 e_dbg("Cannot determine PHY addr. Erroring out\n");
417 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
420 ret_val
= e1000e_get_phy_id(hw
);
427 case IGP03E1000_E_PHY_ID
:
428 phy
->type
= e1000_phy_igp_3
;
429 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
430 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
431 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
432 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
433 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
434 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
437 case IFE_PLUS_E_PHY_ID
:
439 phy
->type
= e1000_phy_ife
;
440 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
441 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
442 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
443 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
445 case BME1000_E_PHY_ID
:
446 phy
->type
= e1000_phy_bm
;
447 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
448 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
449 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
450 phy
->ops
.commit
= e1000e_phy_sw_reset
;
451 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
452 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
453 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
456 return -E1000_ERR_PHY
;
464 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
465 * @hw: pointer to the HW structure
467 * Initialize family-specific NVM parameters and function
470 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
472 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
473 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
474 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
477 /* Can't read flash registers if the register set isn't mapped. */
478 if (!hw
->flash_address
) {
479 e_dbg("ERROR: Flash registers not mapped\n");
480 return -E1000_ERR_CONFIG
;
483 nvm
->type
= e1000_nvm_flash_sw
;
485 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
488 * sector_X_addr is a "sector"-aligned address (4096 bytes)
489 * Add 1 to sector_end_addr since this sector is included in
492 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
493 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
495 /* flash_base_addr is byte-aligned */
496 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
499 * find total size of the NVM, then cut in half since the total
500 * size represents two separate NVM banks.
502 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
503 << FLASH_SECTOR_ADDR_SHIFT
;
504 nvm
->flash_bank_size
/= 2;
505 /* Adjust to word count */
506 nvm
->flash_bank_size
/= sizeof(u16
);
508 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
510 /* Clear shadow ram */
511 for (i
= 0; i
< nvm
->word_size
; i
++) {
512 dev_spec
->shadow_ram
[i
].modified
= false;
513 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
520 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
521 * @hw: pointer to the HW structure
523 * Initialize family-specific MAC parameters and function
526 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
528 struct e1000_hw
*hw
= &adapter
->hw
;
529 struct e1000_mac_info
*mac
= &hw
->mac
;
531 /* Set media type function pointer */
532 hw
->phy
.media_type
= e1000_media_type_copper
;
534 /* Set mta register count */
535 mac
->mta_reg_count
= 32;
536 /* Set rar entry count */
537 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
538 if (mac
->type
== e1000_ich8lan
)
539 mac
->rar_entry_count
--;
541 mac
->has_fwsm
= true;
542 /* ARC subsystem not supported */
543 mac
->arc_subsystem_valid
= false;
544 /* Adaptive IFS supported */
545 mac
->adaptive_ifs
= true;
552 /* check management mode */
553 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_ich8lan
;
555 mac
->ops
.id_led_init
= e1000e_id_led_init
;
557 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
559 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
560 /* turn on/off LED */
561 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
562 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
566 /* check management mode */
567 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_pchlan
;
569 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
571 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
573 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
574 /* turn on/off LED */
575 mac
->ops
.led_on
= e1000_led_on_pchlan
;
576 mac
->ops
.led_off
= e1000_led_off_pchlan
;
582 /* Enable PCS Lock-loss workaround for ICH8 */
583 if (mac
->type
== e1000_ich8lan
)
584 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
586 /* Gate automatic PHY configuration by hardware on managed 82579 */
587 if ((mac
->type
== e1000_pch2lan
) &&
588 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
589 e1000_gate_hw_phy_config_ich8lan(hw
, true);
595 * e1000_set_eee_pchlan - Enable/disable EEE support
596 * @hw: pointer to the HW structure
598 * Enable/disable EEE based on setting in dev_spec structure. The bits in
599 * the LPI Control register will remain set only if/when link is up.
601 static s32
e1000_set_eee_pchlan(struct e1000_hw
*hw
)
606 if (hw
->phy
.type
!= e1000_phy_82579
)
609 ret_val
= e1e_rphy(hw
, I82579_LPI_CTRL
, &phy_reg
);
613 if (hw
->dev_spec
.ich8lan
.eee_disable
)
614 phy_reg
&= ~I82579_LPI_CTRL_ENABLE_MASK
;
616 phy_reg
|= I82579_LPI_CTRL_ENABLE_MASK
;
618 ret_val
= e1e_wphy(hw
, I82579_LPI_CTRL
, phy_reg
);
624 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
625 * @hw: pointer to the HW structure
627 * Checks to see of the link status of the hardware has changed. If a
628 * change in link status has been detected, then we read the PHY registers
629 * to get the current speed/duplex if link exists.
631 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
633 struct e1000_mac_info
*mac
= &hw
->mac
;
638 * We only want to go out to the PHY registers to see if Auto-Neg
639 * has completed and/or if our link status has changed. The
640 * get_link_status flag is set upon receiving a Link Status
641 * Change or Rx Sequence Error interrupt.
643 if (!mac
->get_link_status
) {
649 * First we want to see if the MII Status Register reports
650 * link. If so, then we want to get the current speed/duplex
653 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
657 if (hw
->mac
.type
== e1000_pchlan
) {
658 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
664 goto out
; /* No link detected */
666 mac
->get_link_status
= false;
668 if (hw
->phy
.type
== e1000_phy_82578
) {
669 ret_val
= e1000_link_stall_workaround_hv(hw
);
674 if (hw
->mac
.type
== e1000_pch2lan
) {
675 ret_val
= e1000_k1_workaround_lv(hw
);
681 * Check if there was DownShift, must be checked
682 * immediately after link-up
684 e1000e_check_downshift(hw
);
686 /* Enable/Disable EEE after link up */
687 ret_val
= e1000_set_eee_pchlan(hw
);
692 * If we are forcing speed/duplex, then we simply return since
693 * we have already determined whether we have link or not.
696 ret_val
= -E1000_ERR_CONFIG
;
701 * Auto-Neg is enabled. Auto Speed Detection takes care
702 * of MAC speed/duplex configuration. So we only need to
703 * configure Collision Distance in the MAC.
705 e1000e_config_collision_dist(hw
);
708 * Configure Flow Control now that Auto-Neg has completed.
709 * First, we need to restore the desired flow control
710 * settings because we may have had to re-autoneg with a
711 * different link partner.
713 ret_val
= e1000e_config_fc_after_link_up(hw
);
715 e_dbg("Error configuring flow control\n");
721 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
723 struct e1000_hw
*hw
= &adapter
->hw
;
726 rc
= e1000_init_mac_params_ich8lan(adapter
);
730 rc
= e1000_init_nvm_params_ich8lan(hw
);
734 switch (hw
->mac
.type
) {
738 rc
= e1000_init_phy_params_ich8lan(hw
);
742 rc
= e1000_init_phy_params_pchlan(hw
);
750 if (adapter
->hw
.phy
.type
== e1000_phy_ife
) {
751 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
752 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
755 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
756 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
757 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
759 /* Disable EEE by default until IEEE802.3az spec is finalized */
760 if (adapter
->flags2
& FLAG2_HAS_EEE
)
761 adapter
->hw
.dev_spec
.ich8lan
.eee_disable
= true;
766 static DEFINE_MUTEX(nvm_mutex
);
769 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
770 * @hw: pointer to the HW structure
772 * Acquires the mutex for performing NVM operations.
774 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw
*hw
)
776 mutex_lock(&nvm_mutex
);
782 * e1000_release_nvm_ich8lan - Release NVM mutex
783 * @hw: pointer to the HW structure
785 * Releases the mutex used while performing NVM operations.
787 static void e1000_release_nvm_ich8lan(struct e1000_hw
*hw
)
789 mutex_unlock(&nvm_mutex
);
792 static DEFINE_MUTEX(swflag_mutex
);
795 * e1000_acquire_swflag_ich8lan - Acquire software control flag
796 * @hw: pointer to the HW structure
798 * Acquires the software control flag for performing PHY and select
801 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
803 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
806 mutex_lock(&swflag_mutex
);
809 extcnf_ctrl
= er32(EXTCNF_CTRL
);
810 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
818 e_dbg("SW/FW/HW has locked the resource for too long.\n");
819 ret_val
= -E1000_ERR_CONFIG
;
823 timeout
= SW_FLAG_TIMEOUT
;
825 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
826 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
829 extcnf_ctrl
= er32(EXTCNF_CTRL
);
830 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
838 e_dbg("Failed to acquire the semaphore.\n");
839 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
840 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
841 ret_val
= -E1000_ERR_CONFIG
;
847 mutex_unlock(&swflag_mutex
);
853 * e1000_release_swflag_ich8lan - Release software control flag
854 * @hw: pointer to the HW structure
856 * Releases the software control flag for performing PHY and select
859 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
863 extcnf_ctrl
= er32(EXTCNF_CTRL
);
864 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
865 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
867 mutex_unlock(&swflag_mutex
);
871 * e1000_check_mng_mode_ich8lan - Checks management mode
872 * @hw: pointer to the HW structure
874 * This checks if the adapter has any manageability enabled.
875 * This is a function pointer entry point only called by read/write
876 * routines for the PHY and NVM parts.
878 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
883 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
884 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
885 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
889 * e1000_check_mng_mode_pchlan - Checks management mode
890 * @hw: pointer to the HW structure
892 * This checks if the adapter has iAMT enabled.
893 * This is a function pointer entry point only called by read/write
894 * routines for the PHY and NVM parts.
896 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
)
901 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
902 (fwsm
& (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
906 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
907 * @hw: pointer to the HW structure
909 * Checks if firmware is blocking the reset of the PHY.
910 * This is a function pointer entry point only called by
913 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
919 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
923 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
924 * @hw: pointer to the HW structure
926 * Assumes semaphore already acquired.
929 static s32
e1000_write_smbus_addr(struct e1000_hw
*hw
)
932 u32 strap
= er32(STRAP
);
935 strap
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
937 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, &phy_data
);
941 phy_data
&= ~HV_SMB_ADDR_MASK
;
942 phy_data
|= (strap
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
);
943 phy_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
944 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, phy_data
);
951 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
952 * @hw: pointer to the HW structure
954 * SW should configure the LCD from the NVM extended configuration region
955 * as a workaround for certain parts.
957 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
959 struct e1000_phy_info
*phy
= &hw
->phy
;
960 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
962 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
965 * Initialize the PHY from the NVM on ICH platforms. This
966 * is needed due to an issue where the NVM configuration is
967 * not properly autoloaded after power transitions.
968 * Therefore, after each PHY reset, we will load the
969 * configuration data out of the NVM manually.
971 switch (hw
->mac
.type
) {
973 if (phy
->type
!= e1000_phy_igp_3
)
976 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_AMT
) ||
977 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_C
)) {
978 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
984 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
990 ret_val
= hw
->phy
.ops
.acquire(hw
);
994 data
= er32(FEXTNVM
);
995 if (!(data
& sw_cfg_mask
))
999 * Make sure HW does not configure LCD from PHY
1000 * extended configuration before SW configuration
1002 data
= er32(EXTCNF_CTRL
);
1003 if (!(hw
->mac
.type
== e1000_pch2lan
)) {
1004 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
1008 cnf_size
= er32(EXTCNF_SIZE
);
1009 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
1010 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
1014 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
1015 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
1017 if ((!(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
) &&
1018 (hw
->mac
.type
== e1000_pchlan
)) ||
1019 (hw
->mac
.type
== e1000_pch2lan
)) {
1021 * HW configures the SMBus address and LEDs when the
1022 * OEM and LCD Write Enable bits are set in the NVM.
1023 * When both NVM bits are cleared, SW will configure
1026 ret_val
= e1000_write_smbus_addr(hw
);
1030 data
= er32(LEDCTL
);
1031 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_LED_CONFIG
,
1037 /* Configure LCD from extended configuration region. */
1039 /* cnf_base_addr is in DWORD */
1040 word_addr
= (u16
)(cnf_base_addr
<< 1);
1042 for (i
= 0; i
< cnf_size
; i
++) {
1043 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1,
1048 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
1053 /* Save off the PHY page for future writes. */
1054 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
1055 phy_page
= reg_data
;
1059 reg_addr
&= PHY_REG_MASK
;
1060 reg_addr
|= phy_page
;
1062 ret_val
= phy
->ops
.write_reg_locked(hw
, (u32
)reg_addr
,
1069 hw
->phy
.ops
.release(hw
);
1074 * e1000_k1_gig_workaround_hv - K1 Si workaround
1075 * @hw: pointer to the HW structure
1076 * @link: link up bool flag
1078 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1079 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1080 * If link is down, the function will restore the default K1 setting located
1083 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
1087 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
1089 if (hw
->mac
.type
!= e1000_pchlan
)
1092 /* Wrap the whole flow with the sw flag */
1093 ret_val
= hw
->phy
.ops
.acquire(hw
);
1097 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1099 if (hw
->phy
.type
== e1000_phy_82578
) {
1100 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, BM_CS_STATUS
,
1105 status_reg
&= BM_CS_STATUS_LINK_UP
|
1106 BM_CS_STATUS_RESOLVED
|
1107 BM_CS_STATUS_SPEED_MASK
;
1109 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
1110 BM_CS_STATUS_RESOLVED
|
1111 BM_CS_STATUS_SPEED_1000
))
1115 if (hw
->phy
.type
== e1000_phy_82577
) {
1116 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, HV_M_STATUS
,
1121 status_reg
&= HV_M_STATUS_LINK_UP
|
1122 HV_M_STATUS_AUTONEG_COMPLETE
|
1123 HV_M_STATUS_SPEED_MASK
;
1125 if (status_reg
== (HV_M_STATUS_LINK_UP
|
1126 HV_M_STATUS_AUTONEG_COMPLETE
|
1127 HV_M_STATUS_SPEED_1000
))
1131 /* Link stall fix for link up */
1132 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, PHY_REG(770, 19),
1138 /* Link stall fix for link down */
1139 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, PHY_REG(770, 19),
1145 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
1148 hw
->phy
.ops
.release(hw
);
1154 * e1000_configure_k1_ich8lan - Configure K1 power state
1155 * @hw: pointer to the HW structure
1156 * @enable: K1 state to configure
1158 * Configure the K1 power state based on the provided parameter.
1159 * Assumes semaphore already acquired.
1161 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1163 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
1171 ret_val
= e1000e_read_kmrn_reg_locked(hw
,
1172 E1000_KMRNCTRLSTA_K1_CONFIG
,
1178 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
1180 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
1182 ret_val
= e1000e_write_kmrn_reg_locked(hw
,
1183 E1000_KMRNCTRLSTA_K1_CONFIG
,
1189 ctrl_ext
= er32(CTRL_EXT
);
1190 ctrl_reg
= er32(CTRL
);
1192 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1193 reg
|= E1000_CTRL_FRCSPD
;
1196 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
1198 ew32(CTRL
, ctrl_reg
);
1199 ew32(CTRL_EXT
, ctrl_ext
);
1207 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1208 * @hw: pointer to the HW structure
1209 * @d0_state: boolean if entering d0 or d3 device state
1211 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1212 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1213 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1215 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
1221 if ((hw
->mac
.type
!= e1000_pch2lan
) && (hw
->mac
.type
!= e1000_pchlan
))
1224 ret_val
= hw
->phy
.ops
.acquire(hw
);
1228 if (!(hw
->mac
.type
== e1000_pch2lan
)) {
1229 mac_reg
= er32(EXTCNF_CTRL
);
1230 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
1234 mac_reg
= er32(FEXTNVM
);
1235 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
1238 mac_reg
= er32(PHY_CTRL
);
1240 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, HV_OEM_BITS
, &oem_reg
);
1244 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
1247 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
1248 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1250 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
1251 oem_reg
|= HV_OEM_BITS_LPLU
;
1253 if (mac_reg
& E1000_PHY_CTRL_NOND0A_GBE_DISABLE
)
1254 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1256 if (mac_reg
& E1000_PHY_CTRL_NOND0A_LPLU
)
1257 oem_reg
|= HV_OEM_BITS_LPLU
;
1259 /* Restart auto-neg to activate the bits */
1260 if (!e1000_check_reset_block(hw
))
1261 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1262 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, HV_OEM_BITS
, oem_reg
);
1265 hw
->phy
.ops
.release(hw
);
1272 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1273 * @hw: pointer to the HW structure
1275 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
)
1280 ret_val
= e1e_rphy(hw
, HV_KMRN_MODE_CTRL
, &data
);
1284 data
|= HV_KMRN_MDIO_SLOW
;
1286 ret_val
= e1e_wphy(hw
, HV_KMRN_MODE_CTRL
, data
);
1292 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1293 * done after every PHY reset.
1295 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1300 if (hw
->mac
.type
!= e1000_pchlan
)
1303 /* Set MDIO slow mode before any other MDIO access */
1304 if (hw
->phy
.type
== e1000_phy_82577
) {
1305 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
1310 if (((hw
->phy
.type
== e1000_phy_82577
) &&
1311 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
1312 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
1313 /* Disable generation of early preamble */
1314 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
1318 /* Preamble tuning for SSC */
1319 ret_val
= e1e_wphy(hw
, PHY_REG(770, 16), 0xA204);
1324 if (hw
->phy
.type
== e1000_phy_82578
) {
1326 * Return registers to default by doing a soft reset then
1327 * writing 0x3140 to the control register.
1329 if (hw
->phy
.revision
< 2) {
1330 e1000e_phy_sw_reset(hw
);
1331 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, 0x3140);
1336 ret_val
= hw
->phy
.ops
.acquire(hw
);
1341 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
1342 hw
->phy
.ops
.release(hw
);
1347 * Configure the K1 Si workaround during phy reset assuming there is
1348 * link so that it disables K1 if link is in 1Gbps.
1350 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
1354 /* Workaround for link disconnects on a busy hub in half duplex */
1355 ret_val
= hw
->phy
.ops
.acquire(hw
);
1358 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
,
1359 PHY_REG(BM_PORT_CTRL_PAGE
, 17),
1363 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
,
1364 PHY_REG(BM_PORT_CTRL_PAGE
, 17),
1367 hw
->phy
.ops
.release(hw
);
1373 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1374 * @hw: pointer to the HW structure
1376 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw
*hw
)
1381 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1382 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1383 mac_reg
= er32(RAL(i
));
1384 e1e_wphy(hw
, BM_RAR_L(i
), (u16
)(mac_reg
& 0xFFFF));
1385 e1e_wphy(hw
, BM_RAR_M(i
), (u16
)((mac_reg
>> 16) & 0xFFFF));
1386 mac_reg
= er32(RAH(i
));
1387 e1e_wphy(hw
, BM_RAR_H(i
), (u16
)(mac_reg
& 0xFFFF));
1388 e1e_wphy(hw
, BM_RAR_CTRL(i
), (u16
)((mac_reg
>> 16) & 0x8000));
1392 static u32
e1000_calc_rx_da_crc(u8 mac
[])
1394 u32 poly
= 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1395 u32 i
, j
, mask
, crc
;
1398 for (i
= 0; i
< 6; i
++) {
1400 for (j
= 8; j
> 0; j
--) {
1401 mask
= (crc
& 1) * (-1);
1402 crc
= (crc
>> 1) ^ (poly
& mask
);
1409 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1411 * @hw: pointer to the HW structure
1412 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1414 s32
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw
, bool enable
)
1421 if (hw
->mac
.type
!= e1000_pch2lan
)
1424 /* disable Rx path while enabling/disabling workaround */
1425 e1e_rphy(hw
, PHY_REG(769, 20), &phy_reg
);
1426 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
| (1 << 14));
1432 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1433 * SHRAL/H) and initial CRC values to the MAC
1435 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1436 u8 mac_addr
[ETH_ALEN
] = {0};
1437 u32 addr_high
, addr_low
;
1439 addr_high
= er32(RAH(i
));
1440 if (!(addr_high
& E1000_RAH_AV
))
1442 addr_low
= er32(RAL(i
));
1443 mac_addr
[0] = (addr_low
& 0xFF);
1444 mac_addr
[1] = ((addr_low
>> 8) & 0xFF);
1445 mac_addr
[2] = ((addr_low
>> 16) & 0xFF);
1446 mac_addr
[3] = ((addr_low
>> 24) & 0xFF);
1447 mac_addr
[4] = (addr_high
& 0xFF);
1448 mac_addr
[5] = ((addr_high
>> 8) & 0xFF);
1451 e1000_calc_rx_da_crc(mac_addr
));
1454 /* Write Rx addresses to the PHY */
1455 e1000_copy_rx_addrs_to_phy_ich8lan(hw
);
1457 /* Enable jumbo frame workaround in the MAC */
1458 mac_reg
= er32(FFLT_DBG
);
1459 mac_reg
&= ~(1 << 14);
1460 mac_reg
|= (7 << 15);
1461 ew32(FFLT_DBG
, mac_reg
);
1463 mac_reg
= er32(RCTL
);
1464 mac_reg
|= E1000_RCTL_SECRC
;
1465 ew32(RCTL
, mac_reg
);
1467 ret_val
= e1000e_read_kmrn_reg(hw
,
1468 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1472 ret_val
= e1000e_write_kmrn_reg(hw
,
1473 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1477 ret_val
= e1000e_read_kmrn_reg(hw
,
1478 E1000_KMRNCTRLSTA_HD_CTRL
,
1482 data
&= ~(0xF << 8);
1484 ret_val
= e1000e_write_kmrn_reg(hw
,
1485 E1000_KMRNCTRLSTA_HD_CTRL
,
1490 /* Enable jumbo frame workaround in the PHY */
1491 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
1492 data
&= ~(0x7F << 5);
1493 data
|= (0x37 << 5);
1494 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
1497 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
1499 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
1502 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
1503 data
&= ~(0x3FF << 2);
1504 data
|= (0x1A << 2);
1505 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
1508 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0xFE00);
1511 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
1512 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
| (1 << 10));
1516 /* Write MAC register values back to h/w defaults */
1517 mac_reg
= er32(FFLT_DBG
);
1518 mac_reg
&= ~(0xF << 14);
1519 ew32(FFLT_DBG
, mac_reg
);
1521 mac_reg
= er32(RCTL
);
1522 mac_reg
&= ~E1000_RCTL_SECRC
;
1523 ew32(RCTL
, mac_reg
);
1525 ret_val
= e1000e_read_kmrn_reg(hw
,
1526 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1530 ret_val
= e1000e_write_kmrn_reg(hw
,
1531 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1535 ret_val
= e1000e_read_kmrn_reg(hw
,
1536 E1000_KMRNCTRLSTA_HD_CTRL
,
1540 data
&= ~(0xF << 8);
1542 ret_val
= e1000e_write_kmrn_reg(hw
,
1543 E1000_KMRNCTRLSTA_HD_CTRL
,
1548 /* Write PHY register values back to h/w defaults */
1549 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
1550 data
&= ~(0x7F << 5);
1551 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
1554 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
1556 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
1559 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
1560 data
&= ~(0x3FF << 2);
1562 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
1565 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0x7E00);
1568 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
1569 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
& ~(1 << 10));
1574 /* re-enable Rx path after enabling/disabling workaround */
1575 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
& ~(1 << 14));
1582 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1583 * done after every PHY reset.
1585 static s32
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1589 if (hw
->mac
.type
!= e1000_pch2lan
)
1592 /* Set MDIO slow mode before any other MDIO access */
1593 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
1600 * e1000_k1_gig_workaround_lv - K1 Si workaround
1601 * @hw: pointer to the HW structure
1603 * Workaround to set the K1 beacon duration for 82579 parts
1605 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
)
1611 if (hw
->mac
.type
!= e1000_pch2lan
)
1614 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1615 ret_val
= e1e_rphy(hw
, HV_M_STATUS
, &status_reg
);
1619 if ((status_reg
& (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
))
1620 == (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
)) {
1621 mac_reg
= er32(FEXTNVM4
);
1622 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
1624 if (status_reg
& HV_M_STATUS_SPEED_1000
)
1625 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_8USEC
;
1627 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_16USEC
;
1629 ew32(FEXTNVM4
, mac_reg
);
1637 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1638 * @hw: pointer to the HW structure
1639 * @gate: boolean set to true to gate, false to ungate
1641 * Gate/ungate the automatic PHY configuration via hardware; perform
1642 * the configuration via software instead.
1644 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
)
1648 if (hw
->mac
.type
!= e1000_pch2lan
)
1651 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1654 extcnf_ctrl
|= E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
1656 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
1658 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1663 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1664 * @hw: pointer to the HW structure
1666 * Check the appropriate indication the MAC has finished configuring the
1667 * PHY after a software reset.
1669 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
1671 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
1673 /* Wait for basic configuration completes before proceeding */
1675 data
= er32(STATUS
);
1676 data
&= E1000_STATUS_LAN_INIT_DONE
;
1678 } while ((!data
) && --loop
);
1681 * If basic configuration is incomplete before the above loop
1682 * count reaches 0, loading the configuration from NVM will
1683 * leave the PHY in a bad state possibly resulting in no link.
1686 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1688 /* Clear the Init Done bit for the next init event */
1689 data
= er32(STATUS
);
1690 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
1695 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1696 * @hw: pointer to the HW structure
1698 static s32
e1000_post_phy_reset_ich8lan(struct e1000_hw
*hw
)
1703 if (e1000_check_reset_block(hw
))
1706 /* Allow time for h/w to get to quiescent state after reset */
1709 /* Perform any necessary post-reset workarounds */
1710 switch (hw
->mac
.type
) {
1712 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
1717 ret_val
= e1000_lv_phy_workarounds_ich8lan(hw
);
1725 /* Dummy read to clear the phy wakeup bit after lcd reset */
1726 if (hw
->mac
.type
>= e1000_pchlan
)
1727 e1e_rphy(hw
, BM_WUC
, ®
);
1729 /* Configure the LCD with the extended configuration region in NVM */
1730 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
1734 /* Configure the LCD with the OEM bits in NVM */
1735 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
1737 /* Ungate automatic PHY configuration on non-managed 82579 */
1738 if ((hw
->mac
.type
== e1000_pch2lan
) &&
1739 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
1741 e1000_gate_hw_phy_config_ich8lan(hw
, false);
1749 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1750 * @hw: pointer to the HW structure
1753 * This is a function pointer entry point called by drivers
1754 * or other shared routines.
1756 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
1760 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1761 if ((hw
->mac
.type
== e1000_pch2lan
) &&
1762 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
1763 e1000_gate_hw_phy_config_ich8lan(hw
, true);
1765 ret_val
= e1000e_phy_hw_reset_generic(hw
);
1769 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
1776 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1777 * @hw: pointer to the HW structure
1778 * @active: true to enable LPLU, false to disable
1780 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1781 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1782 * the phy speed. This function will manually set the LPLU bit and restart
1783 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1784 * since it configures the same bit.
1786 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
1791 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
1796 oem_reg
|= HV_OEM_BITS_LPLU
;
1798 oem_reg
&= ~HV_OEM_BITS_LPLU
;
1800 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1801 ret_val
= e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
1808 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1809 * @hw: pointer to the HW structure
1810 * @active: true to enable LPLU, false to disable
1812 * Sets the LPLU D0 state according to the active flag. When
1813 * activating LPLU this function also disables smart speed
1814 * and vice versa. LPLU will not be activated unless the
1815 * device autonegotiation advertisement meets standards of
1816 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1817 * This is a function pointer entry point only called by
1818 * PHY setup routines.
1820 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1822 struct e1000_phy_info
*phy
= &hw
->phy
;
1827 if (phy
->type
== e1000_phy_ife
)
1830 phy_ctrl
= er32(PHY_CTRL
);
1833 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
1834 ew32(PHY_CTRL
, phy_ctrl
);
1836 if (phy
->type
!= e1000_phy_igp_3
)
1840 * Call gig speed drop workaround on LPLU before accessing
1843 if (hw
->mac
.type
== e1000_ich8lan
)
1844 e1000e_gig_downshift_workaround_ich8lan(hw
);
1846 /* When LPLU is enabled, we should disable SmartSpeed */
1847 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1848 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1849 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1853 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
1854 ew32(PHY_CTRL
, phy_ctrl
);
1856 if (phy
->type
!= e1000_phy_igp_3
)
1860 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1861 * during Dx states where the power conservation is most
1862 * important. During driver activity we should enable
1863 * SmartSpeed, so performance is maintained.
1865 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1866 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1871 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1872 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1876 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1877 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1882 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1883 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1894 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1895 * @hw: pointer to the HW structure
1896 * @active: true to enable LPLU, false to disable
1898 * Sets the LPLU D3 state according to the active flag. When
1899 * activating LPLU this function also disables smart speed
1900 * and vice versa. LPLU will not be activated unless the
1901 * device autonegotiation advertisement meets standards of
1902 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1903 * This is a function pointer entry point only called by
1904 * PHY setup routines.
1906 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1908 struct e1000_phy_info
*phy
= &hw
->phy
;
1913 phy_ctrl
= er32(PHY_CTRL
);
1916 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
1917 ew32(PHY_CTRL
, phy_ctrl
);
1919 if (phy
->type
!= e1000_phy_igp_3
)
1923 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1924 * during Dx states where the power conservation is most
1925 * important. During driver activity we should enable
1926 * SmartSpeed, so performance is maintained.
1928 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1929 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1934 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1935 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1939 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1940 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1945 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1946 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1951 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1952 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1953 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1954 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
1955 ew32(PHY_CTRL
, phy_ctrl
);
1957 if (phy
->type
!= e1000_phy_igp_3
)
1961 * Call gig speed drop workaround on LPLU before accessing
1964 if (hw
->mac
.type
== e1000_ich8lan
)
1965 e1000e_gig_downshift_workaround_ich8lan(hw
);
1967 /* When LPLU is enabled, we should disable SmartSpeed */
1968 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1972 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1973 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1980 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1981 * @hw: pointer to the HW structure
1982 * @bank: pointer to the variable that returns the active bank
1984 * Reads signature byte from the NVM using the flash access registers.
1985 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1987 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
1990 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1991 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
1992 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
1996 switch (hw
->mac
.type
) {
2000 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
2001 E1000_EECD_SEC1VAL_VALID_MASK
) {
2002 if (eecd
& E1000_EECD_SEC1VAL
)
2009 e_dbg("Unable to determine valid NVM bank via EEC - "
2010 "reading flash signature\n");
2013 /* set bank to 0 in case flash read fails */
2017 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
2021 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2022 E1000_ICH_NVM_SIG_VALUE
) {
2028 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
2033 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2034 E1000_ICH_NVM_SIG_VALUE
) {
2039 e_dbg("ERROR: No valid NVM bank present\n");
2040 return -E1000_ERR_NVM
;
2047 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2048 * @hw: pointer to the HW structure
2049 * @offset: The offset (in bytes) of the word(s) to read.
2050 * @words: Size of data to read in words
2051 * @data: Pointer to the word(s) to read at offset.
2053 * Reads a word(s) from the NVM using the flash access registers.
2055 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2058 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2059 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2065 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2067 e_dbg("nvm parameter(s) out of bounds\n");
2068 ret_val
= -E1000_ERR_NVM
;
2072 nvm
->ops
.acquire(hw
);
2074 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2076 e_dbg("Could not detect valid bank, assuming bank 0\n");
2080 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
2081 act_offset
+= offset
;
2084 for (i
= 0; i
< words
; i
++) {
2085 if ((dev_spec
->shadow_ram
) &&
2086 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
2087 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
2089 ret_val
= e1000_read_flash_word_ich8lan(hw
,
2098 nvm
->ops
.release(hw
);
2102 e_dbg("NVM read error: %d\n", ret_val
);
2108 * e1000_flash_cycle_init_ich8lan - Initialize flash
2109 * @hw: pointer to the HW structure
2111 * This function does initial flash setup so that a new read/write/erase cycle
2114 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
2116 union ich8_hws_flash_status hsfsts
;
2117 s32 ret_val
= -E1000_ERR_NVM
;
2120 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2122 /* Check if the flash descriptor is valid */
2123 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
2124 e_dbg("Flash descriptor invalid. "
2125 "SW Sequencing must be used.\n");
2126 return -E1000_ERR_NVM
;
2129 /* Clear FCERR and DAEL in hw status by writing 1 */
2130 hsfsts
.hsf_status
.flcerr
= 1;
2131 hsfsts
.hsf_status
.dael
= 1;
2133 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2136 * Either we should have a hardware SPI cycle in progress
2137 * bit to check against, in order to start a new cycle or
2138 * FDONE bit should be changed in the hardware so that it
2139 * is 1 after hardware reset, which can then be used as an
2140 * indication whether a cycle is in progress or has been
2144 if (hsfsts
.hsf_status
.flcinprog
== 0) {
2146 * There is no cycle running at present,
2147 * so we can start a cycle.
2148 * Begin by setting Flash Cycle Done.
2150 hsfsts
.hsf_status
.flcdone
= 1;
2151 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2155 * Otherwise poll for sometime so the current
2156 * cycle has a chance to end before giving up.
2158 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
2159 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
2160 if (hsfsts
.hsf_status
.flcinprog
== 0) {
2168 * Successful in waiting for previous cycle to timeout,
2169 * now set the Flash Cycle Done.
2171 hsfsts
.hsf_status
.flcdone
= 1;
2172 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2174 e_dbg("Flash controller busy, cannot get access\n");
2182 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2183 * @hw: pointer to the HW structure
2184 * @timeout: maximum time to wait for completion
2186 * This function starts a flash cycle and waits for its completion.
2188 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
2190 union ich8_hws_flash_ctrl hsflctl
;
2191 union ich8_hws_flash_status hsfsts
;
2192 s32 ret_val
= -E1000_ERR_NVM
;
2195 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2196 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2197 hsflctl
.hsf_ctrl
.flcgo
= 1;
2198 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2200 /* wait till FDONE bit is set to 1 */
2202 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2203 if (hsfsts
.hsf_status
.flcdone
== 1)
2206 } while (i
++ < timeout
);
2208 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
2215 * e1000_read_flash_word_ich8lan - Read word from flash
2216 * @hw: pointer to the HW structure
2217 * @offset: offset to data location
2218 * @data: pointer to the location for storing the data
2220 * Reads the flash word at offset into data. Offset is converted
2221 * to bytes before read.
2223 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2226 /* Must convert offset into bytes. */
2229 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
2233 * e1000_read_flash_byte_ich8lan - Read byte from flash
2234 * @hw: pointer to the HW structure
2235 * @offset: The offset of the byte to read.
2236 * @data: Pointer to a byte to store the value read.
2238 * Reads a single byte from the NVM using the flash access registers.
2240 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2246 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
2256 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2257 * @hw: pointer to the HW structure
2258 * @offset: The offset (in bytes) of the byte or word to read.
2259 * @size: Size of data to read, 1=byte 2=word
2260 * @data: Pointer to the word to store the value read.
2262 * Reads a byte or word from the NVM using the flash access registers.
2264 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2267 union ich8_hws_flash_status hsfsts
;
2268 union ich8_hws_flash_ctrl hsflctl
;
2269 u32 flash_linear_addr
;
2271 s32 ret_val
= -E1000_ERR_NVM
;
2274 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2275 return -E1000_ERR_NVM
;
2277 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2278 hw
->nvm
.flash_base_addr
;
2283 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2287 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2288 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2289 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
2290 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
2291 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2293 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2295 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2296 ICH_FLASH_READ_COMMAND_TIMEOUT
);
2299 * Check if FCERR is set to 1, if set to 1, clear it
2300 * and try the whole sequence a few more times, else
2301 * read in (shift in) the Flash Data0, the order is
2302 * least significant byte first msb to lsb
2305 flash_data
= er32flash(ICH_FLASH_FDATA0
);
2307 *data
= (u8
)(flash_data
& 0x000000FF);
2308 } else if (size
== 2) {
2309 *data
= (u16
)(flash_data
& 0x0000FFFF);
2314 * If we've gotten here, then things are probably
2315 * completely hosed, but if the error condition is
2316 * detected, it won't hurt to give it another try...
2317 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2319 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2320 if (hsfsts
.hsf_status
.flcerr
== 1) {
2321 /* Repeat for some time before giving up. */
2323 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
2324 e_dbg("Timeout error - flash cycle "
2325 "did not complete.\n");
2329 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2335 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2336 * @hw: pointer to the HW structure
2337 * @offset: The offset (in bytes) of the word(s) to write.
2338 * @words: Size of data to write in words
2339 * @data: Pointer to the word(s) to write at offset.
2341 * Writes a byte or word to the NVM using the flash access registers.
2343 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2346 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2347 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2350 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2352 e_dbg("nvm parameter(s) out of bounds\n");
2353 return -E1000_ERR_NVM
;
2356 nvm
->ops
.acquire(hw
);
2358 for (i
= 0; i
< words
; i
++) {
2359 dev_spec
->shadow_ram
[offset
+i
].modified
= true;
2360 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
2363 nvm
->ops
.release(hw
);
2369 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2370 * @hw: pointer to the HW structure
2372 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2373 * which writes the checksum to the shadow ram. The changes in the shadow
2374 * ram are then committed to the EEPROM by processing each bank at a time
2375 * checking for the modified bit and writing only the pending changes.
2376 * After a successful commit, the shadow ram is cleared and is ready for
2379 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
2381 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2382 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2383 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
2387 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
2391 if (nvm
->type
!= e1000_nvm_flash_sw
)
2394 nvm
->ops
.acquire(hw
);
2397 * We're writing to the opposite bank so if we're on bank 1,
2398 * write to bank 0 etc. We also need to erase the segment that
2399 * is going to be written
2401 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2403 e_dbg("Could not detect valid bank, assuming bank 0\n");
2408 new_bank_offset
= nvm
->flash_bank_size
;
2409 old_bank_offset
= 0;
2410 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
2414 old_bank_offset
= nvm
->flash_bank_size
;
2415 new_bank_offset
= 0;
2416 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
2421 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2423 * Determine whether to write the value stored
2424 * in the other NVM bank or a modified value stored
2427 if (dev_spec
->shadow_ram
[i
].modified
) {
2428 data
= dev_spec
->shadow_ram
[i
].value
;
2430 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
2438 * If the word is 0x13, then make sure the signature bits
2439 * (15:14) are 11b until the commit has completed.
2440 * This will allow us to write 10b which indicates the
2441 * signature is valid. We want to do this after the write
2442 * has completed so that we don't mark the segment valid
2443 * while the write is still in progress
2445 if (i
== E1000_ICH_NVM_SIG_WORD
)
2446 data
|= E1000_ICH_NVM_SIG_MASK
;
2448 /* Convert offset to bytes. */
2449 act_offset
= (i
+ new_bank_offset
) << 1;
2452 /* Write the bytes to the new bank. */
2453 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2460 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2468 * Don't bother writing the segment valid bits if sector
2469 * programming failed.
2472 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2473 e_dbg("Flash commit failed.\n");
2478 * Finally validate the new segment by setting bit 15:14
2479 * to 10b in word 0x13 , this can be done without an
2480 * erase as well since these bits are 11 to start with
2481 * and we need to change bit 14 to 0b
2483 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
2484 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
2489 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2496 * And invalidate the previously valid segment by setting
2497 * its signature word (0x13) high_byte to 0b. This can be
2498 * done without an erase because flash erase sets all bits
2499 * to 1's. We can write 1's to 0's without an erase
2501 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
2502 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
2506 /* Great! Everything worked, we can now clear the cached entries. */
2507 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2508 dev_spec
->shadow_ram
[i
].modified
= false;
2509 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
2513 nvm
->ops
.release(hw
);
2516 * Reload the EEPROM, or else modifications will not appear
2517 * until after the next adapter reset.
2520 e1000e_reload_nvm(hw
);
2526 e_dbg("NVM update error: %d\n", ret_val
);
2532 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2533 * @hw: pointer to the HW structure
2535 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2536 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2537 * calculated, in which case we need to calculate the checksum and set bit 6.
2539 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
2545 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2546 * needs to be fixed. This bit is an indication that the NVM
2547 * was prepared by OEM software and did not calculate the
2548 * checksum...a likely scenario.
2550 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
2554 if ((data
& 0x40) == 0) {
2556 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
2559 ret_val
= e1000e_update_nvm_checksum(hw
);
2564 return e1000e_validate_nvm_checksum_generic(hw
);
2568 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2569 * @hw: pointer to the HW structure
2571 * To prevent malicious write/erase of the NVM, set it to be read-only
2572 * so that the hardware ignores all write/erase cycles of the NVM via
2573 * the flash control registers. The shadow-ram copy of the NVM will
2574 * still be updated, however any updates to this copy will not stick
2575 * across driver reloads.
2577 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
2579 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2580 union ich8_flash_protected_range pr0
;
2581 union ich8_hws_flash_status hsfsts
;
2584 nvm
->ops
.acquire(hw
);
2586 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
2588 /* Write-protect GbE Sector of NVM */
2589 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
2590 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
2591 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
2592 pr0
.range
.wpe
= true;
2593 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
2596 * Lock down a subset of GbE Flash Control Registers, e.g.
2597 * PR0 to prevent the write-protection from being lifted.
2598 * Once FLOCKDN is set, the registers protected by it cannot
2599 * be written until FLOCKDN is cleared by a hardware reset.
2601 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2602 hsfsts
.hsf_status
.flockdn
= true;
2603 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2605 nvm
->ops
.release(hw
);
2609 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2610 * @hw: pointer to the HW structure
2611 * @offset: The offset (in bytes) of the byte/word to read.
2612 * @size: Size of data to read, 1=byte 2=word
2613 * @data: The byte(s) to write to the NVM.
2615 * Writes one/two bytes to the NVM using the flash access registers.
2617 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2620 union ich8_hws_flash_status hsfsts
;
2621 union ich8_hws_flash_ctrl hsflctl
;
2622 u32 flash_linear_addr
;
2627 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
2628 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2629 return -E1000_ERR_NVM
;
2631 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2632 hw
->nvm
.flash_base_addr
;
2637 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2641 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2642 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2643 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
2644 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
2645 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2647 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2650 flash_data
= (u32
)data
& 0x00FF;
2652 flash_data
= (u32
)data
;
2654 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
2657 * check if FCERR is set to 1 , if set to 1, clear it
2658 * and try the whole sequence a few more times else done
2660 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2661 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
2666 * If we're here, then things are most likely
2667 * completely hosed, but if the error condition
2668 * is detected, it won't hurt to give it another
2669 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2671 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2672 if (hsfsts
.hsf_status
.flcerr
== 1)
2673 /* Repeat for some time before giving up. */
2675 if (hsfsts
.hsf_status
.flcdone
== 0) {
2676 e_dbg("Timeout error - flash cycle "
2677 "did not complete.");
2680 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2686 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2687 * @hw: pointer to the HW structure
2688 * @offset: The index of the byte to read.
2689 * @data: The byte to write to the NVM.
2691 * Writes a single byte to the NVM using the flash access registers.
2693 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2696 u16 word
= (u16
)data
;
2698 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
2702 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2703 * @hw: pointer to the HW structure
2704 * @offset: The offset of the byte to write.
2705 * @byte: The byte to write to the NVM.
2707 * Writes a single byte to the NVM using the flash access registers.
2708 * Goes through a retry algorithm before giving up.
2710 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
2711 u32 offset
, u8 byte
)
2714 u16 program_retries
;
2716 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2720 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
2721 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
2723 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2727 if (program_retries
== 100)
2728 return -E1000_ERR_NVM
;
2734 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2735 * @hw: pointer to the HW structure
2736 * @bank: 0 for first bank, 1 for second bank, etc.
2738 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2739 * bank N is 4096 * N + flash_reg_addr.
2741 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
2743 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2744 union ich8_hws_flash_status hsfsts
;
2745 union ich8_hws_flash_ctrl hsflctl
;
2746 u32 flash_linear_addr
;
2747 /* bank size is in 16bit words - adjust to bytes */
2748 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
2751 s32 j
, iteration
, sector_size
;
2753 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2756 * Determine HW Sector size: Read BERASE bits of hw flash status
2758 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2759 * consecutive sectors. The start index for the nth Hw sector
2760 * can be calculated as = bank * 4096 + n * 256
2761 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2762 * The start index for the nth Hw sector can be calculated
2764 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2765 * (ich9 only, otherwise error condition)
2766 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2768 switch (hsfsts
.hsf_status
.berasesz
) {
2770 /* Hw sector size 256 */
2771 sector_size
= ICH_FLASH_SEG_SIZE_256
;
2772 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
2775 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
2779 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
2783 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
2787 return -E1000_ERR_NVM
;
2790 /* Start with the base address, then add the sector offset. */
2791 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
2792 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
2794 for (j
= 0; j
< iteration
; j
++) {
2797 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2802 * Write a value 11 (block Erase) in Flash
2803 * Cycle field in hw flash control
2805 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2806 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
2807 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2810 * Write the last 24 bits of an index within the
2811 * block into Flash Linear address field in Flash
2814 flash_linear_addr
+= (j
* sector_size
);
2815 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2817 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2818 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
2823 * Check if FCERR is set to 1. If 1,
2824 * clear it and try the whole sequence
2825 * a few more times else Done
2827 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2828 if (hsfsts
.hsf_status
.flcerr
== 1)
2829 /* repeat for some time before giving up */
2831 else if (hsfsts
.hsf_status
.flcdone
== 0)
2833 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
2840 * e1000_valid_led_default_ich8lan - Set the default LED settings
2841 * @hw: pointer to the HW structure
2842 * @data: Pointer to the LED settings
2844 * Reads the LED default settings from the NVM to data. If the NVM LED
2845 * settings is all 0's or F's, set the LED default to a valid LED default
2848 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
2852 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
2854 e_dbg("NVM Read Error\n");
2858 if (*data
== ID_LED_RESERVED_0000
||
2859 *data
== ID_LED_RESERVED_FFFF
)
2860 *data
= ID_LED_DEFAULT_ICH8LAN
;
2866 * e1000_id_led_init_pchlan - store LED configurations
2867 * @hw: pointer to the HW structure
2869 * PCH does not control LEDs via the LEDCTL register, rather it uses
2870 * the PHY LED configuration register.
2872 * PCH also does not have an "always on" or "always off" mode which
2873 * complicates the ID feature. Instead of using the "on" mode to indicate
2874 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2875 * use "link_up" mode. The LEDs will still ID on request if there is no
2876 * link based on logic in e1000_led_[on|off]_pchlan().
2878 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
2880 struct e1000_mac_info
*mac
= &hw
->mac
;
2882 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
2883 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
2884 u16 data
, i
, temp
, shift
;
2886 /* Get default ID LED modes */
2887 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
2891 mac
->ledctl_default
= er32(LEDCTL
);
2892 mac
->ledctl_mode1
= mac
->ledctl_default
;
2893 mac
->ledctl_mode2
= mac
->ledctl_default
;
2895 for (i
= 0; i
< 4; i
++) {
2896 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
2899 case ID_LED_ON1_DEF2
:
2900 case ID_LED_ON1_ON2
:
2901 case ID_LED_ON1_OFF2
:
2902 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2903 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
2905 case ID_LED_OFF1_DEF2
:
2906 case ID_LED_OFF1_ON2
:
2907 case ID_LED_OFF1_OFF2
:
2908 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2909 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
2916 case ID_LED_DEF1_ON2
:
2917 case ID_LED_ON1_ON2
:
2918 case ID_LED_OFF1_ON2
:
2919 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2920 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
2922 case ID_LED_DEF1_OFF2
:
2923 case ID_LED_ON1_OFF2
:
2924 case ID_LED_OFF1_OFF2
:
2925 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2926 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
2939 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2940 * @hw: pointer to the HW structure
2942 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2943 * register, so the the bus width is hard coded.
2945 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
2947 struct e1000_bus_info
*bus
= &hw
->bus
;
2950 ret_val
= e1000e_get_bus_info_pcie(hw
);
2953 * ICH devices are "PCI Express"-ish. They have
2954 * a configuration space, but do not contain
2955 * PCI Express Capability registers, so bus width
2956 * must be hardcoded.
2958 if (bus
->width
== e1000_bus_width_unknown
)
2959 bus
->width
= e1000_bus_width_pcie_x1
;
2965 * e1000_reset_hw_ich8lan - Reset the hardware
2966 * @hw: pointer to the HW structure
2968 * Does a full reset of the hardware which includes a reset of the PHY and
2971 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
2973 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2979 * Prevent the PCI-E bus from sticking if there is no TLP connection
2980 * on the last TLP read/write transaction when MAC is reset.
2982 ret_val
= e1000e_disable_pcie_master(hw
);
2984 e_dbg("PCI-E Master disable polling has failed.\n");
2986 e_dbg("Masking off all interrupts\n");
2987 ew32(IMC
, 0xffffffff);
2990 * Disable the Transmit and Receive units. Then delay to allow
2991 * any pending transactions to complete before we hit the MAC
2992 * with the global reset.
2995 ew32(TCTL
, E1000_TCTL_PSP
);
3000 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3001 if (hw
->mac
.type
== e1000_ich8lan
) {
3002 /* Set Tx and Rx buffer allocation to 8k apiece. */
3003 ew32(PBA
, E1000_PBA_8K
);
3004 /* Set Packet Buffer Size to 16k. */
3005 ew32(PBS
, E1000_PBS_16K
);
3008 if (hw
->mac
.type
== e1000_pchlan
) {
3009 /* Save the NVM K1 bit setting*/
3010 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, ®
);
3014 if (reg
& E1000_NVM_K1_ENABLE
)
3015 dev_spec
->nvm_k1_enabled
= true;
3017 dev_spec
->nvm_k1_enabled
= false;
3022 if (!e1000_check_reset_block(hw
)) {
3024 * Full-chip reset requires MAC and PHY reset at the same
3025 * time to make sure the interface between MAC and the
3026 * external PHY is reset.
3028 ctrl
|= E1000_CTRL_PHY_RST
;
3031 * Gate automatic PHY configuration by hardware on
3034 if ((hw
->mac
.type
== e1000_pch2lan
) &&
3035 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
3036 e1000_gate_hw_phy_config_ich8lan(hw
, true);
3038 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
3039 e_dbg("Issuing a global reset to ich8lan\n");
3040 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
3044 e1000_release_swflag_ich8lan(hw
);
3046 if (ctrl
& E1000_CTRL_PHY_RST
) {
3047 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
3051 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
3057 * For PCH, this write will make sure that any noise
3058 * will be detected as a CRC error and be dropped rather than show up
3059 * as a bad packet to the DMA engine.
3061 if (hw
->mac
.type
== e1000_pchlan
)
3062 ew32(CRC_OFFSET
, 0x65656565);
3064 ew32(IMC
, 0xffffffff);
3067 kab
= er32(KABGTXD
);
3068 kab
|= E1000_KABGTXD_BGSQLBIAS
;
3076 * e1000_init_hw_ich8lan - Initialize the hardware
3077 * @hw: pointer to the HW structure
3079 * Prepares the hardware for transmit and receive by doing the following:
3080 * - initialize hardware bits
3081 * - initialize LED identification
3082 * - setup receive address registers
3083 * - setup flow control
3084 * - setup transmit descriptors
3085 * - clear statistics
3087 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
3089 struct e1000_mac_info
*mac
= &hw
->mac
;
3090 u32 ctrl_ext
, txdctl
, snoop
;
3094 e1000_initialize_hw_bits_ich8lan(hw
);
3096 /* Initialize identification LED */
3097 ret_val
= mac
->ops
.id_led_init(hw
);
3099 e_dbg("Error initializing identification LED\n");
3100 /* This is not fatal and we should not stop init due to this */
3102 /* Setup the receive address. */
3103 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
3105 /* Zero out the Multicast HASH table */
3106 e_dbg("Zeroing the MTA\n");
3107 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
3108 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
3111 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3112 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3113 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3115 if (hw
->phy
.type
== e1000_phy_82578
) {
3116 hw
->phy
.ops
.read_reg(hw
, BM_WUC
, &i
);
3117 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
3122 /* Setup link and flow control */
3123 ret_val
= e1000_setup_link_ich8lan(hw
);
3125 /* Set the transmit descriptor write-back policy for both queues */
3126 txdctl
= er32(TXDCTL(0));
3127 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3128 E1000_TXDCTL_FULL_TX_DESC_WB
;
3129 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3130 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
3131 ew32(TXDCTL(0), txdctl
);
3132 txdctl
= er32(TXDCTL(1));
3133 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3134 E1000_TXDCTL_FULL_TX_DESC_WB
;
3135 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3136 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
3137 ew32(TXDCTL(1), txdctl
);
3140 * ICH8 has opposite polarity of no_snoop bits.
3141 * By default, we should use snoop behavior.
3143 if (mac
->type
== e1000_ich8lan
)
3144 snoop
= PCIE_ICH8_SNOOP_ALL
;
3146 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
3147 e1000e_set_pcie_no_snoop(hw
, snoop
);
3149 ctrl_ext
= er32(CTRL_EXT
);
3150 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
3151 ew32(CTRL_EXT
, ctrl_ext
);
3154 * Clear all of the statistics registers (clear on read). It is
3155 * important that we do this after we have tried to establish link
3156 * because the symbol error count will increment wildly if there
3159 e1000_clear_hw_cntrs_ich8lan(hw
);
3164 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3165 * @hw: pointer to the HW structure
3167 * Sets/Clears required hardware bits necessary for correctly setting up the
3168 * hardware for transmit and receive.
3170 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
3174 /* Extended Device Control */
3175 reg
= er32(CTRL_EXT
);
3177 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3178 if (hw
->mac
.type
>= e1000_pchlan
)
3179 reg
|= E1000_CTRL_EXT_PHYPDEN
;
3180 ew32(CTRL_EXT
, reg
);
3182 /* Transmit Descriptor Control 0 */
3183 reg
= er32(TXDCTL(0));
3185 ew32(TXDCTL(0), reg
);
3187 /* Transmit Descriptor Control 1 */
3188 reg
= er32(TXDCTL(1));
3190 ew32(TXDCTL(1), reg
);
3192 /* Transmit Arbitration Control 0 */
3193 reg
= er32(TARC(0));
3194 if (hw
->mac
.type
== e1000_ich8lan
)
3195 reg
|= (1 << 28) | (1 << 29);
3196 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3199 /* Transmit Arbitration Control 1 */
3200 reg
= er32(TARC(1));
3201 if (er32(TCTL
) & E1000_TCTL_MULR
)
3205 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
3209 if (hw
->mac
.type
== e1000_ich8lan
) {
3216 * work-around descriptor data corruption issue during nfs v2 udp
3217 * traffic, just disable the nfs filtering capability
3220 reg
|= (E1000_RFCTL_NFSW_DIS
| E1000_RFCTL_NFSR_DIS
);
3225 * e1000_setup_link_ich8lan - Setup flow control and link settings
3226 * @hw: pointer to the HW structure
3228 * Determines which flow control settings to use, then configures flow
3229 * control. Calls the appropriate media-specific link configuration
3230 * function. Assuming the adapter has a valid link partner, a valid link
3231 * should be established. Assumes the hardware has previously been reset
3232 * and the transmitter and receiver are not enabled.
3234 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
3238 if (e1000_check_reset_block(hw
))
3242 * ICH parts do not have a word in the NVM to determine
3243 * the default flow control setting, so we explicitly
3246 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
3247 /* Workaround h/w hang when Tx flow control enabled */
3248 if (hw
->mac
.type
== e1000_pchlan
)
3249 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
3251 hw
->fc
.requested_mode
= e1000_fc_full
;
3255 * Save off the requested flow control mode for use later. Depending
3256 * on the link partner's capabilities, we may or may not use this mode.
3258 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
3260 e_dbg("After fix-ups FlowControl is now = %x\n",
3261 hw
->fc
.current_mode
);
3263 /* Continue to configure the copper link. */
3264 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
3268 ew32(FCTTV
, hw
->fc
.pause_time
);
3269 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3270 (hw
->phy
.type
== e1000_phy_82579
) ||
3271 (hw
->phy
.type
== e1000_phy_82577
)) {
3272 ew32(FCRTV_PCH
, hw
->fc
.refresh_time
);
3274 ret_val
= hw
->phy
.ops
.write_reg(hw
,
3275 PHY_REG(BM_PORT_CTRL_PAGE
, 27),
3281 return e1000e_set_fc_watermarks(hw
);
3285 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3286 * @hw: pointer to the HW structure
3288 * Configures the kumeran interface to the PHY to wait the appropriate time
3289 * when polling the PHY, then call the generic setup_copper_link to finish
3290 * configuring the copper link.
3292 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
3299 ctrl
|= E1000_CTRL_SLU
;
3300 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
3304 * Set the mac to wait the maximum time between each iteration
3305 * and increase the max iterations when polling the phy;
3306 * this fixes erroneous timeouts at 10Mbps.
3308 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_TIMEOUTS
, 0xFFFF);
3311 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3316 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3321 switch (hw
->phy
.type
) {
3322 case e1000_phy_igp_3
:
3323 ret_val
= e1000e_copper_link_setup_igp(hw
);
3328 case e1000_phy_82578
:
3329 ret_val
= e1000e_copper_link_setup_m88(hw
);
3333 case e1000_phy_82577
:
3334 case e1000_phy_82579
:
3335 ret_val
= e1000_copper_link_setup_82577(hw
);
3340 ret_val
= hw
->phy
.ops
.read_reg(hw
, IFE_PHY_MDIX_CONTROL
,
3345 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
3347 switch (hw
->phy
.mdix
) {
3349 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
3352 reg_data
|= IFE_PMC_FORCE_MDIX
;
3356 reg_data
|= IFE_PMC_AUTO_MDIX
;
3359 ret_val
= hw
->phy
.ops
.write_reg(hw
, IFE_PHY_MDIX_CONTROL
,
3367 return e1000e_setup_copper_link(hw
);
3371 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3372 * @hw: pointer to the HW structure
3373 * @speed: pointer to store current link speed
3374 * @duplex: pointer to store the current link duplex
3376 * Calls the generic get_speed_and_duplex to retrieve the current link
3377 * information and then calls the Kumeran lock loss workaround for links at
3380 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
3385 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
3389 if ((hw
->mac
.type
== e1000_ich8lan
) &&
3390 (hw
->phy
.type
== e1000_phy_igp_3
) &&
3391 (*speed
== SPEED_1000
)) {
3392 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
3399 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3400 * @hw: pointer to the HW structure
3402 * Work-around for 82566 Kumeran PCS lock loss:
3403 * On link status change (i.e. PCI reset, speed change) and link is up and
3405 * 0) if workaround is optionally disabled do nothing
3406 * 1) wait 1ms for Kumeran link to come up
3407 * 2) check Kumeran Diagnostic register PCS lock loss bit
3408 * 3) if not set the link is locked (all is good), otherwise...
3410 * 5) repeat up to 10 times
3411 * Note: this is only called for IGP3 copper when speed is 1gb.
3413 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
3415 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3421 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
3425 * Make sure link is up before proceeding. If not just return.
3426 * Attempting this while link is negotiating fouled up link
3429 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3433 for (i
= 0; i
< 10; i
++) {
3434 /* read once to clear */
3435 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
3438 /* and again to get new status */
3439 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
3443 /* check for PCS lock */
3444 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
3447 /* Issue PHY reset */
3448 e1000_phy_hw_reset(hw
);
3451 /* Disable GigE link negotiation */
3452 phy_ctrl
= er32(PHY_CTRL
);
3453 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
3454 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
3455 ew32(PHY_CTRL
, phy_ctrl
);
3458 * Call gig speed drop workaround on Gig disable before accessing
3461 e1000e_gig_downshift_workaround_ich8lan(hw
);
3463 /* unable to acquire PCS lock */
3464 return -E1000_ERR_PHY
;
3468 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3469 * @hw: pointer to the HW structure
3470 * @state: boolean value used to set the current Kumeran workaround state
3472 * If ICH8, set the current Kumeran workaround state (enabled - true
3473 * /disabled - false).
3475 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
3478 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3480 if (hw
->mac
.type
!= e1000_ich8lan
) {
3481 e_dbg("Workaround applies to ICH8 only.\n");
3485 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
3489 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3490 * @hw: pointer to the HW structure
3492 * Workaround for 82566 power-down on D3 entry:
3493 * 1) disable gigabit link
3494 * 2) write VR power-down enable
3496 * Continue if successful, else issue LCD reset and repeat
3498 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
3504 if (hw
->phy
.type
!= e1000_phy_igp_3
)
3507 /* Try the workaround twice (if needed) */
3510 reg
= er32(PHY_CTRL
);
3511 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
3512 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
3513 ew32(PHY_CTRL
, reg
);
3516 * Call gig speed drop workaround on Gig disable before
3517 * accessing any PHY registers
3519 if (hw
->mac
.type
== e1000_ich8lan
)
3520 e1000e_gig_downshift_workaround_ich8lan(hw
);
3522 /* Write VR power-down enable */
3523 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
3524 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
3525 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
3527 /* Read it back and test */
3528 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
3529 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
3530 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
3533 /* Issue PHY reset and repeat at most one more time */
3535 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
3541 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3542 * @hw: pointer to the HW structure
3544 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3545 * LPLU, Gig disable, MDIC PHY reset):
3546 * 1) Set Kumeran Near-end loopback
3547 * 2) Clear Kumeran Near-end loopback
3548 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3550 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
3555 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
3556 (hw
->phy
.type
!= e1000_phy_igp_3
))
3559 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3563 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
3564 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3568 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
3569 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3574 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3575 * @hw: pointer to the HW structure
3577 * During S0 to Sx transition, it is possible the link remains at gig
3578 * instead of negotiating to a lower speed. Before going to Sx, set
3579 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3582 * Should only be called for applicable parts.
3584 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
3589 phy_ctrl
= er32(PHY_CTRL
);
3590 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
| E1000_PHY_CTRL_GBE_DISABLE
;
3591 ew32(PHY_CTRL
, phy_ctrl
);
3593 if (hw
->mac
.type
>= e1000_pchlan
) {
3594 e1000_oem_bits_config_ich8lan(hw
, true);
3595 ret_val
= hw
->phy
.ops
.acquire(hw
);
3598 e1000_write_smbus_addr(hw
);
3599 hw
->phy
.ops
.release(hw
);
3604 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3605 * @hw: pointer to the HW structure
3607 * Return the LED back to the default configuration.
3609 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
3611 if (hw
->phy
.type
== e1000_phy_ife
)
3612 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
3614 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
3619 * e1000_led_on_ich8lan - Turn LEDs on
3620 * @hw: pointer to the HW structure
3624 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
3626 if (hw
->phy
.type
== e1000_phy_ife
)
3627 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
3628 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
3630 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
3635 * e1000_led_off_ich8lan - Turn LEDs off
3636 * @hw: pointer to the HW structure
3638 * Turn off the LEDs.
3640 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
3642 if (hw
->phy
.type
== e1000_phy_ife
)
3643 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
3644 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
3646 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
3651 * e1000_setup_led_pchlan - Configures SW controllable LED
3652 * @hw: pointer to the HW structure
3654 * This prepares the SW controllable LED for use.
3656 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
3658 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
,
3659 (u16
)hw
->mac
.ledctl_mode1
);
3663 * e1000_cleanup_led_pchlan - Restore the default LED operation
3664 * @hw: pointer to the HW structure
3666 * Return the LED back to the default configuration.
3668 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
3670 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
,
3671 (u16
)hw
->mac
.ledctl_default
);
3675 * e1000_led_on_pchlan - Turn LEDs on
3676 * @hw: pointer to the HW structure
3680 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
3682 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
3686 * If no link, then turn LED on by setting the invert bit
3687 * for each LED that's mode is "link_up" in ledctl_mode2.
3689 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3690 for (i
= 0; i
< 3; i
++) {
3691 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3692 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3693 E1000_LEDCTL_MODE_LINK_UP
)
3695 if (led
& E1000_PHY_LED0_IVRT
)
3696 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3698 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3702 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
, data
);
3706 * e1000_led_off_pchlan - Turn LEDs off
3707 * @hw: pointer to the HW structure
3709 * Turn off the LEDs.
3711 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
3713 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
3717 * If no link, then turn LED off by clearing the invert bit
3718 * for each LED that's mode is "link_up" in ledctl_mode1.
3720 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3721 for (i
= 0; i
< 3; i
++) {
3722 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3723 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3724 E1000_LEDCTL_MODE_LINK_UP
)
3726 if (led
& E1000_PHY_LED0_IVRT
)
3727 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3729 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3733 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
, data
);
3737 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3738 * @hw: pointer to the HW structure
3740 * Read appropriate register for the config done bit for completion status
3741 * and configure the PHY through s/w for EEPROM-less parts.
3743 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3744 * config done bit, so only an error is logged and continues. If we were
3745 * to return with error, EEPROM-less silicon would not be able to be reset
3748 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
3754 e1000e_get_cfg_done(hw
);
3756 /* Wait for indication from h/w that it has completed basic config */
3757 if (hw
->mac
.type
>= e1000_ich10lan
) {
3758 e1000_lan_init_done_ich8lan(hw
);
3760 ret_val
= e1000e_get_auto_rd_done(hw
);
3763 * When auto config read does not complete, do not
3764 * return with an error. This can happen in situations
3765 * where there is no eeprom and prevents getting link.
3767 e_dbg("Auto Read Done did not complete\n");
3772 /* Clear PHY Reset Asserted bit */
3773 status
= er32(STATUS
);
3774 if (status
& E1000_STATUS_PHYRA
)
3775 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
3777 e_dbg("PHY Reset Asserted not set - needs delay\n");
3779 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3780 if (hw
->mac
.type
<= e1000_ich9lan
) {
3781 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
3782 (hw
->phy
.type
== e1000_phy_igp_3
)) {
3783 e1000e_phy_init_script_igp3(hw
);
3786 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
3787 /* Maybe we should do a basic PHY config */
3788 e_dbg("EEPROM not present\n");
3789 ret_val
= -E1000_ERR_CONFIG
;
3797 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3798 * @hw: pointer to the HW structure
3800 * In the case of a PHY power down to save power, or to turn off link during a
3801 * driver unload, or wake on lan is not enabled, remove the link.
3803 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
3805 /* If the management interface is not enabled, then power down */
3806 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
3807 hw
->phy
.ops
.check_reset_block(hw
)))
3808 e1000_power_down_phy_copper(hw
);
3812 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3813 * @hw: pointer to the HW structure
3815 * Clears hardware counters specific to the silicon family and calls
3816 * clear_hw_cntrs_generic to clear all general purpose counters.
3818 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
3822 e1000e_clear_hw_cntrs_base(hw
);
3838 /* Clear PHY statistics registers */
3839 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3840 (hw
->phy
.type
== e1000_phy_82579
) ||
3841 (hw
->phy
.type
== e1000_phy_82577
)) {
3842 hw
->phy
.ops
.read_reg(hw
, HV_SCC_UPPER
, &phy_data
);
3843 hw
->phy
.ops
.read_reg(hw
, HV_SCC_LOWER
, &phy_data
);
3844 hw
->phy
.ops
.read_reg(hw
, HV_ECOL_UPPER
, &phy_data
);
3845 hw
->phy
.ops
.read_reg(hw
, HV_ECOL_LOWER
, &phy_data
);
3846 hw
->phy
.ops
.read_reg(hw
, HV_MCC_UPPER
, &phy_data
);
3847 hw
->phy
.ops
.read_reg(hw
, HV_MCC_LOWER
, &phy_data
);
3848 hw
->phy
.ops
.read_reg(hw
, HV_LATECOL_UPPER
, &phy_data
);
3849 hw
->phy
.ops
.read_reg(hw
, HV_LATECOL_LOWER
, &phy_data
);
3850 hw
->phy
.ops
.read_reg(hw
, HV_COLC_UPPER
, &phy_data
);
3851 hw
->phy
.ops
.read_reg(hw
, HV_COLC_LOWER
, &phy_data
);
3852 hw
->phy
.ops
.read_reg(hw
, HV_DC_UPPER
, &phy_data
);
3853 hw
->phy
.ops
.read_reg(hw
, HV_DC_LOWER
, &phy_data
);
3854 hw
->phy
.ops
.read_reg(hw
, HV_TNCRS_UPPER
, &phy_data
);
3855 hw
->phy
.ops
.read_reg(hw
, HV_TNCRS_LOWER
, &phy_data
);
3859 static struct e1000_mac_operations ich8_mac_ops
= {
3860 .id_led_init
= e1000e_id_led_init
,
3861 /* check_mng_mode dependent on mac type */
3862 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
3863 /* cleanup_led dependent on mac type */
3864 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
3865 .get_bus_info
= e1000_get_bus_info_ich8lan
,
3866 .set_lan_id
= e1000_set_lan_id_single_port
,
3867 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
3868 /* led_on dependent on mac type */
3869 /* led_off dependent on mac type */
3870 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
3871 .reset_hw
= e1000_reset_hw_ich8lan
,
3872 .init_hw
= e1000_init_hw_ich8lan
,
3873 .setup_link
= e1000_setup_link_ich8lan
,
3874 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
3875 /* id_led_init dependent on mac type */
3878 static struct e1000_phy_operations ich8_phy_ops
= {
3879 .acquire
= e1000_acquire_swflag_ich8lan
,
3880 .check_reset_block
= e1000_check_reset_block_ich8lan
,
3882 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
3883 .get_cable_length
= e1000e_get_cable_length_igp_2
,
3884 .read_reg
= e1000e_read_phy_reg_igp
,
3885 .release
= e1000_release_swflag_ich8lan
,
3886 .reset
= e1000_phy_hw_reset_ich8lan
,
3887 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
3888 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
3889 .write_reg
= e1000e_write_phy_reg_igp
,
3892 static struct e1000_nvm_operations ich8_nvm_ops
= {
3893 .acquire
= e1000_acquire_nvm_ich8lan
,
3894 .read
= e1000_read_nvm_ich8lan
,
3895 .release
= e1000_release_nvm_ich8lan
,
3896 .update
= e1000_update_nvm_checksum_ich8lan
,
3897 .valid_led_default
= e1000_valid_led_default_ich8lan
,
3898 .validate
= e1000_validate_nvm_checksum_ich8lan
,
3899 .write
= e1000_write_nvm_ich8lan
,
3902 struct e1000_info e1000_ich8_info
= {
3903 .mac
= e1000_ich8lan
,
3904 .flags
= FLAG_HAS_WOL
3906 | FLAG_RX_CSUM_ENABLED
3907 | FLAG_HAS_CTRLEXT_ON_LOAD
3912 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
3913 .get_variants
= e1000_get_variants_ich8lan
,
3914 .mac_ops
= &ich8_mac_ops
,
3915 .phy_ops
= &ich8_phy_ops
,
3916 .nvm_ops
= &ich8_nvm_ops
,
3919 struct e1000_info e1000_ich9_info
= {
3920 .mac
= e1000_ich9lan
,
3921 .flags
= FLAG_HAS_JUMBO_FRAMES
3924 | FLAG_RX_CSUM_ENABLED
3925 | FLAG_HAS_CTRLEXT_ON_LOAD
3931 .max_hw_frame_size
= DEFAULT_JUMBO
,
3932 .get_variants
= e1000_get_variants_ich8lan
,
3933 .mac_ops
= &ich8_mac_ops
,
3934 .phy_ops
= &ich8_phy_ops
,
3935 .nvm_ops
= &ich8_nvm_ops
,
3938 struct e1000_info e1000_ich10_info
= {
3939 .mac
= e1000_ich10lan
,
3940 .flags
= FLAG_HAS_JUMBO_FRAMES
3943 | FLAG_RX_CSUM_ENABLED
3944 | FLAG_HAS_CTRLEXT_ON_LOAD
3950 .max_hw_frame_size
= DEFAULT_JUMBO
,
3951 .get_variants
= e1000_get_variants_ich8lan
,
3952 .mac_ops
= &ich8_mac_ops
,
3953 .phy_ops
= &ich8_phy_ops
,
3954 .nvm_ops
= &ich8_nvm_ops
,
3957 struct e1000_info e1000_pch_info
= {
3958 .mac
= e1000_pchlan
,
3959 .flags
= FLAG_IS_ICH
3961 | FLAG_RX_CSUM_ENABLED
3962 | FLAG_HAS_CTRLEXT_ON_LOAD
3965 | FLAG_HAS_JUMBO_FRAMES
3966 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
3968 .flags2
= FLAG2_HAS_PHY_STATS
,
3970 .max_hw_frame_size
= 4096,
3971 .get_variants
= e1000_get_variants_ich8lan
,
3972 .mac_ops
= &ich8_mac_ops
,
3973 .phy_ops
= &ich8_phy_ops
,
3974 .nvm_ops
= &ich8_nvm_ops
,
3977 struct e1000_info e1000_pch2_info
= {
3978 .mac
= e1000_pch2lan
,
3979 .flags
= FLAG_IS_ICH
3981 | FLAG_RX_CSUM_ENABLED
3982 | FLAG_HAS_CTRLEXT_ON_LOAD
3985 | FLAG_HAS_JUMBO_FRAMES
3987 .flags2
= FLAG2_HAS_PHY_STATS
3990 .max_hw_frame_size
= DEFAULT_JUMBO
,
3991 .get_variants
= e1000_get_variants_ich8lan
,
3992 .mac_ops
= &ich8_mac_ops
,
3993 .phy_ops
= &ich8_phy_ops
,
3994 .nvm_ops
= &ich8_nvm_ops
,