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[E1000E]: New pci-express e1000 driver (currently for ICH9 devices only)
[deliverable/linux.git] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 */
42
43 #include <linux/netdevice.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/pci.h>
47
48 #include "e1000.h"
49
50 #define ICH_FLASH_GFPREG 0x0000
51 #define ICH_FLASH_HSFSTS 0x0004
52 #define ICH_FLASH_HSFCTL 0x0006
53 #define ICH_FLASH_FADDR 0x0008
54 #define ICH_FLASH_FDATA0 0x0010
55
56 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
57 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
58 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
59 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
60 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
61
62 #define ICH_CYCLE_READ 0
63 #define ICH_CYCLE_WRITE 2
64 #define ICH_CYCLE_ERASE 3
65
66 #define FLASH_GFPREG_BASE_MASK 0x1FFF
67 #define FLASH_SECTOR_ADDR_SHIFT 12
68
69 #define ICH_FLASH_SEG_SIZE_256 256
70 #define ICH_FLASH_SEG_SIZE_4K 4096
71 #define ICH_FLASH_SEG_SIZE_8K 8192
72 #define ICH_FLASH_SEG_SIZE_64K 65536
73
74
75 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
76
77 #define E1000_ICH_MNG_IAMT_MODE 0x2
78
79 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
80 (ID_LED_DEF1_OFF2 << 8) | \
81 (ID_LED_DEF1_ON2 << 4) | \
82 (ID_LED_DEF1_DEF2))
83
84 #define E1000_ICH_NVM_SIG_WORD 0x13
85 #define E1000_ICH_NVM_SIG_MASK 0xC000
86
87 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
88
89 #define E1000_FEXTNVM_SW_CONFIG 1
90 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
91
92 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
93
94 #define E1000_ICH_RAR_ENTRIES 7
95
96 #define PHY_PAGE_SHIFT 5
97 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
98 ((reg) & MAX_PHY_REG_ADDRESS))
99 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
100 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
101
102 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
103 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
104 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
105
106 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
107 /* Offset 04h HSFSTS */
108 union ich8_hws_flash_status {
109 struct ich8_hsfsts {
110 u16 flcdone :1; /* bit 0 Flash Cycle Done */
111 u16 flcerr :1; /* bit 1 Flash Cycle Error */
112 u16 dael :1; /* bit 2 Direct Access error Log */
113 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
114 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
115 u16 reserved1 :2; /* bit 13:6 Reserved */
116 u16 reserved2 :6; /* bit 13:6 Reserved */
117 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
118 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
119 } hsf_status;
120 u16 regval;
121 };
122
123 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
124 /* Offset 06h FLCTL */
125 union ich8_hws_flash_ctrl {
126 struct ich8_hsflctl {
127 u16 flcgo :1; /* 0 Flash Cycle Go */
128 u16 flcycle :2; /* 2:1 Flash Cycle */
129 u16 reserved :5; /* 7:3 Reserved */
130 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
131 u16 flockdn :6; /* 15:10 Reserved */
132 } hsf_ctrl;
133 u16 regval;
134 };
135
136 /* ICH Flash Region Access Permissions */
137 union ich8_hws_flash_regacc {
138 struct ich8_flracc {
139 u32 grra :8; /* 0:7 GbE region Read Access */
140 u32 grwa :8; /* 8:15 GbE region Write Access */
141 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
142 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
143 } hsf_flregacc;
144 u16 regval;
145 };
146
147 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
148 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
149 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
150 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
151 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
152 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
153 u32 offset, u8 byte);
154 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
155 u16 *data);
156 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
157 u8 size, u16 *data);
158 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
159 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
160
161 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
162 {
163 return readw(hw->flash_address + reg);
164 }
165
166 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
167 {
168 return readl(hw->flash_address + reg);
169 }
170
171 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
172 {
173 writew(val, hw->flash_address + reg);
174 }
175
176 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
177 {
178 writel(val, hw->flash_address + reg);
179 }
180
181 #define er16flash(reg) __er16flash(hw, (reg))
182 #define er32flash(reg) __er32flash(hw, (reg))
183 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
184 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
185
186 /**
187 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
188 * @hw: pointer to the HW structure
189 *
190 * Initialize family-specific PHY parameters and function pointers.
191 **/
192 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
193 {
194 struct e1000_phy_info *phy = &hw->phy;
195 s32 ret_val;
196 u16 i = 0;
197
198 phy->addr = 1;
199 phy->reset_delay_us = 100;
200
201 phy->id = 0;
202 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
203 (i++ < 100)) {
204 msleep(1);
205 ret_val = e1000e_get_phy_id(hw);
206 if (ret_val)
207 return ret_val;
208 }
209
210 /* Verify phy id */
211 switch (phy->id) {
212 case IGP03E1000_E_PHY_ID:
213 phy->type = e1000_phy_igp_3;
214 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
215 break;
216 case IFE_E_PHY_ID:
217 case IFE_PLUS_E_PHY_ID:
218 case IFE_C_E_PHY_ID:
219 phy->type = e1000_phy_ife;
220 phy->autoneg_mask = E1000_ALL_NOT_GIG;
221 break;
222 default:
223 return -E1000_ERR_PHY;
224 break;
225 }
226
227 return 0;
228 }
229
230 /**
231 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
232 * @hw: pointer to the HW structure
233 *
234 * Initialize family-specific NVM parameters and function
235 * pointers.
236 **/
237 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
238 {
239 struct e1000_nvm_info *nvm = &hw->nvm;
240 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
241 u32 gfpreg;
242 u32 sector_base_addr;
243 u32 sector_end_addr;
244 u16 i;
245
246 /* Can't read flash registers if the register set isn't mapped.
247 */
248 if (!hw->flash_address) {
249 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
250 return -E1000_ERR_CONFIG;
251 }
252
253 nvm->type = e1000_nvm_flash_sw;
254
255 gfpreg = er32flash(ICH_FLASH_GFPREG);
256
257 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
258 * Add 1 to sector_end_addr since this sector is included in
259 * the overall size. */
260 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
261 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
262
263 /* flash_base_addr is byte-aligned */
264 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
265
266 /* find total size of the NVM, then cut in half since the total
267 * size represents two separate NVM banks. */
268 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
269 << FLASH_SECTOR_ADDR_SHIFT;
270 nvm->flash_bank_size /= 2;
271 /* Adjust to word count */
272 nvm->flash_bank_size /= sizeof(u16);
273
274 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
275
276 /* Clear shadow ram */
277 for (i = 0; i < nvm->word_size; i++) {
278 dev_spec->shadow_ram[i].modified = 0;
279 dev_spec->shadow_ram[i].value = 0xFFFF;
280 }
281
282 return 0;
283 }
284
285 /**
286 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
287 * @hw: pointer to the HW structure
288 *
289 * Initialize family-specific MAC parameters and function
290 * pointers.
291 **/
292 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
293 {
294 struct e1000_hw *hw = &adapter->hw;
295 struct e1000_mac_info *mac = &hw->mac;
296
297 /* Set media type function pointer */
298 hw->media_type = e1000_media_type_copper;
299
300 /* Set mta register count */
301 mac->mta_reg_count = 32;
302 /* Set rar entry count */
303 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
304 if (mac->type == e1000_ich8lan)
305 mac->rar_entry_count--;
306 /* Set if manageability features are enabled. */
307 mac->arc_subsystem_valid = 1;
308
309 /* Enable PCS Lock-loss workaround for ICH8 */
310 if (mac->type == e1000_ich8lan)
311 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
312
313 return 0;
314 }
315
316 static s32 e1000_get_invariants_ich8lan(struct e1000_adapter *adapter)
317 {
318 struct e1000_hw *hw = &adapter->hw;
319 s32 rc;
320
321 rc = e1000_init_mac_params_ich8lan(adapter);
322 if (rc)
323 return rc;
324
325 rc = e1000_init_nvm_params_ich8lan(hw);
326 if (rc)
327 return rc;
328
329 rc = e1000_init_phy_params_ich8lan(hw);
330 if (rc)
331 return rc;
332
333 if ((adapter->hw.mac.type == e1000_ich8lan) &&
334 (adapter->hw.phy.type == e1000_phy_igp_3))
335 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
336
337 return 0;
338 }
339
340 /**
341 * e1000_acquire_swflag_ich8lan - Acquire software control flag
342 * @hw: pointer to the HW structure
343 *
344 * Acquires the software control flag for performing NVM and PHY
345 * operations. This is a function pointer entry point only called by
346 * read/write routines for the PHY and NVM parts.
347 **/
348 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
349 {
350 u32 extcnf_ctrl;
351 u32 timeout = PHY_CFG_TIMEOUT;
352
353 while (timeout) {
354 extcnf_ctrl = er32(EXTCNF_CTRL);
355 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
356 ew32(EXTCNF_CTRL, extcnf_ctrl);
357
358 extcnf_ctrl = er32(EXTCNF_CTRL);
359 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
360 break;
361 mdelay(1);
362 timeout--;
363 }
364
365 if (!timeout) {
366 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
367 return -E1000_ERR_CONFIG;
368 }
369
370 return 0;
371 }
372
373 /**
374 * e1000_release_swflag_ich8lan - Release software control flag
375 * @hw: pointer to the HW structure
376 *
377 * Releases the software control flag for performing NVM and PHY operations.
378 * This is a function pointer entry point only called by read/write
379 * routines for the PHY and NVM parts.
380 **/
381 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
382 {
383 u32 extcnf_ctrl;
384
385 extcnf_ctrl = er32(EXTCNF_CTRL);
386 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
387 ew32(EXTCNF_CTRL, extcnf_ctrl);
388 }
389
390 /**
391 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
392 * @hw: pointer to the HW structure
393 *
394 * Checks if firmware is blocking the reset of the PHY.
395 * This is a function pointer entry point only called by
396 * reset routines.
397 **/
398 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
399 {
400 u32 fwsm;
401
402 fwsm = er32(FWSM);
403
404 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
405 }
406
407 /**
408 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
409 * @hw: pointer to the HW structure
410 *
411 * Forces the speed and duplex settings of the PHY.
412 * This is a function pointer entry point only called by
413 * PHY setup routines.
414 **/
415 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
416 {
417 struct e1000_phy_info *phy = &hw->phy;
418 s32 ret_val;
419 u16 data;
420 bool link;
421
422 if (phy->type != e1000_phy_ife) {
423 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
424 return ret_val;
425 }
426
427 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
428 if (ret_val)
429 return ret_val;
430
431 e1000e_phy_force_speed_duplex_setup(hw, &data);
432
433 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
434 if (ret_val)
435 return ret_val;
436
437 /* Disable MDI-X support for 10/100 */
438 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
439 if (ret_val)
440 return ret_val;
441
442 data &= ~IFE_PMC_AUTO_MDIX;
443 data &= ~IFE_PMC_FORCE_MDIX;
444
445 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
446 if (ret_val)
447 return ret_val;
448
449 hw_dbg(hw, "IFE PMC: %X\n", data);
450
451 udelay(1);
452
453 if (phy->wait_for_link) {
454 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
455
456 ret_val = e1000e_phy_has_link_generic(hw,
457 PHY_FORCE_LIMIT,
458 100000,
459 &link);
460 if (ret_val)
461 return ret_val;
462
463 if (!link)
464 hw_dbg(hw, "Link taking longer than expected.\n");
465
466 /* Try once more */
467 ret_val = e1000e_phy_has_link_generic(hw,
468 PHY_FORCE_LIMIT,
469 100000,
470 &link);
471 if (ret_val)
472 return ret_val;
473 }
474
475 return 0;
476 }
477
478 /**
479 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
480 * @hw: pointer to the HW structure
481 *
482 * Resets the PHY
483 * This is a function pointer entry point called by drivers
484 * or other shared routines.
485 **/
486 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
487 {
488 struct e1000_phy_info *phy = &hw->phy;
489 u32 i;
490 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
491 s32 ret_val;
492 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
493 u16 word_addr, reg_data, reg_addr, phy_page = 0;
494
495 ret_val = e1000e_phy_hw_reset_generic(hw);
496 if (ret_val)
497 return ret_val;
498
499 /* Initialize the PHY from the NVM on ICH platforms. This
500 * is needed due to an issue where the NVM configuration is
501 * not properly autoloaded after power transitions.
502 * Therefore, after each PHY reset, we will load the
503 * configuration data out of the NVM manually.
504 */
505 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
506 struct e1000_adapter *adapter = hw->adapter;
507
508 /* Check if SW needs configure the PHY */
509 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
510 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
511 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
512 else
513 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
514
515 data = er32(FEXTNVM);
516 if (!(data & sw_cfg_mask))
517 return 0;
518
519 /* Wait for basic configuration completes before proceeding*/
520 do {
521 data = er32(STATUS);
522 data &= E1000_STATUS_LAN_INIT_DONE;
523 udelay(100);
524 } while ((!data) && --loop);
525
526 /* If basic configuration is incomplete before the above loop
527 * count reaches 0, loading the configuration from NVM will
528 * leave the PHY in a bad state possibly resulting in no link.
529 */
530 if (loop == 0) {
531 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
532 }
533
534 /* Clear the Init Done bit for the next init event */
535 data = er32(STATUS);
536 data &= ~E1000_STATUS_LAN_INIT_DONE;
537 ew32(STATUS, data);
538
539 /* Make sure HW does not configure LCD from PHY
540 * extended configuration before SW configuration */
541 data = er32(EXTCNF_CTRL);
542 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
543 return 0;
544
545 cnf_size = er32(EXTCNF_SIZE);
546 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
547 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
548 if (!cnf_size)
549 return 0;
550
551 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
552 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
553
554 /* Configure LCD from extended configuration
555 * region. */
556
557 /* cnf_base_addr is in DWORD */
558 word_addr = (u16)(cnf_base_addr << 1);
559
560 for (i = 0; i < cnf_size; i++) {
561 ret_val = e1000_read_nvm(hw,
562 (word_addr + i * 2),
563 1,
564 &reg_data);
565 if (ret_val)
566 return ret_val;
567
568 ret_val = e1000_read_nvm(hw,
569 (word_addr + i * 2 + 1),
570 1,
571 &reg_addr);
572 if (ret_val)
573 return ret_val;
574
575 /* Save off the PHY page for future writes. */
576 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
577 phy_page = reg_data;
578 continue;
579 }
580
581 reg_addr |= phy_page;
582
583 ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
584 if (ret_val)
585 return ret_val;
586 }
587 }
588
589 return 0;
590 }
591
592 /**
593 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
594 * @hw: pointer to the HW structure
595 *
596 * Populates "phy" structure with various feature states.
597 * This function is only called by other family-specific
598 * routines.
599 **/
600 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
601 {
602 struct e1000_phy_info *phy = &hw->phy;
603 s32 ret_val;
604 u16 data;
605 bool link;
606
607 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
608 if (ret_val)
609 return ret_val;
610
611 if (!link) {
612 hw_dbg(hw, "Phy info is only valid if link is up\n");
613 return -E1000_ERR_CONFIG;
614 }
615
616 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
617 if (ret_val)
618 return ret_val;
619 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
620
621 if (phy->polarity_correction) {
622 ret_val = e1000_check_polarity_ife_ich8lan(hw);
623 if (ret_val)
624 return ret_val;
625 } else {
626 /* Polarity is forced */
627 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
628 ? e1000_rev_polarity_reversed
629 : e1000_rev_polarity_normal;
630 }
631
632 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
633 if (ret_val)
634 return ret_val;
635
636 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
637
638 /* The following parameters are undefined for 10/100 operation. */
639 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
640 phy->local_rx = e1000_1000t_rx_status_undefined;
641 phy->remote_rx = e1000_1000t_rx_status_undefined;
642
643 return 0;
644 }
645
646 /**
647 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
648 * @hw: pointer to the HW structure
649 *
650 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
651 * This is a function pointer entry point called by drivers
652 * or other shared routines.
653 **/
654 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
655 {
656 switch (hw->phy.type) {
657 case e1000_phy_ife:
658 return e1000_get_phy_info_ife_ich8lan(hw);
659 break;
660 case e1000_phy_igp_3:
661 return e1000e_get_phy_info_igp(hw);
662 break;
663 default:
664 break;
665 }
666
667 return -E1000_ERR_PHY_TYPE;
668 }
669
670 /**
671 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
672 * @hw: pointer to the HW structure
673 *
674 * Polarity is determined on the polarity reveral feature being enabled.
675 * This function is only called by other family-specific
676 * routines.
677 **/
678 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
679 {
680 struct e1000_phy_info *phy = &hw->phy;
681 s32 ret_val;
682 u16 phy_data, offset, mask;
683
684 /* Polarity is determined based on the reversal feature
685 * being enabled.
686 */
687 if (phy->polarity_correction) {
688 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
689 mask = IFE_PESC_POLARITY_REVERSED;
690 } else {
691 offset = IFE_PHY_SPECIAL_CONTROL;
692 mask = IFE_PSC_FORCE_POLARITY;
693 }
694
695 ret_val = e1e_rphy(hw, offset, &phy_data);
696
697 if (!ret_val)
698 phy->cable_polarity = (phy_data & mask)
699 ? e1000_rev_polarity_reversed
700 : e1000_rev_polarity_normal;
701
702 return ret_val;
703 }
704
705 /**
706 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
707 * @hw: pointer to the HW structure
708 * @active: TRUE to enable LPLU, FALSE to disable
709 *
710 * Sets the LPLU D0 state according to the active flag. When
711 * activating LPLU this function also disables smart speed
712 * and vice versa. LPLU will not be activated unless the
713 * device autonegotiation advertisement meets standards of
714 * either 10 or 10/100 or 10/100/1000 at all duplexes.
715 * This is a function pointer entry point only called by
716 * PHY setup routines.
717 **/
718 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
719 {
720 struct e1000_phy_info *phy = &hw->phy;
721 u32 phy_ctrl;
722 s32 ret_val = 0;
723 u16 data;
724
725 if (phy->type != e1000_phy_igp_3)
726 return ret_val;
727
728 phy_ctrl = er32(PHY_CTRL);
729
730 if (active) {
731 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
732 ew32(PHY_CTRL, phy_ctrl);
733
734 /* Call gig speed drop workaround on LPLU before accessing
735 * any PHY registers */
736 if ((hw->mac.type == e1000_ich8lan) &&
737 (hw->phy.type == e1000_phy_igp_3))
738 e1000e_gig_downshift_workaround_ich8lan(hw);
739
740 /* When LPLU is enabled, we should disable SmartSpeed */
741 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
742 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
743 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
744 if (ret_val)
745 return ret_val;
746 } else {
747 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
748 ew32(PHY_CTRL, phy_ctrl);
749
750 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
751 * during Dx states where the power conservation is most
752 * important. During driver activity we should enable
753 * SmartSpeed, so performance is maintained. */
754 if (phy->smart_speed == e1000_smart_speed_on) {
755 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
756 &data);
757 if (ret_val)
758 return ret_val;
759
760 data |= IGP01E1000_PSCFR_SMART_SPEED;
761 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
762 data);
763 if (ret_val)
764 return ret_val;
765 } else if (phy->smart_speed == e1000_smart_speed_off) {
766 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
767 &data);
768 if (ret_val)
769 return ret_val;
770
771 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
772 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
773 data);
774 if (ret_val)
775 return ret_val;
776 }
777 }
778
779 return 0;
780 }
781
782 /**
783 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
784 * @hw: pointer to the HW structure
785 * @active: TRUE to enable LPLU, FALSE to disable
786 *
787 * Sets the LPLU D3 state according to the active flag. When
788 * activating LPLU this function also disables smart speed
789 * and vice versa. LPLU will not be activated unless the
790 * device autonegotiation advertisement meets standards of
791 * either 10 or 10/100 or 10/100/1000 at all duplexes.
792 * This is a function pointer entry point only called by
793 * PHY setup routines.
794 **/
795 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
796 {
797 struct e1000_phy_info *phy = &hw->phy;
798 u32 phy_ctrl;
799 s32 ret_val;
800 u16 data;
801
802 phy_ctrl = er32(PHY_CTRL);
803
804 if (!active) {
805 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
806 ew32(PHY_CTRL, phy_ctrl);
807 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
808 * during Dx states where the power conservation is most
809 * important. During driver activity we should enable
810 * SmartSpeed, so performance is maintained. */
811 if (phy->smart_speed == e1000_smart_speed_on) {
812 ret_val = e1e_rphy(hw,
813 IGP01E1000_PHY_PORT_CONFIG,
814 &data);
815 if (ret_val)
816 return ret_val;
817
818 data |= IGP01E1000_PSCFR_SMART_SPEED;
819 ret_val = e1e_wphy(hw,
820 IGP01E1000_PHY_PORT_CONFIG,
821 data);
822 if (ret_val)
823 return ret_val;
824 } else if (phy->smart_speed == e1000_smart_speed_off) {
825 ret_val = e1e_rphy(hw,
826 IGP01E1000_PHY_PORT_CONFIG,
827 &data);
828 if (ret_val)
829 return ret_val;
830
831 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
832 ret_val = e1e_wphy(hw,
833 IGP01E1000_PHY_PORT_CONFIG,
834 data);
835 if (ret_val)
836 return ret_val;
837 }
838 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
839 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
840 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
841 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
842 ew32(PHY_CTRL, phy_ctrl);
843
844 /* Call gig speed drop workaround on LPLU before accessing
845 * any PHY registers */
846 if ((hw->mac.type == e1000_ich8lan) &&
847 (hw->phy.type == e1000_phy_igp_3))
848 e1000e_gig_downshift_workaround_ich8lan(hw);
849
850 /* When LPLU is enabled, we should disable SmartSpeed */
851 ret_val = e1e_rphy(hw,
852 IGP01E1000_PHY_PORT_CONFIG,
853 &data);
854 if (ret_val)
855 return ret_val;
856
857 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
858 ret_val = e1e_wphy(hw,
859 IGP01E1000_PHY_PORT_CONFIG,
860 data);
861 }
862
863 return 0;
864 }
865
866 /**
867 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
868 * @hw: pointer to the HW structure
869 * @offset: The offset (in bytes) of the word(s) to read.
870 * @words: Size of data to read in words
871 * @data: Pointer to the word(s) to read at offset.
872 *
873 * Reads a word(s) from the NVM using the flash access registers.
874 **/
875 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
876 u16 *data)
877 {
878 struct e1000_nvm_info *nvm = &hw->nvm;
879 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
880 u32 act_offset;
881 s32 ret_val;
882 u16 i, word;
883
884 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
885 (words == 0)) {
886 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
887 return -E1000_ERR_NVM;
888 }
889
890 ret_val = e1000_acquire_swflag_ich8lan(hw);
891 if (ret_val)
892 return ret_val;
893
894 /* Start with the bank offset, then add the relative offset. */
895 act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
896 ? nvm->flash_bank_size
897 : 0;
898 act_offset += offset;
899
900 for (i = 0; i < words; i++) {
901 if ((dev_spec->shadow_ram) &&
902 (dev_spec->shadow_ram[offset+i].modified)) {
903 data[i] = dev_spec->shadow_ram[offset+i].value;
904 } else {
905 ret_val = e1000_read_flash_word_ich8lan(hw,
906 act_offset + i,
907 &word);
908 if (ret_val)
909 break;
910 data[i] = word;
911 }
912 }
913
914 e1000_release_swflag_ich8lan(hw);
915
916 return ret_val;
917 }
918
919 /**
920 * e1000_flash_cycle_init_ich8lan - Initialize flash
921 * @hw: pointer to the HW structure
922 *
923 * This function does initial flash setup so that a new read/write/erase cycle
924 * can be started.
925 **/
926 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
927 {
928 union ich8_hws_flash_status hsfsts;
929 s32 ret_val = -E1000_ERR_NVM;
930 s32 i = 0;
931
932 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
933
934 /* Check if the flash descriptor is valid */
935 if (hsfsts.hsf_status.fldesvalid == 0) {
936 hw_dbg(hw, "Flash descriptor invalid. "
937 "SW Sequencing must be used.");
938 return -E1000_ERR_NVM;
939 }
940
941 /* Clear FCERR and DAEL in hw status by writing 1 */
942 hsfsts.hsf_status.flcerr = 1;
943 hsfsts.hsf_status.dael = 1;
944
945 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
946
947 /* Either we should have a hardware SPI cycle in progress
948 * bit to check against, in order to start a new cycle or
949 * FDONE bit should be changed in the hardware so that it
950 * is 1 after harware reset, which can then be used as an
951 * indication whether a cycle is in progress or has been
952 * completed.
953 */
954
955 if (hsfsts.hsf_status.flcinprog == 0) {
956 /* There is no cycle running at present,
957 * so we can start a cycle */
958 /* Begin by setting Flash Cycle Done. */
959 hsfsts.hsf_status.flcdone = 1;
960 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
961 ret_val = 0;
962 } else {
963 /* otherwise poll for sometime so the current
964 * cycle has a chance to end before giving up. */
965 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
966 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
967 if (hsfsts.hsf_status.flcinprog == 0) {
968 ret_val = 0;
969 break;
970 }
971 udelay(1);
972 }
973 if (ret_val == 0) {
974 /* Successful in waiting for previous cycle to timeout,
975 * now set the Flash Cycle Done. */
976 hsfsts.hsf_status.flcdone = 1;
977 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
978 } else {
979 hw_dbg(hw, "Flash controller busy, cannot get access");
980 }
981 }
982
983 return ret_val;
984 }
985
986 /**
987 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
988 * @hw: pointer to the HW structure
989 * @timeout: maximum time to wait for completion
990 *
991 * This function starts a flash cycle and waits for its completion.
992 **/
993 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
994 {
995 union ich8_hws_flash_ctrl hsflctl;
996 union ich8_hws_flash_status hsfsts;
997 s32 ret_val = -E1000_ERR_NVM;
998 u32 i = 0;
999
1000 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1001 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1002 hsflctl.hsf_ctrl.flcgo = 1;
1003 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1004
1005 /* wait till FDONE bit is set to 1 */
1006 do {
1007 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1008 if (hsfsts.hsf_status.flcdone == 1)
1009 break;
1010 udelay(1);
1011 } while (i++ < timeout);
1012
1013 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1014 return 0;
1015
1016 return ret_val;
1017 }
1018
1019 /**
1020 * e1000_read_flash_word_ich8lan - Read word from flash
1021 * @hw: pointer to the HW structure
1022 * @offset: offset to data location
1023 * @data: pointer to the location for storing the data
1024 *
1025 * Reads the flash word at offset into data. Offset is converted
1026 * to bytes before read.
1027 **/
1028 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1029 u16 *data)
1030 {
1031 /* Must convert offset into bytes. */
1032 offset <<= 1;
1033
1034 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1035 }
1036
1037 /**
1038 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1039 * @hw: pointer to the HW structure
1040 * @offset: The offset (in bytes) of the byte or word to read.
1041 * @size: Size of data to read, 1=byte 2=word
1042 * @data: Pointer to the word to store the value read.
1043 *
1044 * Reads a byte or word from the NVM using the flash access registers.
1045 **/
1046 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1047 u8 size, u16 *data)
1048 {
1049 union ich8_hws_flash_status hsfsts;
1050 union ich8_hws_flash_ctrl hsflctl;
1051 u32 flash_linear_addr;
1052 u32 flash_data = 0;
1053 s32 ret_val = -E1000_ERR_NVM;
1054 u8 count = 0;
1055
1056 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1057 return -E1000_ERR_NVM;
1058
1059 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1060 hw->nvm.flash_base_addr;
1061
1062 do {
1063 udelay(1);
1064 /* Steps */
1065 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1066 if (ret_val != 0)
1067 break;
1068
1069 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1070 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1071 hsflctl.hsf_ctrl.fldbcount = size - 1;
1072 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1073 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1074
1075 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1076
1077 ret_val = e1000_flash_cycle_ich8lan(hw,
1078 ICH_FLASH_READ_COMMAND_TIMEOUT);
1079
1080 /* Check if FCERR is set to 1, if set to 1, clear it
1081 * and try the whole sequence a few more times, else
1082 * read in (shift in) the Flash Data0, the order is
1083 * least significant byte first msb to lsb */
1084 if (ret_val == 0) {
1085 flash_data = er32flash(ICH_FLASH_FDATA0);
1086 if (size == 1) {
1087 *data = (u8)(flash_data & 0x000000FF);
1088 } else if (size == 2) {
1089 *data = (u16)(flash_data & 0x0000FFFF);
1090 }
1091 break;
1092 } else {
1093 /* If we've gotten here, then things are probably
1094 * completely hosed, but if the error condition is
1095 * detected, it won't hurt to give it another try...
1096 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1097 */
1098 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1099 if (hsfsts.hsf_status.flcerr == 1) {
1100 /* Repeat for some time before giving up. */
1101 continue;
1102 } else if (hsfsts.hsf_status.flcdone == 0) {
1103 hw_dbg(hw, "Timeout error - flash cycle "
1104 "did not complete.");
1105 break;
1106 }
1107 }
1108 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1109
1110 return ret_val;
1111 }
1112
1113 /**
1114 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1115 * @hw: pointer to the HW structure
1116 * @offset: The offset (in bytes) of the word(s) to write.
1117 * @words: Size of data to write in words
1118 * @data: Pointer to the word(s) to write at offset.
1119 *
1120 * Writes a byte or word to the NVM using the flash access registers.
1121 **/
1122 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1123 u16 *data)
1124 {
1125 struct e1000_nvm_info *nvm = &hw->nvm;
1126 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1127 s32 ret_val;
1128 u16 i;
1129
1130 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1131 (words == 0)) {
1132 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1133 return -E1000_ERR_NVM;
1134 }
1135
1136 ret_val = e1000_acquire_swflag_ich8lan(hw);
1137 if (ret_val)
1138 return ret_val;
1139
1140 for (i = 0; i < words; i++) {
1141 dev_spec->shadow_ram[offset+i].modified = 1;
1142 dev_spec->shadow_ram[offset+i].value = data[i];
1143 }
1144
1145 e1000_release_swflag_ich8lan(hw);
1146
1147 return 0;
1148 }
1149
1150 /**
1151 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1152 * @hw: pointer to the HW structure
1153 *
1154 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1155 * which writes the checksum to the shadow ram. The changes in the shadow
1156 * ram are then committed to the EEPROM by processing each bank at a time
1157 * checking for the modified bit and writing only the pending changes.
1158 * After a succesful commit, the shadow ram is cleared and is ready for
1159 * future writes.
1160 **/
1161 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1162 {
1163 struct e1000_nvm_info *nvm = &hw->nvm;
1164 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1165 u32 i, act_offset, new_bank_offset, old_bank_offset;
1166 s32 ret_val;
1167 u16 data;
1168
1169 ret_val = e1000e_update_nvm_checksum_generic(hw);
1170 if (ret_val)
1171 return ret_val;;
1172
1173 if (nvm->type != e1000_nvm_flash_sw)
1174 return ret_val;;
1175
1176 ret_val = e1000_acquire_swflag_ich8lan(hw);
1177 if (ret_val)
1178 return ret_val;;
1179
1180 /* We're writing to the opposite bank so if we're on bank 1,
1181 * write to bank 0 etc. We also need to erase the segment that
1182 * is going to be written */
1183 if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
1184 new_bank_offset = nvm->flash_bank_size;
1185 old_bank_offset = 0;
1186 e1000_erase_flash_bank_ich8lan(hw, 1);
1187 } else {
1188 old_bank_offset = nvm->flash_bank_size;
1189 new_bank_offset = 0;
1190 e1000_erase_flash_bank_ich8lan(hw, 0);
1191 }
1192
1193 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1194 /* Determine whether to write the value stored
1195 * in the other NVM bank or a modified value stored
1196 * in the shadow RAM */
1197 if (dev_spec->shadow_ram[i].modified) {
1198 data = dev_spec->shadow_ram[i].value;
1199 } else {
1200 e1000_read_flash_word_ich8lan(hw,
1201 i + old_bank_offset,
1202 &data);
1203 }
1204
1205 /* If the word is 0x13, then make sure the signature bits
1206 * (15:14) are 11b until the commit has completed.
1207 * This will allow us to write 10b which indicates the
1208 * signature is valid. We want to do this after the write
1209 * has completed so that we don't mark the segment valid
1210 * while the write is still in progress */
1211 if (i == E1000_ICH_NVM_SIG_WORD)
1212 data |= E1000_ICH_NVM_SIG_MASK;
1213
1214 /* Convert offset to bytes. */
1215 act_offset = (i + new_bank_offset) << 1;
1216
1217 udelay(100);
1218 /* Write the bytes to the new bank. */
1219 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1220 act_offset,
1221 (u8)data);
1222 if (ret_val)
1223 break;
1224
1225 udelay(100);
1226 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1227 act_offset + 1,
1228 (u8)(data >> 8));
1229 if (ret_val)
1230 break;
1231 }
1232
1233 /* Don't bother writing the segment valid bits if sector
1234 * programming failed. */
1235 if (ret_val) {
1236 hw_dbg(hw, "Flash commit failed.\n");
1237 e1000_release_swflag_ich8lan(hw);
1238 return ret_val;
1239 }
1240
1241 /* Finally validate the new segment by setting bit 15:14
1242 * to 10b in word 0x13 , this can be done without an
1243 * erase as well since these bits are 11 to start with
1244 * and we need to change bit 14 to 0b */
1245 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1246 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1247 data &= 0xBFFF;
1248 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1249 act_offset * 2 + 1,
1250 (u8)(data >> 8));
1251 if (ret_val) {
1252 e1000_release_swflag_ich8lan(hw);
1253 return ret_val;
1254 }
1255
1256 /* And invalidate the previously valid segment by setting
1257 * its signature word (0x13) high_byte to 0b. This can be
1258 * done without an erase because flash erase sets all bits
1259 * to 1's. We can write 1's to 0's without an erase */
1260 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1261 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1262 if (ret_val) {
1263 e1000_release_swflag_ich8lan(hw);
1264 return ret_val;
1265 }
1266
1267 /* Great! Everything worked, we can now clear the cached entries. */
1268 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1269 dev_spec->shadow_ram[i].modified = 0;
1270 dev_spec->shadow_ram[i].value = 0xFFFF;
1271 }
1272
1273 e1000_release_swflag_ich8lan(hw);
1274
1275 /* Reload the EEPROM, or else modifications will not appear
1276 * until after the next adapter reset.
1277 */
1278 e1000e_reload_nvm(hw);
1279 msleep(10);
1280
1281 return ret_val;
1282 }
1283
1284 /**
1285 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1286 * @hw: pointer to the HW structure
1287 *
1288 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1289 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1290 * calculated, in which case we need to calculate the checksum and set bit 6.
1291 **/
1292 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1293 {
1294 s32 ret_val;
1295 u16 data;
1296
1297 /* Read 0x19 and check bit 6. If this bit is 0, the checksum
1298 * needs to be fixed. This bit is an indication that the NVM
1299 * was prepared by OEM software and did not calculate the
1300 * checksum...a likely scenario.
1301 */
1302 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1303 if (ret_val)
1304 return ret_val;
1305
1306 if ((data & 0x40) == 0) {
1307 data |= 0x40;
1308 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1309 if (ret_val)
1310 return ret_val;
1311 ret_val = e1000e_update_nvm_checksum(hw);
1312 if (ret_val)
1313 return ret_val;
1314 }
1315
1316 return e1000e_validate_nvm_checksum_generic(hw);
1317 }
1318
1319 /**
1320 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1321 * @hw: pointer to the HW structure
1322 * @offset: The offset (in bytes) of the byte/word to read.
1323 * @size: Size of data to read, 1=byte 2=word
1324 * @data: The byte(s) to write to the NVM.
1325 *
1326 * Writes one/two bytes to the NVM using the flash access registers.
1327 **/
1328 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1329 u8 size, u16 data)
1330 {
1331 union ich8_hws_flash_status hsfsts;
1332 union ich8_hws_flash_ctrl hsflctl;
1333 u32 flash_linear_addr;
1334 u32 flash_data = 0;
1335 s32 ret_val;
1336 u8 count = 0;
1337
1338 if (size < 1 || size > 2 || data > size * 0xff ||
1339 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1340 return -E1000_ERR_NVM;
1341
1342 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1343 hw->nvm.flash_base_addr;
1344
1345 do {
1346 udelay(1);
1347 /* Steps */
1348 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1349 if (ret_val)
1350 break;
1351
1352 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1353 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1354 hsflctl.hsf_ctrl.fldbcount = size -1;
1355 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1356 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1357
1358 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1359
1360 if (size == 1)
1361 flash_data = (u32)data & 0x00FF;
1362 else
1363 flash_data = (u32)data;
1364
1365 ew32flash(ICH_FLASH_FDATA0, flash_data);
1366
1367 /* check if FCERR is set to 1 , if set to 1, clear it
1368 * and try the whole sequence a few more times else done */
1369 ret_val = e1000_flash_cycle_ich8lan(hw,
1370 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1371 if (!ret_val)
1372 break;
1373
1374 /* If we're here, then things are most likely
1375 * completely hosed, but if the error condition
1376 * is detected, it won't hurt to give it another
1377 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1378 */
1379 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1380 if (hsfsts.hsf_status.flcerr == 1)
1381 /* Repeat for some time before giving up. */
1382 continue;
1383 if (hsfsts.hsf_status.flcdone == 0) {
1384 hw_dbg(hw, "Timeout error - flash cycle "
1385 "did not complete.");
1386 break;
1387 }
1388 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1389
1390 return ret_val;
1391 }
1392
1393 /**
1394 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1395 * @hw: pointer to the HW structure
1396 * @offset: The index of the byte to read.
1397 * @data: The byte to write to the NVM.
1398 *
1399 * Writes a single byte to the NVM using the flash access registers.
1400 **/
1401 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1402 u8 data)
1403 {
1404 u16 word = (u16)data;
1405
1406 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1407 }
1408
1409 /**
1410 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1411 * @hw: pointer to the HW structure
1412 * @offset: The offset of the byte to write.
1413 * @byte: The byte to write to the NVM.
1414 *
1415 * Writes a single byte to the NVM using the flash access registers.
1416 * Goes through a retry algorithm before giving up.
1417 **/
1418 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1419 u32 offset, u8 byte)
1420 {
1421 s32 ret_val;
1422 u16 program_retries;
1423
1424 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1425 if (!ret_val)
1426 return ret_val;
1427
1428 for (program_retries = 0; program_retries < 100; program_retries++) {
1429 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1430 udelay(100);
1431 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1432 if (!ret_val)
1433 break;
1434 }
1435 if (program_retries == 100)
1436 return -E1000_ERR_NVM;
1437
1438 return 0;
1439 }
1440
1441 /**
1442 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1443 * @hw: pointer to the HW structure
1444 * @bank: 0 for first bank, 1 for second bank, etc.
1445 *
1446 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1447 * bank N is 4096 * N + flash_reg_addr.
1448 **/
1449 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1450 {
1451 struct e1000_nvm_info *nvm = &hw->nvm;
1452 union ich8_hws_flash_status hsfsts;
1453 union ich8_hws_flash_ctrl hsflctl;
1454 u32 flash_linear_addr;
1455 /* bank size is in 16bit words - adjust to bytes */
1456 u32 flash_bank_size = nvm->flash_bank_size * 2;
1457 s32 ret_val;
1458 s32 count = 0;
1459 s32 iteration;
1460 s32 sector_size;
1461 s32 j;
1462
1463 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1464
1465 /* Determine HW Sector size: Read BERASE bits of hw flash status
1466 * register */
1467 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
1468 * consecutive sectors. The start index for the nth Hw sector
1469 * can be calculated as = bank * 4096 + n * 256
1470 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1471 * The start index for the nth Hw sector can be calculated
1472 * as = bank * 4096
1473 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1474 * (ich9 only, otherwise error condition)
1475 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1476 */
1477 switch (hsfsts.hsf_status.berasesz) {
1478 case 0:
1479 /* Hw sector size 256 */
1480 sector_size = ICH_FLASH_SEG_SIZE_256;
1481 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1482 break;
1483 case 1:
1484 sector_size = ICH_FLASH_SEG_SIZE_4K;
1485 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1486 break;
1487 case 2:
1488 if (hw->mac.type == e1000_ich9lan) {
1489 sector_size = ICH_FLASH_SEG_SIZE_8K;
1490 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1491 } else {
1492 return -E1000_ERR_NVM;
1493 }
1494 break;
1495 case 3:
1496 sector_size = ICH_FLASH_SEG_SIZE_64K;
1497 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1498 break;
1499 default:
1500 return -E1000_ERR_NVM;
1501 }
1502
1503 /* Start with the base address, then add the sector offset. */
1504 flash_linear_addr = hw->nvm.flash_base_addr;
1505 flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1506
1507 for (j = 0; j < iteration ; j++) {
1508 do {
1509 /* Steps */
1510 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1511 if (ret_val)
1512 return ret_val;
1513
1514 /* Write a value 11 (block Erase) in Flash
1515 * Cycle field in hw flash control */
1516 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1517 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1518 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1519
1520 /* Write the last 24 bits of an index within the
1521 * block into Flash Linear address field in Flash
1522 * Address.
1523 */
1524 flash_linear_addr += (j * sector_size);
1525 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1526
1527 ret_val = e1000_flash_cycle_ich8lan(hw,
1528 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1529 if (ret_val == 0)
1530 break;
1531
1532 /* Check if FCERR is set to 1. If 1,
1533 * clear it and try the whole sequence
1534 * a few more times else Done */
1535 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1536 if (hsfsts.hsf_status.flcerr == 1)
1537 /* repeat for some time before
1538 * giving up */
1539 continue;
1540 else if (hsfsts.hsf_status.flcdone == 0)
1541 return ret_val;
1542 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1543 }
1544
1545 return 0;
1546 }
1547
1548 /**
1549 * e1000_valid_led_default_ich8lan - Set the default LED settings
1550 * @hw: pointer to the HW structure
1551 * @data: Pointer to the LED settings
1552 *
1553 * Reads the LED default settings from the NVM to data. If the NVM LED
1554 * settings is all 0's or F's, set the LED default to a valid LED default
1555 * setting.
1556 **/
1557 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1558 {
1559 s32 ret_val;
1560
1561 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1562 if (ret_val) {
1563 hw_dbg(hw, "NVM Read Error\n");
1564 return ret_val;
1565 }
1566
1567 if (*data == ID_LED_RESERVED_0000 ||
1568 *data == ID_LED_RESERVED_FFFF)
1569 *data = ID_LED_DEFAULT_ICH8LAN;
1570
1571 return 0;
1572 }
1573
1574 /**
1575 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1576 * @hw: pointer to the HW structure
1577 *
1578 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1579 * register, so the the bus width is hard coded.
1580 **/
1581 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1582 {
1583 struct e1000_bus_info *bus = &hw->bus;
1584 s32 ret_val;
1585
1586 ret_val = e1000e_get_bus_info_pcie(hw);
1587
1588 /* ICH devices are "PCI Express"-ish. They have
1589 * a configuration space, but do not contain
1590 * PCI Express Capability registers, so bus width
1591 * must be hardcoded.
1592 */
1593 if (bus->width == e1000_bus_width_unknown)
1594 bus->width = e1000_bus_width_pcie_x1;
1595
1596 return ret_val;
1597 }
1598
1599 /**
1600 * e1000_reset_hw_ich8lan - Reset the hardware
1601 * @hw: pointer to the HW structure
1602 *
1603 * Does a full reset of the hardware which includes a reset of the PHY and
1604 * MAC.
1605 **/
1606 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1607 {
1608 u32 ctrl, icr, kab;
1609 s32 ret_val;
1610
1611 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1612 * on the last TLP read/write transaction when MAC is reset.
1613 */
1614 ret_val = e1000e_disable_pcie_master(hw);
1615 if (ret_val) {
1616 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1617 }
1618
1619 hw_dbg(hw, "Masking off all interrupts\n");
1620 ew32(IMC, 0xffffffff);
1621
1622 /* Disable the Transmit and Receive units. Then delay to allow
1623 * any pending transactions to complete before we hit the MAC
1624 * with the global reset.
1625 */
1626 ew32(RCTL, 0);
1627 ew32(TCTL, E1000_TCTL_PSP);
1628 e1e_flush();
1629
1630 msleep(10);
1631
1632 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1633 if (hw->mac.type == e1000_ich8lan) {
1634 /* Set Tx and Rx buffer allocation to 8k apiece. */
1635 ew32(PBA, E1000_PBA_8K);
1636 /* Set Packet Buffer Size to 16k. */
1637 ew32(PBS, E1000_PBS_16K);
1638 }
1639
1640 ctrl = er32(CTRL);
1641
1642 if (!e1000_check_reset_block(hw)) {
1643 /* PHY HW reset requires MAC CORE reset at the same
1644 * time to make sure the interface between MAC and the
1645 * external PHY is reset.
1646 */
1647 ctrl |= E1000_CTRL_PHY_RST;
1648 }
1649 ret_val = e1000_acquire_swflag_ich8lan(hw);
1650 hw_dbg(hw, "Issuing a global reset to ich8lan");
1651 ew32(CTRL, (ctrl | E1000_CTRL_RST));
1652 msleep(20);
1653
1654 ret_val = e1000e_get_auto_rd_done(hw);
1655 if (ret_val) {
1656 /*
1657 * When auto config read does not complete, do not
1658 * return with an error. This can happen in situations
1659 * where there is no eeprom and prevents getting link.
1660 */
1661 hw_dbg(hw, "Auto Read Done did not complete\n");
1662 }
1663
1664 ew32(IMC, 0xffffffff);
1665 icr = er32(ICR);
1666
1667 kab = er32(KABGTXD);
1668 kab |= E1000_KABGTXD_BGSQLBIAS;
1669 ew32(KABGTXD, kab);
1670
1671 return ret_val;
1672 }
1673
1674 /**
1675 * e1000_init_hw_ich8lan - Initialize the hardware
1676 * @hw: pointer to the HW structure
1677 *
1678 * Prepares the hardware for transmit and receive by doing the following:
1679 * - initialize hardware bits
1680 * - initialize LED identification
1681 * - setup receive address registers
1682 * - setup flow control
1683 * - setup transmit discriptors
1684 * - clear statistics
1685 **/
1686 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1687 {
1688 struct e1000_mac_info *mac = &hw->mac;
1689 u32 ctrl_ext, txdctl, snoop;
1690 s32 ret_val;
1691 u16 i;
1692
1693 e1000_initialize_hw_bits_ich8lan(hw);
1694
1695 /* Initialize identification LED */
1696 ret_val = e1000e_id_led_init(hw);
1697 if (ret_val) {
1698 hw_dbg(hw, "Error initializing identification LED\n");
1699 return ret_val;
1700 }
1701
1702 /* Setup the receive address. */
1703 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1704
1705 /* Zero out the Multicast HASH table */
1706 hw_dbg(hw, "Zeroing the MTA\n");
1707 for (i = 0; i < mac->mta_reg_count; i++)
1708 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1709
1710 /* Setup link and flow control */
1711 ret_val = e1000_setup_link_ich8lan(hw);
1712
1713 /* Set the transmit descriptor write-back policy for both queues */
1714 txdctl = er32(TXDCTL);
1715 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1716 E1000_TXDCTL_FULL_TX_DESC_WB;
1717 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1718 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1719 ew32(TXDCTL, txdctl);
1720 txdctl = er32(TXDCTL1);
1721 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1722 E1000_TXDCTL_FULL_TX_DESC_WB;
1723 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1724 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1725 ew32(TXDCTL1, txdctl);
1726
1727 /* ICH8 has opposite polarity of no_snoop bits.
1728 * By default, we should use snoop behavior. */
1729 if (mac->type == e1000_ich8lan)
1730 snoop = PCIE_ICH8_SNOOP_ALL;
1731 else
1732 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1733 e1000e_set_pcie_no_snoop(hw, snoop);
1734
1735 ctrl_ext = er32(CTRL_EXT);
1736 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1737 ew32(CTRL_EXT, ctrl_ext);
1738
1739 /* Clear all of the statistics registers (clear on read). It is
1740 * important that we do this after we have tried to establish link
1741 * because the symbol error count will increment wildly if there
1742 * is no link.
1743 */
1744 e1000_clear_hw_cntrs_ich8lan(hw);
1745
1746 return 0;
1747 }
1748 /**
1749 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1750 * @hw: pointer to the HW structure
1751 *
1752 * Sets/Clears required hardware bits necessary for correctly setting up the
1753 * hardware for transmit and receive.
1754 **/
1755 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1756 {
1757 u32 reg;
1758
1759 /* Extended Device Control */
1760 reg = er32(CTRL_EXT);
1761 reg |= (1 << 22);
1762 ew32(CTRL_EXT, reg);
1763
1764 /* Transmit Descriptor Control 0 */
1765 reg = er32(TXDCTL);
1766 reg |= (1 << 22);
1767 ew32(TXDCTL, reg);
1768
1769 /* Transmit Descriptor Control 1 */
1770 reg = er32(TXDCTL1);
1771 reg |= (1 << 22);
1772 ew32(TXDCTL1, reg);
1773
1774 /* Transmit Arbitration Control 0 */
1775 reg = er32(TARC0);
1776 if (hw->mac.type == e1000_ich8lan)
1777 reg |= (1 << 28) | (1 << 29);
1778 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
1779 ew32(TARC0, reg);
1780
1781 /* Transmit Arbitration Control 1 */
1782 reg = er32(TARC1);
1783 if (er32(TCTL) & E1000_TCTL_MULR)
1784 reg &= ~(1 << 28);
1785 else
1786 reg |= (1 << 28);
1787 reg |= (1 << 24) | (1 << 26) | (1 << 30);
1788 ew32(TARC1, reg);
1789
1790 /* Device Status */
1791 if (hw->mac.type == e1000_ich8lan) {
1792 reg = er32(STATUS);
1793 reg &= ~(1 << 31);
1794 ew32(STATUS, reg);
1795 }
1796 }
1797
1798 /**
1799 * e1000_setup_link_ich8lan - Setup flow control and link settings
1800 * @hw: pointer to the HW structure
1801 *
1802 * Determines which flow control settings to use, then configures flow
1803 * control. Calls the appropriate media-specific link configuration
1804 * function. Assuming the adapter has a valid link partner, a valid link
1805 * should be established. Assumes the hardware has previously been reset
1806 * and the transmitter and receiver are not enabled.
1807 **/
1808 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
1809 {
1810 struct e1000_mac_info *mac = &hw->mac;
1811 s32 ret_val;
1812
1813 if (e1000_check_reset_block(hw))
1814 return 0;
1815
1816 /* ICH parts do not have a word in the NVM to determine
1817 * the default flow control setting, so we explicitly
1818 * set it to full.
1819 */
1820 if (mac->fc == e1000_fc_default)
1821 mac->fc = e1000_fc_full;
1822
1823 mac->original_fc = mac->fc;
1824
1825 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", mac->fc);
1826
1827 /* Continue to configure the copper link. */
1828 ret_val = e1000_setup_copper_link_ich8lan(hw);
1829 if (ret_val)
1830 return ret_val;
1831
1832 ew32(FCTTV, mac->fc_pause_time);
1833
1834 return e1000e_set_fc_watermarks(hw);
1835 }
1836
1837 /**
1838 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
1839 * @hw: pointer to the HW structure
1840 *
1841 * Configures the kumeran interface to the PHY to wait the appropriate time
1842 * when polling the PHY, then call the generic setup_copper_link to finish
1843 * configuring the copper link.
1844 **/
1845 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
1846 {
1847 u32 ctrl;
1848 s32 ret_val;
1849 u16 reg_data;
1850
1851 ctrl = er32(CTRL);
1852 ctrl |= E1000_CTRL_SLU;
1853 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1854 ew32(CTRL, ctrl);
1855
1856 /* Set the mac to wait the maximum time between each iteration
1857 * and increase the max iterations when polling the phy;
1858 * this fixes erroneous timeouts at 10Mbps. */
1859 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1860 if (ret_val)
1861 return ret_val;
1862 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1863 if (ret_val)
1864 return ret_val;
1865 reg_data |= 0x3F;
1866 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1867 if (ret_val)
1868 return ret_val;
1869
1870 if (hw->phy.type == e1000_phy_igp_3) {
1871 ret_val = e1000e_copper_link_setup_igp(hw);
1872 if (ret_val)
1873 return ret_val;
1874 }
1875
1876 return e1000e_setup_copper_link(hw);
1877 }
1878
1879 /**
1880 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
1881 * @hw: pointer to the HW structure
1882 * @speed: pointer to store current link speed
1883 * @duplex: pointer to store the current link duplex
1884 *
1885 * Calls the generic get_speed_and_duplex to retreive the current link
1886 * information and then calls the Kumeran lock loss workaround for links at
1887 * gigabit speeds.
1888 **/
1889 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
1890 u16 *duplex)
1891 {
1892 s32 ret_val;
1893
1894 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
1895 if (ret_val)
1896 return ret_val;
1897
1898 if ((hw->mac.type == e1000_ich8lan) &&
1899 (hw->phy.type == e1000_phy_igp_3) &&
1900 (*speed == SPEED_1000)) {
1901 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
1902 }
1903
1904 return ret_val;
1905 }
1906
1907 /**
1908 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
1909 * @hw: pointer to the HW structure
1910 *
1911 * Work-around for 82566 Kumeran PCS lock loss:
1912 * On link status change (i.e. PCI reset, speed change) and link is up and
1913 * speed is gigabit-
1914 * 0) if workaround is optionally disabled do nothing
1915 * 1) wait 1ms for Kumeran link to come up
1916 * 2) check Kumeran Diagnostic register PCS lock loss bit
1917 * 3) if not set the link is locked (all is good), otherwise...
1918 * 4) reset the PHY
1919 * 5) repeat up to 10 times
1920 * Note: this is only called for IGP3 copper when speed is 1gb.
1921 **/
1922 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
1923 {
1924 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1925 u32 phy_ctrl;
1926 s32 ret_val;
1927 u16 i, data;
1928 bool link;
1929
1930 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
1931 return 0;
1932
1933 /* Make sure link is up before proceeding. If not just return.
1934 * Attempting this while link is negotiating fouled up link
1935 * stability */
1936 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1937 if (!link)
1938 return 0;
1939
1940 for (i = 0; i < 10; i++) {
1941 /* read once to clear */
1942 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
1943 if (ret_val)
1944 return ret_val;
1945 /* and again to get new status */
1946 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 /* check for PCS lock */
1951 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
1952 return 0;
1953
1954 /* Issue PHY reset */
1955 e1000_phy_hw_reset(hw);
1956 mdelay(5);
1957 }
1958 /* Disable GigE link negotiation */
1959 phy_ctrl = er32(PHY_CTRL);
1960 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
1961 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
1962 ew32(PHY_CTRL, phy_ctrl);
1963
1964 /* Call gig speed drop workaround on Giga disable before accessing
1965 * any PHY registers */
1966 e1000e_gig_downshift_workaround_ich8lan(hw);
1967
1968 /* unable to acquire PCS lock */
1969 return -E1000_ERR_PHY;
1970 }
1971
1972 /**
1973 * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
1974 * @hw: pointer to the HW structure
1975 * @state: boolean value used to set the current Kumaran workaround state
1976 *
1977 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
1978 * /disabled - FALSE).
1979 **/
1980 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
1981 bool state)
1982 {
1983 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1984
1985 if (hw->mac.type != e1000_ich8lan) {
1986 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
1987 return;
1988 }
1989
1990 dev_spec->kmrn_lock_loss_workaround_enabled = state;
1991 }
1992
1993 /**
1994 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
1995 * @hw: pointer to the HW structure
1996 *
1997 * Workaround for 82566 power-down on D3 entry:
1998 * 1) disable gigabit link
1999 * 2) write VR power-down enable
2000 * 3) read it back
2001 * Continue if successful, else issue LCD reset and repeat
2002 **/
2003 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2004 {
2005 u32 reg;
2006 u16 data;
2007 u8 retry = 0;
2008
2009 if (hw->phy.type != e1000_phy_igp_3)
2010 return;
2011
2012 /* Try the workaround twice (if needed) */
2013 do {
2014 /* Disable link */
2015 reg = er32(PHY_CTRL);
2016 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2017 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2018 ew32(PHY_CTRL, reg);
2019
2020 /* Call gig speed drop workaround on Giga disable before
2021 * accessing any PHY registers */
2022 if (hw->mac.type == e1000_ich8lan)
2023 e1000e_gig_downshift_workaround_ich8lan(hw);
2024
2025 /* Write VR power-down enable */
2026 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2027 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2028 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2029
2030 /* Read it back and test */
2031 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2032 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2033 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2034 break;
2035
2036 /* Issue PHY reset and repeat at most one more time */
2037 reg = er32(CTRL);
2038 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2039 retry++;
2040 } while (retry);
2041 }
2042
2043 /**
2044 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2045 * @hw: pointer to the HW structure
2046 *
2047 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2048 * LPLU, Giga disable, MDIC PHY reset):
2049 * 1) Set Kumeran Near-end loopback
2050 * 2) Clear Kumeran Near-end loopback
2051 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2052 **/
2053 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2054 {
2055 s32 ret_val;
2056 u16 reg_data;
2057
2058 if ((hw->mac.type != e1000_ich8lan) ||
2059 (hw->phy.type != e1000_phy_igp_3))
2060 return;
2061
2062 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2063 &reg_data);
2064 if (ret_val)
2065 return;
2066 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2067 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2068 reg_data);
2069 if (ret_val)
2070 return;
2071 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2072 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2073 reg_data);
2074 }
2075
2076 /**
2077 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2078 * @hw: pointer to the HW structure
2079 *
2080 * Return the LED back to the default configuration.
2081 **/
2082 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2083 {
2084 if (hw->phy.type == e1000_phy_ife)
2085 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2086
2087 ew32(LEDCTL, hw->mac.ledctl_default);
2088 return 0;
2089 }
2090
2091 /**
2092 * e1000_led_on_ich8lan - Turn LED's on
2093 * @hw: pointer to the HW structure
2094 *
2095 * Turn on the LED's.
2096 **/
2097 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2098 {
2099 if (hw->phy.type == e1000_phy_ife)
2100 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2101 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2102
2103 ew32(LEDCTL, hw->mac.ledctl_mode2);
2104 return 0;
2105 }
2106
2107 /**
2108 * e1000_led_off_ich8lan - Turn LED's off
2109 * @hw: pointer to the HW structure
2110 *
2111 * Turn off the LED's.
2112 **/
2113 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2114 {
2115 if (hw->phy.type == e1000_phy_ife)
2116 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2117 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2118
2119 ew32(LEDCTL, hw->mac.ledctl_mode1);
2120 return 0;
2121 }
2122
2123 /**
2124 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2125 * @hw: pointer to the HW structure
2126 *
2127 * Clears hardware counters specific to the silicon family and calls
2128 * clear_hw_cntrs_generic to clear all general purpose counters.
2129 **/
2130 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2131 {
2132 u32 temp;
2133
2134 e1000e_clear_hw_cntrs_base(hw);
2135
2136 temp = er32(ALGNERRC);
2137 temp = er32(RXERRC);
2138 temp = er32(TNCRS);
2139 temp = er32(CEXTERR);
2140 temp = er32(TSCTC);
2141 temp = er32(TSCTFC);
2142
2143 temp = er32(MGTPRC);
2144 temp = er32(MGTPDC);
2145 temp = er32(MGTPTC);
2146
2147 temp = er32(IAC);
2148 temp = er32(ICRXOC);
2149
2150 }
2151
2152 static struct e1000_mac_operations ich8_mac_ops = {
2153 .mng_mode_enab = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
2154 .check_for_link = e1000e_check_for_copper_link,
2155 .cleanup_led = e1000_cleanup_led_ich8lan,
2156 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
2157 .get_bus_info = e1000_get_bus_info_ich8lan,
2158 .get_link_up_info = e1000_get_link_up_info_ich8lan,
2159 .led_on = e1000_led_on_ich8lan,
2160 .led_off = e1000_led_off_ich8lan,
2161 .mc_addr_list_update = e1000e_mc_addr_list_update_generic,
2162 .reset_hw = e1000_reset_hw_ich8lan,
2163 .init_hw = e1000_init_hw_ich8lan,
2164 .setup_link = e1000_setup_link_ich8lan,
2165 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2166 };
2167
2168 static struct e1000_phy_operations ich8_phy_ops = {
2169 .acquire_phy = e1000_acquire_swflag_ich8lan,
2170 .check_reset_block = e1000_check_reset_block_ich8lan,
2171 .commit_phy = NULL,
2172 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
2173 .get_cfg_done = e1000e_get_cfg_done,
2174 .get_cable_length = e1000e_get_cable_length_igp_2,
2175 .get_phy_info = e1000_get_phy_info_ich8lan,
2176 .read_phy_reg = e1000e_read_phy_reg_igp,
2177 .release_phy = e1000_release_swflag_ich8lan,
2178 .reset_phy = e1000_phy_hw_reset_ich8lan,
2179 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
2180 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
2181 .write_phy_reg = e1000e_write_phy_reg_igp,
2182 };
2183
2184 static struct e1000_nvm_operations ich8_nvm_ops = {
2185 .acquire_nvm = e1000_acquire_swflag_ich8lan,
2186 .read_nvm = e1000_read_nvm_ich8lan,
2187 .release_nvm = e1000_release_swflag_ich8lan,
2188 .update_nvm = e1000_update_nvm_checksum_ich8lan,
2189 .valid_led_default = e1000_valid_led_default_ich8lan,
2190 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
2191 .write_nvm = e1000_write_nvm_ich8lan,
2192 };
2193
2194 struct e1000_info e1000_ich8_info = {
2195 .mac = e1000_ich8lan,
2196 .flags = FLAG_HAS_WOL
2197 | FLAG_RX_CSUM_ENABLED
2198 | FLAG_HAS_CTRLEXT_ON_LOAD
2199 | FLAG_HAS_AMT
2200 | FLAG_HAS_FLASH
2201 | FLAG_APME_IN_WUC,
2202 .pba = 8,
2203 .get_invariants = e1000_get_invariants_ich8lan,
2204 .mac_ops = &ich8_mac_ops,
2205 .phy_ops = &ich8_phy_ops,
2206 .nvm_ops = &ich8_nvm_ops,
2207 };
2208
2209 struct e1000_info e1000_ich9_info = {
2210 .mac = e1000_ich9lan,
2211 .flags = FLAG_HAS_JUMBO_FRAMES
2212 | FLAG_HAS_WOL
2213 | FLAG_RX_CSUM_ENABLED
2214 | FLAG_HAS_CTRLEXT_ON_LOAD
2215 | FLAG_HAS_AMT
2216 | FLAG_HAS_ERT
2217 | FLAG_HAS_FLASH
2218 | FLAG_APME_IN_WUC,
2219 .pba = 10,
2220 .get_invariants = e1000_get_invariants_ich8lan,
2221 .mac_ops = &ich8_mac_ops,
2222 .phy_ops = &ich8_phy_ops,
2223 .nvm_ops = &ich8_nvm_ops,
2224 };
2225
Linux kernel - Deliverables
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