1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
57 #include <linux/netdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/delay.h>
60 #include <linux/pci.h>
64 #define ICH_FLASH_GFPREG 0x0000
65 #define ICH_FLASH_HSFSTS 0x0004
66 #define ICH_FLASH_HSFCTL 0x0006
67 #define ICH_FLASH_FADDR 0x0008
68 #define ICH_FLASH_FDATA0 0x0010
69 #define ICH_FLASH_PR0 0x0074
71 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
74 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
75 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
77 #define ICH_CYCLE_READ 0
78 #define ICH_CYCLE_WRITE 2
79 #define ICH_CYCLE_ERASE 3
81 #define FLASH_GFPREG_BASE_MASK 0x1FFF
82 #define FLASH_SECTOR_ADDR_SHIFT 12
84 #define ICH_FLASH_SEG_SIZE_256 256
85 #define ICH_FLASH_SEG_SIZE_4K 4096
86 #define ICH_FLASH_SEG_SIZE_8K 8192
87 #define ICH_FLASH_SEG_SIZE_64K 65536
90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
92 #define E1000_ICH_MNG_IAMT_MODE 0x2
94 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
95 (ID_LED_DEF1_OFF2 << 8) | \
96 (ID_LED_DEF1_ON2 << 4) | \
99 #define E1000_ICH_NVM_SIG_WORD 0x13
100 #define E1000_ICH_NVM_SIG_MASK 0xC000
101 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
102 #define E1000_ICH_NVM_SIG_VALUE 0x80
104 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
106 #define E1000_FEXTNVM_SW_CONFIG 1
107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
109 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
111 #define E1000_ICH_RAR_ENTRIES 7
113 #define PHY_PAGE_SHIFT 5
114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
115 ((reg) & MAX_PHY_REG_ADDRESS))
116 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
117 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
121 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
123 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
125 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
126 /* Offset 04h HSFSTS */
127 union ich8_hws_flash_status
{
129 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
130 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
131 u16 dael
:1; /* bit 2 Direct Access error Log */
132 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
133 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
134 u16 reserved1
:2; /* bit 13:6 Reserved */
135 u16 reserved2
:6; /* bit 13:6 Reserved */
136 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
137 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
142 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
143 /* Offset 06h FLCTL */
144 union ich8_hws_flash_ctrl
{
145 struct ich8_hsflctl
{
146 u16 flcgo
:1; /* 0 Flash Cycle Go */
147 u16 flcycle
:2; /* 2:1 Flash Cycle */
148 u16 reserved
:5; /* 7:3 Reserved */
149 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
150 u16 flockdn
:6; /* 15:10 Reserved */
155 /* ICH Flash Region Access Permissions */
156 union ich8_hws_flash_regacc
{
158 u32 grra
:8; /* 0:7 GbE region Read Access */
159 u32 grwa
:8; /* 8:15 GbE region Write Access */
160 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
161 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
166 /* ICH Flash Protected Region */
167 union ich8_flash_protected_range
{
169 u32 base
:13; /* 0:12 Protected Range Base */
170 u32 reserved1
:2; /* 13:14 Reserved */
171 u32 rpe
:1; /* 15 Read Protection Enable */
172 u32 limit
:13; /* 16:28 Protected Range Limit */
173 u32 reserved2
:2; /* 29:30 Reserved */
174 u32 wpe
:1; /* 31 Write Protection Enable */
179 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
180 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
181 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
182 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
);
183 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
184 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
185 u32 offset
, u8 byte
);
186 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
188 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
190 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
192 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
193 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
194 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
195 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
196 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
197 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
198 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
199 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
200 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
201 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
202 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
204 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
206 return readw(hw
->flash_address
+ reg
);
209 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
211 return readl(hw
->flash_address
+ reg
);
214 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
216 writew(val
, hw
->flash_address
+ reg
);
219 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
221 writel(val
, hw
->flash_address
+ reg
);
224 #define er16flash(reg) __er16flash(hw, (reg))
225 #define er32flash(reg) __er32flash(hw, (reg))
226 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
227 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
230 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
231 * @hw: pointer to the HW structure
233 * Initialize family-specific PHY parameters and function pointers.
235 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
237 struct e1000_phy_info
*phy
= &hw
->phy
;
241 phy
->reset_delay_us
= 100;
243 phy
->ops
.check_polarity
= e1000_check_polarity_ife_ich8lan
;
244 phy
->ops
.read_phy_reg
= e1000_read_phy_reg_hv
;
245 phy
->ops
.write_phy_reg
= e1000_write_phy_reg_hv
;
246 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
248 phy
->id
= e1000_phy_unknown
;
249 e1000e_get_phy_id(hw
);
250 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
252 if (phy
->type
== e1000_phy_82577
) {
253 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
254 phy
->ops
.force_speed_duplex
=
255 e1000_phy_force_speed_duplex_82577
;
256 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
257 phy
->ops
.get_phy_info
= e1000_get_phy_info_82577
;
258 phy
->ops
.commit_phy
= e1000e_phy_sw_reset
;
265 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
266 * @hw: pointer to the HW structure
268 * Initialize family-specific PHY parameters and function pointers.
270 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
272 struct e1000_phy_info
*phy
= &hw
->phy
;
277 phy
->reset_delay_us
= 100;
280 * We may need to do this twice - once for IGP and if that fails,
281 * we'll set BM func pointers and try again
283 ret_val
= e1000e_determine_phy_address(hw
);
285 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
286 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
287 ret_val
= e1000e_determine_phy_address(hw
);
293 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
296 ret_val
= e1000e_get_phy_id(hw
);
303 case IGP03E1000_E_PHY_ID
:
304 phy
->type
= e1000_phy_igp_3
;
305 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
308 case IFE_PLUS_E_PHY_ID
:
310 phy
->type
= e1000_phy_ife
;
311 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
313 case BME1000_E_PHY_ID
:
314 phy
->type
= e1000_phy_bm
;
315 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
316 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
317 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
318 hw
->phy
.ops
.commit_phy
= e1000e_phy_sw_reset
;
321 return -E1000_ERR_PHY
;
325 phy
->ops
.check_polarity
= e1000_check_polarity_ife_ich8lan
;
331 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
332 * @hw: pointer to the HW structure
334 * Initialize family-specific NVM parameters and function
337 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
339 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
340 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
342 u32 sector_base_addr
;
346 /* Can't read flash registers if the register set isn't mapped. */
347 if (!hw
->flash_address
) {
348 hw_dbg(hw
, "ERROR: Flash registers not mapped\n");
349 return -E1000_ERR_CONFIG
;
352 nvm
->type
= e1000_nvm_flash_sw
;
354 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
357 * sector_X_addr is a "sector"-aligned address (4096 bytes)
358 * Add 1 to sector_end_addr since this sector is included in
361 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
362 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
364 /* flash_base_addr is byte-aligned */
365 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
368 * find total size of the NVM, then cut in half since the total
369 * size represents two separate NVM banks.
371 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
372 << FLASH_SECTOR_ADDR_SHIFT
;
373 nvm
->flash_bank_size
/= 2;
374 /* Adjust to word count */
375 nvm
->flash_bank_size
/= sizeof(u16
);
377 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
379 /* Clear shadow ram */
380 for (i
= 0; i
< nvm
->word_size
; i
++) {
381 dev_spec
->shadow_ram
[i
].modified
= 0;
382 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
389 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
390 * @hw: pointer to the HW structure
392 * Initialize family-specific MAC parameters and function
395 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
397 struct e1000_hw
*hw
= &adapter
->hw
;
398 struct e1000_mac_info
*mac
= &hw
->mac
;
400 /* Set media type function pointer */
401 hw
->phy
.media_type
= e1000_media_type_copper
;
403 /* Set mta register count */
404 mac
->mta_reg_count
= 32;
405 /* Set rar entry count */
406 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
407 if (mac
->type
== e1000_ich8lan
)
408 mac
->rar_entry_count
--;
409 /* Set if manageability features are enabled. */
410 mac
->arc_subsystem_valid
= 1;
418 mac
->ops
.id_led_init
= e1000e_id_led_init
;
420 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
422 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
423 /* turn on/off LED */
424 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
425 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
429 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
431 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
433 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
434 /* turn on/off LED */
435 mac
->ops
.led_on
= e1000_led_on_pchlan
;
436 mac
->ops
.led_off
= e1000_led_off_pchlan
;
442 /* Enable PCS Lock-loss workaround for ICH8 */
443 if (mac
->type
== e1000_ich8lan
)
444 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, 1);
449 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
451 struct e1000_hw
*hw
= &adapter
->hw
;
454 rc
= e1000_init_mac_params_ich8lan(adapter
);
458 rc
= e1000_init_nvm_params_ich8lan(hw
);
462 if (hw
->mac
.type
== e1000_pchlan
)
463 rc
= e1000_init_phy_params_pchlan(hw
);
465 rc
= e1000_init_phy_params_ich8lan(hw
);
469 if (adapter
->hw
.phy
.type
== e1000_phy_ife
) {
470 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
471 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
474 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
475 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
476 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
481 static DEFINE_MUTEX(nvm_mutex
);
484 * e1000_acquire_swflag_ich8lan - Acquire software control flag
485 * @hw: pointer to the HW structure
487 * Acquires the software control flag for performing NVM and PHY
488 * operations. This is a function pointer entry point only called by
489 * read/write routines for the PHY and NVM parts.
491 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
494 u32 timeout
= PHY_CFG_TIMEOUT
;
498 mutex_lock(&nvm_mutex
);
501 extcnf_ctrl
= er32(EXTCNF_CTRL
);
503 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)) {
504 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
505 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
507 extcnf_ctrl
= er32(EXTCNF_CTRL
);
508 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
516 hw_dbg(hw
, "FW or HW has locked the resource for too long.\n");
517 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
518 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
519 mutex_unlock(&nvm_mutex
);
520 return -E1000_ERR_CONFIG
;
527 * e1000_release_swflag_ich8lan - Release software control flag
528 * @hw: pointer to the HW structure
530 * Releases the software control flag for performing NVM and PHY operations.
531 * This is a function pointer entry point only called by read/write
532 * routines for the PHY and NVM parts.
534 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
538 extcnf_ctrl
= er32(EXTCNF_CTRL
);
539 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
540 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
542 mutex_unlock(&nvm_mutex
);
546 * e1000_check_mng_mode_ich8lan - Checks management mode
547 * @hw: pointer to the HW structure
549 * This checks if the adapter has manageability enabled.
550 * This is a function pointer entry point only called by read/write
551 * routines for the PHY and NVM parts.
553 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
555 u32 fwsm
= er32(FWSM
);
557 return (fwsm
& E1000_FWSM_MODE_MASK
) ==
558 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
);
562 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
563 * @hw: pointer to the HW structure
565 * Checks if firmware is blocking the reset of the PHY.
566 * This is a function pointer entry point only called by
569 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
575 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
579 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
580 * @hw: pointer to the HW structure
582 * Forces the speed and duplex settings of the PHY.
583 * This is a function pointer entry point only called by
584 * PHY setup routines.
586 static s32
e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw
*hw
)
588 struct e1000_phy_info
*phy
= &hw
->phy
;
593 if (phy
->type
!= e1000_phy_ife
) {
594 ret_val
= e1000e_phy_force_speed_duplex_igp(hw
);
598 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
602 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
604 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
608 /* Disable MDI-X support for 10/100 */
609 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
613 data
&= ~IFE_PMC_AUTO_MDIX
;
614 data
&= ~IFE_PMC_FORCE_MDIX
;
616 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
620 hw_dbg(hw
, "IFE PMC: %X\n", data
);
624 if (phy
->autoneg_wait_to_complete
) {
625 hw_dbg(hw
, "Waiting for forced speed/duplex link on IFE phy.\n");
627 ret_val
= e1000e_phy_has_link_generic(hw
,
635 hw_dbg(hw
, "Link taking longer than expected.\n");
638 ret_val
= e1000e_phy_has_link_generic(hw
,
650 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
651 * done after every PHY reset.
653 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
657 if (hw
->mac
.type
!= e1000_pchlan
)
660 if (((hw
->phy
.type
== e1000_phy_82577
) &&
661 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
662 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
663 /* Disable generation of early preamble */
664 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
668 /* Preamble tuning for SSC */
669 ret_val
= e1e_wphy(hw
, PHY_REG(770, 16), 0xA204);
674 if (hw
->phy
.type
== e1000_phy_82578
) {
676 * Return registers to default by doing a soft reset then
677 * writing 0x3140 to the control register.
679 if (hw
->phy
.revision
< 2) {
680 e1000e_phy_sw_reset(hw
);
681 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, 0x3140);
686 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
690 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
691 hw
->phy
.ops
.release_phy(hw
);
697 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
698 * @hw: pointer to the HW structure
701 * This is a function pointer entry point called by drivers
702 * or other shared routines.
704 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
706 struct e1000_phy_info
*phy
= &hw
->phy
;
708 u32 data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
710 u16 loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
711 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
713 ret_val
= e1000e_phy_hw_reset_generic(hw
);
717 if (hw
->mac
.type
== e1000_pchlan
) {
718 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
724 * Initialize the PHY from the NVM on ICH platforms. This
725 * is needed due to an issue where the NVM configuration is
726 * not properly autoloaded after power transitions.
727 * Therefore, after each PHY reset, we will load the
728 * configuration data out of the NVM manually.
730 if (hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) {
731 struct e1000_adapter
*adapter
= hw
->adapter
;
733 /* Check if SW needs configure the PHY */
734 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
735 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
))
736 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
738 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
740 data
= er32(FEXTNVM
);
741 if (!(data
& sw_cfg_mask
))
744 /* Wait for basic configuration completes before proceeding*/
747 data
&= E1000_STATUS_LAN_INIT_DONE
;
749 } while ((!data
) && --loop
);
752 * If basic configuration is incomplete before the above loop
753 * count reaches 0, loading the configuration from NVM will
754 * leave the PHY in a bad state possibly resulting in no link.
757 hw_dbg(hw
, "LAN_INIT_DONE not set, increase timeout\n");
760 /* Clear the Init Done bit for the next init event */
762 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
766 * Make sure HW does not configure LCD from PHY
767 * extended configuration before SW configuration
769 data
= er32(EXTCNF_CTRL
);
770 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
773 cnf_size
= er32(EXTCNF_SIZE
);
774 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
775 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
779 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
780 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
782 /* Configure LCD from extended configuration region. */
784 /* cnf_base_addr is in DWORD */
785 word_addr
= (u16
)(cnf_base_addr
<< 1);
787 for (i
= 0; i
< cnf_size
; i
++) {
788 ret_val
= e1000_read_nvm(hw
,
795 ret_val
= e1000_read_nvm(hw
,
796 (word_addr
+ i
* 2 + 1),
802 /* Save off the PHY page for future writes. */
803 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
808 reg_addr
|= phy_page
;
810 ret_val
= e1e_wphy(hw
, (u32
)reg_addr
, reg_data
);
820 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
821 * @hw: pointer to the HW structure
823 * Populates "phy" structure with various feature states.
824 * This function is only called by other family-specific
827 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw
*hw
)
829 struct e1000_phy_info
*phy
= &hw
->phy
;
834 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
839 hw_dbg(hw
, "Phy info is only valid if link is up\n");
840 return -E1000_ERR_CONFIG
;
843 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
846 phy
->polarity_correction
= (!(data
& IFE_PSC_AUTO_POLARITY_DISABLE
));
848 if (phy
->polarity_correction
) {
849 ret_val
= phy
->ops
.check_polarity(hw
);
853 /* Polarity is forced */
854 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
855 ? e1000_rev_polarity_reversed
856 : e1000_rev_polarity_normal
;
859 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
863 phy
->is_mdix
= (data
& IFE_PMC_MDIX_STATUS
);
865 /* The following parameters are undefined for 10/100 operation. */
866 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
867 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
868 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
874 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
875 * @hw: pointer to the HW structure
877 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
878 * This is a function pointer entry point called by drivers
879 * or other shared routines.
881 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw
*hw
)
883 switch (hw
->phy
.type
) {
885 return e1000_get_phy_info_ife_ich8lan(hw
);
887 case e1000_phy_igp_3
:
889 case e1000_phy_82578
:
890 case e1000_phy_82577
:
891 return e1000e_get_phy_info_igp(hw
);
897 return -E1000_ERR_PHY_TYPE
;
901 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
902 * @hw: pointer to the HW structure
904 * Polarity is determined on the polarity reversal feature being enabled.
905 * This function is only called by other family-specific
908 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
)
910 struct e1000_phy_info
*phy
= &hw
->phy
;
912 u16 phy_data
, offset
, mask
;
915 * Polarity is determined based on the reversal feature being enabled.
917 if (phy
->polarity_correction
) {
918 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
919 mask
= IFE_PESC_POLARITY_REVERSED
;
921 offset
= IFE_PHY_SPECIAL_CONTROL
;
922 mask
= IFE_PSC_FORCE_POLARITY
;
925 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
928 phy
->cable_polarity
= (phy_data
& mask
)
929 ? e1000_rev_polarity_reversed
930 : e1000_rev_polarity_normal
;
936 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
937 * @hw: pointer to the HW structure
938 * @active: TRUE to enable LPLU, FALSE to disable
940 * Sets the LPLU D0 state according to the active flag. When
941 * activating LPLU this function also disables smart speed
942 * and vice versa. LPLU will not be activated unless the
943 * device autonegotiation advertisement meets standards of
944 * either 10 or 10/100 or 10/100/1000 at all duplexes.
945 * This is a function pointer entry point only called by
946 * PHY setup routines.
948 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
950 struct e1000_phy_info
*phy
= &hw
->phy
;
955 if (phy
->type
== e1000_phy_ife
)
958 phy_ctrl
= er32(PHY_CTRL
);
961 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
962 ew32(PHY_CTRL
, phy_ctrl
);
965 * Call gig speed drop workaround on LPLU before accessing
968 if ((hw
->mac
.type
== e1000_ich8lan
) &&
969 (hw
->phy
.type
== e1000_phy_igp_3
))
970 e1000e_gig_downshift_workaround_ich8lan(hw
);
972 /* When LPLU is enabled, we should disable SmartSpeed */
973 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
974 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
975 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
979 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
980 ew32(PHY_CTRL
, phy_ctrl
);
983 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
984 * during Dx states where the power conservation is most
985 * important. During driver activity we should enable
986 * SmartSpeed, so performance is maintained.
988 if (phy
->smart_speed
== e1000_smart_speed_on
) {
989 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
994 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
995 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
999 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1000 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1005 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1006 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1017 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1018 * @hw: pointer to the HW structure
1019 * @active: TRUE to enable LPLU, FALSE to disable
1021 * Sets the LPLU D3 state according to the active flag. When
1022 * activating LPLU this function also disables smart speed
1023 * and vice versa. LPLU will not be activated unless the
1024 * device autonegotiation advertisement meets standards of
1025 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1026 * This is a function pointer entry point only called by
1027 * PHY setup routines.
1029 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1031 struct e1000_phy_info
*phy
= &hw
->phy
;
1036 phy_ctrl
= er32(PHY_CTRL
);
1039 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
1040 ew32(PHY_CTRL
, phy_ctrl
);
1042 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1043 * during Dx states where the power conservation is most
1044 * important. During driver activity we should enable
1045 * SmartSpeed, so performance is maintained.
1047 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1048 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1053 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1054 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1058 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1059 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1064 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1065 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1070 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1071 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1072 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1073 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
1074 ew32(PHY_CTRL
, phy_ctrl
);
1077 * Call gig speed drop workaround on LPLU before accessing
1080 if ((hw
->mac
.type
== e1000_ich8lan
) &&
1081 (hw
->phy
.type
== e1000_phy_igp_3
))
1082 e1000e_gig_downshift_workaround_ich8lan(hw
);
1084 /* When LPLU is enabled, we should disable SmartSpeed */
1085 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1089 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1090 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1097 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1098 * @hw: pointer to the HW structure
1099 * @bank: pointer to the variable that returns the active bank
1101 * Reads signature byte from the NVM using the flash access registers.
1102 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1104 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
1107 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1108 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
1109 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
1113 switch (hw
->mac
.type
) {
1117 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
1118 E1000_EECD_SEC1VAL_VALID_MASK
) {
1119 if (eecd
& E1000_EECD_SEC1VAL
)
1126 hw_dbg(hw
, "Unable to determine valid NVM bank via EEC - "
1127 "reading flash signature\n");
1130 /* set bank to 0 in case flash read fails */
1134 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
1138 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1139 E1000_ICH_NVM_SIG_VALUE
) {
1145 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
1150 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1151 E1000_ICH_NVM_SIG_VALUE
) {
1156 hw_dbg(hw
, "ERROR: No valid NVM bank present\n");
1157 return -E1000_ERR_NVM
;
1164 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1165 * @hw: pointer to the HW structure
1166 * @offset: The offset (in bytes) of the word(s) to read.
1167 * @words: Size of data to read in words
1168 * @data: Pointer to the word(s) to read at offset.
1170 * Reads a word(s) from the NVM using the flash access registers.
1172 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1175 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1176 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1182 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1184 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1185 return -E1000_ERR_NVM
;
1188 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1192 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1196 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
1197 act_offset
+= offset
;
1199 for (i
= 0; i
< words
; i
++) {
1200 if ((dev_spec
->shadow_ram
) &&
1201 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
1202 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
1204 ret_val
= e1000_read_flash_word_ich8lan(hw
,
1214 e1000_release_swflag_ich8lan(hw
);
1218 hw_dbg(hw
, "NVM read error: %d\n", ret_val
);
1224 * e1000_flash_cycle_init_ich8lan - Initialize flash
1225 * @hw: pointer to the HW structure
1227 * This function does initial flash setup so that a new read/write/erase cycle
1230 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
1232 union ich8_hws_flash_status hsfsts
;
1233 s32 ret_val
= -E1000_ERR_NVM
;
1236 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1238 /* Check if the flash descriptor is valid */
1239 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
1240 hw_dbg(hw
, "Flash descriptor invalid. "
1241 "SW Sequencing must be used.");
1242 return -E1000_ERR_NVM
;
1245 /* Clear FCERR and DAEL in hw status by writing 1 */
1246 hsfsts
.hsf_status
.flcerr
= 1;
1247 hsfsts
.hsf_status
.dael
= 1;
1249 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1252 * Either we should have a hardware SPI cycle in progress
1253 * bit to check against, in order to start a new cycle or
1254 * FDONE bit should be changed in the hardware so that it
1255 * is 1 after hardware reset, which can then be used as an
1256 * indication whether a cycle is in progress or has been
1260 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1262 * There is no cycle running at present,
1263 * so we can start a cycle
1264 * Begin by setting Flash Cycle Done.
1266 hsfsts
.hsf_status
.flcdone
= 1;
1267 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1271 * otherwise poll for sometime so the current
1272 * cycle has a chance to end before giving up.
1274 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1275 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1276 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1284 * Successful in waiting for previous cycle to timeout,
1285 * now set the Flash Cycle Done.
1287 hsfsts
.hsf_status
.flcdone
= 1;
1288 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1290 hw_dbg(hw
, "Flash controller busy, cannot get access");
1298 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1299 * @hw: pointer to the HW structure
1300 * @timeout: maximum time to wait for completion
1302 * This function starts a flash cycle and waits for its completion.
1304 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1306 union ich8_hws_flash_ctrl hsflctl
;
1307 union ich8_hws_flash_status hsfsts
;
1308 s32 ret_val
= -E1000_ERR_NVM
;
1311 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1312 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1313 hsflctl
.hsf_ctrl
.flcgo
= 1;
1314 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1316 /* wait till FDONE bit is set to 1 */
1318 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1319 if (hsfsts
.hsf_status
.flcdone
== 1)
1322 } while (i
++ < timeout
);
1324 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1331 * e1000_read_flash_word_ich8lan - Read word from flash
1332 * @hw: pointer to the HW structure
1333 * @offset: offset to data location
1334 * @data: pointer to the location for storing the data
1336 * Reads the flash word at offset into data. Offset is converted
1337 * to bytes before read.
1339 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1342 /* Must convert offset into bytes. */
1345 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1349 * e1000_read_flash_byte_ich8lan - Read byte from flash
1350 * @hw: pointer to the HW structure
1351 * @offset: The offset of the byte to read.
1352 * @data: Pointer to a byte to store the value read.
1354 * Reads a single byte from the NVM using the flash access registers.
1356 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1362 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
1372 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1373 * @hw: pointer to the HW structure
1374 * @offset: The offset (in bytes) of the byte or word to read.
1375 * @size: Size of data to read, 1=byte 2=word
1376 * @data: Pointer to the word to store the value read.
1378 * Reads a byte or word from the NVM using the flash access registers.
1380 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1383 union ich8_hws_flash_status hsfsts
;
1384 union ich8_hws_flash_ctrl hsflctl
;
1385 u32 flash_linear_addr
;
1387 s32 ret_val
= -E1000_ERR_NVM
;
1390 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1391 return -E1000_ERR_NVM
;
1393 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1394 hw
->nvm
.flash_base_addr
;
1399 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1403 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1404 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1405 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1406 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1407 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1409 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1411 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1412 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1415 * Check if FCERR is set to 1, if set to 1, clear it
1416 * and try the whole sequence a few more times, else
1417 * read in (shift in) the Flash Data0, the order is
1418 * least significant byte first msb to lsb
1421 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1423 *data
= (u8
)(flash_data
& 0x000000FF);
1424 } else if (size
== 2) {
1425 *data
= (u16
)(flash_data
& 0x0000FFFF);
1430 * If we've gotten here, then things are probably
1431 * completely hosed, but if the error condition is
1432 * detected, it won't hurt to give it another try...
1433 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1435 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1436 if (hsfsts
.hsf_status
.flcerr
== 1) {
1437 /* Repeat for some time before giving up. */
1439 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1440 hw_dbg(hw
, "Timeout error - flash cycle "
1441 "did not complete.");
1445 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1451 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1452 * @hw: pointer to the HW structure
1453 * @offset: The offset (in bytes) of the word(s) to write.
1454 * @words: Size of data to write in words
1455 * @data: Pointer to the word(s) to write at offset.
1457 * Writes a byte or word to the NVM using the flash access registers.
1459 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1462 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1463 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1467 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1469 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1470 return -E1000_ERR_NVM
;
1473 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1477 for (i
= 0; i
< words
; i
++) {
1478 dev_spec
->shadow_ram
[offset
+i
].modified
= 1;
1479 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1482 e1000_release_swflag_ich8lan(hw
);
1488 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1489 * @hw: pointer to the HW structure
1491 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1492 * which writes the checksum to the shadow ram. The changes in the shadow
1493 * ram are then committed to the EEPROM by processing each bank at a time
1494 * checking for the modified bit and writing only the pending changes.
1495 * After a successful commit, the shadow ram is cleared and is ready for
1498 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1500 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1501 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1502 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
1506 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1510 if (nvm
->type
!= e1000_nvm_flash_sw
)
1513 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1518 * We're writing to the opposite bank so if we're on bank 1,
1519 * write to bank 0 etc. We also need to erase the segment that
1520 * is going to be written
1522 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1524 e1000_release_swflag_ich8lan(hw
);
1529 new_bank_offset
= nvm
->flash_bank_size
;
1530 old_bank_offset
= 0;
1531 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
1533 e1000_release_swflag_ich8lan(hw
);
1537 old_bank_offset
= nvm
->flash_bank_size
;
1538 new_bank_offset
= 0;
1539 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
1541 e1000_release_swflag_ich8lan(hw
);
1546 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1548 * Determine whether to write the value stored
1549 * in the other NVM bank or a modified value stored
1552 if (dev_spec
->shadow_ram
[i
].modified
) {
1553 data
= dev_spec
->shadow_ram
[i
].value
;
1555 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
1563 * If the word is 0x13, then make sure the signature bits
1564 * (15:14) are 11b until the commit has completed.
1565 * This will allow us to write 10b which indicates the
1566 * signature is valid. We want to do this after the write
1567 * has completed so that we don't mark the segment valid
1568 * while the write is still in progress
1570 if (i
== E1000_ICH_NVM_SIG_WORD
)
1571 data
|= E1000_ICH_NVM_SIG_MASK
;
1573 /* Convert offset to bytes. */
1574 act_offset
= (i
+ new_bank_offset
) << 1;
1577 /* Write the bytes to the new bank. */
1578 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1585 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1593 * Don't bother writing the segment valid bits if sector
1594 * programming failed.
1597 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1598 hw_dbg(hw
, "Flash commit failed.\n");
1599 e1000_release_swflag_ich8lan(hw
);
1604 * Finally validate the new segment by setting bit 15:14
1605 * to 10b in word 0x13 , this can be done without an
1606 * erase as well since these bits are 11 to start with
1607 * and we need to change bit 14 to 0b
1609 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1610 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1612 e1000_release_swflag_ich8lan(hw
);
1616 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1620 e1000_release_swflag_ich8lan(hw
);
1625 * And invalidate the previously valid segment by setting
1626 * its signature word (0x13) high_byte to 0b. This can be
1627 * done without an erase because flash erase sets all bits
1628 * to 1's. We can write 1's to 0's without an erase
1630 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1631 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1633 e1000_release_swflag_ich8lan(hw
);
1637 /* Great! Everything worked, we can now clear the cached entries. */
1638 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1639 dev_spec
->shadow_ram
[i
].modified
= 0;
1640 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1643 e1000_release_swflag_ich8lan(hw
);
1646 * Reload the EEPROM, or else modifications will not appear
1647 * until after the next adapter reset.
1649 e1000e_reload_nvm(hw
);
1654 hw_dbg(hw
, "NVM update error: %d\n", ret_val
);
1660 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1661 * @hw: pointer to the HW structure
1663 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1664 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1665 * calculated, in which case we need to calculate the checksum and set bit 6.
1667 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1673 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1674 * needs to be fixed. This bit is an indication that the NVM
1675 * was prepared by OEM software and did not calculate the
1676 * checksum...a likely scenario.
1678 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1682 if ((data
& 0x40) == 0) {
1684 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1687 ret_val
= e1000e_update_nvm_checksum(hw
);
1692 return e1000e_validate_nvm_checksum_generic(hw
);
1696 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1697 * @hw: pointer to the HW structure
1699 * To prevent malicious write/erase of the NVM, set it to be read-only
1700 * so that the hardware ignores all write/erase cycles of the NVM via
1701 * the flash control registers. The shadow-ram copy of the NVM will
1702 * still be updated, however any updates to this copy will not stick
1703 * across driver reloads.
1705 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
1707 union ich8_flash_protected_range pr0
;
1708 union ich8_hws_flash_status hsfsts
;
1712 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1716 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
1718 /* Write-protect GbE Sector of NVM */
1719 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
1720 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
1721 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
1722 pr0
.range
.wpe
= true;
1723 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
1726 * Lock down a subset of GbE Flash Control Registers, e.g.
1727 * PR0 to prevent the write-protection from being lifted.
1728 * Once FLOCKDN is set, the registers protected by it cannot
1729 * be written until FLOCKDN is cleared by a hardware reset.
1731 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1732 hsfsts
.hsf_status
.flockdn
= true;
1733 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1735 e1000_release_swflag_ich8lan(hw
);
1739 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1740 * @hw: pointer to the HW structure
1741 * @offset: The offset (in bytes) of the byte/word to read.
1742 * @size: Size of data to read, 1=byte 2=word
1743 * @data: The byte(s) to write to the NVM.
1745 * Writes one/two bytes to the NVM using the flash access registers.
1747 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1750 union ich8_hws_flash_status hsfsts
;
1751 union ich8_hws_flash_ctrl hsflctl
;
1752 u32 flash_linear_addr
;
1757 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
1758 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1759 return -E1000_ERR_NVM
;
1761 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1762 hw
->nvm
.flash_base_addr
;
1767 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1771 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1772 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1773 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
1774 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
1775 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1777 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1780 flash_data
= (u32
)data
& 0x00FF;
1782 flash_data
= (u32
)data
;
1784 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
1787 * check if FCERR is set to 1 , if set to 1, clear it
1788 * and try the whole sequence a few more times else done
1790 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1791 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
1796 * If we're here, then things are most likely
1797 * completely hosed, but if the error condition
1798 * is detected, it won't hurt to give it another
1799 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1801 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1802 if (hsfsts
.hsf_status
.flcerr
== 1)
1803 /* Repeat for some time before giving up. */
1805 if (hsfsts
.hsf_status
.flcdone
== 0) {
1806 hw_dbg(hw
, "Timeout error - flash cycle "
1807 "did not complete.");
1810 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1816 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1817 * @hw: pointer to the HW structure
1818 * @offset: The index of the byte to read.
1819 * @data: The byte to write to the NVM.
1821 * Writes a single byte to the NVM using the flash access registers.
1823 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1826 u16 word
= (u16
)data
;
1828 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
1832 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1833 * @hw: pointer to the HW structure
1834 * @offset: The offset of the byte to write.
1835 * @byte: The byte to write to the NVM.
1837 * Writes a single byte to the NVM using the flash access registers.
1838 * Goes through a retry algorithm before giving up.
1840 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
1841 u32 offset
, u8 byte
)
1844 u16 program_retries
;
1846 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1850 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
1851 hw_dbg(hw
, "Retrying Byte %2.2X at offset %u\n", byte
, offset
);
1853 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1857 if (program_retries
== 100)
1858 return -E1000_ERR_NVM
;
1864 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1865 * @hw: pointer to the HW structure
1866 * @bank: 0 for first bank, 1 for second bank, etc.
1868 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1869 * bank N is 4096 * N + flash_reg_addr.
1871 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
1873 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1874 union ich8_hws_flash_status hsfsts
;
1875 union ich8_hws_flash_ctrl hsflctl
;
1876 u32 flash_linear_addr
;
1877 /* bank size is in 16bit words - adjust to bytes */
1878 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
1885 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1888 * Determine HW Sector size: Read BERASE bits of hw flash status
1890 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1891 * consecutive sectors. The start index for the nth Hw sector
1892 * can be calculated as = bank * 4096 + n * 256
1893 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1894 * The start index for the nth Hw sector can be calculated
1896 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1897 * (ich9 only, otherwise error condition)
1898 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1900 switch (hsfsts
.hsf_status
.berasesz
) {
1902 /* Hw sector size 256 */
1903 sector_size
= ICH_FLASH_SEG_SIZE_256
;
1904 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
1907 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
1908 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_4K
;
1911 if (hw
->mac
.type
== e1000_ich9lan
) {
1912 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
1913 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_8K
;
1915 return -E1000_ERR_NVM
;
1919 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
1920 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_64K
;
1923 return -E1000_ERR_NVM
;
1926 /* Start with the base address, then add the sector offset. */
1927 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
1928 flash_linear_addr
+= (bank
) ? (sector_size
* iteration
) : 0;
1930 for (j
= 0; j
< iteration
; j
++) {
1933 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1938 * Write a value 11 (block Erase) in Flash
1939 * Cycle field in hw flash control
1941 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1942 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
1943 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1946 * Write the last 24 bits of an index within the
1947 * block into Flash Linear address field in Flash
1950 flash_linear_addr
+= (j
* sector_size
);
1951 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1953 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1954 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
1959 * Check if FCERR is set to 1. If 1,
1960 * clear it and try the whole sequence
1961 * a few more times else Done
1963 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1964 if (hsfsts
.hsf_status
.flcerr
== 1)
1965 /* repeat for some time before giving up */
1967 else if (hsfsts
.hsf_status
.flcdone
== 0)
1969 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
1976 * e1000_valid_led_default_ich8lan - Set the default LED settings
1977 * @hw: pointer to the HW structure
1978 * @data: Pointer to the LED settings
1980 * Reads the LED default settings from the NVM to data. If the NVM LED
1981 * settings is all 0's or F's, set the LED default to a valid LED default
1984 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
1988 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1990 hw_dbg(hw
, "NVM Read Error\n");
1994 if (*data
== ID_LED_RESERVED_0000
||
1995 *data
== ID_LED_RESERVED_FFFF
)
1996 *data
= ID_LED_DEFAULT_ICH8LAN
;
2002 * e1000_id_led_init_pchlan - store LED configurations
2003 * @hw: pointer to the HW structure
2005 * PCH does not control LEDs via the LEDCTL register, rather it uses
2006 * the PHY LED configuration register.
2008 * PCH also does not have an "always on" or "always off" mode which
2009 * complicates the ID feature. Instead of using the "on" mode to indicate
2010 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2011 * use "link_up" mode. The LEDs will still ID on request if there is no
2012 * link based on logic in e1000_led_[on|off]_pchlan().
2014 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
2016 struct e1000_mac_info
*mac
= &hw
->mac
;
2018 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
2019 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
2020 u16 data
, i
, temp
, shift
;
2022 /* Get default ID LED modes */
2023 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
2027 mac
->ledctl_default
= er32(LEDCTL
);
2028 mac
->ledctl_mode1
= mac
->ledctl_default
;
2029 mac
->ledctl_mode2
= mac
->ledctl_default
;
2031 for (i
= 0; i
< 4; i
++) {
2032 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
2035 case ID_LED_ON1_DEF2
:
2036 case ID_LED_ON1_ON2
:
2037 case ID_LED_ON1_OFF2
:
2038 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2039 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
2041 case ID_LED_OFF1_DEF2
:
2042 case ID_LED_OFF1_ON2
:
2043 case ID_LED_OFF1_OFF2
:
2044 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2045 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
2052 case ID_LED_DEF1_ON2
:
2053 case ID_LED_ON1_ON2
:
2054 case ID_LED_OFF1_ON2
:
2055 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2056 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
2058 case ID_LED_DEF1_OFF2
:
2059 case ID_LED_ON1_OFF2
:
2060 case ID_LED_OFF1_OFF2
:
2061 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2062 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
2075 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2076 * @hw: pointer to the HW structure
2078 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2079 * register, so the the bus width is hard coded.
2081 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
2083 struct e1000_bus_info
*bus
= &hw
->bus
;
2086 ret_val
= e1000e_get_bus_info_pcie(hw
);
2089 * ICH devices are "PCI Express"-ish. They have
2090 * a configuration space, but do not contain
2091 * PCI Express Capability registers, so bus width
2092 * must be hardcoded.
2094 if (bus
->width
== e1000_bus_width_unknown
)
2095 bus
->width
= e1000_bus_width_pcie_x1
;
2101 * e1000_reset_hw_ich8lan - Reset the hardware
2102 * @hw: pointer to the HW structure
2104 * Does a full reset of the hardware which includes a reset of the PHY and
2107 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
2113 * Prevent the PCI-E bus from sticking if there is no TLP connection
2114 * on the last TLP read/write transaction when MAC is reset.
2116 ret_val
= e1000e_disable_pcie_master(hw
);
2118 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
2121 hw_dbg(hw
, "Masking off all interrupts\n");
2122 ew32(IMC
, 0xffffffff);
2125 * Disable the Transmit and Receive units. Then delay to allow
2126 * any pending transactions to complete before we hit the MAC
2127 * with the global reset.
2130 ew32(TCTL
, E1000_TCTL_PSP
);
2135 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2136 if (hw
->mac
.type
== e1000_ich8lan
) {
2137 /* Set Tx and Rx buffer allocation to 8k apiece. */
2138 ew32(PBA
, E1000_PBA_8K
);
2139 /* Set Packet Buffer Size to 16k. */
2140 ew32(PBS
, E1000_PBS_16K
);
2145 if (!e1000_check_reset_block(hw
)) {
2147 * PHY HW reset requires MAC CORE reset at the same
2148 * time to make sure the interface between MAC and the
2149 * external PHY is reset.
2151 ctrl
|= E1000_CTRL_PHY_RST
;
2153 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
2154 /* Whether or not the swflag was acquired, we need to reset the part */
2155 hw_dbg(hw
, "Issuing a global reset to ich8lan\n");
2156 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
2160 /* release the swflag because it is not reset by
2163 e1000_release_swflag_ich8lan(hw
);
2166 ret_val
= e1000e_get_auto_rd_done(hw
);
2169 * When auto config read does not complete, do not
2170 * return with an error. This can happen in situations
2171 * where there is no eeprom and prevents getting link.
2173 hw_dbg(hw
, "Auto Read Done did not complete\n");
2176 ew32(IMC
, 0xffffffff);
2179 kab
= er32(KABGTXD
);
2180 kab
|= E1000_KABGTXD_BGSQLBIAS
;
2183 if (hw
->mac
.type
== e1000_pchlan
)
2184 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2190 * e1000_init_hw_ich8lan - Initialize the hardware
2191 * @hw: pointer to the HW structure
2193 * Prepares the hardware for transmit and receive by doing the following:
2194 * - initialize hardware bits
2195 * - initialize LED identification
2196 * - setup receive address registers
2197 * - setup flow control
2198 * - setup transmit descriptors
2199 * - clear statistics
2201 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
2203 struct e1000_mac_info
*mac
= &hw
->mac
;
2204 u32 ctrl_ext
, txdctl
, snoop
;
2208 e1000_initialize_hw_bits_ich8lan(hw
);
2210 /* Initialize identification LED */
2211 ret_val
= mac
->ops
.id_led_init(hw
);
2213 hw_dbg(hw
, "Error initializing identification LED\n");
2217 /* Setup the receive address. */
2218 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
2220 /* Zero out the Multicast HASH table */
2221 hw_dbg(hw
, "Zeroing the MTA\n");
2222 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
2223 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
2225 /* Setup link and flow control */
2226 ret_val
= e1000_setup_link_ich8lan(hw
);
2228 /* Set the transmit descriptor write-back policy for both queues */
2229 txdctl
= er32(TXDCTL(0));
2230 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2231 E1000_TXDCTL_FULL_TX_DESC_WB
;
2232 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2233 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2234 ew32(TXDCTL(0), txdctl
);
2235 txdctl
= er32(TXDCTL(1));
2236 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2237 E1000_TXDCTL_FULL_TX_DESC_WB
;
2238 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2239 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2240 ew32(TXDCTL(1), txdctl
);
2243 * ICH8 has opposite polarity of no_snoop bits.
2244 * By default, we should use snoop behavior.
2246 if (mac
->type
== e1000_ich8lan
)
2247 snoop
= PCIE_ICH8_SNOOP_ALL
;
2249 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
2250 e1000e_set_pcie_no_snoop(hw
, snoop
);
2252 ctrl_ext
= er32(CTRL_EXT
);
2253 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
2254 ew32(CTRL_EXT
, ctrl_ext
);
2257 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2258 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2259 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2261 if (hw
->phy
.type
== e1000_phy_82578
) {
2262 e1e_rphy(hw
, BM_WUC
, &i
);
2263 e1000e_phy_hw_reset_generic(hw
);
2267 * Clear all of the statistics registers (clear on read). It is
2268 * important that we do this after we have tried to establish link
2269 * because the symbol error count will increment wildly if there
2272 e1000_clear_hw_cntrs_ich8lan(hw
);
2277 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2278 * @hw: pointer to the HW structure
2280 * Sets/Clears required hardware bits necessary for correctly setting up the
2281 * hardware for transmit and receive.
2283 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
2287 /* Extended Device Control */
2288 reg
= er32(CTRL_EXT
);
2290 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2291 if (hw
->mac
.type
>= e1000_pchlan
)
2292 reg
|= E1000_CTRL_EXT_PHYPDEN
;
2293 ew32(CTRL_EXT
, reg
);
2295 /* Transmit Descriptor Control 0 */
2296 reg
= er32(TXDCTL(0));
2298 ew32(TXDCTL(0), reg
);
2300 /* Transmit Descriptor Control 1 */
2301 reg
= er32(TXDCTL(1));
2303 ew32(TXDCTL(1), reg
);
2305 /* Transmit Arbitration Control 0 */
2306 reg
= er32(TARC(0));
2307 if (hw
->mac
.type
== e1000_ich8lan
)
2308 reg
|= (1 << 28) | (1 << 29);
2309 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2312 /* Transmit Arbitration Control 1 */
2313 reg
= er32(TARC(1));
2314 if (er32(TCTL
) & E1000_TCTL_MULR
)
2318 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
2322 if (hw
->mac
.type
== e1000_ich8lan
) {
2330 * e1000_setup_link_ich8lan - Setup flow control and link settings
2331 * @hw: pointer to the HW structure
2333 * Determines which flow control settings to use, then configures flow
2334 * control. Calls the appropriate media-specific link configuration
2335 * function. Assuming the adapter has a valid link partner, a valid link
2336 * should be established. Assumes the hardware has previously been reset
2337 * and the transmitter and receiver are not enabled.
2339 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
2343 if (e1000_check_reset_block(hw
))
2347 * ICH parts do not have a word in the NVM to determine
2348 * the default flow control setting, so we explicitly
2351 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
2352 /* Workaround h/w hang when Tx flow control enabled */
2353 if (hw
->mac
.type
== e1000_pchlan
)
2354 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
2356 hw
->fc
.requested_mode
= e1000_fc_full
;
2360 * Save off the requested flow control mode for use later. Depending
2361 * on the link partner's capabilities, we may or may not use this mode.
2363 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2365 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n",
2366 hw
->fc
.current_mode
);
2368 /* Continue to configure the copper link. */
2369 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
2373 ew32(FCTTV
, hw
->fc
.pause_time
);
2374 if ((hw
->phy
.type
== e1000_phy_82578
) ||
2375 (hw
->phy
.type
== e1000_phy_82577
)) {
2376 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
2377 PHY_REG(BM_PORT_CTRL_PAGE
, 27),
2383 return e1000e_set_fc_watermarks(hw
);
2387 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2388 * @hw: pointer to the HW structure
2390 * Configures the kumeran interface to the PHY to wait the appropriate time
2391 * when polling the PHY, then call the generic setup_copper_link to finish
2392 * configuring the copper link.
2394 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
2401 ctrl
|= E1000_CTRL_SLU
;
2402 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2406 * Set the mac to wait the maximum time between each iteration
2407 * and increase the max iterations when polling the phy;
2408 * this fixes erroneous timeouts at 10Mbps.
2410 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
2413 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
2417 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
2421 switch (hw
->phy
.type
) {
2422 case e1000_phy_igp_3
:
2423 ret_val
= e1000e_copper_link_setup_igp(hw
);
2428 case e1000_phy_82578
:
2429 ret_val
= e1000e_copper_link_setup_m88(hw
);
2433 case e1000_phy_82577
:
2434 ret_val
= e1000_copper_link_setup_82577(hw
);
2439 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IFE_PHY_MDIX_CONTROL
,
2444 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
2446 switch (hw
->phy
.mdix
) {
2448 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
2451 reg_data
|= IFE_PMC_FORCE_MDIX
;
2455 reg_data
|= IFE_PMC_AUTO_MDIX
;
2458 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, IFE_PHY_MDIX_CONTROL
,
2466 return e1000e_setup_copper_link(hw
);
2470 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2471 * @hw: pointer to the HW structure
2472 * @speed: pointer to store current link speed
2473 * @duplex: pointer to store the current link duplex
2475 * Calls the generic get_speed_and_duplex to retrieve the current link
2476 * information and then calls the Kumeran lock loss workaround for links at
2479 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
2484 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2488 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2489 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2490 (*speed
== SPEED_1000
)) {
2491 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2498 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2499 * @hw: pointer to the HW structure
2501 * Work-around for 82566 Kumeran PCS lock loss:
2502 * On link status change (i.e. PCI reset, speed change) and link is up and
2504 * 0) if workaround is optionally disabled do nothing
2505 * 1) wait 1ms for Kumeran link to come up
2506 * 2) check Kumeran Diagnostic register PCS lock loss bit
2507 * 3) if not set the link is locked (all is good), otherwise...
2509 * 5) repeat up to 10 times
2510 * Note: this is only called for IGP3 copper when speed is 1gb.
2512 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2514 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2520 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2524 * Make sure link is up before proceeding. If not just return.
2525 * Attempting this while link is negotiating fouled up link
2528 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2532 for (i
= 0; i
< 10; i
++) {
2533 /* read once to clear */
2534 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2537 /* and again to get new status */
2538 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2542 /* check for PCS lock */
2543 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2546 /* Issue PHY reset */
2547 e1000_phy_hw_reset(hw
);
2550 /* Disable GigE link negotiation */
2551 phy_ctrl
= er32(PHY_CTRL
);
2552 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2553 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2554 ew32(PHY_CTRL
, phy_ctrl
);
2557 * Call gig speed drop workaround on Gig disable before accessing
2560 e1000e_gig_downshift_workaround_ich8lan(hw
);
2562 /* unable to acquire PCS lock */
2563 return -E1000_ERR_PHY
;
2567 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2568 * @hw: pointer to the HW structure
2569 * @state: boolean value used to set the current Kumeran workaround state
2571 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2572 * /disabled - FALSE).
2574 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2577 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2579 if (hw
->mac
.type
!= e1000_ich8lan
) {
2580 hw_dbg(hw
, "Workaround applies to ICH8 only.\n");
2584 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2588 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2589 * @hw: pointer to the HW structure
2591 * Workaround for 82566 power-down on D3 entry:
2592 * 1) disable gigabit link
2593 * 2) write VR power-down enable
2595 * Continue if successful, else issue LCD reset and repeat
2597 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2603 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2606 /* Try the workaround twice (if needed) */
2609 reg
= er32(PHY_CTRL
);
2610 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2611 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2612 ew32(PHY_CTRL
, reg
);
2615 * Call gig speed drop workaround on Gig disable before
2616 * accessing any PHY registers
2618 if (hw
->mac
.type
== e1000_ich8lan
)
2619 e1000e_gig_downshift_workaround_ich8lan(hw
);
2621 /* Write VR power-down enable */
2622 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2623 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2624 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2626 /* Read it back and test */
2627 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2628 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2629 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2632 /* Issue PHY reset and repeat at most one more time */
2634 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2640 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2641 * @hw: pointer to the HW structure
2643 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2644 * LPLU, Gig disable, MDIC PHY reset):
2645 * 1) Set Kumeran Near-end loopback
2646 * 2) Clear Kumeran Near-end loopback
2647 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2649 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
2654 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
2655 (hw
->phy
.type
!= e1000_phy_igp_3
))
2658 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2662 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2663 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2667 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2668 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2673 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2674 * @hw: pointer to the HW structure
2676 * During S0 to Sx transition, it is possible the link remains at gig
2677 * instead of negotiating to a lower speed. Before going to Sx, set
2678 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2681 * Should only be called for applicable parts.
2683 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
2687 switch (hw
->mac
.type
) {
2689 case e1000_ich10lan
:
2691 phy_ctrl
= er32(PHY_CTRL
);
2692 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
2693 E1000_PHY_CTRL_GBE_DISABLE
;
2694 ew32(PHY_CTRL
, phy_ctrl
);
2696 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2697 if (hw
->mac
.type
== e1000_pchlan
)
2707 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2708 * @hw: pointer to the HW structure
2710 * Return the LED back to the default configuration.
2712 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
2714 if (hw
->phy
.type
== e1000_phy_ife
)
2715 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
2717 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
2722 * e1000_led_on_ich8lan - Turn LEDs on
2723 * @hw: pointer to the HW structure
2727 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
2729 if (hw
->phy
.type
== e1000_phy_ife
)
2730 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2731 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
2733 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
2738 * e1000_led_off_ich8lan - Turn LEDs off
2739 * @hw: pointer to the HW structure
2741 * Turn off the LEDs.
2743 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
2745 if (hw
->phy
.type
== e1000_phy_ife
)
2746 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2747 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
2749 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
2754 * e1000_setup_led_pchlan - Configures SW controllable LED
2755 * @hw: pointer to the HW structure
2757 * This prepares the SW controllable LED for use.
2759 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
2761 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
,
2762 (u16
)hw
->mac
.ledctl_mode1
);
2766 * e1000_cleanup_led_pchlan - Restore the default LED operation
2767 * @hw: pointer to the HW structure
2769 * Return the LED back to the default configuration.
2771 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
2773 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
,
2774 (u16
)hw
->mac
.ledctl_default
);
2778 * e1000_led_on_pchlan - Turn LEDs on
2779 * @hw: pointer to the HW structure
2783 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
2785 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
2789 * If no link, then turn LED on by setting the invert bit
2790 * for each LED that's mode is "link_up" in ledctl_mode2.
2792 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
2793 for (i
= 0; i
< 3; i
++) {
2794 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
2795 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
2796 E1000_LEDCTL_MODE_LINK_UP
)
2798 if (led
& E1000_PHY_LED0_IVRT
)
2799 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
2801 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
2805 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
, data
);
2809 * e1000_led_off_pchlan - Turn LEDs off
2810 * @hw: pointer to the HW structure
2812 * Turn off the LEDs.
2814 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
2816 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
2820 * If no link, then turn LED off by clearing the invert bit
2821 * for each LED that's mode is "link_up" in ledctl_mode1.
2823 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
2824 for (i
= 0; i
< 3; i
++) {
2825 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
2826 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
2827 E1000_LEDCTL_MODE_LINK_UP
)
2829 if (led
& E1000_PHY_LED0_IVRT
)
2830 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
2832 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
2836 return hw
->phy
.ops
.write_phy_reg(hw
, HV_LED_CONFIG
, data
);
2840 * e1000_get_cfg_done_ich8lan - Read config done bit
2841 * @hw: pointer to the HW structure
2843 * Read the management control register for the config done bit for
2844 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2845 * to read the config done bit, so an error is *ONLY* logged and returns
2846 * 0. If we were to return with error, EEPROM-less silicon
2847 * would not be able to be reset or change link.
2849 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
2853 e1000e_get_cfg_done(hw
);
2855 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2856 if ((hw
->mac
.type
!= e1000_ich10lan
) &&
2857 (hw
->mac
.type
!= e1000_pchlan
)) {
2858 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
2859 (hw
->phy
.type
== e1000_phy_igp_3
)) {
2860 e1000e_phy_init_script_igp3(hw
);
2863 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
2864 /* Maybe we should do a basic PHY config */
2865 hw_dbg(hw
, "EEPROM not present\n");
2866 return -E1000_ERR_CONFIG
;
2874 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2875 * @hw: pointer to the HW structure
2877 * Clears hardware counters specific to the silicon family and calls
2878 * clear_hw_cntrs_generic to clear all general purpose counters.
2880 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
2885 e1000e_clear_hw_cntrs_base(hw
);
2887 temp
= er32(ALGNERRC
);
2888 temp
= er32(RXERRC
);
2890 temp
= er32(CEXTERR
);
2892 temp
= er32(TSCTFC
);
2894 temp
= er32(MGTPRC
);
2895 temp
= er32(MGTPDC
);
2896 temp
= er32(MGTPTC
);
2899 temp
= er32(ICRXOC
);
2901 /* Clear PHY statistics registers */
2902 if ((hw
->phy
.type
== e1000_phy_82578
) ||
2903 (hw
->phy
.type
== e1000_phy_82577
)) {
2904 hw
->phy
.ops
.read_phy_reg(hw
, HV_SCC_UPPER
, &phy_data
);
2905 hw
->phy
.ops
.read_phy_reg(hw
, HV_SCC_LOWER
, &phy_data
);
2906 hw
->phy
.ops
.read_phy_reg(hw
, HV_ECOL_UPPER
, &phy_data
);
2907 hw
->phy
.ops
.read_phy_reg(hw
, HV_ECOL_LOWER
, &phy_data
);
2908 hw
->phy
.ops
.read_phy_reg(hw
, HV_MCC_UPPER
, &phy_data
);
2909 hw
->phy
.ops
.read_phy_reg(hw
, HV_MCC_LOWER
, &phy_data
);
2910 hw
->phy
.ops
.read_phy_reg(hw
, HV_LATECOL_UPPER
, &phy_data
);
2911 hw
->phy
.ops
.read_phy_reg(hw
, HV_LATECOL_LOWER
, &phy_data
);
2912 hw
->phy
.ops
.read_phy_reg(hw
, HV_COLC_UPPER
, &phy_data
);
2913 hw
->phy
.ops
.read_phy_reg(hw
, HV_COLC_LOWER
, &phy_data
);
2914 hw
->phy
.ops
.read_phy_reg(hw
, HV_DC_UPPER
, &phy_data
);
2915 hw
->phy
.ops
.read_phy_reg(hw
, HV_DC_LOWER
, &phy_data
);
2916 hw
->phy
.ops
.read_phy_reg(hw
, HV_TNCRS_UPPER
, &phy_data
);
2917 hw
->phy
.ops
.read_phy_reg(hw
, HV_TNCRS_LOWER
, &phy_data
);
2921 static struct e1000_mac_operations ich8_mac_ops
= {
2922 .id_led_init
= e1000e_id_led_init
,
2923 .check_mng_mode
= e1000_check_mng_mode_ich8lan
,
2924 .check_for_link
= e1000e_check_for_copper_link
,
2925 /* cleanup_led dependent on mac type */
2926 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
2927 .get_bus_info
= e1000_get_bus_info_ich8lan
,
2928 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
2929 /* led_on dependent on mac type */
2930 /* led_off dependent on mac type */
2931 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
2932 .reset_hw
= e1000_reset_hw_ich8lan
,
2933 .init_hw
= e1000_init_hw_ich8lan
,
2934 .setup_link
= e1000_setup_link_ich8lan
,
2935 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
2936 /* id_led_init dependent on mac type */
2939 static struct e1000_phy_operations ich8_phy_ops
= {
2940 .acquire_phy
= e1000_acquire_swflag_ich8lan
,
2941 .check_reset_block
= e1000_check_reset_block_ich8lan
,
2943 .force_speed_duplex
= e1000_phy_force_speed_duplex_ich8lan
,
2944 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
2945 .get_cable_length
= e1000e_get_cable_length_igp_2
,
2946 .get_phy_info
= e1000_get_phy_info_ich8lan
,
2947 .read_phy_reg
= e1000e_read_phy_reg_igp
,
2948 .release_phy
= e1000_release_swflag_ich8lan
,
2949 .reset_phy
= e1000_phy_hw_reset_ich8lan
,
2950 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
2951 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
2952 .write_phy_reg
= e1000e_write_phy_reg_igp
,
2955 static struct e1000_nvm_operations ich8_nvm_ops
= {
2956 .acquire_nvm
= e1000_acquire_swflag_ich8lan
,
2957 .read_nvm
= e1000_read_nvm_ich8lan
,
2958 .release_nvm
= e1000_release_swflag_ich8lan
,
2959 .update_nvm
= e1000_update_nvm_checksum_ich8lan
,
2960 .valid_led_default
= e1000_valid_led_default_ich8lan
,
2961 .validate_nvm
= e1000_validate_nvm_checksum_ich8lan
,
2962 .write_nvm
= e1000_write_nvm_ich8lan
,
2965 struct e1000_info e1000_ich8_info
= {
2966 .mac
= e1000_ich8lan
,
2967 .flags
= FLAG_HAS_WOL
2969 | FLAG_RX_CSUM_ENABLED
2970 | FLAG_HAS_CTRLEXT_ON_LOAD
2975 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
2976 .get_variants
= e1000_get_variants_ich8lan
,
2977 .mac_ops
= &ich8_mac_ops
,
2978 .phy_ops
= &ich8_phy_ops
,
2979 .nvm_ops
= &ich8_nvm_ops
,
2982 struct e1000_info e1000_ich9_info
= {
2983 .mac
= e1000_ich9lan
,
2984 .flags
= FLAG_HAS_JUMBO_FRAMES
2987 | FLAG_RX_CSUM_ENABLED
2988 | FLAG_HAS_CTRLEXT_ON_LOAD
2994 .max_hw_frame_size
= DEFAULT_JUMBO
,
2995 .get_variants
= e1000_get_variants_ich8lan
,
2996 .mac_ops
= &ich8_mac_ops
,
2997 .phy_ops
= &ich8_phy_ops
,
2998 .nvm_ops
= &ich8_nvm_ops
,
3001 struct e1000_info e1000_ich10_info
= {
3002 .mac
= e1000_ich10lan
,
3003 .flags
= FLAG_HAS_JUMBO_FRAMES
3006 | FLAG_RX_CSUM_ENABLED
3007 | FLAG_HAS_CTRLEXT_ON_LOAD
3013 .max_hw_frame_size
= DEFAULT_JUMBO
,
3014 .get_variants
= e1000_get_variants_ich8lan
,
3015 .mac_ops
= &ich8_mac_ops
,
3016 .phy_ops
= &ich8_phy_ops
,
3017 .nvm_ops
= &ich8_nvm_ops
,
3020 struct e1000_info e1000_pch_info
= {
3021 .mac
= e1000_pchlan
,
3022 .flags
= FLAG_IS_ICH
3024 | FLAG_RX_CSUM_ENABLED
3025 | FLAG_HAS_CTRLEXT_ON_LOAD
3028 | FLAG_HAS_JUMBO_FRAMES
3031 .max_hw_frame_size
= 4096,
3032 .get_variants
= e1000_get_variants_ich8lan
,
3033 .mac_ops
= &ich8_mac_ops
,
3034 .phy_ops
= &ich8_phy_ops
,
3035 .nvm_ops
= &ich8_nvm_ops
,