1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/netdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/delay.h>
32 #include <linux/pci.h>
37 e1000_mng_mode_none
= 0,
41 e1000_mng_mode_host_if_only
44 #define E1000_FACTPS_MNGCG 0x20000000
46 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management
47 * Technology signature */
50 * e1000e_get_bus_info_pcie - Get PCIe bus information
51 * @hw: pointer to the HW structure
53 * Determines and stores the system bus information for a particular
54 * network interface. The following bus information is determined and stored:
55 * bus speed, bus width, type (PCIe), and PCIe function.
57 s32
e1000e_get_bus_info_pcie(struct e1000_hw
*hw
)
59 struct e1000_bus_info
*bus
= &hw
->bus
;
60 struct e1000_adapter
*adapter
= hw
->adapter
;
62 u16 pcie_link_status
, pci_header_type
, cap_offset
;
64 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
66 bus
->width
= e1000_bus_width_unknown
;
68 pci_read_config_word(adapter
->pdev
,
69 cap_offset
+ PCIE_LINK_STATUS
,
71 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
72 PCIE_LINK_WIDTH_MASK
) >>
73 PCIE_LINK_WIDTH_SHIFT
);
76 pci_read_config_word(adapter
->pdev
, PCI_HEADER_TYPE_REGISTER
,
78 if (pci_header_type
& PCI_HEADER_TYPE_MULTIFUNC
) {
79 status
= er32(STATUS
);
80 bus
->func
= (status
& E1000_STATUS_FUNC_MASK
)
81 >> E1000_STATUS_FUNC_SHIFT
;
90 * e1000e_write_vfta - Write value to VLAN filter table
91 * @hw: pointer to the HW structure
92 * @offset: register offset in VLAN filter table
93 * @value: register value written to VLAN filter table
95 * Writes value at the given offset in the register array which stores
96 * the VLAN filter table.
98 void e1000e_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
100 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, value
);
105 * e1000e_init_rx_addrs - Initialize receive address's
106 * @hw: pointer to the HW structure
107 * @rar_count: receive address registers
109 * Setups the receive address registers by setting the base receive address
110 * register to the devices MAC address and clearing all the other receive
111 * address registers to 0.
113 void e1000e_init_rx_addrs(struct e1000_hw
*hw
, u16 rar_count
)
117 /* Setup the receive address */
118 hw_dbg(hw
, "Programming MAC Address into RAR[0]\n");
120 e1000e_rar_set(hw
, hw
->mac
.addr
, 0);
122 /* Zero out the other (rar_entry_count - 1) receive addresses */
123 hw_dbg(hw
, "Clearing RAR[1-%u]\n", rar_count
-1);
124 for (i
= 1; i
< rar_count
; i
++) {
125 E1000_WRITE_REG_ARRAY(hw
, E1000_RA
, (i
<< 1), 0);
127 E1000_WRITE_REG_ARRAY(hw
, E1000_RA
, ((i
<< 1) + 1), 0);
133 * e1000e_rar_set - Set receive address register
134 * @hw: pointer to the HW structure
135 * @addr: pointer to the receive address
136 * @index: receive address array register
138 * Sets the receive address array register at index to the address passed
141 void e1000e_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
143 u32 rar_low
, rar_high
;
145 /* HW expects these in little endian so we reverse the byte order
146 * from network order (big endian) to little endian
148 rar_low
= ((u32
) addr
[0] |
149 ((u32
) addr
[1] << 8) |
150 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
152 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
154 rar_high
|= E1000_RAH_AV
;
156 E1000_WRITE_REG_ARRAY(hw
, E1000_RA
, (index
<< 1), rar_low
);
157 E1000_WRITE_REG_ARRAY(hw
, E1000_RA
, ((index
<< 1) + 1), rar_high
);
161 * e1000_mta_set - Set multicast filter table address
162 * @hw: pointer to the HW structure
163 * @hash_value: determines the MTA register and bit to set
165 * The multicast table address is a register array of 32-bit registers.
166 * The hash_value is used to determine what register the bit is in, the
167 * current value is read, the new bit is OR'd in and the new value is
168 * written back into the register.
170 static void e1000_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
172 u32 hash_bit
, hash_reg
, mta
;
174 /* The MTA is a register array of 32-bit registers. It is
175 * treated like an array of (32*mta_reg_count) bits. We want to
176 * set bit BitArray[hash_value]. So we figure out what register
177 * the bit is in, read it, OR in the new bit, then write
178 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
179 * mask to bits 31:5 of the hash value which gives us the
180 * register we're modifying. The hash bit within that register
181 * is determined by the lower 5 bits of the hash value.
183 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
184 hash_bit
= hash_value
& 0x1F;
186 mta
= E1000_READ_REG_ARRAY(hw
, E1000_MTA
, hash_reg
);
188 mta
|= (1 << hash_bit
);
190 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, hash_reg
, mta
);
195 * e1000_hash_mc_addr - Generate a multicast hash value
196 * @hw: pointer to the HW structure
197 * @mc_addr: pointer to a multicast address
199 * Generates a multicast address hash value which is used to determine
200 * the multicast filter table array address and new table value. See
201 * e1000_mta_set_generic()
203 static u32
e1000_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
205 u32 hash_value
, hash_mask
;
208 /* Register count multiplied by bits per register */
209 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
211 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
212 * where 0xFF would still fall within the hash mask. */
213 while (hash_mask
>> bit_shift
!= 0xFF)
216 /* The portion of the address that is used for the hash table
217 * is determined by the mc_filter_type setting.
218 * The algorithm is such that there is a total of 8 bits of shifting.
219 * The bit_shift for a mc_filter_type of 0 represents the number of
220 * left-shifts where the MSB of mc_addr[5] would still fall within
221 * the hash_mask. Case 0 does this exactly. Since there are a total
222 * of 8 bits of shifting, then mc_addr[4] will shift right the
223 * remaining number of bits. Thus 8 - bit_shift. The rest of the
224 * cases are a variation of this algorithm...essentially raising the
225 * number of bits to shift mc_addr[5] left, while still keeping the
226 * 8-bit shifting total.
228 /* For example, given the following Destination MAC Address and an
229 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
230 * we can see that the bit_shift for case 0 is 4. These are the hash
231 * values resulting from each mc_filter_type...
232 * [0] [1] [2] [3] [4] [5]
236 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
237 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
238 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
239 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
241 switch (hw
->mac
.mc_filter_type
) {
256 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
257 (((u16
) mc_addr
[5]) << bit_shift
)));
263 * e1000e_mc_addr_list_update_generic - Update Multicast addresses
264 * @hw: pointer to the HW structure
265 * @mc_addr_list: array of multicast addresses to program
266 * @mc_addr_count: number of multicast addresses to program
267 * @rar_used_count: the first RAR register free to program
268 * @rar_count: total number of supported Receive Address Registers
270 * Updates the Receive Address Registers and Multicast Table Array.
271 * The caller must have a packed mc_addr_list of multicast addresses.
272 * The parameter rar_count will usually be hw->mac.rar_entry_count
273 * unless there are workarounds that change this.
275 void e1000e_mc_addr_list_update_generic(struct e1000_hw
*hw
,
276 u8
*mc_addr_list
, u32 mc_addr_count
,
277 u32 rar_used_count
, u32 rar_count
)
282 /* Load the first set of multicast addresses into the exact
283 * filters (RAR). If there are not enough to fill the RAR
284 * array, clear the filters.
286 for (i
= rar_used_count
; i
< rar_count
; i
++) {
288 e1000e_rar_set(hw
, mc_addr_list
, i
);
290 mc_addr_list
+= ETH_ALEN
;
292 E1000_WRITE_REG_ARRAY(hw
, E1000_RA
, i
<< 1, 0);
294 E1000_WRITE_REG_ARRAY(hw
, E1000_RA
, (i
<< 1) + 1, 0);
299 /* Clear the old settings from the MTA */
300 hw_dbg(hw
, "Clearing MTA\n");
301 for (i
= 0; i
< hw
->mac
.mta_reg_count
; i
++) {
302 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
306 /* Load any remaining multicast addresses into the hash table. */
307 for (; mc_addr_count
> 0; mc_addr_count
--) {
308 hash_value
= e1000_hash_mc_addr(hw
, mc_addr_list
);
309 hw_dbg(hw
, "Hash value = 0x%03X\n", hash_value
);
310 e1000_mta_set(hw
, hash_value
);
311 mc_addr_list
+= ETH_ALEN
;
316 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
317 * @hw: pointer to the HW structure
319 * Clears the base hardware counters by reading the counter registers.
321 void e1000e_clear_hw_cntrs_base(struct e1000_hw
*hw
)
325 temp
= er32(CRCERRS
);
326 temp
= er32(SYMERRS
);
331 temp
= er32(LATECOL
);
338 temp
= er32(XOFFRXC
);
339 temp
= er32(XOFFTXC
);
365 * e1000e_check_for_copper_link - Check for link (Copper)
366 * @hw: pointer to the HW structure
368 * Checks to see of the link status of the hardware has changed. If a
369 * change in link status has been detected, then we read the PHY registers
370 * to get the current speed/duplex if link exists.
372 s32
e1000e_check_for_copper_link(struct e1000_hw
*hw
)
374 struct e1000_mac_info
*mac
= &hw
->mac
;
378 /* We only want to go out to the PHY registers to see if Auto-Neg
379 * has completed and/or if our link status has changed. The
380 * get_link_status flag is set upon receiving a Link Status
381 * Change or Rx Sequence Error interrupt.
383 if (!mac
->get_link_status
)
386 /* First we want to see if the MII Status Register reports
387 * link. If so, then we want to get the current speed/duplex
390 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
395 return ret_val
; /* No link detected */
397 mac
->get_link_status
= 0;
399 /* Check if there was DownShift, must be checked
400 * immediately after link-up */
401 e1000e_check_downshift(hw
);
403 /* If we are forcing speed/duplex, then we simply return since
404 * we have already determined whether we have link or not.
407 ret_val
= -E1000_ERR_CONFIG
;
411 /* Auto-Neg is enabled. Auto Speed Detection takes care
412 * of MAC speed/duplex configuration. So we only need to
413 * configure Collision Distance in the MAC.
415 e1000e_config_collision_dist(hw
);
417 /* Configure Flow Control now that Auto-Neg has completed.
418 * First, we need to restore the desired flow control
419 * settings because we may have had to re-autoneg with a
420 * different link partner.
422 ret_val
= e1000e_config_fc_after_link_up(hw
);
424 hw_dbg(hw
, "Error configuring flow control\n");
431 * e1000e_check_for_fiber_link - Check for link (Fiber)
432 * @hw: pointer to the HW structure
434 * Checks for link up on the hardware. If link is not up and we have
435 * a signal, then we need to force link up.
437 s32
e1000e_check_for_fiber_link(struct e1000_hw
*hw
)
439 struct e1000_mac_info
*mac
= &hw
->mac
;
446 status
= er32(STATUS
);
449 /* If we don't have link (auto-negotiation failed or link partner
450 * cannot auto-negotiate), the cable is plugged in (we have signal),
451 * and our link partner is not trying to auto-negotiate with us (we
452 * are receiving idles or data), we need to force link up. We also
453 * need to give auto-negotiation time to complete, in case the cable
454 * was just plugged in. The autoneg_failed flag does this.
456 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
457 if ((ctrl
& E1000_CTRL_SWDPIN1
) && (!(status
& E1000_STATUS_LU
)) &&
458 (!(rxcw
& E1000_RXCW_C
))) {
459 if (mac
->autoneg_failed
== 0) {
460 mac
->autoneg_failed
= 1;
463 hw_dbg(hw
, "NOT RXing /C/, disable AutoNeg and force link.\n");
465 /* Disable auto-negotiation in the TXCW register */
466 ew32(TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
468 /* Force link-up and also force full-duplex. */
470 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
473 /* Configure Flow Control after forcing link up. */
474 ret_val
= e1000e_config_fc_after_link_up(hw
);
476 hw_dbg(hw
, "Error configuring flow control\n");
479 } else if ((ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
480 /* If we are forcing link and we are receiving /C/ ordered
481 * sets, re-enable auto-negotiation in the TXCW register
482 * and disable forced link in the Device Control register
483 * in an attempt to auto-negotiate with our link partner.
485 hw_dbg(hw
, "RXing /C/, enable AutoNeg and stop forcing link.\n");
486 ew32(TXCW
, mac
->txcw
);
487 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
489 mac
->serdes_has_link
= 1;
496 * e1000e_check_for_serdes_link - Check for link (Serdes)
497 * @hw: pointer to the HW structure
499 * Checks for link up on the hardware. If link is not up and we have
500 * a signal, then we need to force link up.
502 s32
e1000e_check_for_serdes_link(struct e1000_hw
*hw
)
504 struct e1000_mac_info
*mac
= &hw
->mac
;
511 status
= er32(STATUS
);
514 /* If we don't have link (auto-negotiation failed or link partner
515 * cannot auto-negotiate), and our link partner is not trying to
516 * auto-negotiate with us (we are receiving idles or data),
517 * we need to force link up. We also need to give auto-negotiation
520 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
521 if ((!(status
& E1000_STATUS_LU
)) && (!(rxcw
& E1000_RXCW_C
))) {
522 if (mac
->autoneg_failed
== 0) {
523 mac
->autoneg_failed
= 1;
526 hw_dbg(hw
, "NOT RXing /C/, disable AutoNeg and force link.\n");
528 /* Disable auto-negotiation in the TXCW register */
529 ew32(TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
531 /* Force link-up and also force full-duplex. */
533 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
536 /* Configure Flow Control after forcing link up. */
537 ret_val
= e1000e_config_fc_after_link_up(hw
);
539 hw_dbg(hw
, "Error configuring flow control\n");
542 } else if ((ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
543 /* If we are forcing link and we are receiving /C/ ordered
544 * sets, re-enable auto-negotiation in the TXCW register
545 * and disable forced link in the Device Control register
546 * in an attempt to auto-negotiate with our link partner.
548 hw_dbg(hw
, "RXing /C/, enable AutoNeg and stop forcing link.\n");
549 ew32(TXCW
, mac
->txcw
);
550 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
552 mac
->serdes_has_link
= 1;
553 } else if (!(E1000_TXCW_ANE
& er32(TXCW
))) {
554 /* If we force link for non-auto-negotiation switch, check
555 * link status based on MAC synchronization for internal
558 /* SYNCH bit and IV bit are sticky. */
560 if (E1000_RXCW_SYNCH
& er32(RXCW
)) {
561 if (!(rxcw
& E1000_RXCW_IV
)) {
562 mac
->serdes_has_link
= 1;
563 hw_dbg(hw
, "SERDES: Link is up.\n");
566 mac
->serdes_has_link
= 0;
567 hw_dbg(hw
, "SERDES: Link is down.\n");
571 if (E1000_TXCW_ANE
& er32(TXCW
)) {
572 status
= er32(STATUS
);
573 mac
->serdes_has_link
= (status
& E1000_STATUS_LU
);
580 * e1000_set_default_fc_generic - Set flow control default values
581 * @hw: pointer to the HW structure
583 * Read the EEPROM for the default values for flow control and store the
586 static s32
e1000_set_default_fc_generic(struct e1000_hw
*hw
)
588 struct e1000_mac_info
*mac
= &hw
->mac
;
592 if (mac
->fc
!= e1000_fc_default
)
595 /* Read and store word 0x0F of the EEPROM. This word contains bits
596 * that determine the hardware's default PAUSE (flow control) mode,
597 * a bit that determines whether the HW defaults to enabling or
598 * disabling auto-negotiation, and the direction of the
599 * SW defined pins. If there is no SW over-ride of the flow
600 * control setting, then the variable hw->fc will
601 * be initialized based on a value in the EEPROM.
603 ret_val
= e1000_read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1, &nvm_data
);
606 hw_dbg(hw
, "NVM Read Error\n");
610 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
611 mac
->fc
= e1000_fc_none
;
612 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) ==
614 mac
->fc
= e1000_fc_tx_pause
;
616 mac
->fc
= e1000_fc_full
;
622 * e1000e_setup_link - Setup flow control and link settings
623 * @hw: pointer to the HW structure
625 * Determines which flow control settings to use, then configures flow
626 * control. Calls the appropriate media-specific link configuration
627 * function. Assuming the adapter has a valid link partner, a valid link
628 * should be established. Assumes the hardware has previously been reset
629 * and the transmitter and receiver are not enabled.
631 s32
e1000e_setup_link(struct e1000_hw
*hw
)
633 struct e1000_mac_info
*mac
= &hw
->mac
;
636 /* In the case of the phy reset being blocked, we already have a link.
637 * We do not need to set it up again.
639 if (e1000_check_reset_block(hw
))
642 ret_val
= e1000_set_default_fc_generic(hw
);
646 /* We want to save off the original Flow Control configuration just
647 * in case we get disconnected and then reconnected into a different
648 * hub or switch with different Flow Control capabilities.
650 mac
->original_fc
= mac
->fc
;
652 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n", mac
->fc
);
654 /* Call the necessary media_type subroutine to configure the link. */
655 ret_val
= mac
->ops
.setup_physical_interface(hw
);
659 /* Initialize the flow control address, type, and PAUSE timer
660 * registers to their default values. This is done even if flow
661 * control is disabled, because it does not hurt anything to
662 * initialize these registers.
664 hw_dbg(hw
, "Initializing the Flow Control address, type and timer regs\n");
665 ew32(FCT
, FLOW_CONTROL_TYPE
);
666 ew32(FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
667 ew32(FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
669 ew32(FCTTV
, mac
->fc_pause_time
);
671 return e1000e_set_fc_watermarks(hw
);
675 * e1000_commit_fc_settings_generic - Configure flow control
676 * @hw: pointer to the HW structure
678 * Write the flow control settings to the Transmit Config Word Register (TXCW)
679 * base on the flow control settings in e1000_mac_info.
681 static s32
e1000_commit_fc_settings_generic(struct e1000_hw
*hw
)
683 struct e1000_mac_info
*mac
= &hw
->mac
;
686 /* Check for a software override of the flow control settings, and
687 * setup the device accordingly. If auto-negotiation is enabled, then
688 * software will have to set the "PAUSE" bits to the correct value in
689 * the Transmit Config Word Register (TXCW) and re-start auto-
690 * negotiation. However, if auto-negotiation is disabled, then
691 * software will have to manually configure the two flow control enable
692 * bits in the CTRL register.
694 * The possible values of the "fc" parameter are:
695 * 0: Flow control is completely disabled
696 * 1: Rx flow control is enabled (we can receive pause frames,
697 * but not send pause frames).
698 * 2: Tx flow control is enabled (we can send pause frames but we
699 * do not support receiving pause frames).
700 * 3: Both Rx and TX flow control (symmetric) are enabled.
704 /* Flow control completely disabled by a software over-ride. */
705 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
707 case e1000_fc_rx_pause
:
708 /* RX Flow control is enabled and TX Flow control is disabled
709 * by a software over-ride. Since there really isn't a way to
710 * advertise that we are capable of RX Pause ONLY, we will
711 * advertise that we support both symmetric and asymmetric RX
712 * PAUSE. Later, we will disable the adapter's ability to send
715 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
717 case e1000_fc_tx_pause
:
718 /* TX Flow control is enabled, and RX Flow control is disabled,
719 * by a software over-ride.
721 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
724 /* Flow control (both RX and TX) is enabled by a software
727 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
730 hw_dbg(hw
, "Flow control param set incorrectly\n");
731 return -E1000_ERR_CONFIG
;
742 * e1000_poll_fiber_serdes_link_generic - Poll for link up
743 * @hw: pointer to the HW structure
745 * Polls for link up by reading the status register, if link fails to come
746 * up with auto-negotiation, then the link is forced if a signal is detected.
748 static s32
e1000_poll_fiber_serdes_link_generic(struct e1000_hw
*hw
)
750 struct e1000_mac_info
*mac
= &hw
->mac
;
754 /* If we have a signal (the cable is plugged in, or assumed true for
755 * serdes media) then poll for a "Link-Up" indication in the Device
756 * Status Register. Time-out if a link isn't seen in 500 milliseconds
757 * seconds (Auto-negotiation should complete in less than 500
758 * milliseconds even if the other end is doing it in SW).
760 for (i
= 0; i
< FIBER_LINK_UP_LIMIT
; i
++) {
762 status
= er32(STATUS
);
763 if (status
& E1000_STATUS_LU
)
766 if (i
== FIBER_LINK_UP_LIMIT
) {
767 hw_dbg(hw
, "Never got a valid link from auto-neg!!!\n");
768 mac
->autoneg_failed
= 1;
769 /* AutoNeg failed to achieve a link, so we'll call
770 * mac->check_for_link. This routine will force the
771 * link up if we detect a signal. This will allow us to
772 * communicate with non-autonegotiating link partners.
774 ret_val
= mac
->ops
.check_for_link(hw
);
776 hw_dbg(hw
, "Error while checking for link\n");
779 mac
->autoneg_failed
= 0;
781 mac
->autoneg_failed
= 0;
782 hw_dbg(hw
, "Valid Link Found\n");
789 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
790 * @hw: pointer to the HW structure
792 * Configures collision distance and flow control for fiber and serdes
793 * links. Upon successful setup, poll for link.
795 s32
e1000e_setup_fiber_serdes_link(struct e1000_hw
*hw
)
802 /* Take the link out of reset */
803 ctrl
&= ~E1000_CTRL_LRST
;
805 e1000e_config_collision_dist(hw
);
807 ret_val
= e1000_commit_fc_settings_generic(hw
);
811 /* Since auto-negotiation is enabled, take the link out of reset (the
812 * link will be in reset, because we previously reset the chip). This
813 * will restart auto-negotiation. If auto-negotiation is successful
814 * then the link-up status bit will be set and the flow control enable
815 * bits (RFCE and TFCE) will be set according to their negotiated value.
817 hw_dbg(hw
, "Auto-negotiation enabled\n");
823 /* For these adapters, the SW defineable pin 1 is set when the optics
824 * detect a signal. If we have a signal, then poll for a "Link-Up"
827 if (hw
->media_type
== e1000_media_type_internal_serdes
||
828 (er32(CTRL
) & E1000_CTRL_SWDPIN1
)) {
829 ret_val
= e1000_poll_fiber_serdes_link_generic(hw
);
831 hw_dbg(hw
, "No signal detected\n");
838 * e1000e_config_collision_dist - Configure collision distance
839 * @hw: pointer to the HW structure
841 * Configures the collision distance to the default value and is used
842 * during link setup. Currently no func pointer exists and all
843 * implementations are handled in the generic version of this function.
845 void e1000e_config_collision_dist(struct e1000_hw
*hw
)
851 tctl
&= ~E1000_TCTL_COLD
;
852 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
859 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
860 * @hw: pointer to the HW structure
862 * Sets the flow control high/low threshold (watermark) registers. If
863 * flow control XON frame transmission is enabled, then set XON frame
864 * tansmission as well.
866 s32
e1000e_set_fc_watermarks(struct e1000_hw
*hw
)
868 struct e1000_mac_info
*mac
= &hw
->mac
;
869 u32 fcrtl
= 0, fcrth
= 0;
871 /* Set the flow control receive threshold registers. Normally,
872 * these registers will be set to a default threshold that may be
873 * adjusted later by the driver's runtime code. However, if the
874 * ability to transmit pause frames is not enabled, then these
875 * registers will be set to 0.
877 if (mac
->fc
& e1000_fc_tx_pause
) {
878 /* We need to set up the Receive Threshold high and low water
879 * marks as well as (optionally) enabling the transmission of
882 fcrtl
= mac
->fc_low_water
;
883 fcrtl
|= E1000_FCRTL_XONE
;
884 fcrth
= mac
->fc_high_water
;
893 * e1000e_force_mac_fc - Force the MAC's flow control settings
894 * @hw: pointer to the HW structure
896 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
897 * device control register to reflect the adapter settings. TFCE and RFCE
898 * need to be explicitly set by software when a copper PHY is used because
899 * autonegotiation is managed by the PHY rather than the MAC. Software must
900 * also configure these bits when link is forced on a fiber connection.
902 s32
e1000e_force_mac_fc(struct e1000_hw
*hw
)
904 struct e1000_mac_info
*mac
= &hw
->mac
;
909 /* Because we didn't get link via the internal auto-negotiation
910 * mechanism (we either forced link or we got link via PHY
911 * auto-neg), we have to manually enable/disable transmit an
912 * receive flow control.
914 * The "Case" statement below enables/disable flow control
915 * according to the "mac->fc" parameter.
917 * The possible values of the "fc" parameter are:
918 * 0: Flow control is completely disabled
919 * 1: Rx flow control is enabled (we can receive pause
920 * frames but not send pause frames).
921 * 2: Tx flow control is enabled (we can send pause frames
922 * frames but we do not receive pause frames).
923 * 3: Both Rx and TX flow control (symmetric) is enabled.
924 * other: No other values should be possible at this point.
926 hw_dbg(hw
, "mac->fc = %u\n", mac
->fc
);
930 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
932 case e1000_fc_rx_pause
:
933 ctrl
&= (~E1000_CTRL_TFCE
);
934 ctrl
|= E1000_CTRL_RFCE
;
936 case e1000_fc_tx_pause
:
937 ctrl
&= (~E1000_CTRL_RFCE
);
938 ctrl
|= E1000_CTRL_TFCE
;
941 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
944 hw_dbg(hw
, "Flow control param set incorrectly\n");
945 return -E1000_ERR_CONFIG
;
954 * e1000e_config_fc_after_link_up - Configures flow control after link
955 * @hw: pointer to the HW structure
957 * Checks the status of auto-negotiation after link up to ensure that the
958 * speed and duplex were not forced. If the link needed to be forced, then
959 * flow control needs to be forced also. If auto-negotiation is enabled
960 * and did not fail, then we configure flow control based on our link
963 s32
e1000e_config_fc_after_link_up(struct e1000_hw
*hw
)
965 struct e1000_mac_info
*mac
= &hw
->mac
;
967 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
970 /* Check for the case where we have fiber media and auto-neg failed
971 * so we had to force link. In this case, we need to force the
972 * configuration of the MAC to match the "fc" parameter.
974 if (mac
->autoneg_failed
) {
975 if (hw
->media_type
== e1000_media_type_fiber
||
976 hw
->media_type
== e1000_media_type_internal_serdes
)
977 ret_val
= e1000e_force_mac_fc(hw
);
979 if (hw
->media_type
== e1000_media_type_copper
)
980 ret_val
= e1000e_force_mac_fc(hw
);
984 hw_dbg(hw
, "Error forcing flow control settings\n");
988 /* Check for the case where we have copper media and auto-neg is
989 * enabled. In this case, we need to check and see if Auto-Neg
990 * has completed, and if so, how the PHY and link partner has
991 * flow control configured.
993 if ((hw
->media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
994 /* Read the MII Status Register and check to see if AutoNeg
995 * has completed. We read this twice because this reg has
996 * some "sticky" (latched) bits.
998 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &mii_status_reg
);
1001 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &mii_status_reg
);
1005 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
1006 hw_dbg(hw
, "Copper PHY and Auto Neg "
1007 "has not completed.\n");
1011 /* The AutoNeg process has completed, so we now need to
1012 * read both the Auto Negotiation Advertisement
1013 * Register (Address 4) and the Auto_Negotiation Base
1014 * Page Ability Register (Address 5) to determine how
1015 * flow control was negotiated.
1017 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_nway_adv_reg
);
1020 ret_val
= e1e_rphy(hw
, PHY_LP_ABILITY
, &mii_nway_lp_ability_reg
);
1024 /* Two bits in the Auto Negotiation Advertisement Register
1025 * (Address 4) and two bits in the Auto Negotiation Base
1026 * Page Ability Register (Address 5) determine flow control
1027 * for both the PHY and the link partner. The following
1028 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1029 * 1999, describes these PAUSE resolution bits and how flow
1030 * control is determined based upon these settings.
1031 * NOTE: DC = Don't Care
1033 * LOCAL DEVICE | LINK PARTNER
1034 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1035 *-------|---------|-------|---------|--------------------
1036 * 0 | 0 | DC | DC | e1000_fc_none
1037 * 0 | 1 | 0 | DC | e1000_fc_none
1038 * 0 | 1 | 1 | 0 | e1000_fc_none
1039 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1040 * 1 | 0 | 0 | DC | e1000_fc_none
1041 * 1 | DC | 1 | DC | e1000_fc_full
1042 * 1 | 1 | 0 | 0 | e1000_fc_none
1043 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1046 /* Are both PAUSE bits set to 1? If so, this implies
1047 * Symmetric Flow Control is enabled at both ends. The
1048 * ASM_DIR bits are irrelevant per the spec.
1050 * For Symmetric Flow Control:
1052 * LOCAL DEVICE | LINK PARTNER
1053 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1054 *-------|---------|-------|---------|--------------------
1055 * 1 | DC | 1 | DC | E1000_fc_full
1058 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1059 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
1060 /* Now we need to check if the user selected RX ONLY
1061 * of pause frames. In this case, we had to advertise
1062 * FULL flow control because we could not advertise RX
1063 * ONLY. Hence, we must now check to see if we need to
1064 * turn OFF the TRANSMISSION of PAUSE frames.
1066 if (mac
->original_fc
== e1000_fc_full
) {
1067 mac
->fc
= e1000_fc_full
;
1068 hw_dbg(hw
, "Flow Control = FULL.\r\n");
1070 mac
->fc
= e1000_fc_rx_pause
;
1071 hw_dbg(hw
, "Flow Control = "
1072 "RX PAUSE frames only.\r\n");
1075 /* For receiving PAUSE frames ONLY.
1077 * LOCAL DEVICE | LINK PARTNER
1078 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1079 *-------|---------|-------|---------|--------------------
1080 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1083 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1084 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
1085 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
1086 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
1087 mac
->fc
= e1000_fc_tx_pause
;
1088 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\r\n");
1090 /* For transmitting PAUSE frames ONLY.
1092 * LOCAL DEVICE | LINK PARTNER
1093 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1094 *-------|---------|-------|---------|--------------------
1095 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1098 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1099 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
1100 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
1101 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
1102 mac
->fc
= e1000_fc_rx_pause
;
1103 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\r\n");
1105 /* Per the IEEE spec, at this point flow control should be
1106 * disabled. However, we want to consider that we could
1107 * be connected to a legacy switch that doesn't advertise
1108 * desired flow control, but can be forced on the link
1109 * partner. So if we advertised no flow control, that is
1110 * what we will resolve to. If we advertised some kind of
1111 * receive capability (Rx Pause Only or Full Flow Control)
1112 * and the link partner advertised none, we will configure
1113 * ourselves to enable Rx Flow Control only. We can do
1114 * this safely for two reasons: If the link partner really
1115 * didn't want flow control enabled, and we enable Rx, no
1116 * harm done since we won't be receiving any PAUSE frames
1117 * anyway. If the intent on the link partner was to have
1118 * flow control enabled, then by us enabling RX only, we
1119 * can at least receive pause frames and process them.
1120 * This is a good idea because in most cases, since we are
1121 * predominantly a server NIC, more times than not we will
1122 * be asked to delay transmission of packets than asking
1123 * our link partner to pause transmission of frames.
1125 else if ((mac
->original_fc
== e1000_fc_none
) ||
1126 (mac
->original_fc
== e1000_fc_tx_pause
)) {
1127 mac
->fc
= e1000_fc_none
;
1128 hw_dbg(hw
, "Flow Control = NONE.\r\n");
1130 mac
->fc
= e1000_fc_rx_pause
;
1131 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\r\n");
1134 /* Now we need to do one last check... If we auto-
1135 * negotiated to HALF DUPLEX, flow control should not be
1136 * enabled per IEEE 802.3 spec.
1138 ret_val
= mac
->ops
.get_link_up_info(hw
, &speed
, &duplex
);
1140 hw_dbg(hw
, "Error getting link speed and duplex\n");
1144 if (duplex
== HALF_DUPLEX
)
1145 mac
->fc
= e1000_fc_none
;
1147 /* Now we call a subroutine to actually force the MAC
1148 * controller to use the correct flow control settings.
1150 ret_val
= e1000e_force_mac_fc(hw
);
1152 hw_dbg(hw
, "Error forcing flow control settings\n");
1161 * e1000e_get_speed_and_duplex_copper - Retreive current speed/duplex
1162 * @hw: pointer to the HW structure
1163 * @speed: stores the current speed
1164 * @duplex: stores the current duplex
1166 * Read the status register for the current speed/duplex and store the current
1167 * speed and duplex for copper connections.
1169 s32
e1000e_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
, u16
*duplex
)
1173 status
= er32(STATUS
);
1174 if (status
& E1000_STATUS_SPEED_1000
) {
1175 *speed
= SPEED_1000
;
1176 hw_dbg(hw
, "1000 Mbs, ");
1177 } else if (status
& E1000_STATUS_SPEED_100
) {
1179 hw_dbg(hw
, "100 Mbs, ");
1182 hw_dbg(hw
, "10 Mbs, ");
1185 if (status
& E1000_STATUS_FD
) {
1186 *duplex
= FULL_DUPLEX
;
1187 hw_dbg(hw
, "Full Duplex\n");
1189 *duplex
= HALF_DUPLEX
;
1190 hw_dbg(hw
, "Half Duplex\n");
1197 * e1000e_get_speed_and_duplex_fiber_serdes - Retreive current speed/duplex
1198 * @hw: pointer to the HW structure
1199 * @speed: stores the current speed
1200 * @duplex: stores the current duplex
1202 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1203 * for fiber/serdes links.
1205 s32
e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw
*hw
, u16
*speed
, u16
*duplex
)
1207 *speed
= SPEED_1000
;
1208 *duplex
= FULL_DUPLEX
;
1214 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1215 * @hw: pointer to the HW structure
1217 * Acquire the HW semaphore to access the PHY or NVM
1219 s32
e1000e_get_hw_semaphore(struct e1000_hw
*hw
)
1222 s32 timeout
= hw
->nvm
.word_size
+ 1;
1225 /* Get the SW semaphore */
1226 while (i
< timeout
) {
1228 if (!(swsm
& E1000_SWSM_SMBI
))
1236 hw_dbg(hw
, "Driver can't access device - SMBI bit is set.\n");
1237 return -E1000_ERR_NVM
;
1240 /* Get the FW semaphore. */
1241 for (i
= 0; i
< timeout
; i
++) {
1243 ew32(SWSM
, swsm
| E1000_SWSM_SWESMBI
);
1245 /* Semaphore acquired if bit latched */
1246 if (er32(SWSM
) & E1000_SWSM_SWESMBI
)
1253 /* Release semaphores */
1254 e1000e_put_hw_semaphore(hw
);
1255 hw_dbg(hw
, "Driver can't access the NVM\n");
1256 return -E1000_ERR_NVM
;
1263 * e1000e_put_hw_semaphore - Release hardware semaphore
1264 * @hw: pointer to the HW structure
1266 * Release hardware semaphore used to access the PHY or NVM
1268 void e1000e_put_hw_semaphore(struct e1000_hw
*hw
)
1273 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1278 * e1000e_get_auto_rd_done - Check for auto read completion
1279 * @hw: pointer to the HW structure
1281 * Check EEPROM for Auto Read done bit.
1283 s32
e1000e_get_auto_rd_done(struct e1000_hw
*hw
)
1287 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1288 if (er32(EECD
) & E1000_EECD_AUTO_RD
)
1294 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1295 hw_dbg(hw
, "Auto read by HW from NVM has not completed.\n");
1296 return -E1000_ERR_RESET
;
1303 * e1000e_valid_led_default - Verify a valid default LED config
1304 * @hw: pointer to the HW structure
1305 * @data: pointer to the NVM (EEPROM)
1307 * Read the EEPROM for the current default LED configuration. If the
1308 * LED configuration is not valid, set to a valid LED configuration.
1310 s32
e1000e_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1314 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1316 hw_dbg(hw
, "NVM Read Error\n");
1320 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
1321 *data
= ID_LED_DEFAULT
;
1327 * e1000e_id_led_init -
1328 * @hw: pointer to the HW structure
1331 s32
e1000e_id_led_init(struct e1000_hw
*hw
)
1333 struct e1000_mac_info
*mac
= &hw
->mac
;
1335 const u32 ledctl_mask
= 0x000000FF;
1336 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1337 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1339 const u16 led_mask
= 0x0F;
1341 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
1345 mac
->ledctl_default
= er32(LEDCTL
);
1346 mac
->ledctl_mode1
= mac
->ledctl_default
;
1347 mac
->ledctl_mode2
= mac
->ledctl_default
;
1349 for (i
= 0; i
< 4; i
++) {
1350 temp
= (data
>> (i
<< 2)) & led_mask
;
1352 case ID_LED_ON1_DEF2
:
1353 case ID_LED_ON1_ON2
:
1354 case ID_LED_ON1_OFF2
:
1355 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1356 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1358 case ID_LED_OFF1_DEF2
:
1359 case ID_LED_OFF1_ON2
:
1360 case ID_LED_OFF1_OFF2
:
1361 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1362 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1369 case ID_LED_DEF1_ON2
:
1370 case ID_LED_ON1_ON2
:
1371 case ID_LED_OFF1_ON2
:
1372 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1373 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1375 case ID_LED_DEF1_OFF2
:
1376 case ID_LED_ON1_OFF2
:
1377 case ID_LED_OFF1_OFF2
:
1378 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1379 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1391 * e1000e_cleanup_led_generic - Set LED config to default operation
1392 * @hw: pointer to the HW structure
1394 * Remove the current LED configuration and set the LED configuration
1395 * to the default value, saved from the EEPROM.
1397 s32
e1000e_cleanup_led_generic(struct e1000_hw
*hw
)
1399 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
1404 * e1000e_blink_led - Blink LED
1405 * @hw: pointer to the HW structure
1407 * Blink the led's which are set to be on.
1409 s32
e1000e_blink_led(struct e1000_hw
*hw
)
1411 u32 ledctl_blink
= 0;
1414 if (hw
->media_type
== e1000_media_type_fiber
) {
1415 /* always blink LED0 for PCI-E fiber */
1416 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1417 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1419 /* set the blink bit for each LED that's "on" (0x0E)
1420 * in ledctl_mode2 */
1421 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1422 for (i
= 0; i
< 4; i
++)
1423 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1424 E1000_LEDCTL_MODE_LED_ON
)
1425 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
<<
1429 ew32(LEDCTL
, ledctl_blink
);
1435 * e1000e_led_on_generic - Turn LED on
1436 * @hw: pointer to the HW structure
1440 s32
e1000e_led_on_generic(struct e1000_hw
*hw
)
1444 switch (hw
->media_type
) {
1445 case e1000_media_type_fiber
:
1447 ctrl
&= ~E1000_CTRL_SWDPIN0
;
1448 ctrl
|= E1000_CTRL_SWDPIO0
;
1451 case e1000_media_type_copper
:
1452 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
1462 * e1000e_led_off_generic - Turn LED off
1463 * @hw: pointer to the HW structure
1467 s32
e1000e_led_off_generic(struct e1000_hw
*hw
)
1471 switch (hw
->media_type
) {
1472 case e1000_media_type_fiber
:
1474 ctrl
|= E1000_CTRL_SWDPIN0
;
1475 ctrl
|= E1000_CTRL_SWDPIO0
;
1478 case e1000_media_type_copper
:
1479 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
1489 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1490 * @hw: pointer to the HW structure
1491 * @no_snoop: bitmap of snoop events
1493 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1495 void e1000e_set_pcie_no_snoop(struct e1000_hw
*hw
, u32 no_snoop
)
1501 gcr
&= ~(PCIE_NO_SNOOP_ALL
);
1508 * e1000e_disable_pcie_master - Disables PCI-express master access
1509 * @hw: pointer to the HW structure
1511 * Returns 0 if successful, else returns -10
1512 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1513 * the master requests to be disabled.
1515 * Disables PCI-Express master access and verifies there are no pending
1518 s32
e1000e_disable_pcie_master(struct e1000_hw
*hw
)
1521 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1524 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1528 if (!(er32(STATUS
) &
1529 E1000_STATUS_GIO_MASTER_ENABLE
))
1536 hw_dbg(hw
, "Master requests are pending.\n");
1537 return -E1000_ERR_MASTER_REQUESTS_PENDING
;
1544 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1545 * @hw: pointer to the HW structure
1547 * Reset the Adaptive Interframe Spacing throttle to default values.
1549 void e1000e_reset_adaptive(struct e1000_hw
*hw
)
1551 struct e1000_mac_info
*mac
= &hw
->mac
;
1553 mac
->current_ifs_val
= 0;
1554 mac
->ifs_min_val
= IFS_MIN
;
1555 mac
->ifs_max_val
= IFS_MAX
;
1556 mac
->ifs_step_size
= IFS_STEP
;
1557 mac
->ifs_ratio
= IFS_RATIO
;
1559 mac
->in_ifs_mode
= 0;
1564 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1565 * @hw: pointer to the HW structure
1567 * Update the Adaptive Interframe Spacing Throttle value based on the
1568 * time between transmitted packets and time between collisions.
1570 void e1000e_update_adaptive(struct e1000_hw
*hw
)
1572 struct e1000_mac_info
*mac
= &hw
->mac
;
1574 if ((mac
->collision_delta
* mac
->ifs_ratio
) > mac
->tx_packet_delta
) {
1575 if (mac
->tx_packet_delta
> MIN_NUM_XMITS
) {
1576 mac
->in_ifs_mode
= 1;
1577 if (mac
->current_ifs_val
< mac
->ifs_max_val
) {
1578 if (!mac
->current_ifs_val
)
1579 mac
->current_ifs_val
= mac
->ifs_min_val
;
1581 mac
->current_ifs_val
+=
1584 mac
->current_ifs_val
);
1588 if (mac
->in_ifs_mode
&&
1589 (mac
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
1590 mac
->current_ifs_val
= 0;
1591 mac
->in_ifs_mode
= 0;
1598 * e1000_raise_eec_clk - Raise EEPROM clock
1599 * @hw: pointer to the HW structure
1600 * @eecd: pointer to the EEPROM
1602 * Enable/Raise the EEPROM clock bit.
1604 static void e1000_raise_eec_clk(struct e1000_hw
*hw
, u32
*eecd
)
1606 *eecd
= *eecd
| E1000_EECD_SK
;
1609 udelay(hw
->nvm
.delay_usec
);
1613 * e1000_lower_eec_clk - Lower EEPROM clock
1614 * @hw: pointer to the HW structure
1615 * @eecd: pointer to the EEPROM
1617 * Clear/Lower the EEPROM clock bit.
1619 static void e1000_lower_eec_clk(struct e1000_hw
*hw
, u32
*eecd
)
1621 *eecd
= *eecd
& ~E1000_EECD_SK
;
1624 udelay(hw
->nvm
.delay_usec
);
1628 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1629 * @hw: pointer to the HW structure
1630 * @data: data to send to the EEPROM
1631 * @count: number of bits to shift out
1633 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1634 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1635 * In order to do this, "data" must be broken down into bits.
1637 static void e1000_shift_out_eec_bits(struct e1000_hw
*hw
, u16 data
, u16 count
)
1639 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1640 u32 eecd
= er32(EECD
);
1643 mask
= 0x01 << (count
- 1);
1644 if (nvm
->type
== e1000_nvm_eeprom_spi
)
1645 eecd
|= E1000_EECD_DO
;
1648 eecd
&= ~E1000_EECD_DI
;
1651 eecd
|= E1000_EECD_DI
;
1656 udelay(nvm
->delay_usec
);
1658 e1000_raise_eec_clk(hw
, &eecd
);
1659 e1000_lower_eec_clk(hw
, &eecd
);
1664 eecd
&= ~E1000_EECD_DI
;
1669 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1670 * @hw: pointer to the HW structure
1671 * @count: number of bits to shift in
1673 * In order to read a register from the EEPROM, we need to shift 'count' bits
1674 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1675 * the EEPROM (setting the SK bit), and then reading the value of the data out
1676 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1679 static u16
e1000_shift_in_eec_bits(struct e1000_hw
*hw
, u16 count
)
1687 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
1690 for (i
= 0; i
< count
; i
++) {
1692 e1000_raise_eec_clk(hw
, &eecd
);
1696 eecd
&= ~E1000_EECD_DI
;
1697 if (eecd
& E1000_EECD_DO
)
1700 e1000_lower_eec_clk(hw
, &eecd
);
1707 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1708 * @hw: pointer to the HW structure
1709 * @ee_reg: EEPROM flag for polling
1711 * Polls the EEPROM status bit for either read or write completion based
1712 * upon the value of 'ee_reg'.
1714 s32
e1000e_poll_eerd_eewr_done(struct e1000_hw
*hw
, int ee_reg
)
1716 u32 attempts
= 100000;
1719 for (i
= 0; i
< attempts
; i
++) {
1720 if (ee_reg
== E1000_NVM_POLL_READ
)
1725 if (reg
& E1000_NVM_RW_REG_DONE
)
1731 return -E1000_ERR_NVM
;
1735 * e1000e_acquire_nvm - Generic request for access to EEPROM
1736 * @hw: pointer to the HW structure
1738 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1739 * Return successful if access grant bit set, else clear the request for
1740 * EEPROM access and return -E1000_ERR_NVM (-1).
1742 s32
e1000e_acquire_nvm(struct e1000_hw
*hw
)
1744 u32 eecd
= er32(EECD
);
1745 s32 timeout
= E1000_NVM_GRANT_ATTEMPTS
;
1747 ew32(EECD
, eecd
| E1000_EECD_REQ
);
1751 if (eecd
& E1000_EECD_GNT
)
1759 eecd
&= ~E1000_EECD_REQ
;
1761 hw_dbg(hw
, "Could not acquire NVM grant\n");
1762 return -E1000_ERR_NVM
;
1769 * e1000_standby_nvm - Return EEPROM to standby state
1770 * @hw: pointer to the HW structure
1772 * Return the EEPROM to a standby state.
1774 static void e1000_standby_nvm(struct e1000_hw
*hw
)
1776 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1777 u32 eecd
= er32(EECD
);
1779 if (nvm
->type
== e1000_nvm_eeprom_spi
) {
1780 /* Toggle CS to flush commands */
1781 eecd
|= E1000_EECD_CS
;
1784 udelay(nvm
->delay_usec
);
1785 eecd
&= ~E1000_EECD_CS
;
1788 udelay(nvm
->delay_usec
);
1793 * e1000_stop_nvm - Terminate EEPROM command
1794 * @hw: pointer to the HW structure
1796 * Terminates the current command by inverting the EEPROM's chip select pin.
1798 static void e1000_stop_nvm(struct e1000_hw
*hw
)
1803 if (hw
->nvm
.type
== e1000_nvm_eeprom_spi
) {
1805 eecd
|= E1000_EECD_CS
;
1806 e1000_lower_eec_clk(hw
, &eecd
);
1811 * e1000e_release_nvm - Release exclusive access to EEPROM
1812 * @hw: pointer to the HW structure
1814 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1816 void e1000e_release_nvm(struct e1000_hw
*hw
)
1823 eecd
&= ~E1000_EECD_REQ
;
1828 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1829 * @hw: pointer to the HW structure
1831 * Setups the EEPROM for reading and writing.
1833 static s32
e1000_ready_nvm_eeprom(struct e1000_hw
*hw
)
1835 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1836 u32 eecd
= er32(EECD
);
1840 if (nvm
->type
== e1000_nvm_eeprom_spi
) {
1841 /* Clear SK and CS */
1842 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
1845 timeout
= NVM_MAX_RETRY_SPI
;
1847 /* Read "Status Register" repeatedly until the LSB is cleared.
1848 * The EEPROM will signal that the command has been completed
1849 * by clearing bit 0 of the internal status register. If it's
1850 * not cleared within 'timeout', then error out. */
1852 e1000_shift_out_eec_bits(hw
, NVM_RDSR_OPCODE_SPI
,
1853 hw
->nvm
.opcode_bits
);
1854 spi_stat_reg
= (u8
)e1000_shift_in_eec_bits(hw
, 8);
1855 if (!(spi_stat_reg
& NVM_STATUS_RDY_SPI
))
1859 e1000_standby_nvm(hw
);
1864 hw_dbg(hw
, "SPI NVM Status error\n");
1865 return -E1000_ERR_NVM
;
1873 * e1000e_read_nvm_spi - Read EEPROM's using SPI
1874 * @hw: pointer to the HW structure
1875 * @offset: offset of word in the EEPROM to read
1876 * @words: number of words to read
1877 * @data: word read from the EEPROM
1879 * Reads a 16 bit word from the EEPROM.
1881 s32
e1000e_read_nvm_spi(struct e1000_hw
*hw
, u16 offset
, u16 words
, u16
*data
)
1883 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1887 u8 read_opcode
= NVM_READ_OPCODE_SPI
;
1889 /* A check for invalid values: offset too large, too many words,
1890 * and not enough words. */
1891 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
1893 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1894 return -E1000_ERR_NVM
;
1897 ret_val
= nvm
->ops
.acquire_nvm(hw
);
1901 ret_val
= e1000_ready_nvm_eeprom(hw
);
1903 nvm
->ops
.release_nvm(hw
);
1907 e1000_standby_nvm(hw
);
1909 if ((nvm
->address_bits
== 8) && (offset
>= 128))
1910 read_opcode
|= NVM_A8_OPCODE_SPI
;
1912 /* Send the READ command (opcode + addr) */
1913 e1000_shift_out_eec_bits(hw
, read_opcode
, nvm
->opcode_bits
);
1914 e1000_shift_out_eec_bits(hw
, (u16
)(offset
*2), nvm
->address_bits
);
1916 /* Read the data. SPI NVMs increment the address with each byte
1917 * read and will roll over if reading beyond the end. This allows
1918 * us to read the whole NVM from any offset */
1919 for (i
= 0; i
< words
; i
++) {
1920 word_in
= e1000_shift_in_eec_bits(hw
, 16);
1921 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
1924 nvm
->ops
.release_nvm(hw
);
1929 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
1930 * @hw: pointer to the HW structure
1931 * @offset: offset of word in the EEPROM to read
1932 * @words: number of words to read
1933 * @data: word read from the EEPROM
1935 * Reads a 16 bit word from the EEPROM using the EERD register.
1937 s32
e1000e_read_nvm_eerd(struct e1000_hw
*hw
, u16 offset
, u16 words
, u16
*data
)
1939 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1943 /* A check for invalid values: offset too large, too many words,
1944 * and not enough words. */
1945 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
1947 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1948 return -E1000_ERR_NVM
;
1951 for (i
= 0; i
< words
; i
++) {
1952 eerd
= ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) +
1953 E1000_NVM_RW_REG_START
;
1956 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_READ
);
1960 data
[i
] = (er32(EERD
) >>
1961 E1000_NVM_RW_REG_DATA
);
1968 * e1000e_write_nvm_spi - Write to EEPROM using SPI
1969 * @hw: pointer to the HW structure
1970 * @offset: offset within the EEPROM to be written to
1971 * @words: number of words to write
1972 * @data: 16 bit word(s) to be written to the EEPROM
1974 * Writes data to EEPROM at offset using SPI interface.
1976 * If e1000e_update_nvm_checksum is not called after this function , the
1977 * EEPROM will most likley contain an invalid checksum.
1979 s32
e1000e_write_nvm_spi(struct e1000_hw
*hw
, u16 offset
, u16 words
, u16
*data
)
1981 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1985 /* A check for invalid values: offset too large, too many words,
1986 * and not enough words. */
1987 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
1989 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1990 return -E1000_ERR_NVM
;
1993 ret_val
= nvm
->ops
.acquire_nvm(hw
);
1999 while (widx
< words
) {
2000 u8 write_opcode
= NVM_WRITE_OPCODE_SPI
;
2002 ret_val
= e1000_ready_nvm_eeprom(hw
);
2004 nvm
->ops
.release_nvm(hw
);
2008 e1000_standby_nvm(hw
);
2010 /* Send the WRITE ENABLE command (8 bit opcode) */
2011 e1000_shift_out_eec_bits(hw
, NVM_WREN_OPCODE_SPI
,
2014 e1000_standby_nvm(hw
);
2016 /* Some SPI eeproms use the 8th address bit embedded in the
2018 if ((nvm
->address_bits
== 8) && (offset
>= 128))
2019 write_opcode
|= NVM_A8_OPCODE_SPI
;
2021 /* Send the Write command (8-bit opcode + addr) */
2022 e1000_shift_out_eec_bits(hw
, write_opcode
, nvm
->opcode_bits
);
2023 e1000_shift_out_eec_bits(hw
, (u16
)((offset
+ widx
) * 2),
2026 /* Loop to allow for up to whole page write of eeprom */
2027 while (widx
< words
) {
2028 u16 word_out
= data
[widx
];
2029 word_out
= (word_out
>> 8) | (word_out
<< 8);
2030 e1000_shift_out_eec_bits(hw
, word_out
, 16);
2033 if ((((offset
+ widx
) * 2) % nvm
->page_size
) == 0) {
2034 e1000_standby_nvm(hw
);
2045 * e1000e_read_mac_addr - Read device MAC address
2046 * @hw: pointer to the HW structure
2048 * Reads the device MAC address from the EEPROM and stores the value.
2049 * Since devices with two ports use the same EEPROM, we increment the
2050 * last bit in the MAC address for the second port.
2052 s32
e1000e_read_mac_addr(struct e1000_hw
*hw
)
2055 u16 offset
, nvm_data
, i
;
2057 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
2059 ret_val
= e1000_read_nvm(hw
, offset
, 1, &nvm_data
);
2061 hw_dbg(hw
, "NVM Read Error\n");
2064 hw
->mac
.perm_addr
[i
] = (u8
)(nvm_data
& 0xFF);
2065 hw
->mac
.perm_addr
[i
+1] = (u8
)(nvm_data
>> 8);
2068 /* Flip last bit of mac address if we're on second port */
2069 if (hw
->bus
.func
== E1000_FUNC_1
)
2070 hw
->mac
.perm_addr
[5] ^= 1;
2072 for (i
= 0; i
< ETH_ALEN
; i
++)
2073 hw
->mac
.addr
[i
] = hw
->mac
.perm_addr
[i
];
2079 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2080 * @hw: pointer to the HW structure
2082 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2083 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2085 s32
e1000e_validate_nvm_checksum_generic(struct e1000_hw
*hw
)
2091 for (i
= 0; i
< (NVM_CHECKSUM_REG
+ 1); i
++) {
2092 ret_val
= e1000_read_nvm(hw
, i
, 1, &nvm_data
);
2094 hw_dbg(hw
, "NVM Read Error\n");
2097 checksum
+= nvm_data
;
2100 if (checksum
!= (u16
) NVM_SUM
) {
2101 hw_dbg(hw
, "NVM Checksum Invalid\n");
2102 return -E1000_ERR_NVM
;
2109 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2110 * @hw: pointer to the HW structure
2112 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2113 * up to the checksum. Then calculates the EEPROM checksum and writes the
2114 * value to the EEPROM.
2116 s32
e1000e_update_nvm_checksum_generic(struct e1000_hw
*hw
)
2122 for (i
= 0; i
< NVM_CHECKSUM_REG
; i
++) {
2123 ret_val
= e1000_read_nvm(hw
, i
, 1, &nvm_data
);
2125 hw_dbg(hw
, "NVM Read Error while updating checksum.\n");
2128 checksum
+= nvm_data
;
2130 checksum
= (u16
) NVM_SUM
- checksum
;
2131 ret_val
= e1000_write_nvm(hw
, NVM_CHECKSUM_REG
, 1, &checksum
);
2133 hw_dbg(hw
, "NVM Write Error while updating checksum.\n");
2139 * e1000e_reload_nvm - Reloads EEPROM
2140 * @hw: pointer to the HW structure
2142 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2143 * extended control register.
2145 void e1000e_reload_nvm(struct e1000_hw
*hw
)
2150 ctrl_ext
= er32(CTRL_EXT
);
2151 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
2152 ew32(CTRL_EXT
, ctrl_ext
);
2157 * e1000_calculate_checksum - Calculate checksum for buffer
2158 * @buffer: pointer to EEPROM
2159 * @length: size of EEPROM to calculate a checksum for
2161 * Calculates the checksum for some buffer on a specified length. The
2162 * checksum calculated is returned.
2164 static u8
e1000_calculate_checksum(u8
*buffer
, u32 length
)
2172 for (i
= 0; i
< length
; i
++)
2175 return (u8
) (0 - sum
);
2179 * e1000_mng_enable_host_if - Checks host interface is enabled
2180 * @hw: pointer to the HW structure
2182 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2184 * This function checks whether the HOST IF is enabled for command operaton
2185 * and also checks whether the previous command is completed. It busy waits
2186 * in case of previous command is not completed.
2188 static s32
e1000_mng_enable_host_if(struct e1000_hw
*hw
)
2193 /* Check that the host interface is enabled. */
2195 if ((hicr
& E1000_HICR_EN
) == 0) {
2196 hw_dbg(hw
, "E1000_HOST_EN bit disabled.\n");
2197 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
2199 /* check the previous command is completed */
2200 for (i
= 0; i
< E1000_MNG_DHCP_COMMAND_TIMEOUT
; i
++) {
2202 if (!(hicr
& E1000_HICR_C
))
2207 if (i
== E1000_MNG_DHCP_COMMAND_TIMEOUT
) {
2208 hw_dbg(hw
, "Previous command timeout failed .\n");
2209 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
2216 * e1000e_check_mng_mode - check managament mode
2217 * @hw: pointer to the HW structure
2219 * Reads the firmware semaphore register and returns true (>0) if
2220 * manageability is enabled, else false (0).
2222 bool e1000e_check_mng_mode(struct e1000_hw
*hw
)
2224 u32 fwsm
= er32(FWSM
);
2226 return (fwsm
& E1000_FWSM_MODE_MASK
) == hw
->mac
.ops
.mng_mode_enab
;
2230 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX
2231 * @hw: pointer to the HW structure
2233 * Enables packet filtering on transmit packets if manageability is enabled
2234 * and host interface is enabled.
2236 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw
*hw
)
2238 struct e1000_host_mng_dhcp_cookie
*hdr
= &hw
->mng_cookie
;
2239 u32
*buffer
= (u32
*)&hw
->mng_cookie
;
2241 s32 ret_val
, hdr_csum
, csum
;
2244 /* No manageability, no filtering */
2245 if (!e1000e_check_mng_mode(hw
)) {
2246 hw
->mac
.tx_pkt_filtering
= 0;
2250 /* If we can't read from the host interface for whatever
2251 * reason, disable filtering.
2253 ret_val
= e1000_mng_enable_host_if(hw
);
2255 hw
->mac
.tx_pkt_filtering
= 0;
2259 /* Read in the header. Length and offset are in dwords. */
2260 len
= E1000_MNG_DHCP_COOKIE_LENGTH
>> 2;
2261 offset
= E1000_MNG_DHCP_COOKIE_OFFSET
>> 2;
2262 for (i
= 0; i
< len
; i
++)
2263 *(buffer
+ i
) = E1000_READ_REG_ARRAY(hw
, E1000_HOST_IF
, offset
+ i
);
2264 hdr_csum
= hdr
->checksum
;
2266 csum
= e1000_calculate_checksum((u8
*)hdr
,
2267 E1000_MNG_DHCP_COOKIE_LENGTH
);
2268 /* If either the checksums or signature don't match, then
2269 * the cookie area isn't considered valid, in which case we
2270 * take the safe route of assuming Tx filtering is enabled.
2272 if ((hdr_csum
!= csum
) || (hdr
->signature
!= E1000_IAMT_SIGNATURE
)) {
2273 hw
->mac
.tx_pkt_filtering
= 1;
2277 /* Cookie area is valid, make the final check for filtering. */
2278 if (!(hdr
->status
& E1000_MNG_DHCP_COOKIE_STATUS_PARSING
)) {
2279 hw
->mac
.tx_pkt_filtering
= 0;
2283 hw
->mac
.tx_pkt_filtering
= 1;
2288 * e1000_mng_write_cmd_header - Writes manageability command header
2289 * @hw: pointer to the HW structure
2290 * @hdr: pointer to the host interface command header
2292 * Writes the command header after does the checksum calculation.
2294 static s32
e1000_mng_write_cmd_header(struct e1000_hw
*hw
,
2295 struct e1000_host_mng_command_header
*hdr
)
2297 u16 i
, length
= sizeof(struct e1000_host_mng_command_header
);
2299 /* Write the whole command header structure with new checksum. */
2301 hdr
->checksum
= e1000_calculate_checksum((u8
*)hdr
, length
);
2304 /* Write the relevant command block into the ram area. */
2305 for (i
= 0; i
< length
; i
++) {
2306 E1000_WRITE_REG_ARRAY(hw
, E1000_HOST_IF
, i
,
2307 *((u32
*) hdr
+ i
));
2315 * e1000_mng_host_if_write - Writes to the manageability host interface
2316 * @hw: pointer to the HW structure
2317 * @buffer: pointer to the host interface buffer
2318 * @length: size of the buffer
2319 * @offset: location in the buffer to write to
2320 * @sum: sum of the data (not checksum)
2322 * This function writes the buffer content at the offset given on the host if.
2323 * It also does alignment considerations to do the writes in most efficient
2324 * way. Also fills up the sum of the buffer in *buffer parameter.
2326 static s32
e1000_mng_host_if_write(struct e1000_hw
*hw
, u8
*buffer
,
2327 u16 length
, u16 offset
, u8
*sum
)
2330 u8
*bufptr
= buffer
;
2332 u16 remaining
, i
, j
, prev_bytes
;
2334 /* sum = only sum of the data and it is not checksum */
2336 if (length
== 0 || offset
+ length
> E1000_HI_MAX_MNG_DATA_LENGTH
)
2337 return -E1000_ERR_PARAM
;
2340 prev_bytes
= offset
& 0x3;
2344 data
= E1000_READ_REG_ARRAY(hw
, E1000_HOST_IF
, offset
);
2345 for (j
= prev_bytes
; j
< sizeof(u32
); j
++) {
2346 *(tmp
+ j
) = *bufptr
++;
2349 E1000_WRITE_REG_ARRAY(hw
, E1000_HOST_IF
, offset
, data
);
2350 length
-= j
- prev_bytes
;
2354 remaining
= length
& 0x3;
2355 length
-= remaining
;
2357 /* Calculate length in DWORDs */
2360 /* The device driver writes the relevant command block into the
2362 for (i
= 0; i
< length
; i
++) {
2363 for (j
= 0; j
< sizeof(u32
); j
++) {
2364 *(tmp
+ j
) = *bufptr
++;
2368 E1000_WRITE_REG_ARRAY(hw
, E1000_HOST_IF
, offset
+ i
, data
);
2371 for (j
= 0; j
< sizeof(u32
); j
++) {
2373 *(tmp
+ j
) = *bufptr
++;
2379 E1000_WRITE_REG_ARRAY(hw
, E1000_HOST_IF
, offset
+ i
, data
);
2386 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2387 * @hw: pointer to the HW structure
2388 * @buffer: pointer to the host interface
2389 * @length: size of the buffer
2391 * Writes the DHCP information to the host interface.
2393 s32
e1000e_mng_write_dhcp_info(struct e1000_hw
*hw
, u8
*buffer
, u16 length
)
2395 struct e1000_host_mng_command_header hdr
;
2399 hdr
.command_id
= E1000_MNG_DHCP_TX_PAYLOAD_CMD
;
2400 hdr
.command_length
= length
;
2405 /* Enable the host interface */
2406 ret_val
= e1000_mng_enable_host_if(hw
);
2410 /* Populate the host interface with the contents of "buffer". */
2411 ret_val
= e1000_mng_host_if_write(hw
, buffer
, length
,
2412 sizeof(hdr
), &(hdr
.checksum
));
2416 /* Write the manageability command header */
2417 ret_val
= e1000_mng_write_cmd_header(hw
, &hdr
);
2421 /* Tell the ARC a new command is pending. */
2423 ew32(HICR
, hicr
| E1000_HICR_C
);
2429 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2430 * @hw: pointer to the HW structure
2432 * Verifies the hardware needs to allow ARPs to be processed by the host.
2434 bool e1000e_enable_mng_pass_thru(struct e1000_hw
*hw
)
2442 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
2443 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
2446 if (hw
->mac
.arc_subsystem_valid
) {
2448 factps
= er32(FACTPS
);
2450 if (!(factps
& E1000_FACTPS_MNGCG
) &&
2451 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
2452 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
2457 if ((manc
& E1000_MANC_SMBUS_EN
) &&
2458 !(manc
& E1000_MANC_ASF_EN
)) {
2467 s32
e1000e_read_part_num(struct e1000_hw
*hw
, u32
*part_num
)
2472 ret_val
= e1000_read_nvm(hw
, NVM_PBA_OFFSET_0
, 1, &nvm_data
);
2474 hw_dbg(hw
, "NVM Read Error\n");
2477 *part_num
= (u32
)(nvm_data
<< 16);
2479 ret_val
= e1000_read_nvm(hw
, NVM_PBA_OFFSET_1
, 1, &nvm_data
);
2481 hw_dbg(hw
, "NVM Read Error\n");
2484 *part_num
|= nvm_data
;