drivers/net/enic/enic.h

   1 /*
   2  * Copyright 2008 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  *
   5  * This program is free software; you may redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16  * SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef _ENIC_H_
  21 #define _ENIC_H_
  22
  23 #include <linux/inet_lro.h>
  24
  25 #include "vnic_enet.h"
  26 #include "vnic_dev.h"
  27 #include "vnic_wq.h"
  28 #include "vnic_rq.h"
  29 #include "vnic_cq.h"
  30 #include "vnic_intr.h"
  31 #include "vnic_stats.h"
  32 #include "vnic_rss.h"
  33
  34 #define DRV_NAME                "enic"
  35 #define DRV_DESCRIPTION         "Cisco 10G Ethernet Driver"
  36 #define DRV_VERSION             "1.0.0.933"
  37 #define DRV_COPYRIGHT           "Copyright 2008 Cisco Systems, Inc"
  38 #define PFX                     DRV_NAME ": "
  39
  40 #define ENIC_LRO_MAX_DESC       8
  41 #define ENIC_LRO_MAX_AGGR       64
  42
  43 enum enic_cq_index {
  44         ENIC_CQ_RQ,
  45         ENIC_CQ_WQ,
  46         ENIC_CQ_MAX,
  47 };
  48
  49 enum enic_intx_intr_index {
  50         ENIC_INTX_WQ_RQ,
  51         ENIC_INTX_ERR,
  52         ENIC_INTX_NOTIFY,
  53         ENIC_INTX_MAX,
  54 };
  55
  56 enum enic_msix_intr_index {
  57         ENIC_MSIX_RQ,
  58         ENIC_MSIX_WQ,
  59         ENIC_MSIX_ERR,
  60         ENIC_MSIX_NOTIFY,
  61         ENIC_MSIX_MAX,
  62 };
  63
  64 struct enic_msix_entry {
  65         int requested;
  66         char devname[IFNAMSIZ];
  67         irqreturn_t (*isr)(int, void *);
  68         void *devid;
  69 };
  70
  71 /* Per-instance private data structure */
  72 struct enic {
  73         struct net_device *netdev;
  74         struct pci_dev *pdev;
  75         struct vnic_enet_config config;
  76         struct vnic_dev_bar bar0;
  77         struct vnic_dev *vdev;
  78         struct timer_list notify_timer;
  79         struct work_struct reset;
  80         struct msix_entry msix_entry[ENIC_MSIX_MAX];
  81         struct enic_msix_entry msix[ENIC_MSIX_MAX];
  82         u32 msg_enable;
  83         spinlock_t devcmd_lock;
  84         u8 mac_addr[ETH_ALEN];
  85         u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
  86         unsigned int mc_count;
  87         int csum_rx_enabled;
  88         u32 port_mtu;
  89
  90         /* work queue cache line section */
  91         ____cacheline_aligned struct vnic_wq wq[1];
  92         spinlock_t wq_lock[1];
  93         unsigned int wq_count;
  94         struct vlan_group *vlan_group;
  95
  96         /* receive queue cache line section */
  97         ____cacheline_aligned struct vnic_rq rq[1];
  98         unsigned int rq_count;
  99         int (*rq_alloc_buf)(struct vnic_rq *rq);
 100         u64 rq_bad_fcs;
 101         struct napi_struct napi;
 102         struct net_lro_mgr lro_mgr;
 103         struct net_lro_desc lro_desc[ENIC_LRO_MAX_DESC];
 104
 105         /* interrupt resource cache line section */
 106         ____cacheline_aligned struct vnic_intr intr[ENIC_MSIX_MAX];
 107         unsigned int intr_count;
 108         u32 __iomem *legacy_pba;                /* memory-mapped */
 109
 110         /* completion queue cache line section */
 111         ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
 112         unsigned int cq_count;
 113 };
 114
 115 #endif /* _ENIC_H_ */