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[deliverable/linux.git] / drivers / net / ethernet / adi / bfin_mac.c
1 /*
2 * Blackfin On-Chip MAC Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #define DRV_VERSION "1.1"
12 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
25 #include <linux/io.h>
26 #include <linux/ioport.h>
27 #include <linux/crc32.h>
28 #include <linux/device.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/platform_device.h>
36
37 #include <asm/dma.h>
38 #include <linux/dma-mapping.h>
39
40 #include <asm/div64.h>
41 #include <asm/dpmc.h>
42 #include <asm/blackfin.h>
43 #include <asm/cacheflush.h>
44 #include <asm/portmux.h>
45 #include <mach/pll.h>
46
47 #include "bfin_mac.h"
48
49 MODULE_AUTHOR("Bryan Wu, Luke Yang");
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
53
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56 # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
57 #else
58 # define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
62 #endif
63
64 #define PKT_BUF_SZ 1580
65
66 #define MAX_TIMEOUT_CNT 500
67
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
77
78 static void desc_list_free(void)
79 {
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83 #if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85 #endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
113 }
114 }
115
116 static int desc_list_init(struct net_device *dev)
117 {
118 int i;
119 struct sk_buff *new_skb;
120 #if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126 #endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
129 sizeof(struct net_dma_desc_tx),
130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
135 sizeof(struct net_dma_desc_rx),
136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
191 if (!new_skb)
192 goto init_error;
193
194 skb_reserve(new_skb, NET_IP_ALIGN);
195 /* Invidate the data cache of skb->data range when it is write back
196 * cache. It will prevent overwritting the new data from DMA
197 */
198 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199 (unsigned long)new_skb->end);
200 r->skb = new_skb;
201
202 /*
203 * enabled DMA
204 * write to memory WNR = 1
205 * wordsize is 32 bits
206 * disable interrupt
207 * 6 half words is desc size
208 * large desc flow
209 */
210 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211 /* since RXDWA is enabled */
212 a->start_addr = (unsigned long)new_skb->data - 2;
213 a->x_count = 0;
214 a->next_dma_desc = b;
215
216 /*
217 * enabled DMA
218 * write to memory WNR = 1
219 * wordsize is 32 bits
220 * enable interrupt
221 * 6 half words is desc size
222 * large desc flow
223 */
224 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225 NDSIZE_6 | DMAFLOW_LARGE;
226 b->start_addr = (unsigned long)(&(r->status));
227 b->x_count = 0;
228
229 rx_list_tail->desc_b.next_dma_desc = a;
230 rx_list_tail->next = r;
231 rx_list_tail = r;
232 }
233 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
234 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235 current_rx_ptr = rx_list_head;
236
237 return 0;
238
239 init_error:
240 desc_list_free();
241 pr_err("kmalloc failed\n");
242 return -ENOMEM;
243 }
244
245
246 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
247
248 /*
249 * MII operations
250 */
251 /* Wait until the previous MDC/MDIO transaction has completed */
252 static int bfin_mdio_poll(void)
253 {
254 int timeout_cnt = MAX_TIMEOUT_CNT;
255
256 /* poll the STABUSY bit */
257 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
258 udelay(1);
259 if (timeout_cnt-- < 0) {
260 pr_err("wait MDC/MDIO transaction to complete timeout\n");
261 return -ETIMEDOUT;
262 }
263 }
264
265 return 0;
266 }
267
268 /* Read an off-chip register in a PHY through the MDC/MDIO port */
269 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
270 {
271 int ret;
272
273 ret = bfin_mdio_poll();
274 if (ret)
275 return ret;
276
277 /* read mode */
278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
280 STABUSY);
281
282 ret = bfin_mdio_poll();
283 if (ret)
284 return ret;
285
286 return (int) bfin_read_EMAC_STADAT();
287 }
288
289 /* Write an off-chip register in a PHY through the MDC/MDIO port */
290 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
291 u16 value)
292 {
293 int ret;
294
295 ret = bfin_mdio_poll();
296 if (ret)
297 return ret;
298
299 bfin_write_EMAC_STADAT((u32) value);
300
301 /* write mode */
302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
304 STAOP |
305 STABUSY);
306
307 return bfin_mdio_poll();
308 }
309
310 static void bfin_mac_adjust_link(struct net_device *dev)
311 {
312 struct bfin_mac_local *lp = netdev_priv(dev);
313 struct phy_device *phydev = lp->phydev;
314 unsigned long flags;
315 int new_state = 0;
316
317 spin_lock_irqsave(&lp->lock, flags);
318 if (phydev->link) {
319 /* Now we make sure that we can be in full duplex mode.
320 * If not, we operate in half-duplex mode. */
321 if (phydev->duplex != lp->old_duplex) {
322 u32 opmode = bfin_read_EMAC_OPMODE();
323 new_state = 1;
324
325 if (phydev->duplex)
326 opmode |= FDMODE;
327 else
328 opmode &= ~(FDMODE);
329
330 bfin_write_EMAC_OPMODE(opmode);
331 lp->old_duplex = phydev->duplex;
332 }
333
334 if (phydev->speed != lp->old_speed) {
335 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
336 u32 opmode = bfin_read_EMAC_OPMODE();
337 switch (phydev->speed) {
338 case 10:
339 opmode |= RMII_10;
340 break;
341 case 100:
342 opmode &= ~RMII_10;
343 break;
344 default:
345 netdev_warn(dev,
346 "Ack! Speed (%d) is not 10/100!\n",
347 phydev->speed);
348 break;
349 }
350 bfin_write_EMAC_OPMODE(opmode);
351 }
352
353 new_state = 1;
354 lp->old_speed = phydev->speed;
355 }
356
357 if (!lp->old_link) {
358 new_state = 1;
359 lp->old_link = 1;
360 }
361 } else if (lp->old_link) {
362 new_state = 1;
363 lp->old_link = 0;
364 lp->old_speed = 0;
365 lp->old_duplex = -1;
366 }
367
368 if (new_state) {
369 u32 opmode = bfin_read_EMAC_OPMODE();
370 phy_print_status(phydev);
371 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
372 }
373
374 spin_unlock_irqrestore(&lp->lock, flags);
375 }
376
377 /* MDC = 2.5 MHz */
378 #define MDC_CLK 2500000
379
380 static int mii_probe(struct net_device *dev, int phy_mode)
381 {
382 struct bfin_mac_local *lp = netdev_priv(dev);
383 struct phy_device *phydev;
384 unsigned short sysctl;
385 u32 sclk, mdc_div;
386
387 /* Enable PHY output early */
388 if (!(bfin_read_VR_CTL() & CLKBUFOE))
389 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
390
391 sclk = get_sclk();
392 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
393
394 sysctl = bfin_read_EMAC_SYSCTL();
395 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
396 bfin_write_EMAC_SYSCTL(sysctl);
397
398 phydev = phy_find_first(lp->mii_bus);
399 if (!phydev) {
400 netdev_err(dev, "no phy device found\n");
401 return -ENODEV;
402 }
403
404 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
405 phy_mode != PHY_INTERFACE_MODE_MII) {
406 netdev_err(dev, "invalid phy interface mode\n");
407 return -EINVAL;
408 }
409
410 phydev = phy_connect(dev, phydev_name(phydev),
411 &bfin_mac_adjust_link, phy_mode);
412
413 if (IS_ERR(phydev)) {
414 netdev_err(dev, "could not attach PHY\n");
415 return PTR_ERR(phydev);
416 }
417
418 /* mask with MAC supported features */
419 phydev->supported &= (SUPPORTED_10baseT_Half
420 | SUPPORTED_10baseT_Full
421 | SUPPORTED_100baseT_Half
422 | SUPPORTED_100baseT_Full
423 | SUPPORTED_Autoneg
424 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
425 | SUPPORTED_MII
426 | SUPPORTED_TP);
427
428 phydev->advertising = phydev->supported;
429
430 lp->old_link = 0;
431 lp->old_speed = 0;
432 lp->old_duplex = -1;
433 lp->phydev = phydev;
434
435 phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
436 MDC_CLK, mdc_div, sclk / 1000000);
437
438 return 0;
439 }
440
441 /*
442 * Ethtool support
443 */
444
445 /*
446 * interrupt routine for magic packet wakeup
447 */
448 static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
449 {
450 return IRQ_HANDLED;
451 }
452
453 static int
454 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
455 {
456 struct bfin_mac_local *lp = netdev_priv(dev);
457
458 if (lp->phydev)
459 return phy_ethtool_gset(lp->phydev, cmd);
460
461 return -EINVAL;
462 }
463
464 static int
465 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
466 {
467 struct bfin_mac_local *lp = netdev_priv(dev);
468
469 if (!capable(CAP_NET_ADMIN))
470 return -EPERM;
471
472 if (lp->phydev)
473 return phy_ethtool_sset(lp->phydev, cmd);
474
475 return -EINVAL;
476 }
477
478 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
479 struct ethtool_drvinfo *info)
480 {
481 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
482 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
483 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
484 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
485 }
486
487 static void bfin_mac_ethtool_getwol(struct net_device *dev,
488 struct ethtool_wolinfo *wolinfo)
489 {
490 struct bfin_mac_local *lp = netdev_priv(dev);
491
492 wolinfo->supported = WAKE_MAGIC;
493 wolinfo->wolopts = lp->wol;
494 }
495
496 static int bfin_mac_ethtool_setwol(struct net_device *dev,
497 struct ethtool_wolinfo *wolinfo)
498 {
499 struct bfin_mac_local *lp = netdev_priv(dev);
500 int rc;
501
502 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
503 WAKE_UCAST |
504 WAKE_MCAST |
505 WAKE_BCAST |
506 WAKE_ARP))
507 return -EOPNOTSUPP;
508
509 lp->wol = wolinfo->wolopts;
510
511 if (lp->wol && !lp->irq_wake_requested) {
512 /* register wake irq handler */
513 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
514 0, "EMAC_WAKE", dev);
515 if (rc)
516 return rc;
517 lp->irq_wake_requested = true;
518 }
519
520 if (!lp->wol && lp->irq_wake_requested) {
521 free_irq(IRQ_MAC_WAKEDET, dev);
522 lp->irq_wake_requested = false;
523 }
524
525 /* Make sure the PHY driver doesn't suspend */
526 device_init_wakeup(&dev->dev, lp->wol);
527
528 return 0;
529 }
530
531 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
532 static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
533 struct ethtool_ts_info *info)
534 {
535 struct bfin_mac_local *lp = netdev_priv(dev);
536
537 info->so_timestamping =
538 SOF_TIMESTAMPING_TX_HARDWARE |
539 SOF_TIMESTAMPING_RX_HARDWARE |
540 SOF_TIMESTAMPING_RAW_HARDWARE;
541 info->phc_index = lp->phc_index;
542 info->tx_types =
543 (1 << HWTSTAMP_TX_OFF) |
544 (1 << HWTSTAMP_TX_ON);
545 info->rx_filters =
546 (1 << HWTSTAMP_FILTER_NONE) |
547 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
548 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
549 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
550 return 0;
551 }
552 #endif
553
554 static const struct ethtool_ops bfin_mac_ethtool_ops = {
555 .get_settings = bfin_mac_ethtool_getsettings,
556 .set_settings = bfin_mac_ethtool_setsettings,
557 .get_link = ethtool_op_get_link,
558 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
559 .get_wol = bfin_mac_ethtool_getwol,
560 .set_wol = bfin_mac_ethtool_setwol,
561 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
562 .get_ts_info = bfin_mac_ethtool_get_ts_info,
563 #endif
564 };
565
566 /**************************************************************************/
567 static void setup_system_regs(struct net_device *dev)
568 {
569 struct bfin_mac_local *lp = netdev_priv(dev);
570 int i;
571 unsigned short sysctl;
572
573 /*
574 * Odd word alignment for Receive Frame DMA word
575 * Configure checksum support and rcve frame word alignment
576 */
577 sysctl = bfin_read_EMAC_SYSCTL();
578 /*
579 * check if interrupt is requested for any PHY,
580 * enable PHY interrupt only if needed
581 */
582 for (i = 0; i < PHY_MAX_ADDR; ++i)
583 if (lp->mii_bus->irq[i] != PHY_POLL)
584 break;
585 if (i < PHY_MAX_ADDR)
586 sysctl |= PHYIE;
587 sysctl |= RXDWA;
588 #if defined(BFIN_MAC_CSUM_OFFLOAD)
589 sysctl |= RXCKS;
590 #else
591 sysctl &= ~RXCKS;
592 #endif
593 bfin_write_EMAC_SYSCTL(sysctl);
594
595 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
596
597 /* Set vlan regs to let 1522 bytes long packets pass through */
598 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
599 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
600
601 /* Initialize the TX DMA channel registers */
602 bfin_write_DMA2_X_COUNT(0);
603 bfin_write_DMA2_X_MODIFY(4);
604 bfin_write_DMA2_Y_COUNT(0);
605 bfin_write_DMA2_Y_MODIFY(0);
606
607 /* Initialize the RX DMA channel registers */
608 bfin_write_DMA1_X_COUNT(0);
609 bfin_write_DMA1_X_MODIFY(4);
610 bfin_write_DMA1_Y_COUNT(0);
611 bfin_write_DMA1_Y_MODIFY(0);
612 }
613
614 static void setup_mac_addr(u8 *mac_addr)
615 {
616 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
617 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
618
619 /* this depends on a little-endian machine */
620 bfin_write_EMAC_ADDRLO(addr_low);
621 bfin_write_EMAC_ADDRHI(addr_hi);
622 }
623
624 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
625 {
626 struct sockaddr *addr = p;
627 if (netif_running(dev))
628 return -EBUSY;
629 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
630 setup_mac_addr(dev->dev_addr);
631 return 0;
632 }
633
634 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
635 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
636
637 static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
638 {
639 u32 ipn = 1000000000UL / input_clk;
640 u32 ppn = 1;
641 unsigned int shift = 0;
642
643 while (ppn <= ipn) {
644 ppn <<= 1;
645 shift++;
646 }
647 *shift_result = shift;
648 return 1000000000UL / ppn;
649 }
650
651 static int bfin_mac_hwtstamp_set(struct net_device *netdev,
652 struct ifreq *ifr)
653 {
654 struct hwtstamp_config config;
655 struct bfin_mac_local *lp = netdev_priv(netdev);
656 u16 ptpctl;
657 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
658
659 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
660 return -EFAULT;
661
662 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
663 __func__, config.flags, config.tx_type, config.rx_filter);
664
665 /* reserved for future extensions */
666 if (config.flags)
667 return -EINVAL;
668
669 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
670 (config.tx_type != HWTSTAMP_TX_ON))
671 return -ERANGE;
672
673 ptpctl = bfin_read_EMAC_PTP_CTL();
674
675 switch (config.rx_filter) {
676 case HWTSTAMP_FILTER_NONE:
677 /*
678 * Dont allow any timestamping
679 */
680 ptpfv3 = 0xFFFFFFFF;
681 bfin_write_EMAC_PTP_FV3(ptpfv3);
682 break;
683 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
684 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
685 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
686 /*
687 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
688 * to enable all the field matches.
689 */
690 ptpctl &= ~0x1F00;
691 bfin_write_EMAC_PTP_CTL(ptpctl);
692 /*
693 * Keep the default values of the EMAC_PTP_FOFF register.
694 */
695 ptpfoff = 0x4A24170C;
696 bfin_write_EMAC_PTP_FOFF(ptpfoff);
697 /*
698 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
699 * registers.
700 */
701 ptpfv1 = 0x11040800;
702 bfin_write_EMAC_PTP_FV1(ptpfv1);
703 ptpfv2 = 0x0140013F;
704 bfin_write_EMAC_PTP_FV2(ptpfv2);
705 /*
706 * The default value (0xFFFC) allows the timestamping of both
707 * received Sync messages and Delay_Req messages.
708 */
709 ptpfv3 = 0xFFFFFFFC;
710 bfin_write_EMAC_PTP_FV3(ptpfv3);
711
712 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
713 break;
714 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
715 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
716 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
717 /* Clear all five comparison mask bits (bits[12:8]) in the
718 * EMAC_PTP_CTL register to enable all the field matches.
719 */
720 ptpctl &= ~0x1F00;
721 bfin_write_EMAC_PTP_CTL(ptpctl);
722 /*
723 * Keep the default values of the EMAC_PTP_FOFF register, except set
724 * the PTPCOF field to 0x2A.
725 */
726 ptpfoff = 0x2A24170C;
727 bfin_write_EMAC_PTP_FOFF(ptpfoff);
728 /*
729 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
730 * registers.
731 */
732 ptpfv1 = 0x11040800;
733 bfin_write_EMAC_PTP_FV1(ptpfv1);
734 ptpfv2 = 0x0140013F;
735 bfin_write_EMAC_PTP_FV2(ptpfv2);
736 /*
737 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
738 * the value to 0xFFF0.
739 */
740 ptpfv3 = 0xFFFFFFF0;
741 bfin_write_EMAC_PTP_FV3(ptpfv3);
742
743 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
744 break;
745 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
746 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
747 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
748 /*
749 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
750 * EFTM and PTPCM field comparison.
751 */
752 ptpctl &= ~0x1100;
753 bfin_write_EMAC_PTP_CTL(ptpctl);
754 /*
755 * Keep the default values of all the fields of the EMAC_PTP_FOFF
756 * register, except set the PTPCOF field to 0x0E.
757 */
758 ptpfoff = 0x0E24170C;
759 bfin_write_EMAC_PTP_FOFF(ptpfoff);
760 /*
761 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
762 * corresponds to PTP messages on the MAC layer.
763 */
764 ptpfv1 = 0x110488F7;
765 bfin_write_EMAC_PTP_FV1(ptpfv1);
766 ptpfv2 = 0x0140013F;
767 bfin_write_EMAC_PTP_FV2(ptpfv2);
768 /*
769 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
770 * messages, set the value to 0xFFF0.
771 */
772 ptpfv3 = 0xFFFFFFF0;
773 bfin_write_EMAC_PTP_FV3(ptpfv3);
774
775 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
776 break;
777 default:
778 return -ERANGE;
779 }
780
781 if (config.tx_type == HWTSTAMP_TX_OFF &&
782 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
783 ptpctl &= ~PTP_EN;
784 bfin_write_EMAC_PTP_CTL(ptpctl);
785
786 SSYNC();
787 } else {
788 ptpctl |= PTP_EN;
789 bfin_write_EMAC_PTP_CTL(ptpctl);
790
791 /*
792 * clear any existing timestamp
793 */
794 bfin_read_EMAC_PTP_RXSNAPLO();
795 bfin_read_EMAC_PTP_RXSNAPHI();
796
797 bfin_read_EMAC_PTP_TXSNAPLO();
798 bfin_read_EMAC_PTP_TXSNAPHI();
799
800 SSYNC();
801 }
802
803 lp->stamp_cfg = config;
804 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
805 -EFAULT : 0;
806 }
807
808 static int bfin_mac_hwtstamp_get(struct net_device *netdev,
809 struct ifreq *ifr)
810 {
811 struct bfin_mac_local *lp = netdev_priv(netdev);
812
813 return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
814 sizeof(lp->stamp_cfg)) ?
815 -EFAULT : 0;
816 }
817
818 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
819 {
820 struct bfin_mac_local *lp = netdev_priv(netdev);
821
822 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
823 int timeout_cnt = MAX_TIMEOUT_CNT;
824
825 /* When doing time stamping, keep the connection to the socket
826 * a while longer
827 */
828 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
829
830 /*
831 * The timestamping is done at the EMAC module's MII/RMII interface
832 * when the module sees the Start of Frame of an event message packet. This
833 * interface is the closest possible place to the physical Ethernet transmission
834 * medium, providing the best timing accuracy.
835 */
836 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
837 udelay(1);
838 if (timeout_cnt == 0)
839 netdev_err(netdev, "timestamp the TX packet failed\n");
840 else {
841 struct skb_shared_hwtstamps shhwtstamps;
842 u64 ns;
843 u64 regval;
844
845 regval = bfin_read_EMAC_PTP_TXSNAPLO();
846 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
847 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
848 ns = regval << lp->shift;
849 shhwtstamps.hwtstamp = ns_to_ktime(ns);
850 skb_tstamp_tx(skb, &shhwtstamps);
851 }
852 }
853 }
854
855 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
856 {
857 struct bfin_mac_local *lp = netdev_priv(netdev);
858 u32 valid;
859 u64 regval, ns;
860 struct skb_shared_hwtstamps *shhwtstamps;
861
862 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
863 return;
864
865 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
866 if (!valid)
867 return;
868
869 shhwtstamps = skb_hwtstamps(skb);
870
871 regval = bfin_read_EMAC_PTP_RXSNAPLO();
872 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
873 ns = regval << lp->shift;
874 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
875 shhwtstamps->hwtstamp = ns_to_ktime(ns);
876 }
877
878 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
879 {
880 struct bfin_mac_local *lp = netdev_priv(netdev);
881 u64 addend, ppb;
882 u32 input_clk, phc_clk;
883
884 /* Initialize hardware timer */
885 input_clk = get_sclk();
886 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
887 addend = phc_clk * (1ULL << 32);
888 do_div(addend, input_clk);
889 bfin_write_EMAC_PTP_ADDEND((u32)addend);
890
891 lp->addend = addend;
892 ppb = 1000000000ULL * input_clk;
893 do_div(ppb, phc_clk);
894 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
895
896 /* Initialize hwstamp config */
897 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
898 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
899 }
900
901 static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
902 {
903 u64 ns;
904 u32 lo, hi;
905
906 lo = bfin_read_EMAC_PTP_TIMELO();
907 hi = bfin_read_EMAC_PTP_TIMEHI();
908
909 ns = ((u64) hi) << 32;
910 ns |= lo;
911 ns <<= lp->shift;
912
913 return ns;
914 }
915
916 static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
917 {
918 u32 hi, lo;
919
920 ns >>= lp->shift;
921 hi = ns >> 32;
922 lo = ns & 0xffffffff;
923
924 bfin_write_EMAC_PTP_TIMELO(lo);
925 bfin_write_EMAC_PTP_TIMEHI(hi);
926 }
927
928 /* PTP Hardware Clock operations */
929
930 static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
931 {
932 u64 adj;
933 u32 diff, addend;
934 int neg_adj = 0;
935 struct bfin_mac_local *lp =
936 container_of(ptp, struct bfin_mac_local, caps);
937
938 if (ppb < 0) {
939 neg_adj = 1;
940 ppb = -ppb;
941 }
942 addend = lp->addend;
943 adj = addend;
944 adj *= ppb;
945 diff = div_u64(adj, 1000000000ULL);
946
947 addend = neg_adj ? addend - diff : addend + diff;
948
949 bfin_write_EMAC_PTP_ADDEND(addend);
950
951 return 0;
952 }
953
954 static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
955 {
956 s64 now;
957 unsigned long flags;
958 struct bfin_mac_local *lp =
959 container_of(ptp, struct bfin_mac_local, caps);
960
961 spin_lock_irqsave(&lp->phc_lock, flags);
962
963 now = bfin_ptp_time_read(lp);
964 now += delta;
965 bfin_ptp_time_write(lp, now);
966
967 spin_unlock_irqrestore(&lp->phc_lock, flags);
968
969 return 0;
970 }
971
972 static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
973 {
974 u64 ns;
975 unsigned long flags;
976 struct bfin_mac_local *lp =
977 container_of(ptp, struct bfin_mac_local, caps);
978
979 spin_lock_irqsave(&lp->phc_lock, flags);
980
981 ns = bfin_ptp_time_read(lp);
982
983 spin_unlock_irqrestore(&lp->phc_lock, flags);
984
985 *ts = ns_to_timespec64(ns);
986
987 return 0;
988 }
989
990 static int bfin_ptp_settime(struct ptp_clock_info *ptp,
991 const struct timespec64 *ts)
992 {
993 u64 ns;
994 unsigned long flags;
995 struct bfin_mac_local *lp =
996 container_of(ptp, struct bfin_mac_local, caps);
997
998 ns = timespec64_to_ns(ts);
999
1000 spin_lock_irqsave(&lp->phc_lock, flags);
1001
1002 bfin_ptp_time_write(lp, ns);
1003
1004 spin_unlock_irqrestore(&lp->phc_lock, flags);
1005
1006 return 0;
1007 }
1008
1009 static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1010 struct ptp_clock_request *rq, int on)
1011 {
1012 return -EOPNOTSUPP;
1013 }
1014
1015 static struct ptp_clock_info bfin_ptp_caps = {
1016 .owner = THIS_MODULE,
1017 .name = "BF518 clock",
1018 .max_adj = 0,
1019 .n_alarm = 0,
1020 .n_ext_ts = 0,
1021 .n_per_out = 0,
1022 .n_pins = 0,
1023 .pps = 0,
1024 .adjfreq = bfin_ptp_adjfreq,
1025 .adjtime = bfin_ptp_adjtime,
1026 .gettime64 = bfin_ptp_gettime,
1027 .settime64 = bfin_ptp_settime,
1028 .enable = bfin_ptp_enable,
1029 };
1030
1031 static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1032 {
1033 struct bfin_mac_local *lp = netdev_priv(netdev);
1034
1035 lp->caps = bfin_ptp_caps;
1036 lp->caps.max_adj = lp->max_ppb;
1037 lp->clock = ptp_clock_register(&lp->caps, dev);
1038 if (IS_ERR(lp->clock))
1039 return PTR_ERR(lp->clock);
1040
1041 lp->phc_index = ptp_clock_index(lp->clock);
1042 spin_lock_init(&lp->phc_lock);
1043
1044 return 0;
1045 }
1046
1047 static void bfin_phc_release(struct bfin_mac_local *lp)
1048 {
1049 ptp_clock_unregister(lp->clock);
1050 }
1051
1052 #else
1053 # define bfin_mac_hwtstamp_is_none(cfg) 0
1054 # define bfin_mac_hwtstamp_init(dev)
1055 # define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
1056 # define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
1057 # define bfin_rx_hwtstamp(dev, skb)
1058 # define bfin_tx_hwtstamp(dev, skb)
1059 # define bfin_phc_init(netdev, dev) 0
1060 # define bfin_phc_release(lp)
1061 #endif
1062
1063 static inline void _tx_reclaim_skb(void)
1064 {
1065 do {
1066 tx_list_head->desc_a.config &= ~DMAEN;
1067 tx_list_head->status.status_word = 0;
1068 if (tx_list_head->skb) {
1069 dev_consume_skb_any(tx_list_head->skb);
1070 tx_list_head->skb = NULL;
1071 }
1072 tx_list_head = tx_list_head->next;
1073
1074 } while (tx_list_head->status.status_word != 0);
1075 }
1076
1077 static void tx_reclaim_skb(struct bfin_mac_local *lp)
1078 {
1079 int timeout_cnt = MAX_TIMEOUT_CNT;
1080
1081 if (tx_list_head->status.status_word != 0)
1082 _tx_reclaim_skb();
1083
1084 if (current_tx_ptr->next == tx_list_head) {
1085 while (tx_list_head->status.status_word == 0) {
1086 /* slow down polling to avoid too many queue stop. */
1087 udelay(10);
1088 /* reclaim skb if DMA is not running. */
1089 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1090 break;
1091 if (timeout_cnt-- < 0)
1092 break;
1093 }
1094
1095 if (timeout_cnt >= 0)
1096 _tx_reclaim_skb();
1097 else
1098 netif_stop_queue(lp->ndev);
1099 }
1100
1101 if (current_tx_ptr->next != tx_list_head &&
1102 netif_queue_stopped(lp->ndev))
1103 netif_wake_queue(lp->ndev);
1104
1105 if (tx_list_head != current_tx_ptr) {
1106 /* shorten the timer interval if tx queue is stopped */
1107 if (netif_queue_stopped(lp->ndev))
1108 lp->tx_reclaim_timer.expires =
1109 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1110 else
1111 lp->tx_reclaim_timer.expires =
1112 jiffies + TX_RECLAIM_JIFFIES;
1113
1114 mod_timer(&lp->tx_reclaim_timer,
1115 lp->tx_reclaim_timer.expires);
1116 }
1117
1118 return;
1119 }
1120
1121 static void tx_reclaim_skb_timeout(unsigned long lp)
1122 {
1123 tx_reclaim_skb((struct bfin_mac_local *)lp);
1124 }
1125
1126 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
1127 struct net_device *dev)
1128 {
1129 struct bfin_mac_local *lp = netdev_priv(dev);
1130 u16 *data;
1131 u32 data_align = (unsigned long)(skb->data) & 0x3;
1132
1133 current_tx_ptr->skb = skb;
1134
1135 if (data_align == 0x2) {
1136 /* move skb->data to current_tx_ptr payload */
1137 data = (u16 *)(skb->data) - 1;
1138 *data = (u16)(skb->len);
1139 /*
1140 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1141 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1142 * of this field are the length of the packet payload in bytes and the higher
1143 * 4 bits are the timestamping enable field.
1144 */
1145 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1146 *data |= 0x1000;
1147
1148 current_tx_ptr->desc_a.start_addr = (u32)data;
1149 /* this is important! */
1150 blackfin_dcache_flush_range((u32)data,
1151 (u32)((u8 *)data + skb->len + 4));
1152 } else {
1153 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
1154 /* enable timestamping for the sent packet */
1155 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1156 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1157 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1158 skb->len);
1159 current_tx_ptr->desc_a.start_addr =
1160 (u32)current_tx_ptr->packet;
1161 blackfin_dcache_flush_range(
1162 (u32)current_tx_ptr->packet,
1163 (u32)(current_tx_ptr->packet + skb->len + 2));
1164 }
1165
1166 /* make sure the internal data buffers in the core are drained
1167 * so that the DMA descriptors are completely written when the
1168 * DMA engine goes to fetch them below
1169 */
1170 SSYNC();
1171
1172 /* always clear status buffer before start tx dma */
1173 current_tx_ptr->status.status_word = 0;
1174
1175 /* enable this packet's dma */
1176 current_tx_ptr->desc_a.config |= DMAEN;
1177
1178 /* tx dma is running, just return */
1179 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1180 goto out;
1181
1182 /* tx dma is not running */
1183 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1184 /* dma enabled, read from memory, size is 6 */
1185 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1186 /* Turn on the EMAC tx */
1187 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1188
1189 out:
1190 bfin_tx_hwtstamp(dev, skb);
1191
1192 current_tx_ptr = current_tx_ptr->next;
1193 dev->stats.tx_packets++;
1194 dev->stats.tx_bytes += (skb->len);
1195
1196 tx_reclaim_skb(lp);
1197
1198 return NETDEV_TX_OK;
1199 }
1200
1201 #define IP_HEADER_OFF 0
1202 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1203 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1204
1205 static void bfin_mac_rx(struct bfin_mac_local *lp)
1206 {
1207 struct net_device *dev = lp->ndev;
1208 struct sk_buff *skb, *new_skb;
1209 unsigned short len;
1210 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1211 unsigned int i;
1212 unsigned char fcs[ETH_FCS_LEN + 1];
1213 #endif
1214
1215 /* check if frame status word reports an error condition
1216 * we which case we simply drop the packet
1217 */
1218 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1219 netdev_notice(dev, "rx: receive error - packet dropped\n");
1220 dev->stats.rx_dropped++;
1221 goto out;
1222 }
1223
1224 /* allocate a new skb for next time receive */
1225 skb = current_rx_ptr->skb;
1226
1227 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1228 if (!new_skb) {
1229 dev->stats.rx_dropped++;
1230 goto out;
1231 }
1232 /* reserve 2 bytes for RXDWA padding */
1233 skb_reserve(new_skb, NET_IP_ALIGN);
1234 /* Invidate the data cache of skb->data range when it is write back
1235 * cache. It will prevent overwritting the new data from DMA
1236 */
1237 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1238 (unsigned long)new_skb->end);
1239
1240 current_rx_ptr->skb = new_skb;
1241 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1242
1243 len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN);
1244 /* Deduce Ethernet FCS length from Ethernet payload length */
1245 len -= ETH_FCS_LEN;
1246 skb_put(skb, len);
1247
1248 skb->protocol = eth_type_trans(skb, dev);
1249
1250 bfin_rx_hwtstamp(dev, skb);
1251
1252 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1253 /* Checksum offloading only works for IPv4 packets with the standard IP header
1254 * length of 20 bytes, because the blackfin MAC checksum calculation is
1255 * based on that assumption. We must NOT use the calculated checksum if our
1256 * IP version or header break that assumption.
1257 */
1258 if (skb->data[IP_HEADER_OFF] == 0x45) {
1259 skb->csum = current_rx_ptr->status.ip_payload_csum;
1260 /*
1261 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1262 * IP checksum is based on 16-bit one's complement algorithm.
1263 * To deduce a value from checksum is equal to add its inversion.
1264 * If the IP payload len is odd, the inversed FCS should also
1265 * begin from odd address and leave first byte zero.
1266 */
1267 if (skb->len % 2) {
1268 fcs[0] = 0;
1269 for (i = 0; i < ETH_FCS_LEN; i++)
1270 fcs[i + 1] = ~skb->data[skb->len + i];
1271 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1272 } else {
1273 for (i = 0; i < ETH_FCS_LEN; i++)
1274 fcs[i] = ~skb->data[skb->len + i];
1275 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1276 }
1277 skb->ip_summed = CHECKSUM_COMPLETE;
1278 }
1279 #endif
1280
1281 napi_gro_receive(&lp->napi, skb);
1282
1283 dev->stats.rx_packets++;
1284 dev->stats.rx_bytes += len;
1285 out:
1286 current_rx_ptr->status.status_word = 0x00000000;
1287 current_rx_ptr = current_rx_ptr->next;
1288 }
1289
1290 static int bfin_mac_poll(struct napi_struct *napi, int budget)
1291 {
1292 int i = 0;
1293 struct bfin_mac_local *lp = container_of(napi,
1294 struct bfin_mac_local,
1295 napi);
1296
1297 while (current_rx_ptr->status.status_word != 0 && i < budget) {
1298 bfin_mac_rx(lp);
1299 i++;
1300 }
1301
1302 if (i < budget) {
1303 napi_complete(napi);
1304 if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags))
1305 enable_irq(IRQ_MAC_RX);
1306 }
1307
1308 return i;
1309 }
1310
1311 /* interrupt routine to handle rx and error signal */
1312 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1313 {
1314 struct bfin_mac_local *lp = netdev_priv(dev_id);
1315 u32 status;
1316
1317 status = bfin_read_DMA1_IRQ_STATUS();
1318
1319 bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR);
1320 if (status & DMA_DONE) {
1321 disable_irq_nosync(IRQ_MAC_RX);
1322 set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags);
1323 napi_schedule(&lp->napi);
1324 }
1325
1326 return IRQ_HANDLED;
1327 }
1328
1329 #ifdef CONFIG_NET_POLL_CONTROLLER
1330 static void bfin_mac_poll_controller(struct net_device *dev)
1331 {
1332 struct bfin_mac_local *lp = netdev_priv(dev);
1333
1334 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1335 tx_reclaim_skb(lp);
1336 }
1337 #endif /* CONFIG_NET_POLL_CONTROLLER */
1338
1339 static void bfin_mac_disable(void)
1340 {
1341 unsigned int opmode;
1342
1343 opmode = bfin_read_EMAC_OPMODE();
1344 opmode &= (~RE);
1345 opmode &= (~TE);
1346 /* Turn off the EMAC */
1347 bfin_write_EMAC_OPMODE(opmode);
1348 }
1349
1350 /*
1351 * Enable Interrupts, Receive, and Transmit
1352 */
1353 static int bfin_mac_enable(struct phy_device *phydev)
1354 {
1355 int ret;
1356 u32 opmode;
1357
1358 pr_debug("%s\n", __func__);
1359
1360 /* Set RX DMA */
1361 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1362 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1363
1364 /* Wait MII done */
1365 ret = bfin_mdio_poll();
1366 if (ret)
1367 return ret;
1368
1369 /* We enable only RX here */
1370 /* ASTP : Enable Automatic Pad Stripping
1371 PR : Promiscuous Mode for test
1372 PSF : Receive frames with total length less than 64 bytes.
1373 FDMODE : Full Duplex Mode
1374 LB : Internal Loopback for test
1375 RE : Receiver Enable */
1376 opmode = bfin_read_EMAC_OPMODE();
1377 if (opmode & FDMODE)
1378 opmode |= PSF;
1379 else
1380 opmode |= DRO | DC | PSF;
1381 opmode |= RE;
1382
1383 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1384 opmode |= RMII; /* For Now only 100MBit are supported */
1385 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1386 if (__SILICON_REVISION__ < 3) {
1387 /*
1388 * This isn't publicly documented (fun times!), but in
1389 * silicon <=0.2, the RX and TX pins are clocked together.
1390 * So in order to recv, we must enable the transmit side
1391 * as well. This will cause a spurious TX interrupt too,
1392 * but we can easily consume that.
1393 */
1394 opmode |= TE;
1395 }
1396 #endif
1397 }
1398
1399 /* Turn on the EMAC rx */
1400 bfin_write_EMAC_OPMODE(opmode);
1401
1402 return 0;
1403 }
1404
1405 /* Our watchdog timed out. Called by the networking layer */
1406 static void bfin_mac_timeout(struct net_device *dev)
1407 {
1408 struct bfin_mac_local *lp = netdev_priv(dev);
1409
1410 pr_debug("%s: %s\n", dev->name, __func__);
1411
1412 bfin_mac_disable();
1413
1414 del_timer(&lp->tx_reclaim_timer);
1415
1416 /* reset tx queue and free skb */
1417 while (tx_list_head != current_tx_ptr) {
1418 tx_list_head->desc_a.config &= ~DMAEN;
1419 tx_list_head->status.status_word = 0;
1420 if (tx_list_head->skb) {
1421 dev_kfree_skb(tx_list_head->skb);
1422 tx_list_head->skb = NULL;
1423 }
1424 tx_list_head = tx_list_head->next;
1425 }
1426
1427 if (netif_queue_stopped(dev))
1428 netif_wake_queue(dev);
1429
1430 bfin_mac_enable(lp->phydev);
1431
1432 /* We can accept TX packets again */
1433 dev->trans_start = jiffies; /* prevent tx timeout */
1434 }
1435
1436 static void bfin_mac_multicast_hash(struct net_device *dev)
1437 {
1438 u32 emac_hashhi, emac_hashlo;
1439 struct netdev_hw_addr *ha;
1440 u32 crc;
1441
1442 emac_hashhi = emac_hashlo = 0;
1443
1444 netdev_for_each_mc_addr(ha, dev) {
1445 crc = ether_crc(ETH_ALEN, ha->addr);
1446 crc >>= 26;
1447
1448 if (crc & 0x20)
1449 emac_hashhi |= 1 << (crc & 0x1f);
1450 else
1451 emac_hashlo |= 1 << (crc & 0x1f);
1452 }
1453
1454 bfin_write_EMAC_HASHHI(emac_hashhi);
1455 bfin_write_EMAC_HASHLO(emac_hashlo);
1456 }
1457
1458 /*
1459 * This routine will, depending on the values passed to it,
1460 * either make it accept multicast packets, go into
1461 * promiscuous mode (for TCPDUMP and cousins) or accept
1462 * a select set of multicast packets
1463 */
1464 static void bfin_mac_set_multicast_list(struct net_device *dev)
1465 {
1466 u32 sysctl;
1467
1468 if (dev->flags & IFF_PROMISC) {
1469 netdev_info(dev, "set promisc mode\n");
1470 sysctl = bfin_read_EMAC_OPMODE();
1471 sysctl |= PR;
1472 bfin_write_EMAC_OPMODE(sysctl);
1473 } else if (dev->flags & IFF_ALLMULTI) {
1474 /* accept all multicast */
1475 sysctl = bfin_read_EMAC_OPMODE();
1476 sysctl |= PAM;
1477 bfin_write_EMAC_OPMODE(sysctl);
1478 } else if (!netdev_mc_empty(dev)) {
1479 /* set up multicast hash table */
1480 sysctl = bfin_read_EMAC_OPMODE();
1481 sysctl |= HM;
1482 bfin_write_EMAC_OPMODE(sysctl);
1483 bfin_mac_multicast_hash(dev);
1484 } else {
1485 /* clear promisc or multicast mode */
1486 sysctl = bfin_read_EMAC_OPMODE();
1487 sysctl &= ~(RAF | PAM);
1488 bfin_write_EMAC_OPMODE(sysctl);
1489 }
1490 }
1491
1492 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1493 {
1494 struct bfin_mac_local *lp = netdev_priv(netdev);
1495
1496 if (!netif_running(netdev))
1497 return -EINVAL;
1498
1499 switch (cmd) {
1500 case SIOCSHWTSTAMP:
1501 return bfin_mac_hwtstamp_set(netdev, ifr);
1502 case SIOCGHWTSTAMP:
1503 return bfin_mac_hwtstamp_get(netdev, ifr);
1504 default:
1505 if (lp->phydev)
1506 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1507 else
1508 return -EOPNOTSUPP;
1509 }
1510 }
1511
1512 /*
1513 * this puts the device in an inactive state
1514 */
1515 static void bfin_mac_shutdown(struct net_device *dev)
1516 {
1517 /* Turn off the EMAC */
1518 bfin_write_EMAC_OPMODE(0x00000000);
1519 /* Turn off the EMAC RX DMA */
1520 bfin_write_DMA1_CONFIG(0x0000);
1521 bfin_write_DMA2_CONFIG(0x0000);
1522 }
1523
1524 /*
1525 * Open and Initialize the interface
1526 *
1527 * Set up everything, reset the card, etc..
1528 */
1529 static int bfin_mac_open(struct net_device *dev)
1530 {
1531 struct bfin_mac_local *lp = netdev_priv(dev);
1532 int ret;
1533 pr_debug("%s: %s\n", dev->name, __func__);
1534
1535 /*
1536 * Check that the address is valid. If its not, refuse
1537 * to bring the device up. The user must specify an
1538 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1539 */
1540 if (!is_valid_ether_addr(dev->dev_addr)) {
1541 netdev_warn(dev, "no valid ethernet hw addr\n");
1542 return -EINVAL;
1543 }
1544
1545 /* initial rx and tx list */
1546 ret = desc_list_init(dev);
1547 if (ret)
1548 return ret;
1549
1550 phy_start(lp->phydev);
1551 setup_system_regs(dev);
1552 setup_mac_addr(dev->dev_addr);
1553
1554 bfin_mac_disable();
1555 ret = bfin_mac_enable(lp->phydev);
1556 if (ret)
1557 return ret;
1558 pr_debug("hardware init finished\n");
1559
1560 napi_enable(&lp->napi);
1561 netif_start_queue(dev);
1562 netif_carrier_on(dev);
1563
1564 return 0;
1565 }
1566
1567 /*
1568 * this makes the board clean up everything that it can
1569 * and not talk to the outside world. Caused by
1570 * an 'ifconfig ethX down'
1571 */
1572 static int bfin_mac_close(struct net_device *dev)
1573 {
1574 struct bfin_mac_local *lp = netdev_priv(dev);
1575 pr_debug("%s: %s\n", dev->name, __func__);
1576
1577 netif_stop_queue(dev);
1578 napi_disable(&lp->napi);
1579 netif_carrier_off(dev);
1580
1581 phy_stop(lp->phydev);
1582 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1583
1584 /* clear everything */
1585 bfin_mac_shutdown(dev);
1586
1587 /* free the rx/tx buffers */
1588 desc_list_free();
1589
1590 return 0;
1591 }
1592
1593 static const struct net_device_ops bfin_mac_netdev_ops = {
1594 .ndo_open = bfin_mac_open,
1595 .ndo_stop = bfin_mac_close,
1596 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1597 .ndo_set_mac_address = bfin_mac_set_mac_address,
1598 .ndo_tx_timeout = bfin_mac_timeout,
1599 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
1600 .ndo_do_ioctl = bfin_mac_ioctl,
1601 .ndo_validate_addr = eth_validate_addr,
1602 .ndo_change_mtu = eth_change_mtu,
1603 #ifdef CONFIG_NET_POLL_CONTROLLER
1604 .ndo_poll_controller = bfin_mac_poll_controller,
1605 #endif
1606 };
1607
1608 static int bfin_mac_probe(struct platform_device *pdev)
1609 {
1610 struct net_device *ndev;
1611 struct bfin_mac_local *lp;
1612 struct platform_device *pd;
1613 struct bfin_mii_bus_platform_data *mii_bus_data;
1614 int rc;
1615
1616 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1617 if (!ndev)
1618 return -ENOMEM;
1619
1620 SET_NETDEV_DEV(ndev, &pdev->dev);
1621 platform_set_drvdata(pdev, ndev);
1622 lp = netdev_priv(ndev);
1623 lp->ndev = ndev;
1624
1625 /* Grab the MAC address in the MAC */
1626 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1627 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1628
1629 /* probe mac */
1630 /*todo: how to proble? which is revision_register */
1631 bfin_write_EMAC_ADDRLO(0x12345678);
1632 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1633 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1634 rc = -ENODEV;
1635 goto out_err_probe_mac;
1636 }
1637
1638
1639 /*
1640 * Is it valid? (Did bootloader initialize it?)
1641 * Grab the MAC from the board somehow
1642 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1643 */
1644 if (!is_valid_ether_addr(ndev->dev_addr)) {
1645 if (bfin_get_ether_addr(ndev->dev_addr) ||
1646 !is_valid_ether_addr(ndev->dev_addr)) {
1647 /* Still not valid, get a random one */
1648 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1649 eth_hw_addr_random(ndev);
1650 }
1651 }
1652
1653 setup_mac_addr(ndev->dev_addr);
1654
1655 if (!dev_get_platdata(&pdev->dev)) {
1656 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1657 rc = -ENODEV;
1658 goto out_err_probe_mac;
1659 }
1660 pd = dev_get_platdata(&pdev->dev);
1661 lp->mii_bus = platform_get_drvdata(pd);
1662 if (!lp->mii_bus) {
1663 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1664 rc = -ENODEV;
1665 goto out_err_probe_mac;
1666 }
1667 lp->mii_bus->priv = ndev;
1668 mii_bus_data = dev_get_platdata(&pd->dev);
1669
1670 rc = mii_probe(ndev, mii_bus_data->phy_mode);
1671 if (rc) {
1672 dev_err(&pdev->dev, "MII Probe failed!\n");
1673 goto out_err_mii_probe;
1674 }
1675
1676 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1677 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1678
1679 ndev->netdev_ops = &bfin_mac_netdev_ops;
1680 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1681
1682 init_timer(&lp->tx_reclaim_timer);
1683 lp->tx_reclaim_timer.data = (unsigned long)lp;
1684 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1685
1686 lp->flags = 0;
1687 netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM);
1688
1689 spin_lock_init(&lp->lock);
1690
1691 /* now, enable interrupts */
1692 /* register irq handler */
1693 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1694 0, "EMAC_RX", ndev);
1695 if (rc) {
1696 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1697 rc = -EBUSY;
1698 goto out_err_request_irq;
1699 }
1700
1701 rc = register_netdev(ndev);
1702 if (rc) {
1703 dev_err(&pdev->dev, "Cannot register net device!\n");
1704 goto out_err_reg_ndev;
1705 }
1706
1707 bfin_mac_hwtstamp_init(ndev);
1708 rc = bfin_phc_init(ndev, &pdev->dev);
1709 if (rc) {
1710 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1711 goto out_err_phc;
1712 }
1713
1714 /* now, print out the card info, in a short format.. */
1715 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1716
1717 return 0;
1718
1719 out_err_phc:
1720 out_err_reg_ndev:
1721 free_irq(IRQ_MAC_RX, ndev);
1722 out_err_request_irq:
1723 netif_napi_del(&lp->napi);
1724 out_err_mii_probe:
1725 mdiobus_unregister(lp->mii_bus);
1726 mdiobus_free(lp->mii_bus);
1727 out_err_probe_mac:
1728 free_netdev(ndev);
1729
1730 return rc;
1731 }
1732
1733 static int bfin_mac_remove(struct platform_device *pdev)
1734 {
1735 struct net_device *ndev = platform_get_drvdata(pdev);
1736 struct bfin_mac_local *lp = netdev_priv(ndev);
1737
1738 bfin_phc_release(lp);
1739
1740 lp->mii_bus->priv = NULL;
1741
1742 unregister_netdev(ndev);
1743
1744 netif_napi_del(&lp->napi);
1745
1746 free_irq(IRQ_MAC_RX, ndev);
1747
1748 free_netdev(ndev);
1749
1750 return 0;
1751 }
1752
1753 #ifdef CONFIG_PM
1754 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1755 {
1756 struct net_device *net_dev = platform_get_drvdata(pdev);
1757 struct bfin_mac_local *lp = netdev_priv(net_dev);
1758
1759 if (lp->wol) {
1760 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1761 bfin_write_EMAC_WKUP_CTL(MPKE);
1762 enable_irq_wake(IRQ_MAC_WAKEDET);
1763 } else {
1764 if (netif_running(net_dev))
1765 bfin_mac_close(net_dev);
1766 }
1767
1768 return 0;
1769 }
1770
1771 static int bfin_mac_resume(struct platform_device *pdev)
1772 {
1773 struct net_device *net_dev = platform_get_drvdata(pdev);
1774 struct bfin_mac_local *lp = netdev_priv(net_dev);
1775
1776 if (lp->wol) {
1777 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1778 bfin_write_EMAC_WKUP_CTL(0);
1779 disable_irq_wake(IRQ_MAC_WAKEDET);
1780 } else {
1781 if (netif_running(net_dev))
1782 bfin_mac_open(net_dev);
1783 }
1784
1785 return 0;
1786 }
1787 #else
1788 #define bfin_mac_suspend NULL
1789 #define bfin_mac_resume NULL
1790 #endif /* CONFIG_PM */
1791
1792 static int bfin_mii_bus_probe(struct platform_device *pdev)
1793 {
1794 struct mii_bus *miibus;
1795 struct bfin_mii_bus_platform_data *mii_bus_pd;
1796 const unsigned short *pin_req;
1797 int rc, i;
1798
1799 mii_bus_pd = dev_get_platdata(&pdev->dev);
1800 if (!mii_bus_pd) {
1801 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1802 return -EINVAL;
1803 }
1804
1805 /*
1806 * We are setting up a network card,
1807 * so set the GPIO pins to Ethernet mode
1808 */
1809 pin_req = mii_bus_pd->mac_peripherals;
1810 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
1811 if (rc) {
1812 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1813 return rc;
1814 }
1815
1816 rc = -ENOMEM;
1817 miibus = mdiobus_alloc();
1818 if (miibus == NULL)
1819 goto out_err_alloc;
1820 miibus->read = bfin_mdiobus_read;
1821 miibus->write = bfin_mdiobus_write;
1822
1823 miibus->parent = &pdev->dev;
1824 miibus->name = "bfin_mii_bus";
1825 miibus->phy_mask = mii_bus_pd->phy_mask;
1826
1827 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1828 pdev->name, pdev->id);
1829
1830 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1831 if (rc != mii_bus_pd->phydev_number)
1832 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1833 mii_bus_pd->phydev_number);
1834 for (i = 0; i < rc; ++i) {
1835 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1836 if (phyaddr < PHY_MAX_ADDR)
1837 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1838 else
1839 dev_err(&pdev->dev,
1840 "Invalid PHY address %i for phydev %i\n",
1841 phyaddr, i);
1842 }
1843
1844 rc = mdiobus_register(miibus);
1845 if (rc) {
1846 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1847 goto out_err_irq_alloc;
1848 }
1849
1850 platform_set_drvdata(pdev, miibus);
1851 return 0;
1852
1853 out_err_irq_alloc:
1854 mdiobus_free(miibus);
1855 out_err_alloc:
1856 peripheral_free_list(pin_req);
1857
1858 return rc;
1859 }
1860
1861 static int bfin_mii_bus_remove(struct platform_device *pdev)
1862 {
1863 struct mii_bus *miibus = platform_get_drvdata(pdev);
1864 struct bfin_mii_bus_platform_data *mii_bus_pd =
1865 dev_get_platdata(&pdev->dev);
1866
1867 mdiobus_unregister(miibus);
1868 mdiobus_free(miibus);
1869 peripheral_free_list(mii_bus_pd->mac_peripherals);
1870
1871 return 0;
1872 }
1873
1874 static struct platform_driver bfin_mii_bus_driver = {
1875 .probe = bfin_mii_bus_probe,
1876 .remove = bfin_mii_bus_remove,
1877 .driver = {
1878 .name = "bfin_mii_bus",
1879 },
1880 };
1881
1882 static struct platform_driver bfin_mac_driver = {
1883 .probe = bfin_mac_probe,
1884 .remove = bfin_mac_remove,
1885 .resume = bfin_mac_resume,
1886 .suspend = bfin_mac_suspend,
1887 .driver = {
1888 .name = KBUILD_MODNAME,
1889 },
1890 };
1891
1892 static struct platform_driver * const drivers[] = {
1893 &bfin_mii_bus_driver,
1894 &bfin_mac_driver,
1895 };
1896
1897 static int __init bfin_mac_init(void)
1898 {
1899 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1900 }
1901
1902 module_init(bfin_mac_init);
1903
1904 static void __exit bfin_mac_cleanup(void)
1905 {
1906 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1907 }
1908
1909 module_exit(bfin_mac_cleanup);
1910
Linux kernel - Deliverables
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