1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/of_device.h>
42 #include <linux/of_mdio.h>
43 #include <linux/of_net.h>
44 #include <linux/of_platform.h>
45 #include <linux/phy.h>
46 #include <linux/platform_device.h>
47 #include <linux/skbuff.h>
48 #include <asm/cacheflush.h>
50 #include "altera_utils.h"
51 #include "altera_tse.h"
52 #include "altera_sgdma.h"
53 #include "altera_msgdma.h"
55 static atomic_t instance_count
= ATOMIC_INIT(~0);
56 /* Module parameters */
57 static int debug
= -1;
58 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
59 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
61 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
62 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
65 #define RX_DESCRIPTORS 64
66 static int dma_rx_num
= RX_DESCRIPTORS
;
67 module_param(dma_rx_num
, int, S_IRUGO
| S_IWUSR
);
68 MODULE_PARM_DESC(dma_rx_num
, "Number of descriptors in the RX list");
70 #define TX_DESCRIPTORS 64
71 static int dma_tx_num
= TX_DESCRIPTORS
;
72 module_param(dma_tx_num
, int, S_IRUGO
| S_IWUSR
);
73 MODULE_PARM_DESC(dma_tx_num
, "Number of descriptors in the TX list");
78 /* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
83 #define ALTERA_RXDMABUFFER_SIZE 2048
85 /* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
90 #define TXQUEUESTOP_THRESHHOLD 2
92 static const struct of_device_id altera_tse_ids
[];
94 static inline u32
tse_tx_avail(struct altera_tse_private
*priv
)
96 return priv
->tx_cons
+ priv
->tx_ring_size
- priv
->tx_prod
- 1;
99 /* MDIO specific functions
101 static int altera_tse_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
103 struct net_device
*ndev
= bus
->priv
;
104 struct altera_tse_private
*priv
= netdev_priv(ndev
);
106 /* set MDIO address */
107 csrwr32((mii_id
& 0x1f), priv
->mac_dev
,
108 tse_csroffs(mdio_phy1_addr
));
111 return csrrd32(priv
->mac_dev
,
112 tse_csroffs(mdio_phy1
) + regnum
* 4) & 0xffff;
115 static int altera_tse_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
118 struct net_device
*ndev
= bus
->priv
;
119 struct altera_tse_private
*priv
= netdev_priv(ndev
);
121 /* set MDIO address */
122 csrwr32((mii_id
& 0x1f), priv
->mac_dev
,
123 tse_csroffs(mdio_phy1_addr
));
126 csrwr32(value
, priv
->mac_dev
, tse_csroffs(mdio_phy1
) + regnum
* 4);
130 static int altera_tse_mdio_create(struct net_device
*dev
, unsigned int id
)
132 struct altera_tse_private
*priv
= netdev_priv(dev
);
135 struct device_node
*mdio_node
= NULL
;
136 struct mii_bus
*mdio
= NULL
;
137 struct device_node
*child_node
= NULL
;
139 for_each_child_of_node(priv
->device
->of_node
, child_node
) {
140 if (of_device_is_compatible(child_node
, "altr,tse-mdio")) {
141 mdio_node
= child_node
;
147 netdev_dbg(dev
, "FOUND MDIO subnode\n");
149 netdev_dbg(dev
, "NO MDIO subnode\n");
153 mdio
= mdiobus_alloc();
155 netdev_err(dev
, "Error allocating MDIO bus\n");
159 mdio
->name
= ALTERA_TSE_RESOURCE_NAME
;
160 mdio
->read
= &altera_tse_mdio_read
;
161 mdio
->write
= &altera_tse_mdio_write
;
162 snprintf(mdio
->id
, MII_BUS_ID_SIZE
, "%s-%u", mdio
->name
, id
);
164 mdio
->irq
= kcalloc(PHY_MAX_ADDR
, sizeof(int), GFP_KERNEL
);
165 if (mdio
->irq
== NULL
) {
169 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
170 mdio
->irq
[i
] = PHY_POLL
;
173 mdio
->parent
= priv
->device
;
175 ret
= of_mdiobus_register(mdio
, mdio_node
);
177 netdev_err(dev
, "Cannot register MDIO bus %s\n",
179 goto out_free_mdio_irq
;
182 if (netif_msg_drv(priv
))
183 netdev_info(dev
, "MDIO bus %s: created\n", mdio
->id
);
195 static void altera_tse_mdio_destroy(struct net_device
*dev
)
197 struct altera_tse_private
*priv
= netdev_priv(dev
);
199 if (priv
->mdio
== NULL
)
202 if (netif_msg_drv(priv
))
203 netdev_info(dev
, "MDIO bus %s: removed\n",
206 mdiobus_unregister(priv
->mdio
);
207 kfree(priv
->mdio
->irq
);
208 mdiobus_free(priv
->mdio
);
212 static int tse_init_rx_buffer(struct altera_tse_private
*priv
,
213 struct tse_buffer
*rxbuffer
, int len
)
215 rxbuffer
->skb
= netdev_alloc_skb_ip_align(priv
->dev
, len
);
219 rxbuffer
->dma_addr
= dma_map_single(priv
->device
, rxbuffer
->skb
->data
,
223 if (dma_mapping_error(priv
->device
, rxbuffer
->dma_addr
)) {
224 netdev_err(priv
->dev
, "%s: DMA mapping error\n", __func__
);
225 dev_kfree_skb_any(rxbuffer
->skb
);
228 rxbuffer
->dma_addr
&= (dma_addr_t
)~3;
233 static void tse_free_rx_buffer(struct altera_tse_private
*priv
,
234 struct tse_buffer
*rxbuffer
)
236 struct sk_buff
*skb
= rxbuffer
->skb
;
237 dma_addr_t dma_addr
= rxbuffer
->dma_addr
;
241 dma_unmap_single(priv
->device
, dma_addr
,
244 dev_kfree_skb_any(skb
);
245 rxbuffer
->skb
= NULL
;
246 rxbuffer
->dma_addr
= 0;
250 /* Unmap and free Tx buffer resources
252 static void tse_free_tx_buffer(struct altera_tse_private
*priv
,
253 struct tse_buffer
*buffer
)
255 if (buffer
->dma_addr
) {
256 if (buffer
->mapped_as_page
)
257 dma_unmap_page(priv
->device
, buffer
->dma_addr
,
258 buffer
->len
, DMA_TO_DEVICE
);
260 dma_unmap_single(priv
->device
, buffer
->dma_addr
,
261 buffer
->len
, DMA_TO_DEVICE
);
262 buffer
->dma_addr
= 0;
265 dev_kfree_skb_any(buffer
->skb
);
270 static int alloc_init_skbufs(struct altera_tse_private
*priv
)
272 unsigned int rx_descs
= priv
->rx_ring_size
;
273 unsigned int tx_descs
= priv
->tx_ring_size
;
277 /* Create Rx ring buffer */
278 priv
->rx_ring
= kcalloc(rx_descs
, sizeof(struct tse_buffer
),
283 /* Create Tx ring buffer */
284 priv
->tx_ring
= kcalloc(tx_descs
, sizeof(struct tse_buffer
),
293 for (i
= 0; i
< rx_descs
; i
++) {
294 ret
= tse_init_rx_buffer(priv
, &priv
->rx_ring
[i
],
295 priv
->rx_dma_buf_sz
);
297 goto err_init_rx_buffers
;
306 tse_free_rx_buffer(priv
, &priv
->rx_ring
[i
]);
307 kfree(priv
->tx_ring
);
309 kfree(priv
->rx_ring
);
314 static void free_skbufs(struct net_device
*dev
)
316 struct altera_tse_private
*priv
= netdev_priv(dev
);
317 unsigned int rx_descs
= priv
->rx_ring_size
;
318 unsigned int tx_descs
= priv
->tx_ring_size
;
321 /* Release the DMA TX/RX socket buffers */
322 for (i
= 0; i
< rx_descs
; i
++)
323 tse_free_rx_buffer(priv
, &priv
->rx_ring
[i
]);
324 for (i
= 0; i
< tx_descs
; i
++)
325 tse_free_tx_buffer(priv
, &priv
->tx_ring
[i
]);
328 kfree(priv
->tx_ring
);
331 /* Reallocate the skb for the reception process
333 static inline void tse_rx_refill(struct altera_tse_private
*priv
)
335 unsigned int rxsize
= priv
->rx_ring_size
;
339 for (; priv
->rx_cons
- priv
->rx_prod
> 0;
341 entry
= priv
->rx_prod
% rxsize
;
342 if (likely(priv
->rx_ring
[entry
].skb
== NULL
)) {
343 ret
= tse_init_rx_buffer(priv
, &priv
->rx_ring
[entry
],
344 priv
->rx_dma_buf_sz
);
345 if (unlikely(ret
!= 0))
347 priv
->dmaops
->add_rx_desc(priv
, &priv
->rx_ring
[entry
]);
352 /* Pull out the VLAN tag and fix up the packet
354 static inline void tse_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
356 struct ethhdr
*eth_hdr
;
358 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
359 !__vlan_get_tag(skb
, &vid
)) {
360 eth_hdr
= (struct ethhdr
*)skb
->data
;
361 memmove(skb
->data
+ VLAN_HLEN
, eth_hdr
, ETH_ALEN
* 2);
362 skb_pull(skb
, VLAN_HLEN
);
363 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vid
);
367 /* Receive a packet: retrieve and pass over to upper levels
369 static int tse_rx(struct altera_tse_private
*priv
, int limit
)
371 unsigned int count
= 0;
372 unsigned int next_entry
;
374 unsigned int entry
= priv
->rx_cons
% priv
->rx_ring_size
;
379 /* Check for count < limit first as get_rx_status is changing
380 * the response-fifo so we must process the next packet
381 * after calling get_rx_status if a response is pending.
382 * (reading the last byte of the response pops the value from the fifo.)
384 while ((count
< limit
) &&
385 ((rxstatus
= priv
->dmaops
->get_rx_status(priv
)) != 0)) {
386 pktstatus
= rxstatus
>> 16;
387 pktlength
= rxstatus
& 0xffff;
389 if ((pktstatus
& 0xFF) || (pktlength
== 0))
390 netdev_err(priv
->dev
,
391 "RCV pktstatus %08X pktlength %08X\n",
392 pktstatus
, pktlength
);
394 /* DMA trasfer from TSE starts with 2 aditional bytes for
395 * IP payload alignment. Status returned by get_rx_status()
396 * contains DMA transfer length. Packet is 2 bytes shorter.
401 next_entry
= (++priv
->rx_cons
) % priv
->rx_ring_size
;
403 skb
= priv
->rx_ring
[entry
].skb
;
404 if (unlikely(!skb
)) {
405 netdev_err(priv
->dev
,
406 "%s: Inconsistent Rx descriptor chain\n",
408 priv
->dev
->stats
.rx_dropped
++;
411 priv
->rx_ring
[entry
].skb
= NULL
;
413 skb_put(skb
, pktlength
);
415 /* make cache consistent with receive packet buffer */
416 dma_sync_single_for_cpu(priv
->device
,
417 priv
->rx_ring
[entry
].dma_addr
,
418 priv
->rx_ring
[entry
].len
,
421 dma_unmap_single(priv
->device
, priv
->rx_ring
[entry
].dma_addr
,
422 priv
->rx_ring
[entry
].len
, DMA_FROM_DEVICE
);
424 if (netif_msg_pktdata(priv
)) {
425 netdev_info(priv
->dev
, "frame received %d bytes\n",
427 print_hex_dump(KERN_ERR
, "data: ", DUMP_PREFIX_OFFSET
,
428 16, 1, skb
->data
, pktlength
, true);
431 tse_rx_vlan(priv
->dev
, skb
);
433 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
434 skb_checksum_none_assert(skb
);
436 napi_gro_receive(&priv
->napi
, skb
);
438 priv
->dev
->stats
.rx_packets
++;
439 priv
->dev
->stats
.rx_bytes
+= pktlength
;
449 /* Reclaim resources after transmission completes
451 static int tse_tx_complete(struct altera_tse_private
*priv
)
453 unsigned int txsize
= priv
->tx_ring_size
;
456 struct tse_buffer
*tx_buff
;
459 spin_lock(&priv
->tx_lock
);
461 ready
= priv
->dmaops
->tx_completions(priv
);
463 /* Free sent buffers */
464 while (ready
&& (priv
->tx_cons
!= priv
->tx_prod
)) {
465 entry
= priv
->tx_cons
% txsize
;
466 tx_buff
= &priv
->tx_ring
[entry
];
468 if (netif_msg_tx_done(priv
))
469 netdev_dbg(priv
->dev
, "%s: curr %d, dirty %d\n",
470 __func__
, priv
->tx_prod
, priv
->tx_cons
);
472 if (likely(tx_buff
->skb
))
473 priv
->dev
->stats
.tx_packets
++;
475 tse_free_tx_buffer(priv
, tx_buff
);
482 if (unlikely(netif_queue_stopped(priv
->dev
) &&
483 tse_tx_avail(priv
) > TSE_TX_THRESH(priv
))) {
484 netif_tx_lock(priv
->dev
);
485 if (netif_queue_stopped(priv
->dev
) &&
486 tse_tx_avail(priv
) > TSE_TX_THRESH(priv
)) {
487 if (netif_msg_tx_done(priv
))
488 netdev_dbg(priv
->dev
, "%s: restart transmit\n",
490 netif_wake_queue(priv
->dev
);
492 netif_tx_unlock(priv
->dev
);
495 spin_unlock(&priv
->tx_lock
);
499 /* NAPI polling function
501 static int tse_poll(struct napi_struct
*napi
, int budget
)
503 struct altera_tse_private
*priv
=
504 container_of(napi
, struct altera_tse_private
, napi
);
506 unsigned long int flags
;
508 tse_tx_complete(priv
);
510 rxcomplete
= tse_rx(priv
, budget
);
512 if (rxcomplete
< budget
) {
514 napi_gro_flush(napi
, false);
515 __napi_complete(napi
);
517 netdev_dbg(priv
->dev
,
518 "NAPI Complete, did %d packets with budget %d\n",
521 spin_lock_irqsave(&priv
->rxdma_irq_lock
, flags
);
522 priv
->dmaops
->enable_rxirq(priv
);
523 priv
->dmaops
->enable_txirq(priv
);
524 spin_unlock_irqrestore(&priv
->rxdma_irq_lock
, flags
);
529 /* DMA TX & RX FIFO interrupt routing
531 static irqreturn_t
altera_isr(int irq
, void *dev_id
)
533 struct net_device
*dev
= dev_id
;
534 struct altera_tse_private
*priv
;
536 if (unlikely(!dev
)) {
537 pr_err("%s: invalid dev pointer\n", __func__
);
540 priv
= netdev_priv(dev
);
542 spin_lock(&priv
->rxdma_irq_lock
);
544 priv
->dmaops
->clear_rxirq(priv
);
545 priv
->dmaops
->clear_txirq(priv
);
546 spin_unlock(&priv
->rxdma_irq_lock
);
548 if (likely(napi_schedule_prep(&priv
->napi
))) {
549 spin_lock(&priv
->rxdma_irq_lock
);
550 priv
->dmaops
->disable_rxirq(priv
);
551 priv
->dmaops
->disable_txirq(priv
);
552 spin_unlock(&priv
->rxdma_irq_lock
);
553 __napi_schedule(&priv
->napi
);
560 /* Transmit a packet (called by the kernel). Dispatches
561 * either the SGDMA method for transmitting or the
562 * MSGDMA method, assumes no scatter/gather support,
563 * implying an assumption that there's only one
564 * physically contiguous fragment starting at
565 * skb->data, for length of skb_headlen(skb).
567 static int tse_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
569 struct altera_tse_private
*priv
= netdev_priv(dev
);
570 unsigned int txsize
= priv
->tx_ring_size
;
572 struct tse_buffer
*buffer
= NULL
;
573 int nfrags
= skb_shinfo(skb
)->nr_frags
;
574 unsigned int nopaged_len
= skb_headlen(skb
);
575 enum netdev_tx ret
= NETDEV_TX_OK
;
578 spin_lock_bh(&priv
->tx_lock
);
580 if (unlikely(tse_tx_avail(priv
) < nfrags
+ 1)) {
581 if (!netif_queue_stopped(dev
)) {
582 netif_stop_queue(dev
);
583 /* This is a hard error, log it. */
584 netdev_err(priv
->dev
,
585 "%s: Tx list full when queue awake\n",
588 ret
= NETDEV_TX_BUSY
;
592 /* Map the first skb fragment */
593 entry
= priv
->tx_prod
% txsize
;
594 buffer
= &priv
->tx_ring
[entry
];
596 dma_addr
= dma_map_single(priv
->device
, skb
->data
, nopaged_len
,
598 if (dma_mapping_error(priv
->device
, dma_addr
)) {
599 netdev_err(priv
->dev
, "%s: DMA mapping error\n", __func__
);
605 buffer
->dma_addr
= dma_addr
;
606 buffer
->len
= nopaged_len
;
608 /* Push data out of the cache hierarchy into main memory */
609 dma_sync_single_for_device(priv
->device
, buffer
->dma_addr
,
610 buffer
->len
, DMA_TO_DEVICE
);
612 priv
->dmaops
->tx_buffer(priv
, buffer
);
614 skb_tx_timestamp(skb
);
617 dev
->stats
.tx_bytes
+= skb
->len
;
619 if (unlikely(tse_tx_avail(priv
) <= TXQUEUESTOP_THRESHHOLD
)) {
620 if (netif_msg_hw(priv
))
621 netdev_dbg(priv
->dev
, "%s: stop transmitted packets\n",
623 netif_stop_queue(dev
);
627 spin_unlock_bh(&priv
->tx_lock
);
632 /* Called every time the controller might need to be made
633 * aware of new link state. The PHY code conveys this
634 * information through variables in the phydev structure, and this
635 * function converts those variables into the appropriate
636 * register values, and can bring down the device if needed.
638 static void altera_tse_adjust_link(struct net_device
*dev
)
640 struct altera_tse_private
*priv
= netdev_priv(dev
);
641 struct phy_device
*phydev
= priv
->phydev
;
644 /* only change config if there is a link */
645 spin_lock(&priv
->mac_cfg_lock
);
647 /* Read old config */
648 u32 cfg_reg
= ioread32(&priv
->mac_dev
->command_config
);
651 if (phydev
->duplex
!= priv
->oldduplex
) {
653 if (!(phydev
->duplex
))
654 cfg_reg
|= MAC_CMDCFG_HD_ENA
;
656 cfg_reg
&= ~MAC_CMDCFG_HD_ENA
;
658 netdev_dbg(priv
->dev
, "%s: Link duplex = 0x%x\n",
659 dev
->name
, phydev
->duplex
);
661 priv
->oldduplex
= phydev
->duplex
;
665 if (phydev
->speed
!= priv
->oldspeed
) {
667 switch (phydev
->speed
) {
669 cfg_reg
|= MAC_CMDCFG_ETH_SPEED
;
670 cfg_reg
&= ~MAC_CMDCFG_ENA_10
;
673 cfg_reg
&= ~MAC_CMDCFG_ETH_SPEED
;
674 cfg_reg
&= ~MAC_CMDCFG_ENA_10
;
677 cfg_reg
&= ~MAC_CMDCFG_ETH_SPEED
;
678 cfg_reg
|= MAC_CMDCFG_ENA_10
;
681 if (netif_msg_link(priv
))
682 netdev_warn(dev
, "Speed (%d) is not 10/100/1000!\n",
686 priv
->oldspeed
= phydev
->speed
;
688 iowrite32(cfg_reg
, &priv
->mac_dev
->command_config
);
690 if (!priv
->oldlink
) {
694 } else if (priv
->oldlink
) {
698 priv
->oldduplex
= -1;
701 if (new_state
&& netif_msg_link(priv
))
702 phy_print_status(phydev
);
704 spin_unlock(&priv
->mac_cfg_lock
);
706 static struct phy_device
*connect_local_phy(struct net_device
*dev
)
708 struct altera_tse_private
*priv
= netdev_priv(dev
);
709 struct phy_device
*phydev
= NULL
;
710 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
712 if (priv
->phy_addr
!= POLL_PHY
) {
713 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
,
714 priv
->mdio
->id
, priv
->phy_addr
);
716 netdev_dbg(dev
, "trying to attach to %s\n", phy_id_fmt
);
718 phydev
= phy_connect(dev
, phy_id_fmt
, &altera_tse_adjust_link
,
721 netdev_err(dev
, "Could not attach to PHY\n");
725 phydev
= phy_find_first(priv
->mdio
);
726 if (phydev
== NULL
) {
727 netdev_err(dev
, "No PHY found\n");
731 ret
= phy_connect_direct(dev
, phydev
, &altera_tse_adjust_link
,
734 netdev_err(dev
, "Could not attach to PHY\n");
741 static int altera_tse_phy_get_addr_mdio_create(struct net_device
*dev
)
743 struct altera_tse_private
*priv
= netdev_priv(dev
);
744 struct device_node
*np
= priv
->device
->of_node
;
747 priv
->phy_iface
= of_get_phy_mode(np
);
749 /* Avoid get phy addr and create mdio if no phy is present */
750 if (!priv
->phy_iface
)
753 /* try to get PHY address from device tree, use PHY autodetection if
754 * no valid address is given
757 if (of_property_read_u32(priv
->device
->of_node
, "phy-addr",
759 priv
->phy_addr
= POLL_PHY
;
762 if (!((priv
->phy_addr
== POLL_PHY
) ||
763 ((priv
->phy_addr
>= 0) && (priv
->phy_addr
< PHY_MAX_ADDR
)))) {
764 netdev_err(dev
, "invalid phy-addr specified %d\n",
769 /* Create/attach to MDIO bus */
770 ret
= altera_tse_mdio_create(dev
,
771 atomic_add_return(1, &instance_count
));
779 /* Initialize driver's PHY state, and attach to the PHY
781 static int init_phy(struct net_device
*dev
)
783 struct altera_tse_private
*priv
= netdev_priv(dev
);
784 struct phy_device
*phydev
;
785 struct device_node
*phynode
;
786 bool fixed_link
= false;
789 /* Avoid init phy in case of no phy present */
790 if (!priv
->phy_iface
)
795 priv
->oldduplex
= -1;
797 phynode
= of_parse_phandle(priv
->device
->of_node
, "phy-handle", 0);
800 /* check if a fixed-link is defined in device-tree */
801 if (of_phy_is_fixed_link(priv
->device
->of_node
)) {
802 rc
= of_phy_register_fixed_link(priv
->device
->of_node
);
804 netdev_err(dev
, "cannot register fixed PHY\n");
808 /* In the case of a fixed PHY, the DT node associated
809 * to the PHY is the Ethernet MAC DT node.
811 phynode
= of_node_get(priv
->device
->of_node
);
814 netdev_dbg(dev
, "fixed-link detected\n");
815 phydev
= of_phy_connect(dev
, phynode
,
816 &altera_tse_adjust_link
,
819 netdev_dbg(dev
, "no phy-handle found\n");
821 netdev_err(dev
, "No phy-handle nor local mdio specified\n");
824 phydev
= connect_local_phy(dev
);
827 netdev_dbg(dev
, "phy-handle found\n");
828 phydev
= of_phy_connect(dev
, phynode
,
829 &altera_tse_adjust_link
, 0, priv
->phy_iface
);
833 netdev_err(dev
, "Could not find the PHY\n");
837 /* Stop Advertising 1000BASE Capability if interface is not GMII
838 * Note: Checkpatch throws CHECKs for the camel case defines below,
841 if ((priv
->phy_iface
== PHY_INTERFACE_MODE_MII
) ||
842 (priv
->phy_iface
== PHY_INTERFACE_MODE_RMII
))
843 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
844 SUPPORTED_1000baseT_Full
);
846 /* Broken HW is sometimes missing the pull-up resistor on the
847 * MDIO line, which results in reads to non-existent devices returning
848 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
849 * device as well. If a fixed-link is used the phy_id is always 0.
850 * Note: phydev->phy_id is the result of reading the UID PHY registers.
852 if ((phydev
->phy_id
== 0) && !fixed_link
) {
853 netdev_err(dev
, "Bad PHY UID 0x%08x\n", phydev
->phy_id
);
854 phy_disconnect(phydev
);
858 netdev_dbg(dev
, "attached to PHY %d UID 0x%08x Link = %d\n",
859 phydev
->addr
, phydev
->phy_id
, phydev
->link
);
861 priv
->phydev
= phydev
;
865 static void tse_update_mac_addr(struct altera_tse_private
*priv
, u8
*addr
)
870 msb
= (addr
[3] << 24) | (addr
[2] << 16) | (addr
[1] << 8) | addr
[0];
871 lsb
= ((addr
[5] << 8) | addr
[4]) & 0xffff;
873 /* Set primary MAC address */
874 csrwr32(msb
, priv
->mac_dev
, tse_csroffs(mac_addr_0
));
875 csrwr32(lsb
, priv
->mac_dev
, tse_csroffs(mac_addr_1
));
878 /* MAC software reset.
879 * When reset is triggered, the MAC function completes the current
880 * transmission or reception, and subsequently disables the transmit and
881 * receive logic, flushes the receive FIFO buffer, and resets the statistics
884 static int reset_mac(struct altera_tse_private
*priv
)
889 dat
= csrrd32(priv
->mac_dev
, tse_csroffs(command_config
));
890 dat
&= ~(MAC_CMDCFG_TX_ENA
| MAC_CMDCFG_RX_ENA
);
891 dat
|= MAC_CMDCFG_SW_RESET
| MAC_CMDCFG_CNT_RESET
;
892 csrwr32(dat
, priv
->mac_dev
, tse_csroffs(command_config
));
895 while (counter
++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR
) {
896 if (tse_bit_is_clear(priv
->mac_dev
, tse_csroffs(command_config
),
897 MAC_CMDCFG_SW_RESET
))
902 if (counter
>= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR
) {
903 dat
= csrrd32(priv
->mac_dev
, tse_csroffs(command_config
));
904 dat
&= ~MAC_CMDCFG_SW_RESET
;
905 csrwr32(dat
, priv
->mac_dev
, tse_csroffs(command_config
));
911 /* Initialize MAC core registers
913 static int init_mac(struct altera_tse_private
*priv
)
915 unsigned int cmd
= 0;
919 csrwr32(priv
->rx_fifo_depth
- ALTERA_TSE_RX_SECTION_EMPTY
,
920 priv
->mac_dev
, tse_csroffs(rx_section_empty
));
922 csrwr32(ALTERA_TSE_RX_SECTION_FULL
, priv
->mac_dev
,
923 tse_csroffs(rx_section_full
));
925 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY
, priv
->mac_dev
,
926 tse_csroffs(rx_almost_empty
));
928 csrwr32(ALTERA_TSE_RX_ALMOST_FULL
, priv
->mac_dev
,
929 tse_csroffs(rx_almost_full
));
932 csrwr32(priv
->tx_fifo_depth
- ALTERA_TSE_TX_SECTION_EMPTY
,
933 priv
->mac_dev
, tse_csroffs(tx_section_empty
));
935 csrwr32(ALTERA_TSE_TX_SECTION_FULL
, priv
->mac_dev
,
936 tse_csroffs(tx_section_full
));
938 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY
, priv
->mac_dev
,
939 tse_csroffs(tx_almost_empty
));
941 csrwr32(ALTERA_TSE_TX_ALMOST_FULL
, priv
->mac_dev
,
942 tse_csroffs(tx_almost_full
));
944 /* MAC Address Configuration */
945 tse_update_mac_addr(priv
, priv
->dev
->dev_addr
);
947 /* MAC Function Configuration */
948 frm_length
= ETH_HLEN
+ priv
->dev
->mtu
+ ETH_FCS_LEN
;
949 csrwr32(frm_length
, priv
->mac_dev
, tse_csroffs(frm_length
));
951 csrwr32(ALTERA_TSE_TX_IPG_LENGTH
, priv
->mac_dev
,
952 tse_csroffs(tx_ipg_length
));
954 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
957 tse_set_bit(priv
->mac_dev
, tse_csroffs(rx_cmd_stat
),
958 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16
);
960 tse_clear_bit(priv
->mac_dev
, tse_csroffs(tx_cmd_stat
),
961 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16
|
962 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC
);
964 /* Set the MAC options */
965 cmd
= csrrd32(priv
->mac_dev
, tse_csroffs(command_config
));
966 cmd
&= ~MAC_CMDCFG_PAD_EN
; /* No padding Removal on Receive */
967 cmd
&= ~MAC_CMDCFG_CRC_FWD
; /* CRC Removal */
968 cmd
|= MAC_CMDCFG_RX_ERR_DISC
; /* Automatically discard frames
971 cmd
|= MAC_CMDCFG_CNTL_FRM_ENA
;
972 cmd
&= ~MAC_CMDCFG_TX_ENA
;
973 cmd
&= ~MAC_CMDCFG_RX_ENA
;
975 /* Default speed and duplex setting, full/100 */
976 cmd
&= ~MAC_CMDCFG_HD_ENA
;
977 cmd
&= ~MAC_CMDCFG_ETH_SPEED
;
978 cmd
&= ~MAC_CMDCFG_ENA_10
;
980 csrwr32(cmd
, priv
->mac_dev
, tse_csroffs(command_config
));
982 csrwr32(ALTERA_TSE_PAUSE_QUANTA
, priv
->mac_dev
,
983 tse_csroffs(pause_quanta
));
985 if (netif_msg_hw(priv
))
986 dev_dbg(priv
->device
,
987 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd
);
992 /* Start/stop MAC transmission logic
994 static void tse_set_mac(struct altera_tse_private
*priv
, bool enable
)
996 u32 value
= csrrd32(priv
->mac_dev
, tse_csroffs(command_config
));
999 value
|= MAC_CMDCFG_TX_ENA
| MAC_CMDCFG_RX_ENA
;
1001 value
&= ~(MAC_CMDCFG_TX_ENA
| MAC_CMDCFG_RX_ENA
);
1003 csrwr32(value
, priv
->mac_dev
, tse_csroffs(command_config
));
1008 static int tse_change_mtu(struct net_device
*dev
, int new_mtu
)
1010 struct altera_tse_private
*priv
= netdev_priv(dev
);
1011 unsigned int max_mtu
= priv
->max_mtu
;
1012 unsigned int min_mtu
= ETH_ZLEN
+ ETH_FCS_LEN
;
1014 if (netif_running(dev
)) {
1015 netdev_err(dev
, "must be stopped to change its MTU\n");
1019 if ((new_mtu
< min_mtu
) || (new_mtu
> max_mtu
)) {
1020 netdev_err(dev
, "invalid MTU, max MTU is: %u\n", max_mtu
);
1025 netdev_update_features(dev
);
1030 static void altera_tse_set_mcfilter(struct net_device
*dev
)
1032 struct altera_tse_private
*priv
= netdev_priv(dev
);
1034 struct netdev_hw_addr
*ha
;
1036 /* clear the hash filter */
1037 for (i
= 0; i
< 64; i
++)
1038 csrwr32(0, priv
->mac_dev
, tse_csroffs(hash_table
) + i
* 4);
1040 netdev_for_each_mc_addr(ha
, dev
) {
1041 unsigned int hash
= 0;
1044 for (mac_octet
= 5; mac_octet
>= 0; mac_octet
--) {
1045 unsigned char xor_bit
= 0;
1046 unsigned char octet
= ha
->addr
[mac_octet
];
1047 unsigned int bitshift
;
1049 for (bitshift
= 0; bitshift
< 8; bitshift
++)
1050 xor_bit
^= ((octet
>> bitshift
) & 0x01);
1052 hash
= (hash
<< 1) | xor_bit
;
1054 csrwr32(1, priv
->mac_dev
, tse_csroffs(hash_table
) + hash
* 4);
1059 static void altera_tse_set_mcfilterall(struct net_device
*dev
)
1061 struct altera_tse_private
*priv
= netdev_priv(dev
);
1064 /* set the hash filter */
1065 for (i
= 0; i
< 64; i
++)
1066 csrwr32(1, priv
->mac_dev
, tse_csroffs(hash_table
) + i
* 4);
1069 /* Set or clear the multicast filter for this adaptor
1071 static void tse_set_rx_mode_hashfilter(struct net_device
*dev
)
1073 struct altera_tse_private
*priv
= netdev_priv(dev
);
1075 spin_lock(&priv
->mac_cfg_lock
);
1077 if (dev
->flags
& IFF_PROMISC
)
1078 tse_set_bit(priv
->mac_dev
, tse_csroffs(command_config
),
1079 MAC_CMDCFG_PROMIS_EN
);
1081 if (dev
->flags
& IFF_ALLMULTI
)
1082 altera_tse_set_mcfilterall(dev
);
1084 altera_tse_set_mcfilter(dev
);
1086 spin_unlock(&priv
->mac_cfg_lock
);
1089 /* Set or clear the multicast filter for this adaptor
1091 static void tse_set_rx_mode(struct net_device
*dev
)
1093 struct altera_tse_private
*priv
= netdev_priv(dev
);
1095 spin_lock(&priv
->mac_cfg_lock
);
1097 if ((dev
->flags
& IFF_PROMISC
) || (dev
->flags
& IFF_ALLMULTI
) ||
1098 !netdev_mc_empty(dev
) || !netdev_uc_empty(dev
))
1099 tse_set_bit(priv
->mac_dev
, tse_csroffs(command_config
),
1100 MAC_CMDCFG_PROMIS_EN
);
1102 tse_clear_bit(priv
->mac_dev
, tse_csroffs(command_config
),
1103 MAC_CMDCFG_PROMIS_EN
);
1105 spin_unlock(&priv
->mac_cfg_lock
);
1108 /* Open and initialize the interface
1110 static int tse_open(struct net_device
*dev
)
1112 struct altera_tse_private
*priv
= netdev_priv(dev
);
1115 unsigned long int flags
;
1117 /* Reset and configure TSE MAC and probe associated PHY */
1118 ret
= priv
->dmaops
->init_dma(priv
);
1120 netdev_err(dev
, "Cannot initialize DMA\n");
1124 if (netif_msg_ifup(priv
))
1125 netdev_warn(dev
, "device MAC address %pM\n",
1128 if ((priv
->revision
< 0xd00) || (priv
->revision
> 0xe00))
1129 netdev_warn(dev
, "TSE revision %x\n", priv
->revision
);
1131 spin_lock(&priv
->mac_cfg_lock
);
1132 ret
= reset_mac(priv
);
1133 /* Note that reset_mac will fail if the clocks are gated by the PHY
1134 * due to the PHY being put into isolation or power down mode.
1135 * This is not an error if reset fails due to no clock.
1138 netdev_dbg(dev
, "Cannot reset MAC core (error: %d)\n", ret
);
1140 ret
= init_mac(priv
);
1141 spin_unlock(&priv
->mac_cfg_lock
);
1143 netdev_err(dev
, "Cannot init MAC core (error: %d)\n", ret
);
1144 goto alloc_skbuf_error
;
1147 priv
->dmaops
->reset_dma(priv
);
1149 /* Create and initialize the TX/RX descriptors chains. */
1150 priv
->rx_ring_size
= dma_rx_num
;
1151 priv
->tx_ring_size
= dma_tx_num
;
1152 ret
= alloc_init_skbufs(priv
);
1154 netdev_err(dev
, "DMA descriptors initialization failed\n");
1155 goto alloc_skbuf_error
;
1159 /* Register RX interrupt */
1160 ret
= request_irq(priv
->rx_irq
, altera_isr
, IRQF_SHARED
,
1163 netdev_err(dev
, "Unable to register RX interrupt %d\n",
1168 /* Register TX interrupt */
1169 ret
= request_irq(priv
->tx_irq
, altera_isr
, IRQF_SHARED
,
1172 netdev_err(dev
, "Unable to register TX interrupt %d\n",
1174 goto tx_request_irq_error
;
1177 /* Enable DMA interrupts */
1178 spin_lock_irqsave(&priv
->rxdma_irq_lock
, flags
);
1179 priv
->dmaops
->enable_rxirq(priv
);
1180 priv
->dmaops
->enable_txirq(priv
);
1182 /* Setup RX descriptor chain */
1183 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
1184 priv
->dmaops
->add_rx_desc(priv
, &priv
->rx_ring
[i
]);
1186 spin_unlock_irqrestore(&priv
->rxdma_irq_lock
, flags
);
1189 phy_start(priv
->phydev
);
1191 napi_enable(&priv
->napi
);
1192 netif_start_queue(dev
);
1194 priv
->dmaops
->start_rxdma(priv
);
1196 /* Start MAC Rx/Tx */
1197 spin_lock(&priv
->mac_cfg_lock
);
1198 tse_set_mac(priv
, true);
1199 spin_unlock(&priv
->mac_cfg_lock
);
1203 tx_request_irq_error
:
1204 free_irq(priv
->rx_irq
, dev
);
1212 /* Stop TSE MAC interface and put the device in an inactive state
1214 static int tse_shutdown(struct net_device
*dev
)
1216 struct altera_tse_private
*priv
= netdev_priv(dev
);
1218 unsigned long int flags
;
1222 phy_stop(priv
->phydev
);
1224 netif_stop_queue(dev
);
1225 napi_disable(&priv
->napi
);
1227 /* Disable DMA interrupts */
1228 spin_lock_irqsave(&priv
->rxdma_irq_lock
, flags
);
1229 priv
->dmaops
->disable_rxirq(priv
);
1230 priv
->dmaops
->disable_txirq(priv
);
1231 spin_unlock_irqrestore(&priv
->rxdma_irq_lock
, flags
);
1233 /* Free the IRQ lines */
1234 free_irq(priv
->rx_irq
, dev
);
1235 free_irq(priv
->tx_irq
, dev
);
1237 /* disable and reset the MAC, empties fifo */
1238 spin_lock(&priv
->mac_cfg_lock
);
1239 spin_lock(&priv
->tx_lock
);
1241 ret
= reset_mac(priv
);
1242 /* Note that reset_mac will fail if the clocks are gated by the PHY
1243 * due to the PHY being put into isolation or power down mode.
1244 * This is not an error if reset fails due to no clock.
1247 netdev_dbg(dev
, "Cannot reset MAC core (error: %d)\n", ret
);
1248 priv
->dmaops
->reset_dma(priv
);
1251 spin_unlock(&priv
->tx_lock
);
1252 spin_unlock(&priv
->mac_cfg_lock
);
1254 priv
->dmaops
->uninit_dma(priv
);
1259 static struct net_device_ops altera_tse_netdev_ops
= {
1260 .ndo_open
= tse_open
,
1261 .ndo_stop
= tse_shutdown
,
1262 .ndo_start_xmit
= tse_start_xmit
,
1263 .ndo_set_mac_address
= eth_mac_addr
,
1264 .ndo_set_rx_mode
= tse_set_rx_mode
,
1265 .ndo_change_mtu
= tse_change_mtu
,
1266 .ndo_validate_addr
= eth_validate_addr
,
1269 static int request_and_map(struct platform_device
*pdev
, const char *name
,
1270 struct resource
**res
, void __iomem
**ptr
)
1272 struct resource
*region
;
1273 struct device
*device
= &pdev
->dev
;
1275 *res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, name
);
1277 dev_err(device
, "resource %s not defined\n", name
);
1281 region
= devm_request_mem_region(device
, (*res
)->start
,
1282 resource_size(*res
), dev_name(device
));
1283 if (region
== NULL
) {
1284 dev_err(device
, "unable to request %s\n", name
);
1288 *ptr
= devm_ioremap_nocache(device
, region
->start
,
1289 resource_size(region
));
1291 dev_err(device
, "ioremap_nocache of %s failed!", name
);
1298 /* Probe Altera TSE MAC device
1300 static int altera_tse_probe(struct platform_device
*pdev
)
1302 struct net_device
*ndev
;
1304 struct resource
*control_port
;
1305 struct resource
*dma_res
;
1306 struct altera_tse_private
*priv
;
1307 const unsigned char *macaddr
;
1308 void __iomem
*descmap
;
1309 const struct of_device_id
*of_id
= NULL
;
1311 ndev
= alloc_etherdev(sizeof(struct altera_tse_private
));
1313 dev_err(&pdev
->dev
, "Could not allocate network device\n");
1317 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1319 priv
= netdev_priv(ndev
);
1320 priv
->device
= &pdev
->dev
;
1322 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
1324 of_id
= of_match_device(altera_tse_ids
, &pdev
->dev
);
1327 priv
->dmaops
= (struct altera_dmaops
*)of_id
->data
;
1331 priv
->dmaops
->altera_dtype
== ALTERA_DTYPE_SGDMA
) {
1332 /* Get the mapped address to the SGDMA descriptor memory */
1333 ret
= request_and_map(pdev
, "s1", &dma_res
, &descmap
);
1335 goto err_free_netdev
;
1337 /* Start of that memory is for transmit descriptors */
1338 priv
->tx_dma_desc
= descmap
;
1340 /* First half is for tx descriptors, other half for tx */
1341 priv
->txdescmem
= resource_size(dma_res
)/2;
1343 priv
->txdescmem_busaddr
= (dma_addr_t
)dma_res
->start
;
1345 priv
->rx_dma_desc
= (void __iomem
*)((uintptr_t)(descmap
+
1347 priv
->rxdescmem
= resource_size(dma_res
)/2;
1348 priv
->rxdescmem_busaddr
= dma_res
->start
;
1349 priv
->rxdescmem_busaddr
+= priv
->txdescmem
;
1351 if (upper_32_bits(priv
->rxdescmem_busaddr
)) {
1352 dev_dbg(priv
->device
,
1353 "SGDMA bus addresses greater than 32-bits\n");
1354 goto err_free_netdev
;
1356 if (upper_32_bits(priv
->txdescmem_busaddr
)) {
1357 dev_dbg(priv
->device
,
1358 "SGDMA bus addresses greater than 32-bits\n");
1359 goto err_free_netdev
;
1361 } else if (priv
->dmaops
&&
1362 priv
->dmaops
->altera_dtype
== ALTERA_DTYPE_MSGDMA
) {
1363 ret
= request_and_map(pdev
, "rx_resp", &dma_res
,
1364 &priv
->rx_dma_resp
);
1366 goto err_free_netdev
;
1368 ret
= request_and_map(pdev
, "tx_desc", &dma_res
,
1369 &priv
->tx_dma_desc
);
1371 goto err_free_netdev
;
1373 priv
->txdescmem
= resource_size(dma_res
);
1374 priv
->txdescmem_busaddr
= dma_res
->start
;
1376 ret
= request_and_map(pdev
, "rx_desc", &dma_res
,
1377 &priv
->rx_dma_desc
);
1379 goto err_free_netdev
;
1381 priv
->rxdescmem
= resource_size(dma_res
);
1382 priv
->rxdescmem_busaddr
= dma_res
->start
;
1385 goto err_free_netdev
;
1388 if (!dma_set_mask(priv
->device
, DMA_BIT_MASK(priv
->dmaops
->dmamask
)))
1389 dma_set_coherent_mask(priv
->device
,
1390 DMA_BIT_MASK(priv
->dmaops
->dmamask
));
1391 else if (!dma_set_mask(priv
->device
, DMA_BIT_MASK(32)))
1392 dma_set_coherent_mask(priv
->device
, DMA_BIT_MASK(32));
1394 goto err_free_netdev
;
1396 /* MAC address space */
1397 ret
= request_and_map(pdev
, "control_port", &control_port
,
1398 (void __iomem
**)&priv
->mac_dev
);
1400 goto err_free_netdev
;
1402 /* xSGDMA Rx Dispatcher address space */
1403 ret
= request_and_map(pdev
, "rx_csr", &dma_res
,
1406 goto err_free_netdev
;
1409 /* xSGDMA Tx Dispatcher address space */
1410 ret
= request_and_map(pdev
, "tx_csr", &dma_res
,
1413 goto err_free_netdev
;
1417 priv
->rx_irq
= platform_get_irq_byname(pdev
, "rx_irq");
1418 if (priv
->rx_irq
== -ENXIO
) {
1419 dev_err(&pdev
->dev
, "cannot obtain Rx IRQ\n");
1421 goto err_free_netdev
;
1425 priv
->tx_irq
= platform_get_irq_byname(pdev
, "tx_irq");
1426 if (priv
->tx_irq
== -ENXIO
) {
1427 dev_err(&pdev
->dev
, "cannot obtain Tx IRQ\n");
1429 goto err_free_netdev
;
1432 /* get FIFO depths from device tree */
1433 if (of_property_read_u32(pdev
->dev
.of_node
, "rx-fifo-depth",
1434 &priv
->rx_fifo_depth
)) {
1435 dev_err(&pdev
->dev
, "cannot obtain rx-fifo-depth\n");
1437 goto err_free_netdev
;
1440 if (of_property_read_u32(pdev
->dev
.of_node
, "tx-fifo-depth",
1441 &priv
->tx_fifo_depth
)) {
1442 dev_err(&pdev
->dev
, "cannot obtain tx-fifo-depth\n");
1444 goto err_free_netdev
;
1447 /* get hash filter settings for this instance */
1449 of_property_read_bool(pdev
->dev
.of_node
,
1450 "altr,has-hash-multicast-filter");
1452 /* Set hash filter to not set for now until the
1453 * multicast filter receive issue is debugged
1455 priv
->hash_filter
= 0;
1457 /* get supplemental address settings for this instance */
1458 priv
->added_unicast
=
1459 of_property_read_bool(pdev
->dev
.of_node
,
1460 "altr,has-supplementary-unicast");
1462 /* Max MTU is 1500, ETH_DATA_LEN */
1463 priv
->max_mtu
= ETH_DATA_LEN
;
1465 /* Get the max mtu from the device tree. Note that the
1466 * "max-frame-size" parameter is actually max mtu. Definition
1467 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1469 of_property_read_u32(pdev
->dev
.of_node
, "max-frame-size",
1472 /* The DMA buffer size already accounts for an alignment bias
1473 * to avoid unaligned access exceptions for the NIOS processor,
1475 priv
->rx_dma_buf_sz
= ALTERA_RXDMABUFFER_SIZE
;
1477 /* get default MAC address from device tree */
1478 macaddr
= of_get_mac_address(pdev
->dev
.of_node
);
1480 ether_addr_copy(ndev
->dev_addr
, macaddr
);
1482 eth_hw_addr_random(ndev
);
1484 /* get phy addr and create mdio */
1485 ret
= altera_tse_phy_get_addr_mdio_create(ndev
);
1488 goto err_free_netdev
;
1490 /* initialize netdev */
1491 ndev
->mem_start
= control_port
->start
;
1492 ndev
->mem_end
= control_port
->end
;
1493 ndev
->netdev_ops
= &altera_tse_netdev_ops
;
1494 altera_tse_set_ethtool_ops(ndev
);
1496 altera_tse_netdev_ops
.ndo_set_rx_mode
= tse_set_rx_mode
;
1498 if (priv
->hash_filter
)
1499 altera_tse_netdev_ops
.ndo_set_rx_mode
=
1500 tse_set_rx_mode_hashfilter
;
1502 /* Scatter/gather IO is not supported,
1503 * so it is turned off
1505 ndev
->hw_features
&= ~NETIF_F_SG
;
1506 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
1508 /* VLAN offloading of tagging, stripping and filtering is not
1509 * supported by hardware, but driver will accommodate the
1510 * extra 4-byte VLAN tag for processing by upper layers
1512 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
1514 /* setup NAPI interface */
1515 netif_napi_add(ndev
, &priv
->napi
, tse_poll
, NAPI_POLL_WEIGHT
);
1517 spin_lock_init(&priv
->mac_cfg_lock
);
1518 spin_lock_init(&priv
->tx_lock
);
1519 spin_lock_init(&priv
->rxdma_irq_lock
);
1521 ret
= register_netdev(ndev
);
1523 dev_err(&pdev
->dev
, "failed to register TSE net device\n");
1524 goto err_register_netdev
;
1527 platform_set_drvdata(pdev
, ndev
);
1529 priv
->revision
= ioread32(&priv
->mac_dev
->megacore_revision
);
1531 if (netif_msg_probe(priv
))
1532 dev_info(&pdev
->dev
, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1533 (priv
->revision
>> 8) & 0xff,
1534 priv
->revision
& 0xff,
1535 (unsigned long) control_port
->start
, priv
->rx_irq
,
1538 ret
= init_phy(ndev
);
1540 netdev_err(ndev
, "Cannot attach to PHY (error: %d)\n", ret
);
1546 unregister_netdev(ndev
);
1547 err_register_netdev
:
1548 netif_napi_del(&priv
->napi
);
1549 altera_tse_mdio_destroy(ndev
);
1555 /* Remove Altera TSE MAC device
1557 static int altera_tse_remove(struct platform_device
*pdev
)
1559 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1560 struct altera_tse_private
*priv
= netdev_priv(ndev
);
1563 phy_disconnect(priv
->phydev
);
1565 platform_set_drvdata(pdev
, NULL
);
1566 altera_tse_mdio_destroy(ndev
);
1567 unregister_netdev(ndev
);
1573 static const struct altera_dmaops altera_dtype_sgdma
= {
1574 .altera_dtype
= ALTERA_DTYPE_SGDMA
,
1576 .reset_dma
= sgdma_reset
,
1577 .enable_txirq
= sgdma_enable_txirq
,
1578 .enable_rxirq
= sgdma_enable_rxirq
,
1579 .disable_txirq
= sgdma_disable_txirq
,
1580 .disable_rxirq
= sgdma_disable_rxirq
,
1581 .clear_txirq
= sgdma_clear_txirq
,
1582 .clear_rxirq
= sgdma_clear_rxirq
,
1583 .tx_buffer
= sgdma_tx_buffer
,
1584 .tx_completions
= sgdma_tx_completions
,
1585 .add_rx_desc
= sgdma_add_rx_desc
,
1586 .get_rx_status
= sgdma_rx_status
,
1587 .init_dma
= sgdma_initialize
,
1588 .uninit_dma
= sgdma_uninitialize
,
1589 .start_rxdma
= sgdma_start_rxdma
,
1592 static const struct altera_dmaops altera_dtype_msgdma
= {
1593 .altera_dtype
= ALTERA_DTYPE_MSGDMA
,
1595 .reset_dma
= msgdma_reset
,
1596 .enable_txirq
= msgdma_enable_txirq
,
1597 .enable_rxirq
= msgdma_enable_rxirq
,
1598 .disable_txirq
= msgdma_disable_txirq
,
1599 .disable_rxirq
= msgdma_disable_rxirq
,
1600 .clear_txirq
= msgdma_clear_txirq
,
1601 .clear_rxirq
= msgdma_clear_rxirq
,
1602 .tx_buffer
= msgdma_tx_buffer
,
1603 .tx_completions
= msgdma_tx_completions
,
1604 .add_rx_desc
= msgdma_add_rx_desc
,
1605 .get_rx_status
= msgdma_rx_status
,
1606 .init_dma
= msgdma_initialize
,
1607 .uninit_dma
= msgdma_uninitialize
,
1608 .start_rxdma
= msgdma_start_rxdma
,
1611 static const struct of_device_id altera_tse_ids
[] = {
1612 { .compatible
= "altr,tse-msgdma-1.0", .data
= &altera_dtype_msgdma
, },
1613 { .compatible
= "altr,tse-1.0", .data
= &altera_dtype_sgdma
, },
1614 { .compatible
= "ALTR,tse-1.0", .data
= &altera_dtype_sgdma
, },
1617 MODULE_DEVICE_TABLE(of
, altera_tse_ids
);
1619 static struct platform_driver altera_tse_driver
= {
1620 .probe
= altera_tse_probe
,
1621 .remove
= altera_tse_remove
,
1625 .name
= ALTERA_TSE_RESOURCE_NAME
,
1626 .of_match_table
= altera_tse_ids
,
1630 module_platform_driver(altera_tse_driver
);
1632 MODULE_AUTHOR("Altera Corporation");
1633 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1634 MODULE_LICENSE("GPL v2");