3 * Alchemy Au1x00 ethernet driver
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
18 * ########################################################################
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, see <http://www.gnu.org/licenses/>.
32 * ########################################################################
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38 #include <linux/capability.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/timer.h>
44 #include <linux/errno.h>
46 #include <linux/ioport.h>
47 #include <linux/bitops.h>
48 #include <linux/slab.h>
49 #include <linux/interrupt.h>
50 #include <linux/netdevice.h>
51 #include <linux/etherdevice.h>
52 #include <linux/ethtool.h>
53 #include <linux/mii.h>
54 #include <linux/skbuff.h>
55 #include <linux/delay.h>
56 #include <linux/crc32.h>
57 #include <linux/phy.h>
58 #include <linux/platform_device.h>
59 #include <linux/cpu.h>
62 #include <asm/mipsregs.h>
64 #include <asm/processor.h>
67 #include <au1xxx_eth.h>
70 #include "au1000_eth.h"
72 #ifdef AU1000_ETH_DEBUG
73 static int au1000_debug
= 5;
75 static int au1000_debug
= 3;
78 #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
82 #define DRV_NAME "au1000_eth"
83 #define DRV_VERSION "1.7"
84 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
85 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
87 MODULE_AUTHOR(DRV_AUTHOR
);
88 MODULE_DESCRIPTION(DRV_DESC
);
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_VERSION
);
92 /* AU1000 MAC registers and bits */
93 #define MAC_CONTROL 0x0
94 # define MAC_RX_ENABLE (1 << 2)
95 # define MAC_TX_ENABLE (1 << 3)
96 # define MAC_DEF_CHECK (1 << 5)
97 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
98 # define MAC_AUTO_PAD (1 << 8)
99 # define MAC_DISABLE_RETRY (1 << 10)
100 # define MAC_DISABLE_BCAST (1 << 11)
101 # define MAC_LATE_COL (1 << 12)
102 # define MAC_HASH_MODE (1 << 13)
103 # define MAC_HASH_ONLY (1 << 15)
104 # define MAC_PASS_ALL (1 << 16)
105 # define MAC_INVERSE_FILTER (1 << 17)
106 # define MAC_PROMISCUOUS (1 << 18)
107 # define MAC_PASS_ALL_MULTI (1 << 19)
108 # define MAC_FULL_DUPLEX (1 << 20)
109 # define MAC_NORMAL_MODE 0
110 # define MAC_INT_LOOPBACK (1 << 21)
111 # define MAC_EXT_LOOPBACK (1 << 22)
112 # define MAC_DISABLE_RX_OWN (1 << 23)
113 # define MAC_BIG_ENDIAN (1 << 30)
114 # define MAC_RX_ALL (1 << 31)
115 #define MAC_ADDRESS_HIGH 0x4
116 #define MAC_ADDRESS_LOW 0x8
117 #define MAC_MCAST_HIGH 0xC
118 #define MAC_MCAST_LOW 0x10
119 #define MAC_MII_CNTRL 0x14
120 # define MAC_MII_BUSY (1 << 0)
121 # define MAC_MII_READ 0
122 # define MAC_MII_WRITE (1 << 1)
123 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125 #define MAC_MII_DATA 0x18
126 #define MAC_FLOW_CNTRL 0x1C
127 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
128 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129 # define MAC_PASS_CONTROL (1 << 2)
130 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
131 #define MAC_VLAN1_TAG 0x20
132 #define MAC_VLAN2_TAG 0x24
134 /* Ethernet Controller Enable */
135 # define MAC_EN_CLOCK_ENABLE (1 << 0)
136 # define MAC_EN_RESET0 (1 << 1)
137 # define MAC_EN_TOSS (0 << 2)
138 # define MAC_EN_CACHEABLE (1 << 3)
139 # define MAC_EN_RESET1 (1 << 4)
140 # define MAC_EN_RESET2 (1 << 5)
141 # define MAC_DMA_RESET (1 << 6)
143 /* Ethernet Controller DMA Channels */
144 /* offsets from MAC_TX_RING_ADDR address */
145 #define MAC_TX_BUFF0_STATUS 0x0
146 # define TX_FRAME_ABORTED (1 << 0)
147 # define TX_JAB_TIMEOUT (1 << 1)
148 # define TX_NO_CARRIER (1 << 2)
149 # define TX_LOSS_CARRIER (1 << 3)
150 # define TX_EXC_DEF (1 << 4)
151 # define TX_LATE_COLL_ABORT (1 << 5)
152 # define TX_EXC_COLL (1 << 6)
153 # define TX_UNDERRUN (1 << 7)
154 # define TX_DEFERRED (1 << 8)
155 # define TX_LATE_COLL (1 << 9)
156 # define TX_COLL_CNT_MASK (0xF << 10)
157 # define TX_PKT_RETRY (1 << 31)
158 #define MAC_TX_BUFF0_ADDR 0x4
159 # define TX_DMA_ENABLE (1 << 0)
160 # define TX_T_DONE (1 << 1)
161 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
162 #define MAC_TX_BUFF0_LEN 0x8
163 #define MAC_TX_BUFF1_STATUS 0x10
164 #define MAC_TX_BUFF1_ADDR 0x14
165 #define MAC_TX_BUFF1_LEN 0x18
166 #define MAC_TX_BUFF2_STATUS 0x20
167 #define MAC_TX_BUFF2_ADDR 0x24
168 #define MAC_TX_BUFF2_LEN 0x28
169 #define MAC_TX_BUFF3_STATUS 0x30
170 #define MAC_TX_BUFF3_ADDR 0x34
171 #define MAC_TX_BUFF3_LEN 0x38
173 /* offsets from MAC_RX_RING_ADDR */
174 #define MAC_RX_BUFF0_STATUS 0x0
175 # define RX_FRAME_LEN_MASK 0x3fff
176 # define RX_WDOG_TIMER (1 << 14)
177 # define RX_RUNT (1 << 15)
178 # define RX_OVERLEN (1 << 16)
179 # define RX_COLL (1 << 17)
180 # define RX_ETHER (1 << 18)
181 # define RX_MII_ERROR (1 << 19)
182 # define RX_DRIBBLING (1 << 20)
183 # define RX_CRC_ERROR (1 << 21)
184 # define RX_VLAN1 (1 << 22)
185 # define RX_VLAN2 (1 << 23)
186 # define RX_LEN_ERROR (1 << 24)
187 # define RX_CNTRL_FRAME (1 << 25)
188 # define RX_U_CNTRL_FRAME (1 << 26)
189 # define RX_MCAST_FRAME (1 << 27)
190 # define RX_BCAST_FRAME (1 << 28)
191 # define RX_FILTER_FAIL (1 << 29)
192 # define RX_PACKET_FILTER (1 << 30)
193 # define RX_MISSED_FRAME (1 << 31)
195 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
196 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198 #define MAC_RX_BUFF0_ADDR 0x4
199 # define RX_DMA_ENABLE (1 << 0)
200 # define RX_T_DONE (1 << 1)
201 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
202 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
203 #define MAC_RX_BUFF1_STATUS 0x10
204 #define MAC_RX_BUFF1_ADDR 0x14
205 #define MAC_RX_BUFF2_STATUS 0x20
206 #define MAC_RX_BUFF2_ADDR 0x24
207 #define MAC_RX_BUFF3_STATUS 0x30
208 #define MAC_RX_BUFF3_ADDR 0x34
211 * Theory of operation
213 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214 * There are four receive and four transmit descriptors. These
215 * descriptors are not in memory; rather, they are just a set of
216 * hardware registers.
218 * Since the Au1000 has a coherent data cache, the receive and
219 * transmit buffers are allocated from the KSEG0 segment. The
220 * hardware registers, however, are still mapped at KSEG1 to
221 * make sure there's no out-of-order writes, and that all writes
222 * complete immediately.
226 * board-specific configurations
228 * PHY detection algorithm
230 * If phy_static_config is undefined, the PHY setup is
233 * mii_probe() first searches the current MAC's MII bus for a PHY,
234 * selecting the first (or last, if phy_search_highest_addr is
235 * defined) PHY address not already claimed by another netdev.
237 * If nothing was found that way when searching for the 2nd ethernet
238 * controller's PHY and phy1_search_mac0 is defined, then
239 * the first MII bus is searched as well for an unclaimed PHY; this is
240 * needed in case of a dual-PHY accessible only through the MAC0's MII
243 * Finally, if no PHY is found, then the corresponding ethernet
244 * controller is not registered to the network subsystem.
247 /* autodetection defaults: phy1_search_mac0 */
251 * most boards PHY setup should be detectable properly with the
252 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253 * you have a switch attached, or want to use the PHY's interrupt
254 * notification capabilities) you can provide a static PHY
257 * IRQs may only be set, if a PHY address was configured
258 * If a PHY address is given, also a bus id is required to be set
260 * ps: make sure the used irqs are configured properly in the board
264 static void au1000_enable_mac(struct net_device
*dev
, int force_reset
)
267 struct au1000_private
*aup
= netdev_priv(dev
);
269 spin_lock_irqsave(&aup
->lock
, flags
);
271 if (force_reset
|| (!aup
->mac_enabled
)) {
272 writel(MAC_EN_CLOCK_ENABLE
, aup
->enable
);
273 wmb(); /* drain writebuffer */
275 writel((MAC_EN_RESET0
| MAC_EN_RESET1
| MAC_EN_RESET2
276 | MAC_EN_CLOCK_ENABLE
), aup
->enable
);
277 wmb(); /* drain writebuffer */
280 aup
->mac_enabled
= 1;
283 spin_unlock_irqrestore(&aup
->lock
, flags
);
289 static int au1000_mdio_read(struct net_device
*dev
, int phy_addr
, int reg
)
291 struct au1000_private
*aup
= netdev_priv(dev
);
292 u32
*const mii_control_reg
= &aup
->mac
->mii_control
;
293 u32
*const mii_data_reg
= &aup
->mac
->mii_data
;
297 while (readl(mii_control_reg
) & MAC_MII_BUSY
) {
299 if (--timedout
== 0) {
300 netdev_err(dev
, "read_MII busy timeout!!\n");
305 mii_control
= MAC_SET_MII_SELECT_REG(reg
) |
306 MAC_SET_MII_SELECT_PHY(phy_addr
) | MAC_MII_READ
;
308 writel(mii_control
, mii_control_reg
);
311 while (readl(mii_control_reg
) & MAC_MII_BUSY
) {
313 if (--timedout
== 0) {
314 netdev_err(dev
, "mdio_read busy timeout!!\n");
318 return readl(mii_data_reg
);
321 static void au1000_mdio_write(struct net_device
*dev
, int phy_addr
,
324 struct au1000_private
*aup
= netdev_priv(dev
);
325 u32
*const mii_control_reg
= &aup
->mac
->mii_control
;
326 u32
*const mii_data_reg
= &aup
->mac
->mii_data
;
330 while (readl(mii_control_reg
) & MAC_MII_BUSY
) {
332 if (--timedout
== 0) {
333 netdev_err(dev
, "mdio_write busy timeout!!\n");
338 mii_control
= MAC_SET_MII_SELECT_REG(reg
) |
339 MAC_SET_MII_SELECT_PHY(phy_addr
) | MAC_MII_WRITE
;
341 writel(value
, mii_data_reg
);
342 writel(mii_control
, mii_control_reg
);
345 static int au1000_mdiobus_read(struct mii_bus
*bus
, int phy_addr
, int regnum
)
347 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
348 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
350 struct net_device
*const dev
= bus
->priv
;
352 /* make sure the MAC associated with this
355 au1000_enable_mac(dev
, 0);
357 return au1000_mdio_read(dev
, phy_addr
, regnum
);
360 static int au1000_mdiobus_write(struct mii_bus
*bus
, int phy_addr
, int regnum
,
363 struct net_device
*const dev
= bus
->priv
;
365 /* make sure the MAC associated with this
368 au1000_enable_mac(dev
, 0);
370 au1000_mdio_write(dev
, phy_addr
, regnum
, value
);
374 static int au1000_mdiobus_reset(struct mii_bus
*bus
)
376 struct net_device
*const dev
= bus
->priv
;
378 /* make sure the MAC associated with this
381 au1000_enable_mac(dev
, 0);
386 static void au1000_hard_stop(struct net_device
*dev
)
388 struct au1000_private
*aup
= netdev_priv(dev
);
391 netif_dbg(aup
, drv
, dev
, "hard stop\n");
393 reg
= readl(&aup
->mac
->control
);
394 reg
&= ~(MAC_RX_ENABLE
| MAC_TX_ENABLE
);
395 writel(reg
, &aup
->mac
->control
);
396 wmb(); /* drain writebuffer */
400 static void au1000_enable_rx_tx(struct net_device
*dev
)
402 struct au1000_private
*aup
= netdev_priv(dev
);
405 netif_dbg(aup
, hw
, dev
, "enable_rx_tx\n");
407 reg
= readl(&aup
->mac
->control
);
408 reg
|= (MAC_RX_ENABLE
| MAC_TX_ENABLE
);
409 writel(reg
, &aup
->mac
->control
);
410 wmb(); /* drain writebuffer */
415 au1000_adjust_link(struct net_device
*dev
)
417 struct au1000_private
*aup
= netdev_priv(dev
);
418 struct phy_device
*phydev
= aup
->phy_dev
;
422 int status_change
= 0;
424 BUG_ON(!aup
->phy_dev
);
426 spin_lock_irqsave(&aup
->lock
, flags
);
428 if (phydev
->link
&& (aup
->old_speed
!= phydev
->speed
)) {
431 switch (phydev
->speed
) {
436 netdev_warn(dev
, "Speed (%d) is not 10/100 ???\n",
441 aup
->old_speed
= phydev
->speed
;
446 if (phydev
->link
&& (aup
->old_duplex
!= phydev
->duplex
)) {
447 /* duplex mode changed */
449 /* switching duplex mode requires to disable rx and tx! */
450 au1000_hard_stop(dev
);
452 reg
= readl(&aup
->mac
->control
);
453 if (DUPLEX_FULL
== phydev
->duplex
) {
454 reg
|= MAC_FULL_DUPLEX
;
455 reg
&= ~MAC_DISABLE_RX_OWN
;
457 reg
&= ~MAC_FULL_DUPLEX
;
458 reg
|= MAC_DISABLE_RX_OWN
;
460 writel(reg
, &aup
->mac
->control
);
461 wmb(); /* drain writebuffer */
464 au1000_enable_rx_tx(dev
);
465 aup
->old_duplex
= phydev
->duplex
;
470 if (phydev
->link
!= aup
->old_link
) {
471 /* link state changed */
476 aup
->old_duplex
= -1;
479 aup
->old_link
= phydev
->link
;
483 spin_unlock_irqrestore(&aup
->lock
, flags
);
487 netdev_info(dev
, "link up (%d/%s)\n",
489 DUPLEX_FULL
== phydev
->duplex
? "Full" : "Half");
491 netdev_info(dev
, "link down\n");
495 static int au1000_mii_probe(struct net_device
*dev
)
497 struct au1000_private
*const aup
= netdev_priv(dev
);
498 struct phy_device
*phydev
= NULL
;
501 if (aup
->phy_static_config
) {
502 BUG_ON(aup
->mac_id
< 0 || aup
->mac_id
> 1);
505 phydev
= aup
->mii_bus
->phy_map
[aup
->phy_addr
];
507 netdev_info(dev
, "using PHY-less setup\n");
511 /* find the first (lowest address) PHY
512 * on the current MAC's MII bus
514 for (phy_addr
= 0; phy_addr
< PHY_MAX_ADDR
; phy_addr
++)
515 if (aup
->mii_bus
->phy_map
[phy_addr
]) {
516 phydev
= aup
->mii_bus
->phy_map
[phy_addr
];
517 if (!aup
->phy_search_highest_addr
)
518 /* break out with first one found */
522 if (aup
->phy1_search_mac0
) {
523 /* try harder to find a PHY */
524 if (!phydev
&& (aup
->mac_id
== 1)) {
525 /* no PHY found, maybe we have a dual PHY? */
526 dev_info(&dev
->dev
, ": no PHY found on MAC1, "
527 "let's see if it's attached to MAC0...\n");
529 /* find the first (lowest address) non-attached
530 * PHY on the MAC0 MII bus
532 for (phy_addr
= 0; phy_addr
< PHY_MAX_ADDR
; phy_addr
++) {
533 struct phy_device
*const tmp_phydev
=
534 aup
->mii_bus
->phy_map
[phy_addr
];
536 if (aup
->mac_id
== 1)
543 /* already claimed by MAC0 */
544 if (tmp_phydev
->attached_dev
)
548 break; /* found it */
554 netdev_err(dev
, "no PHY found\n");
558 /* now we are supposed to have a proper phydev, to attach to... */
559 BUG_ON(phydev
->attached_dev
);
561 phydev
= phy_connect(dev
, dev_name(&phydev
->dev
),
562 &au1000_adjust_link
, PHY_INTERFACE_MODE_MII
);
564 if (IS_ERR(phydev
)) {
565 netdev_err(dev
, "Could not attach to PHY\n");
566 return PTR_ERR(phydev
);
569 /* mask with MAC supported features */
570 phydev
->supported
&= (SUPPORTED_10baseT_Half
571 | SUPPORTED_10baseT_Full
572 | SUPPORTED_100baseT_Half
573 | SUPPORTED_100baseT_Full
575 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
579 phydev
->advertising
= phydev
->supported
;
583 aup
->old_duplex
= -1;
584 aup
->phy_dev
= phydev
;
586 netdev_info(dev
, "attached PHY driver [%s] "
587 "(mii_bus:phy_addr=%s, irq=%d)\n",
588 phydev
->drv
->name
, dev_name(&phydev
->dev
), phydev
->irq
);
595 * Buffer allocation/deallocation routines. The buffer descriptor returned
596 * has the virtual and dma address of a buffer suitable for
597 * both, receive and transmit operations.
599 static struct db_dest
*au1000_GetFreeDB(struct au1000_private
*aup
)
605 aup
->pDBfree
= pDB
->pnext
;
610 void au1000_ReleaseDB(struct au1000_private
*aup
, struct db_dest
*pDB
)
612 struct db_dest
*pDBfree
= aup
->pDBfree
;
614 pDBfree
->pnext
= pDB
;
618 static void au1000_reset_mac_unlocked(struct net_device
*dev
)
620 struct au1000_private
*const aup
= netdev_priv(dev
);
623 au1000_hard_stop(dev
);
625 writel(MAC_EN_CLOCK_ENABLE
, aup
->enable
);
626 wmb(); /* drain writebuffer */
628 writel(0, aup
->enable
);
629 wmb(); /* drain writebuffer */
633 for (i
= 0; i
< NUM_RX_DMA
; i
++) {
634 /* reset control bits */
635 aup
->rx_dma_ring
[i
]->buff_stat
&= ~0xf;
637 for (i
= 0; i
< NUM_TX_DMA
; i
++) {
638 /* reset control bits */
639 aup
->tx_dma_ring
[i
]->buff_stat
&= ~0xf;
642 aup
->mac_enabled
= 0;
646 static void au1000_reset_mac(struct net_device
*dev
)
648 struct au1000_private
*const aup
= netdev_priv(dev
);
651 netif_dbg(aup
, hw
, dev
, "reset mac, aup %x\n",
654 spin_lock_irqsave(&aup
->lock
, flags
);
656 au1000_reset_mac_unlocked(dev
);
658 spin_unlock_irqrestore(&aup
->lock
, flags
);
662 * Setup the receive and transmit "rings". These pointers are the addresses
663 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
664 * these are not descriptors sitting in memory.
667 au1000_setup_hw_rings(struct au1000_private
*aup
, void __iomem
*tx_base
)
671 for (i
= 0; i
< NUM_RX_DMA
; i
++) {
672 aup
->rx_dma_ring
[i
] = (struct rx_dma
*)
673 (tx_base
+ 0x100 + sizeof(struct rx_dma
) * i
);
675 for (i
= 0; i
< NUM_TX_DMA
; i
++) {
676 aup
->tx_dma_ring
[i
] = (struct tx_dma
*)
677 (tx_base
+ sizeof(struct tx_dma
) * i
);
685 static int au1000_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
687 struct au1000_private
*aup
= netdev_priv(dev
);
690 return phy_ethtool_gset(aup
->phy_dev
, cmd
);
695 static int au1000_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
697 struct au1000_private
*aup
= netdev_priv(dev
);
699 if (!capable(CAP_NET_ADMIN
))
703 return phy_ethtool_sset(aup
->phy_dev
, cmd
);
709 au1000_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
711 struct au1000_private
*aup
= netdev_priv(dev
);
713 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
714 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
715 snprintf(info
->bus_info
, sizeof(info
->bus_info
), "%s %d", DRV_NAME
,
719 static void au1000_set_msglevel(struct net_device
*dev
, u32 value
)
721 struct au1000_private
*aup
= netdev_priv(dev
);
722 aup
->msg_enable
= value
;
725 static u32
au1000_get_msglevel(struct net_device
*dev
)
727 struct au1000_private
*aup
= netdev_priv(dev
);
728 return aup
->msg_enable
;
731 static const struct ethtool_ops au1000_ethtool_ops
= {
732 .get_settings
= au1000_get_settings
,
733 .set_settings
= au1000_set_settings
,
734 .get_drvinfo
= au1000_get_drvinfo
,
735 .get_link
= ethtool_op_get_link
,
736 .get_msglevel
= au1000_get_msglevel
,
737 .set_msglevel
= au1000_set_msglevel
,
742 * Initialize the interface.
744 * When the device powers up, the clocks are disabled and the
745 * mac is in reset state. When the interface is closed, we
746 * do the same -- reset the device and disable the clocks to
747 * conserve power. Thus, whenever au1000_init() is called,
748 * the device should already be in reset state.
750 static int au1000_init(struct net_device
*dev
)
752 struct au1000_private
*aup
= netdev_priv(dev
);
757 netif_dbg(aup
, hw
, dev
, "au1000_init\n");
759 /* bring the device out of reset */
760 au1000_enable_mac(dev
, 1);
762 spin_lock_irqsave(&aup
->lock
, flags
);
764 writel(0, &aup
->mac
->control
);
765 aup
->tx_head
= (aup
->tx_dma_ring
[0]->buff_stat
& 0xC) >> 2;
766 aup
->tx_tail
= aup
->tx_head
;
767 aup
->rx_head
= (aup
->rx_dma_ring
[0]->buff_stat
& 0xC) >> 2;
769 writel(dev
->dev_addr
[5]<<8 | dev
->dev_addr
[4],
770 &aup
->mac
->mac_addr_high
);
771 writel(dev
->dev_addr
[3]<<24 | dev
->dev_addr
[2]<<16 |
772 dev
->dev_addr
[1]<<8 | dev
->dev_addr
[0],
773 &aup
->mac
->mac_addr_low
);
776 for (i
= 0; i
< NUM_RX_DMA
; i
++)
777 aup
->rx_dma_ring
[i
]->buff_stat
|= RX_DMA_ENABLE
;
779 wmb(); /* drain writebuffer */
781 control
= MAC_RX_ENABLE
| MAC_TX_ENABLE
;
782 #ifndef CONFIG_CPU_LITTLE_ENDIAN
783 control
|= MAC_BIG_ENDIAN
;
786 if (aup
->phy_dev
->link
&& (DUPLEX_FULL
== aup
->phy_dev
->duplex
))
787 control
|= MAC_FULL_DUPLEX
;
789 control
|= MAC_DISABLE_RX_OWN
;
790 } else { /* PHY-less op, assume full-duplex */
791 control
|= MAC_FULL_DUPLEX
;
794 writel(control
, &aup
->mac
->control
);
795 writel(0x8100, &aup
->mac
->vlan1_tag
); /* activate vlan support */
796 wmb(); /* drain writebuffer */
798 spin_unlock_irqrestore(&aup
->lock
, flags
);
802 static inline void au1000_update_rx_stats(struct net_device
*dev
, u32 status
)
804 struct net_device_stats
*ps
= &dev
->stats
;
807 if (status
& RX_MCAST_FRAME
)
810 if (status
& RX_ERROR
) {
812 if (status
& RX_MISSED_FRAME
)
813 ps
->rx_missed_errors
++;
814 if (status
& (RX_OVERLEN
| RX_RUNT
| RX_LEN_ERROR
))
815 ps
->rx_length_errors
++;
816 if (status
& RX_CRC_ERROR
)
818 if (status
& RX_COLL
)
821 ps
->rx_bytes
+= status
& RX_FRAME_LEN_MASK
;
826 * Au1000 receive routine.
828 static int au1000_rx(struct net_device
*dev
)
830 struct au1000_private
*aup
= netdev_priv(dev
);
833 u32 buff_stat
, status
;
837 netif_dbg(aup
, rx_status
, dev
, "au1000_rx head %d\n", aup
->rx_head
);
839 prxd
= aup
->rx_dma_ring
[aup
->rx_head
];
840 buff_stat
= prxd
->buff_stat
;
841 while (buff_stat
& RX_T_DONE
) {
842 status
= prxd
->status
;
843 pDB
= aup
->rx_db_inuse
[aup
->rx_head
];
844 au1000_update_rx_stats(dev
, status
);
845 if (!(status
& RX_ERROR
)) {
848 frmlen
= (status
& RX_FRAME_LEN_MASK
);
849 frmlen
-= 4; /* Remove FCS */
850 skb
= netdev_alloc_skb(dev
, frmlen
+ 2);
852 dev
->stats
.rx_dropped
++;
855 skb_reserve(skb
, 2); /* 16 byte IP header align */
856 skb_copy_to_linear_data(skb
,
857 (unsigned char *)pDB
->vaddr
, frmlen
);
858 skb_put(skb
, frmlen
);
859 skb
->protocol
= eth_type_trans(skb
, dev
);
860 netif_rx(skb
); /* pass the packet to upper layers */
862 if (au1000_debug
> 4) {
863 pr_err("rx_error(s):");
864 if (status
& RX_MISSED_FRAME
)
866 if (status
& RX_WDOG_TIMER
)
868 if (status
& RX_RUNT
)
870 if (status
& RX_OVERLEN
)
872 if (status
& RX_COLL
)
874 if (status
& RX_MII_ERROR
)
875 pr_cont(" mii error");
876 if (status
& RX_CRC_ERROR
)
877 pr_cont(" crc error");
878 if (status
& RX_LEN_ERROR
)
879 pr_cont(" len error");
880 if (status
& RX_U_CNTRL_FRAME
)
881 pr_cont(" u control frame");
885 prxd
->buff_stat
= (u32
)(pDB
->dma_addr
| RX_DMA_ENABLE
);
886 aup
->rx_head
= (aup
->rx_head
+ 1) & (NUM_RX_DMA
- 1);
887 wmb(); /* drain writebuffer */
889 /* next descriptor */
890 prxd
= aup
->rx_dma_ring
[aup
->rx_head
];
891 buff_stat
= prxd
->buff_stat
;
896 static void au1000_update_tx_stats(struct net_device
*dev
, u32 status
)
898 struct au1000_private
*aup
= netdev_priv(dev
);
899 struct net_device_stats
*ps
= &dev
->stats
;
901 if (status
& TX_FRAME_ABORTED
) {
902 if (!aup
->phy_dev
|| (DUPLEX_FULL
== aup
->phy_dev
->duplex
)) {
903 if (status
& (TX_JAB_TIMEOUT
| TX_UNDERRUN
)) {
904 /* any other tx errors are only valid
905 * in half duplex mode
908 ps
->tx_aborted_errors
++;
912 ps
->tx_aborted_errors
++;
913 if (status
& (TX_NO_CARRIER
| TX_LOSS_CARRIER
))
914 ps
->tx_carrier_errors
++;
920 * Called from the interrupt service routine to acknowledge
921 * the TX DONE bits. This is a must if the irq is setup as
924 static void au1000_tx_ack(struct net_device
*dev
)
926 struct au1000_private
*aup
= netdev_priv(dev
);
929 ptxd
= aup
->tx_dma_ring
[aup
->tx_tail
];
931 while (ptxd
->buff_stat
& TX_T_DONE
) {
932 au1000_update_tx_stats(dev
, ptxd
->status
);
933 ptxd
->buff_stat
&= ~TX_T_DONE
;
935 wmb(); /* drain writebuffer */
937 aup
->tx_tail
= (aup
->tx_tail
+ 1) & (NUM_TX_DMA
- 1);
938 ptxd
= aup
->tx_dma_ring
[aup
->tx_tail
];
942 netif_wake_queue(dev
);
948 * Au1000 interrupt service routine.
950 static irqreturn_t
au1000_interrupt(int irq
, void *dev_id
)
952 struct net_device
*dev
= dev_id
;
954 /* Handle RX interrupts first to minimize chance of overrun */
958 return IRQ_RETVAL(1);
961 static int au1000_open(struct net_device
*dev
)
964 struct au1000_private
*aup
= netdev_priv(dev
);
966 netif_dbg(aup
, drv
, dev
, "open: dev=%p\n", dev
);
968 retval
= request_irq(dev
->irq
, au1000_interrupt
, 0,
971 netdev_err(dev
, "unable to get IRQ %d\n", dev
->irq
);
975 retval
= au1000_init(dev
);
977 netdev_err(dev
, "error in au1000_init\n");
978 free_irq(dev
->irq
, dev
);
983 /* cause the PHY state machine to schedule a link state check */
984 aup
->phy_dev
->state
= PHY_CHANGELINK
;
985 phy_start(aup
->phy_dev
);
988 netif_start_queue(dev
);
990 netif_dbg(aup
, drv
, dev
, "open: Initialization done.\n");
995 static int au1000_close(struct net_device
*dev
)
998 struct au1000_private
*const aup
= netdev_priv(dev
);
1000 netif_dbg(aup
, drv
, dev
, "close: dev=%p\n", dev
);
1003 phy_stop(aup
->phy_dev
);
1005 spin_lock_irqsave(&aup
->lock
, flags
);
1007 au1000_reset_mac_unlocked(dev
);
1009 /* stop the device */
1010 netif_stop_queue(dev
);
1012 /* disable the interrupt */
1013 free_irq(dev
->irq
, dev
);
1014 spin_unlock_irqrestore(&aup
->lock
, flags
);
1020 * Au1000 transmit routine.
1022 static netdev_tx_t
au1000_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1024 struct au1000_private
*aup
= netdev_priv(dev
);
1025 struct net_device_stats
*ps
= &dev
->stats
;
1026 struct tx_dma
*ptxd
;
1028 struct db_dest
*pDB
;
1031 netif_dbg(aup
, tx_queued
, dev
, "tx: aup %x len=%d, data=%p, head %d\n",
1032 (unsigned)aup
, skb
->len
,
1033 skb
->data
, aup
->tx_head
);
1035 ptxd
= aup
->tx_dma_ring
[aup
->tx_head
];
1036 buff_stat
= ptxd
->buff_stat
;
1037 if (buff_stat
& TX_DMA_ENABLE
) {
1038 /* We've wrapped around and the transmitter is still busy */
1039 netif_stop_queue(dev
);
1041 return NETDEV_TX_BUSY
;
1042 } else if (buff_stat
& TX_T_DONE
) {
1043 au1000_update_tx_stats(dev
, ptxd
->status
);
1049 netif_wake_queue(dev
);
1052 pDB
= aup
->tx_db_inuse
[aup
->tx_head
];
1053 skb_copy_from_linear_data(skb
, (void *)pDB
->vaddr
, skb
->len
);
1054 if (skb
->len
< ETH_ZLEN
) {
1055 for (i
= skb
->len
; i
< ETH_ZLEN
; i
++)
1056 ((char *)pDB
->vaddr
)[i
] = 0;
1058 ptxd
->len
= ETH_ZLEN
;
1060 ptxd
->len
= skb
->len
;
1063 ps
->tx_bytes
+= ptxd
->len
;
1065 ptxd
->buff_stat
= pDB
->dma_addr
| TX_DMA_ENABLE
;
1066 wmb(); /* drain writebuffer */
1068 aup
->tx_head
= (aup
->tx_head
+ 1) & (NUM_TX_DMA
- 1);
1069 return NETDEV_TX_OK
;
1073 * The Tx ring has been full longer than the watchdog timeout
1074 * value. The transmitter must be hung?
1076 static void au1000_tx_timeout(struct net_device
*dev
)
1078 netdev_err(dev
, "au1000_tx_timeout: dev=%p\n", dev
);
1079 au1000_reset_mac(dev
);
1081 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1082 netif_wake_queue(dev
);
1085 static void au1000_multicast_list(struct net_device
*dev
)
1087 struct au1000_private
*aup
= netdev_priv(dev
);
1090 netif_dbg(aup
, drv
, dev
, "%s: flags=%x\n", __func__
, dev
->flags
);
1091 reg
= readl(&aup
->mac
->control
);
1092 if (dev
->flags
& IFF_PROMISC
) { /* Set promiscuous. */
1093 reg
|= MAC_PROMISCUOUS
;
1094 } else if ((dev
->flags
& IFF_ALLMULTI
) ||
1095 netdev_mc_count(dev
) > MULTICAST_FILTER_LIMIT
) {
1096 reg
|= MAC_PASS_ALL_MULTI
;
1097 reg
&= ~MAC_PROMISCUOUS
;
1098 netdev_info(dev
, "Pass all multicast\n");
1100 struct netdev_hw_addr
*ha
;
1101 u32 mc_filter
[2]; /* Multicast hash filter */
1103 mc_filter
[1] = mc_filter
[0] = 0;
1104 netdev_for_each_mc_addr(ha
, dev
)
1105 set_bit(ether_crc(ETH_ALEN
, ha
->addr
)>>26,
1107 writel(mc_filter
[1], &aup
->mac
->multi_hash_high
);
1108 writel(mc_filter
[0], &aup
->mac
->multi_hash_low
);
1109 reg
&= ~MAC_PROMISCUOUS
;
1110 reg
|= MAC_HASH_MODE
;
1112 writel(reg
, &aup
->mac
->control
);
1115 static int au1000_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1117 struct au1000_private
*aup
= netdev_priv(dev
);
1119 if (!netif_running(dev
))
1123 return -EINVAL
; /* PHY not controllable */
1125 return phy_mii_ioctl(aup
->phy_dev
, rq
, cmd
);
1128 static const struct net_device_ops au1000_netdev_ops
= {
1129 .ndo_open
= au1000_open
,
1130 .ndo_stop
= au1000_close
,
1131 .ndo_start_xmit
= au1000_tx
,
1132 .ndo_set_rx_mode
= au1000_multicast_list
,
1133 .ndo_do_ioctl
= au1000_ioctl
,
1134 .ndo_tx_timeout
= au1000_tx_timeout
,
1135 .ndo_set_mac_address
= eth_mac_addr
,
1136 .ndo_validate_addr
= eth_validate_addr
,
1137 .ndo_change_mtu
= eth_change_mtu
,
1140 static int au1000_probe(struct platform_device
*pdev
)
1142 struct au1000_private
*aup
= NULL
;
1143 struct au1000_eth_platform_data
*pd
;
1144 struct net_device
*dev
= NULL
;
1145 struct db_dest
*pDB
, *pDBfree
;
1146 int irq
, i
, err
= 0;
1147 struct resource
*base
, *macen
, *macdma
;
1149 base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1151 dev_err(&pdev
->dev
, "failed to retrieve base register\n");
1156 macen
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1158 dev_err(&pdev
->dev
, "failed to retrieve MAC Enable register\n");
1163 irq
= platform_get_irq(pdev
, 0);
1165 dev_err(&pdev
->dev
, "failed to retrieve IRQ\n");
1170 macdma
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
1172 dev_err(&pdev
->dev
, "failed to retrieve MACDMA registers\n");
1177 if (!request_mem_region(base
->start
, resource_size(base
),
1179 dev_err(&pdev
->dev
, "failed to request memory region for base registers\n");
1184 if (!request_mem_region(macen
->start
, resource_size(macen
),
1186 dev_err(&pdev
->dev
, "failed to request memory region for MAC enable register\n");
1191 if (!request_mem_region(macdma
->start
, resource_size(macdma
),
1193 dev_err(&pdev
->dev
, "failed to request MACDMA memory region\n");
1198 dev
= alloc_etherdev(sizeof(struct au1000_private
));
1204 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1205 platform_set_drvdata(pdev
, dev
);
1206 aup
= netdev_priv(dev
);
1208 spin_lock_init(&aup
->lock
);
1209 aup
->msg_enable
= (au1000_debug
< 4 ?
1210 AU1000_DEF_MSG_ENABLE
: au1000_debug
);
1212 /* Allocate the data buffers
1213 * Snooping works fine with eth on all au1xxx
1215 aup
->vaddr
= (u32
)dma_alloc_noncoherent(NULL
, MAX_BUF_SIZE
*
1216 (NUM_TX_BUFFS
+ NUM_RX_BUFFS
),
1219 dev_err(&pdev
->dev
, "failed to allocate data buffers\n");
1224 /* aup->mac is the base address of the MAC's registers */
1225 aup
->mac
= (struct mac_reg
*)
1226 ioremap_nocache(base
->start
, resource_size(base
));
1228 dev_err(&pdev
->dev
, "failed to ioremap MAC registers\n");
1233 /* Setup some variables for quick register address access */
1234 aup
->enable
= (u32
*)ioremap_nocache(macen
->start
,
1235 resource_size(macen
));
1237 dev_err(&pdev
->dev
, "failed to ioremap MAC enable register\n");
1241 aup
->mac_id
= pdev
->id
;
1243 aup
->macdma
= ioremap_nocache(macdma
->start
, resource_size(macdma
));
1245 dev_err(&pdev
->dev
, "failed to ioremap MACDMA registers\n");
1250 au1000_setup_hw_rings(aup
, aup
->macdma
);
1252 writel(0, aup
->enable
);
1253 aup
->mac_enabled
= 0;
1255 pd
= dev_get_platdata(&pdev
->dev
);
1257 dev_info(&pdev
->dev
, "no platform_data passed,"
1258 " PHY search on MAC0\n");
1259 aup
->phy1_search_mac0
= 1;
1261 if (is_valid_ether_addr(pd
->mac
)) {
1262 memcpy(dev
->dev_addr
, pd
->mac
, ETH_ALEN
);
1264 /* Set a random MAC since no valid provided by platform_data. */
1265 eth_hw_addr_random(dev
);
1268 aup
->phy_static_config
= pd
->phy_static_config
;
1269 aup
->phy_search_highest_addr
= pd
->phy_search_highest_addr
;
1270 aup
->phy1_search_mac0
= pd
->phy1_search_mac0
;
1271 aup
->phy_addr
= pd
->phy_addr
;
1272 aup
->phy_busid
= pd
->phy_busid
;
1273 aup
->phy_irq
= pd
->phy_irq
;
1276 if (aup
->phy_busid
&& aup
->phy_busid
> 0) {
1277 dev_err(&pdev
->dev
, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1279 goto err_mdiobus_alloc
;
1282 aup
->mii_bus
= mdiobus_alloc();
1283 if (aup
->mii_bus
== NULL
) {
1284 dev_err(&pdev
->dev
, "failed to allocate mdiobus structure\n");
1286 goto err_mdiobus_alloc
;
1289 aup
->mii_bus
->priv
= dev
;
1290 aup
->mii_bus
->read
= au1000_mdiobus_read
;
1291 aup
->mii_bus
->write
= au1000_mdiobus_write
;
1292 aup
->mii_bus
->reset
= au1000_mdiobus_reset
;
1293 aup
->mii_bus
->name
= "au1000_eth_mii";
1294 snprintf(aup
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
1295 pdev
->name
, aup
->mac_id
);
1296 aup
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1297 if (aup
->mii_bus
->irq
== NULL
) {
1302 for (i
= 0; i
< PHY_MAX_ADDR
; ++i
)
1303 aup
->mii_bus
->irq
[i
] = PHY_POLL
;
1304 /* if known, set corresponding PHY IRQs */
1305 if (aup
->phy_static_config
)
1306 if (aup
->phy_irq
&& aup
->phy_busid
== aup
->mac_id
)
1307 aup
->mii_bus
->irq
[aup
->phy_addr
] = aup
->phy_irq
;
1309 err
= mdiobus_register(aup
->mii_bus
);
1311 dev_err(&pdev
->dev
, "failed to register MDIO bus\n");
1312 goto err_mdiobus_reg
;
1315 err
= au1000_mii_probe(dev
);
1320 /* setup the data buffer descriptors and attach a buffer to each one */
1322 for (i
= 0; i
< (NUM_TX_BUFFS
+NUM_RX_BUFFS
); i
++) {
1323 pDB
->pnext
= pDBfree
;
1325 pDB
->vaddr
= (u32
*)((unsigned)aup
->vaddr
+ MAX_BUF_SIZE
*i
);
1326 pDB
->dma_addr
= (dma_addr_t
)virt_to_bus(pDB
->vaddr
);
1329 aup
->pDBfree
= pDBfree
;
1332 for (i
= 0; i
< NUM_RX_DMA
; i
++) {
1333 pDB
= au1000_GetFreeDB(aup
);
1337 aup
->rx_dma_ring
[i
]->buff_stat
= (unsigned)pDB
->dma_addr
;
1338 aup
->rx_db_inuse
[i
] = pDB
;
1342 for (i
= 0; i
< NUM_TX_DMA
; i
++) {
1343 pDB
= au1000_GetFreeDB(aup
);
1347 aup
->tx_dma_ring
[i
]->buff_stat
= (unsigned)pDB
->dma_addr
;
1348 aup
->tx_dma_ring
[i
]->len
= 0;
1349 aup
->tx_db_inuse
[i
] = pDB
;
1352 dev
->base_addr
= base
->start
;
1354 dev
->netdev_ops
= &au1000_netdev_ops
;
1355 dev
->ethtool_ops
= &au1000_ethtool_ops
;
1356 dev
->watchdog_timeo
= ETH_TX_TIMEOUT
;
1359 * The boot code uses the ethernet controller, so reset it to start
1360 * fresh. au1000_init() expects that the device is in reset state.
1362 au1000_reset_mac(dev
);
1364 err
= register_netdev(dev
);
1366 netdev_err(dev
, "Cannot register net device, aborting.\n");
1370 netdev_info(dev
, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1371 (unsigned long)base
->start
, irq
);
1373 pr_info_once("%s version %s %s\n", DRV_NAME
, DRV_VERSION
, DRV_AUTHOR
);
1378 if (aup
->mii_bus
!= NULL
)
1379 mdiobus_unregister(aup
->mii_bus
);
1381 /* here we should have a valid dev plus aup-> register addresses
1382 * so we can reset the mac properly.
1384 au1000_reset_mac(dev
);
1386 for (i
= 0; i
< NUM_RX_DMA
; i
++) {
1387 if (aup
->rx_db_inuse
[i
])
1388 au1000_ReleaseDB(aup
, aup
->rx_db_inuse
[i
]);
1390 for (i
= 0; i
< NUM_TX_DMA
; i
++) {
1391 if (aup
->tx_db_inuse
[i
])
1392 au1000_ReleaseDB(aup
, aup
->tx_db_inuse
[i
]);
1395 mdiobus_free(aup
->mii_bus
);
1397 iounmap(aup
->macdma
);
1399 iounmap(aup
->enable
);
1403 dma_free_noncoherent(NULL
, MAX_BUF_SIZE
* (NUM_TX_BUFFS
+ NUM_RX_BUFFS
),
1404 (void *)aup
->vaddr
, aup
->dma_addr
);
1408 release_mem_region(macdma
->start
, resource_size(macdma
));
1410 release_mem_region(macen
->start
, resource_size(macen
));
1412 release_mem_region(base
->start
, resource_size(base
));
1417 static int au1000_remove(struct platform_device
*pdev
)
1419 struct net_device
*dev
= platform_get_drvdata(pdev
);
1420 struct au1000_private
*aup
= netdev_priv(dev
);
1422 struct resource
*base
, *macen
;
1424 unregister_netdev(dev
);
1425 mdiobus_unregister(aup
->mii_bus
);
1426 mdiobus_free(aup
->mii_bus
);
1428 for (i
= 0; i
< NUM_RX_DMA
; i
++)
1429 if (aup
->rx_db_inuse
[i
])
1430 au1000_ReleaseDB(aup
, aup
->rx_db_inuse
[i
]);
1432 for (i
= 0; i
< NUM_TX_DMA
; i
++)
1433 if (aup
->tx_db_inuse
[i
])
1434 au1000_ReleaseDB(aup
, aup
->tx_db_inuse
[i
]);
1436 dma_free_noncoherent(NULL
, MAX_BUF_SIZE
*
1437 (NUM_TX_BUFFS
+ NUM_RX_BUFFS
),
1438 (void *)aup
->vaddr
, aup
->dma_addr
);
1440 iounmap(aup
->macdma
);
1442 iounmap(aup
->enable
);
1444 base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
1445 release_mem_region(base
->start
, resource_size(base
));
1447 base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1448 release_mem_region(base
->start
, resource_size(base
));
1450 macen
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1451 release_mem_region(macen
->start
, resource_size(macen
));
1458 static struct platform_driver au1000_eth_driver
= {
1459 .probe
= au1000_probe
,
1460 .remove
= au1000_remove
,
1462 .name
= "au1000-eth",
1466 module_platform_driver(au1000_eth_driver
);
1468 MODULE_ALIAS("platform:au1000-eth");