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net: au1000_eth: fix PHY detection
[deliverable/linux.git] / drivers / net / ethernet / amd / au1000_eth.c
1 /*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, see <http://www.gnu.org/licenses/>.
31 *
32 * ########################################################################
33 *
34 *
35 */
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38 #include <linux/capability.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/timer.h>
44 #include <linux/errno.h>
45 #include <linux/in.h>
46 #include <linux/ioport.h>
47 #include <linux/bitops.h>
48 #include <linux/slab.h>
49 #include <linux/interrupt.h>
50 #include <linux/netdevice.h>
51 #include <linux/etherdevice.h>
52 #include <linux/ethtool.h>
53 #include <linux/mii.h>
54 #include <linux/skbuff.h>
55 #include <linux/delay.h>
56 #include <linux/crc32.h>
57 #include <linux/phy.h>
58 #include <linux/platform_device.h>
59 #include <linux/cpu.h>
60 #include <linux/io.h>
61
62 #include <asm/mipsregs.h>
63 #include <asm/irq.h>
64 #include <asm/processor.h>
65
66 #include <au1000.h>
67 #include <au1xxx_eth.h>
68 #include <prom.h>
69
70 #include "au1000_eth.h"
71
72 #ifdef AU1000_ETH_DEBUG
73 static int au1000_debug = 5;
74 #else
75 static int au1000_debug = 3;
76 #endif
77
78 #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK)
81
82 #define DRV_NAME "au1000_eth"
83 #define DRV_VERSION "1.7"
84 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
85 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
86
87 MODULE_AUTHOR(DRV_AUTHOR);
88 MODULE_DESCRIPTION(DRV_DESC);
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_VERSION);
91
92 /* AU1000 MAC registers and bits */
93 #define MAC_CONTROL 0x0
94 # define MAC_RX_ENABLE (1 << 2)
95 # define MAC_TX_ENABLE (1 << 3)
96 # define MAC_DEF_CHECK (1 << 5)
97 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
98 # define MAC_AUTO_PAD (1 << 8)
99 # define MAC_DISABLE_RETRY (1 << 10)
100 # define MAC_DISABLE_BCAST (1 << 11)
101 # define MAC_LATE_COL (1 << 12)
102 # define MAC_HASH_MODE (1 << 13)
103 # define MAC_HASH_ONLY (1 << 15)
104 # define MAC_PASS_ALL (1 << 16)
105 # define MAC_INVERSE_FILTER (1 << 17)
106 # define MAC_PROMISCUOUS (1 << 18)
107 # define MAC_PASS_ALL_MULTI (1 << 19)
108 # define MAC_FULL_DUPLEX (1 << 20)
109 # define MAC_NORMAL_MODE 0
110 # define MAC_INT_LOOPBACK (1 << 21)
111 # define MAC_EXT_LOOPBACK (1 << 22)
112 # define MAC_DISABLE_RX_OWN (1 << 23)
113 # define MAC_BIG_ENDIAN (1 << 30)
114 # define MAC_RX_ALL (1 << 31)
115 #define MAC_ADDRESS_HIGH 0x4
116 #define MAC_ADDRESS_LOW 0x8
117 #define MAC_MCAST_HIGH 0xC
118 #define MAC_MCAST_LOW 0x10
119 #define MAC_MII_CNTRL 0x14
120 # define MAC_MII_BUSY (1 << 0)
121 # define MAC_MII_READ 0
122 # define MAC_MII_WRITE (1 << 1)
123 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125 #define MAC_MII_DATA 0x18
126 #define MAC_FLOW_CNTRL 0x1C
127 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
128 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129 # define MAC_PASS_CONTROL (1 << 2)
130 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
131 #define MAC_VLAN1_TAG 0x20
132 #define MAC_VLAN2_TAG 0x24
133
134 /* Ethernet Controller Enable */
135 # define MAC_EN_CLOCK_ENABLE (1 << 0)
136 # define MAC_EN_RESET0 (1 << 1)
137 # define MAC_EN_TOSS (0 << 2)
138 # define MAC_EN_CACHEABLE (1 << 3)
139 # define MAC_EN_RESET1 (1 << 4)
140 # define MAC_EN_RESET2 (1 << 5)
141 # define MAC_DMA_RESET (1 << 6)
142
143 /* Ethernet Controller DMA Channels */
144 /* offsets from MAC_TX_RING_ADDR address */
145 #define MAC_TX_BUFF0_STATUS 0x0
146 # define TX_FRAME_ABORTED (1 << 0)
147 # define TX_JAB_TIMEOUT (1 << 1)
148 # define TX_NO_CARRIER (1 << 2)
149 # define TX_LOSS_CARRIER (1 << 3)
150 # define TX_EXC_DEF (1 << 4)
151 # define TX_LATE_COLL_ABORT (1 << 5)
152 # define TX_EXC_COLL (1 << 6)
153 # define TX_UNDERRUN (1 << 7)
154 # define TX_DEFERRED (1 << 8)
155 # define TX_LATE_COLL (1 << 9)
156 # define TX_COLL_CNT_MASK (0xF << 10)
157 # define TX_PKT_RETRY (1 << 31)
158 #define MAC_TX_BUFF0_ADDR 0x4
159 # define TX_DMA_ENABLE (1 << 0)
160 # define TX_T_DONE (1 << 1)
161 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
162 #define MAC_TX_BUFF0_LEN 0x8
163 #define MAC_TX_BUFF1_STATUS 0x10
164 #define MAC_TX_BUFF1_ADDR 0x14
165 #define MAC_TX_BUFF1_LEN 0x18
166 #define MAC_TX_BUFF2_STATUS 0x20
167 #define MAC_TX_BUFF2_ADDR 0x24
168 #define MAC_TX_BUFF2_LEN 0x28
169 #define MAC_TX_BUFF3_STATUS 0x30
170 #define MAC_TX_BUFF3_ADDR 0x34
171 #define MAC_TX_BUFF3_LEN 0x38
172
173 /* offsets from MAC_RX_RING_ADDR */
174 #define MAC_RX_BUFF0_STATUS 0x0
175 # define RX_FRAME_LEN_MASK 0x3fff
176 # define RX_WDOG_TIMER (1 << 14)
177 # define RX_RUNT (1 << 15)
178 # define RX_OVERLEN (1 << 16)
179 # define RX_COLL (1 << 17)
180 # define RX_ETHER (1 << 18)
181 # define RX_MII_ERROR (1 << 19)
182 # define RX_DRIBBLING (1 << 20)
183 # define RX_CRC_ERROR (1 << 21)
184 # define RX_VLAN1 (1 << 22)
185 # define RX_VLAN2 (1 << 23)
186 # define RX_LEN_ERROR (1 << 24)
187 # define RX_CNTRL_FRAME (1 << 25)
188 # define RX_U_CNTRL_FRAME (1 << 26)
189 # define RX_MCAST_FRAME (1 << 27)
190 # define RX_BCAST_FRAME (1 << 28)
191 # define RX_FILTER_FAIL (1 << 29)
192 # define RX_PACKET_FILTER (1 << 30)
193 # define RX_MISSED_FRAME (1 << 31)
194
195 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
196 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198 #define MAC_RX_BUFF0_ADDR 0x4
199 # define RX_DMA_ENABLE (1 << 0)
200 # define RX_T_DONE (1 << 1)
201 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
202 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
203 #define MAC_RX_BUFF1_STATUS 0x10
204 #define MAC_RX_BUFF1_ADDR 0x14
205 #define MAC_RX_BUFF2_STATUS 0x20
206 #define MAC_RX_BUFF2_ADDR 0x24
207 #define MAC_RX_BUFF3_STATUS 0x30
208 #define MAC_RX_BUFF3_ADDR 0x34
209
210 /*
211 * Theory of operation
212 *
213 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214 * There are four receive and four transmit descriptors. These
215 * descriptors are not in memory; rather, they are just a set of
216 * hardware registers.
217 *
218 * Since the Au1000 has a coherent data cache, the receive and
219 * transmit buffers are allocated from the KSEG0 segment. The
220 * hardware registers, however, are still mapped at KSEG1 to
221 * make sure there's no out-of-order writes, and that all writes
222 * complete immediately.
223 */
224
225 /*
226 * board-specific configurations
227 *
228 * PHY detection algorithm
229 *
230 * If phy_static_config is undefined, the PHY setup is
231 * autodetected:
232 *
233 * mii_probe() first searches the current MAC's MII bus for a PHY,
234 * selecting the first (or last, if phy_search_highest_addr is
235 * defined) PHY address not already claimed by another netdev.
236 *
237 * If nothing was found that way when searching for the 2nd ethernet
238 * controller's PHY and phy1_search_mac0 is defined, then
239 * the first MII bus is searched as well for an unclaimed PHY; this is
240 * needed in case of a dual-PHY accessible only through the MAC0's MII
241 * bus.
242 *
243 * Finally, if no PHY is found, then the corresponding ethernet
244 * controller is not registered to the network subsystem.
245 */
246
247 /* autodetection defaults: phy1_search_mac0 */
248
249 /* static PHY setup
250 *
251 * most boards PHY setup should be detectable properly with the
252 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253 * you have a switch attached, or want to use the PHY's interrupt
254 * notification capabilities) you can provide a static PHY
255 * configuration here
256 *
257 * IRQs may only be set, if a PHY address was configured
258 * If a PHY address is given, also a bus id is required to be set
259 *
260 * ps: make sure the used irqs are configured properly in the board
261 * specific irq-map
262 */
263
264 static void au1000_enable_mac(struct net_device *dev, int force_reset)
265 {
266 unsigned long flags;
267 struct au1000_private *aup = netdev_priv(dev);
268
269 spin_lock_irqsave(&aup->lock, flags);
270
271 if (force_reset || (!aup->mac_enabled)) {
272 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
273 wmb(); /* drain writebuffer */
274 mdelay(2);
275 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
276 | MAC_EN_CLOCK_ENABLE), aup->enable);
277 wmb(); /* drain writebuffer */
278 mdelay(2);
279
280 aup->mac_enabled = 1;
281 }
282
283 spin_unlock_irqrestore(&aup->lock, flags);
284 }
285
286 /*
287 * MII operations
288 */
289 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
290 {
291 struct au1000_private *aup = netdev_priv(dev);
292 u32 *const mii_control_reg = &aup->mac->mii_control;
293 u32 *const mii_data_reg = &aup->mac->mii_data;
294 u32 timedout = 20;
295 u32 mii_control;
296
297 while (readl(mii_control_reg) & MAC_MII_BUSY) {
298 mdelay(1);
299 if (--timedout == 0) {
300 netdev_err(dev, "read_MII busy timeout!!\n");
301 return -1;
302 }
303 }
304
305 mii_control = MAC_SET_MII_SELECT_REG(reg) |
306 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
307
308 writel(mii_control, mii_control_reg);
309
310 timedout = 20;
311 while (readl(mii_control_reg) & MAC_MII_BUSY) {
312 mdelay(1);
313 if (--timedout == 0) {
314 netdev_err(dev, "mdio_read busy timeout!!\n");
315 return -1;
316 }
317 }
318 return readl(mii_data_reg);
319 }
320
321 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
322 int reg, u16 value)
323 {
324 struct au1000_private *aup = netdev_priv(dev);
325 u32 *const mii_control_reg = &aup->mac->mii_control;
326 u32 *const mii_data_reg = &aup->mac->mii_data;
327 u32 timedout = 20;
328 u32 mii_control;
329
330 while (readl(mii_control_reg) & MAC_MII_BUSY) {
331 mdelay(1);
332 if (--timedout == 0) {
333 netdev_err(dev, "mdio_write busy timeout!!\n");
334 return;
335 }
336 }
337
338 mii_control = MAC_SET_MII_SELECT_REG(reg) |
339 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
340
341 writel(value, mii_data_reg);
342 writel(mii_control, mii_control_reg);
343 }
344
345 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
346 {
347 struct net_device *const dev = bus->priv;
348
349 /* make sure the MAC associated with this
350 * mii_bus is enabled
351 */
352 au1000_enable_mac(dev, 0);
353
354 return au1000_mdio_read(dev, phy_addr, regnum);
355 }
356
357 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
358 u16 value)
359 {
360 struct net_device *const dev = bus->priv;
361
362 /* make sure the MAC associated with this
363 * mii_bus is enabled
364 */
365 au1000_enable_mac(dev, 0);
366
367 au1000_mdio_write(dev, phy_addr, regnum, value);
368 return 0;
369 }
370
371 static int au1000_mdiobus_reset(struct mii_bus *bus)
372 {
373 struct net_device *const dev = bus->priv;
374
375 /* make sure the MAC associated with this
376 * mii_bus is enabled
377 */
378 au1000_enable_mac(dev, 0);
379
380 return 0;
381 }
382
383 static void au1000_hard_stop(struct net_device *dev)
384 {
385 struct au1000_private *aup = netdev_priv(dev);
386 u32 reg;
387
388 netif_dbg(aup, drv, dev, "hard stop\n");
389
390 reg = readl(&aup->mac->control);
391 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
392 writel(reg, &aup->mac->control);
393 wmb(); /* drain writebuffer */
394 mdelay(10);
395 }
396
397 static void au1000_enable_rx_tx(struct net_device *dev)
398 {
399 struct au1000_private *aup = netdev_priv(dev);
400 u32 reg;
401
402 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
403
404 reg = readl(&aup->mac->control);
405 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
406 writel(reg, &aup->mac->control);
407 wmb(); /* drain writebuffer */
408 mdelay(10);
409 }
410
411 static void
412 au1000_adjust_link(struct net_device *dev)
413 {
414 struct au1000_private *aup = netdev_priv(dev);
415 struct phy_device *phydev = aup->phy_dev;
416 unsigned long flags;
417 u32 reg;
418
419 int status_change = 0;
420
421 BUG_ON(!aup->phy_dev);
422
423 spin_lock_irqsave(&aup->lock, flags);
424
425 if (phydev->link && (aup->old_speed != phydev->speed)) {
426 /* speed changed */
427
428 switch (phydev->speed) {
429 case SPEED_10:
430 case SPEED_100:
431 break;
432 default:
433 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
434 phydev->speed);
435 break;
436 }
437
438 aup->old_speed = phydev->speed;
439
440 status_change = 1;
441 }
442
443 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
444 /* duplex mode changed */
445
446 /* switching duplex mode requires to disable rx and tx! */
447 au1000_hard_stop(dev);
448
449 reg = readl(&aup->mac->control);
450 if (DUPLEX_FULL == phydev->duplex) {
451 reg |= MAC_FULL_DUPLEX;
452 reg &= ~MAC_DISABLE_RX_OWN;
453 } else {
454 reg &= ~MAC_FULL_DUPLEX;
455 reg |= MAC_DISABLE_RX_OWN;
456 }
457 writel(reg, &aup->mac->control);
458 wmb(); /* drain writebuffer */
459 mdelay(1);
460
461 au1000_enable_rx_tx(dev);
462 aup->old_duplex = phydev->duplex;
463
464 status_change = 1;
465 }
466
467 if (phydev->link != aup->old_link) {
468 /* link state changed */
469
470 if (!phydev->link) {
471 /* link went down */
472 aup->old_speed = 0;
473 aup->old_duplex = -1;
474 }
475
476 aup->old_link = phydev->link;
477 status_change = 1;
478 }
479
480 spin_unlock_irqrestore(&aup->lock, flags);
481
482 if (status_change) {
483 if (phydev->link)
484 netdev_info(dev, "link up (%d/%s)\n",
485 phydev->speed,
486 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
487 else
488 netdev_info(dev, "link down\n");
489 }
490 }
491
492 static int au1000_mii_probe(struct net_device *dev)
493 {
494 struct au1000_private *const aup = netdev_priv(dev);
495 struct phy_device *phydev = NULL;
496 int phy_addr;
497
498 if (aup->phy_static_config) {
499 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
500
501 if (aup->phy_addr)
502 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
503 else
504 netdev_info(dev, "using PHY-less setup\n");
505 return 0;
506 }
507
508 /* find the first (lowest address) PHY
509 * on the current MAC's MII bus
510 */
511 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
512 phydev = mdiobus_get_phy(aup->mii_bus, phy_addr);
513 if (phydev && !aup->phy_search_highest_addr)
514 /* break out with first one found */
515 break;
516 }
517
518 if (aup->phy1_search_mac0) {
519 /* try harder to find a PHY */
520 if (!phydev && (aup->mac_id == 1)) {
521 /* no PHY found, maybe we have a dual PHY? */
522 dev_info(&dev->dev, ": no PHY found on MAC1, "
523 "let's see if it's attached to MAC0...\n");
524
525 /* find the first (lowest address) non-attached
526 * PHY on the MAC0 MII bus
527 */
528 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
529 struct phy_device *const tmp_phydev =
530 mdiobus_get_phy(aup->mii_bus,
531 phy_addr);
532
533 if (aup->mac_id == 1)
534 break;
535
536 /* no PHY here... */
537 if (!tmp_phydev)
538 continue;
539
540 /* already claimed by MAC0 */
541 if (tmp_phydev->attached_dev)
542 continue;
543
544 phydev = tmp_phydev;
545 break; /* found it */
546 }
547 }
548 }
549
550 if (!phydev) {
551 netdev_err(dev, "no PHY found\n");
552 return -1;
553 }
554
555 /* now we are supposed to have a proper phydev, to attach to... */
556 BUG_ON(phydev->attached_dev);
557
558 phydev = phy_connect(dev, phydev_name(phydev),
559 &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
560
561 if (IS_ERR(phydev)) {
562 netdev_err(dev, "Could not attach to PHY\n");
563 return PTR_ERR(phydev);
564 }
565
566 /* mask with MAC supported features */
567 phydev->supported &= (SUPPORTED_10baseT_Half
568 | SUPPORTED_10baseT_Full
569 | SUPPORTED_100baseT_Half
570 | SUPPORTED_100baseT_Full
571 | SUPPORTED_Autoneg
572 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
573 | SUPPORTED_MII
574 | SUPPORTED_TP);
575
576 phydev->advertising = phydev->supported;
577
578 aup->old_link = 0;
579 aup->old_speed = 0;
580 aup->old_duplex = -1;
581 aup->phy_dev = phydev;
582
583 phy_attached_info(phydev);
584
585 return 0;
586 }
587
588
589 /*
590 * Buffer allocation/deallocation routines. The buffer descriptor returned
591 * has the virtual and dma address of a buffer suitable for
592 * both, receive and transmit operations.
593 */
594 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
595 {
596 struct db_dest *pDB;
597 pDB = aup->pDBfree;
598
599 if (pDB)
600 aup->pDBfree = pDB->pnext;
601
602 return pDB;
603 }
604
605 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
606 {
607 struct db_dest *pDBfree = aup->pDBfree;
608 if (pDBfree)
609 pDBfree->pnext = pDB;
610 aup->pDBfree = pDB;
611 }
612
613 static void au1000_reset_mac_unlocked(struct net_device *dev)
614 {
615 struct au1000_private *const aup = netdev_priv(dev);
616 int i;
617
618 au1000_hard_stop(dev);
619
620 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
621 wmb(); /* drain writebuffer */
622 mdelay(2);
623 writel(0, aup->enable);
624 wmb(); /* drain writebuffer */
625 mdelay(2);
626
627 aup->tx_full = 0;
628 for (i = 0; i < NUM_RX_DMA; i++) {
629 /* reset control bits */
630 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
631 }
632 for (i = 0; i < NUM_TX_DMA; i++) {
633 /* reset control bits */
634 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
635 }
636
637 aup->mac_enabled = 0;
638
639 }
640
641 static void au1000_reset_mac(struct net_device *dev)
642 {
643 struct au1000_private *const aup = netdev_priv(dev);
644 unsigned long flags;
645
646 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
647 (unsigned)aup);
648
649 spin_lock_irqsave(&aup->lock, flags);
650
651 au1000_reset_mac_unlocked(dev);
652
653 spin_unlock_irqrestore(&aup->lock, flags);
654 }
655
656 /*
657 * Setup the receive and transmit "rings". These pointers are the addresses
658 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
659 * these are not descriptors sitting in memory.
660 */
661 static void
662 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
663 {
664 int i;
665
666 for (i = 0; i < NUM_RX_DMA; i++) {
667 aup->rx_dma_ring[i] = (struct rx_dma *)
668 (tx_base + 0x100 + sizeof(struct rx_dma) * i);
669 }
670 for (i = 0; i < NUM_TX_DMA; i++) {
671 aup->tx_dma_ring[i] = (struct tx_dma *)
672 (tx_base + sizeof(struct tx_dma) * i);
673 }
674 }
675
676 /*
677 * ethtool operations
678 */
679
680 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
681 {
682 struct au1000_private *aup = netdev_priv(dev);
683
684 if (aup->phy_dev)
685 return phy_ethtool_gset(aup->phy_dev, cmd);
686
687 return -EINVAL;
688 }
689
690 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
691 {
692 struct au1000_private *aup = netdev_priv(dev);
693
694 if (!capable(CAP_NET_ADMIN))
695 return -EPERM;
696
697 if (aup->phy_dev)
698 return phy_ethtool_sset(aup->phy_dev, cmd);
699
700 return -EINVAL;
701 }
702
703 static void
704 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
705 {
706 struct au1000_private *aup = netdev_priv(dev);
707
708 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
709 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
710 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
711 aup->mac_id);
712 }
713
714 static void au1000_set_msglevel(struct net_device *dev, u32 value)
715 {
716 struct au1000_private *aup = netdev_priv(dev);
717 aup->msg_enable = value;
718 }
719
720 static u32 au1000_get_msglevel(struct net_device *dev)
721 {
722 struct au1000_private *aup = netdev_priv(dev);
723 return aup->msg_enable;
724 }
725
726 static const struct ethtool_ops au1000_ethtool_ops = {
727 .get_settings = au1000_get_settings,
728 .set_settings = au1000_set_settings,
729 .get_drvinfo = au1000_get_drvinfo,
730 .get_link = ethtool_op_get_link,
731 .get_msglevel = au1000_get_msglevel,
732 .set_msglevel = au1000_set_msglevel,
733 };
734
735
736 /*
737 * Initialize the interface.
738 *
739 * When the device powers up, the clocks are disabled and the
740 * mac is in reset state. When the interface is closed, we
741 * do the same -- reset the device and disable the clocks to
742 * conserve power. Thus, whenever au1000_init() is called,
743 * the device should already be in reset state.
744 */
745 static int au1000_init(struct net_device *dev)
746 {
747 struct au1000_private *aup = netdev_priv(dev);
748 unsigned long flags;
749 int i;
750 u32 control;
751
752 netif_dbg(aup, hw, dev, "au1000_init\n");
753
754 /* bring the device out of reset */
755 au1000_enable_mac(dev, 1);
756
757 spin_lock_irqsave(&aup->lock, flags);
758
759 writel(0, &aup->mac->control);
760 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
761 aup->tx_tail = aup->tx_head;
762 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
763
764 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
765 &aup->mac->mac_addr_high);
766 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
767 dev->dev_addr[1]<<8 | dev->dev_addr[0],
768 &aup->mac->mac_addr_low);
769
770
771 for (i = 0; i < NUM_RX_DMA; i++)
772 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
773
774 wmb(); /* drain writebuffer */
775
776 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
777 #ifndef CONFIG_CPU_LITTLE_ENDIAN
778 control |= MAC_BIG_ENDIAN;
779 #endif
780 if (aup->phy_dev) {
781 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
782 control |= MAC_FULL_DUPLEX;
783 else
784 control |= MAC_DISABLE_RX_OWN;
785 } else { /* PHY-less op, assume full-duplex */
786 control |= MAC_FULL_DUPLEX;
787 }
788
789 writel(control, &aup->mac->control);
790 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
791 wmb(); /* drain writebuffer */
792
793 spin_unlock_irqrestore(&aup->lock, flags);
794 return 0;
795 }
796
797 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
798 {
799 struct net_device_stats *ps = &dev->stats;
800
801 ps->rx_packets++;
802 if (status & RX_MCAST_FRAME)
803 ps->multicast++;
804
805 if (status & RX_ERROR) {
806 ps->rx_errors++;
807 if (status & RX_MISSED_FRAME)
808 ps->rx_missed_errors++;
809 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
810 ps->rx_length_errors++;
811 if (status & RX_CRC_ERROR)
812 ps->rx_crc_errors++;
813 if (status & RX_COLL)
814 ps->collisions++;
815 } else
816 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
817
818 }
819
820 /*
821 * Au1000 receive routine.
822 */
823 static int au1000_rx(struct net_device *dev)
824 {
825 struct au1000_private *aup = netdev_priv(dev);
826 struct sk_buff *skb;
827 struct rx_dma *prxd;
828 u32 buff_stat, status;
829 struct db_dest *pDB;
830 u32 frmlen;
831
832 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
833
834 prxd = aup->rx_dma_ring[aup->rx_head];
835 buff_stat = prxd->buff_stat;
836 while (buff_stat & RX_T_DONE) {
837 status = prxd->status;
838 pDB = aup->rx_db_inuse[aup->rx_head];
839 au1000_update_rx_stats(dev, status);
840 if (!(status & RX_ERROR)) {
841
842 /* good frame */
843 frmlen = (status & RX_FRAME_LEN_MASK);
844 frmlen -= 4; /* Remove FCS */
845 skb = netdev_alloc_skb(dev, frmlen + 2);
846 if (skb == NULL) {
847 dev->stats.rx_dropped++;
848 continue;
849 }
850 skb_reserve(skb, 2); /* 16 byte IP header align */
851 skb_copy_to_linear_data(skb,
852 (unsigned char *)pDB->vaddr, frmlen);
853 skb_put(skb, frmlen);
854 skb->protocol = eth_type_trans(skb, dev);
855 netif_rx(skb); /* pass the packet to upper layers */
856 } else {
857 if (au1000_debug > 4) {
858 pr_err("rx_error(s):");
859 if (status & RX_MISSED_FRAME)
860 pr_cont(" miss");
861 if (status & RX_WDOG_TIMER)
862 pr_cont(" wdog");
863 if (status & RX_RUNT)
864 pr_cont(" runt");
865 if (status & RX_OVERLEN)
866 pr_cont(" overlen");
867 if (status & RX_COLL)
868 pr_cont(" coll");
869 if (status & RX_MII_ERROR)
870 pr_cont(" mii error");
871 if (status & RX_CRC_ERROR)
872 pr_cont(" crc error");
873 if (status & RX_LEN_ERROR)
874 pr_cont(" len error");
875 if (status & RX_U_CNTRL_FRAME)
876 pr_cont(" u control frame");
877 pr_cont("\n");
878 }
879 }
880 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
881 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
882 wmb(); /* drain writebuffer */
883
884 /* next descriptor */
885 prxd = aup->rx_dma_ring[aup->rx_head];
886 buff_stat = prxd->buff_stat;
887 }
888 return 0;
889 }
890
891 static void au1000_update_tx_stats(struct net_device *dev, u32 status)
892 {
893 struct au1000_private *aup = netdev_priv(dev);
894 struct net_device_stats *ps = &dev->stats;
895
896 if (status & TX_FRAME_ABORTED) {
897 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
898 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
899 /* any other tx errors are only valid
900 * in half duplex mode
901 */
902 ps->tx_errors++;
903 ps->tx_aborted_errors++;
904 }
905 } else {
906 ps->tx_errors++;
907 ps->tx_aborted_errors++;
908 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
909 ps->tx_carrier_errors++;
910 }
911 }
912 }
913
914 /*
915 * Called from the interrupt service routine to acknowledge
916 * the TX DONE bits. This is a must if the irq is setup as
917 * edge triggered.
918 */
919 static void au1000_tx_ack(struct net_device *dev)
920 {
921 struct au1000_private *aup = netdev_priv(dev);
922 struct tx_dma *ptxd;
923
924 ptxd = aup->tx_dma_ring[aup->tx_tail];
925
926 while (ptxd->buff_stat & TX_T_DONE) {
927 au1000_update_tx_stats(dev, ptxd->status);
928 ptxd->buff_stat &= ~TX_T_DONE;
929 ptxd->len = 0;
930 wmb(); /* drain writebuffer */
931
932 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
933 ptxd = aup->tx_dma_ring[aup->tx_tail];
934
935 if (aup->tx_full) {
936 aup->tx_full = 0;
937 netif_wake_queue(dev);
938 }
939 }
940 }
941
942 /*
943 * Au1000 interrupt service routine.
944 */
945 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
946 {
947 struct net_device *dev = dev_id;
948
949 /* Handle RX interrupts first to minimize chance of overrun */
950
951 au1000_rx(dev);
952 au1000_tx_ack(dev);
953 return IRQ_RETVAL(1);
954 }
955
956 static int au1000_open(struct net_device *dev)
957 {
958 int retval;
959 struct au1000_private *aup = netdev_priv(dev);
960
961 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
962
963 retval = request_irq(dev->irq, au1000_interrupt, 0,
964 dev->name, dev);
965 if (retval) {
966 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
967 return retval;
968 }
969
970 retval = au1000_init(dev);
971 if (retval) {
972 netdev_err(dev, "error in au1000_init\n");
973 free_irq(dev->irq, dev);
974 return retval;
975 }
976
977 if (aup->phy_dev) {
978 /* cause the PHY state machine to schedule a link state check */
979 aup->phy_dev->state = PHY_CHANGELINK;
980 phy_start(aup->phy_dev);
981 }
982
983 netif_start_queue(dev);
984
985 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
986
987 return 0;
988 }
989
990 static int au1000_close(struct net_device *dev)
991 {
992 unsigned long flags;
993 struct au1000_private *const aup = netdev_priv(dev);
994
995 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
996
997 if (aup->phy_dev)
998 phy_stop(aup->phy_dev);
999
1000 spin_lock_irqsave(&aup->lock, flags);
1001
1002 au1000_reset_mac_unlocked(dev);
1003
1004 /* stop the device */
1005 netif_stop_queue(dev);
1006
1007 /* disable the interrupt */
1008 free_irq(dev->irq, dev);
1009 spin_unlock_irqrestore(&aup->lock, flags);
1010
1011 return 0;
1012 }
1013
1014 /*
1015 * Au1000 transmit routine.
1016 */
1017 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1018 {
1019 struct au1000_private *aup = netdev_priv(dev);
1020 struct net_device_stats *ps = &dev->stats;
1021 struct tx_dma *ptxd;
1022 u32 buff_stat;
1023 struct db_dest *pDB;
1024 int i;
1025
1026 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
1027 (unsigned)aup, skb->len,
1028 skb->data, aup->tx_head);
1029
1030 ptxd = aup->tx_dma_ring[aup->tx_head];
1031 buff_stat = ptxd->buff_stat;
1032 if (buff_stat & TX_DMA_ENABLE) {
1033 /* We've wrapped around and the transmitter is still busy */
1034 netif_stop_queue(dev);
1035 aup->tx_full = 1;
1036 return NETDEV_TX_BUSY;
1037 } else if (buff_stat & TX_T_DONE) {
1038 au1000_update_tx_stats(dev, ptxd->status);
1039 ptxd->len = 0;
1040 }
1041
1042 if (aup->tx_full) {
1043 aup->tx_full = 0;
1044 netif_wake_queue(dev);
1045 }
1046
1047 pDB = aup->tx_db_inuse[aup->tx_head];
1048 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1049 if (skb->len < ETH_ZLEN) {
1050 for (i = skb->len; i < ETH_ZLEN; i++)
1051 ((char *)pDB->vaddr)[i] = 0;
1052
1053 ptxd->len = ETH_ZLEN;
1054 } else
1055 ptxd->len = skb->len;
1056
1057 ps->tx_packets++;
1058 ps->tx_bytes += ptxd->len;
1059
1060 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1061 wmb(); /* drain writebuffer */
1062 dev_kfree_skb(skb);
1063 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1064 return NETDEV_TX_OK;
1065 }
1066
1067 /*
1068 * The Tx ring has been full longer than the watchdog timeout
1069 * value. The transmitter must be hung?
1070 */
1071 static void au1000_tx_timeout(struct net_device *dev)
1072 {
1073 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1074 au1000_reset_mac(dev);
1075 au1000_init(dev);
1076 netif_trans_update(dev); /* prevent tx timeout */
1077 netif_wake_queue(dev);
1078 }
1079
1080 static void au1000_multicast_list(struct net_device *dev)
1081 {
1082 struct au1000_private *aup = netdev_priv(dev);
1083 u32 reg;
1084
1085 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1086 reg = readl(&aup->mac->control);
1087 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1088 reg |= MAC_PROMISCUOUS;
1089 } else if ((dev->flags & IFF_ALLMULTI) ||
1090 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1091 reg |= MAC_PASS_ALL_MULTI;
1092 reg &= ~MAC_PROMISCUOUS;
1093 netdev_info(dev, "Pass all multicast\n");
1094 } else {
1095 struct netdev_hw_addr *ha;
1096 u32 mc_filter[2]; /* Multicast hash filter */
1097
1098 mc_filter[1] = mc_filter[0] = 0;
1099 netdev_for_each_mc_addr(ha, dev)
1100 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1101 (long *)mc_filter);
1102 writel(mc_filter[1], &aup->mac->multi_hash_high);
1103 writel(mc_filter[0], &aup->mac->multi_hash_low);
1104 reg &= ~MAC_PROMISCUOUS;
1105 reg |= MAC_HASH_MODE;
1106 }
1107 writel(reg, &aup->mac->control);
1108 }
1109
1110 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1111 {
1112 struct au1000_private *aup = netdev_priv(dev);
1113
1114 if (!netif_running(dev))
1115 return -EINVAL;
1116
1117 if (!aup->phy_dev)
1118 return -EINVAL; /* PHY not controllable */
1119
1120 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1121 }
1122
1123 static const struct net_device_ops au1000_netdev_ops = {
1124 .ndo_open = au1000_open,
1125 .ndo_stop = au1000_close,
1126 .ndo_start_xmit = au1000_tx,
1127 .ndo_set_rx_mode = au1000_multicast_list,
1128 .ndo_do_ioctl = au1000_ioctl,
1129 .ndo_tx_timeout = au1000_tx_timeout,
1130 .ndo_set_mac_address = eth_mac_addr,
1131 .ndo_validate_addr = eth_validate_addr,
1132 .ndo_change_mtu = eth_change_mtu,
1133 };
1134
1135 static int au1000_probe(struct platform_device *pdev)
1136 {
1137 struct au1000_private *aup = NULL;
1138 struct au1000_eth_platform_data *pd;
1139 struct net_device *dev = NULL;
1140 struct db_dest *pDB, *pDBfree;
1141 int irq, i, err = 0;
1142 struct resource *base, *macen, *macdma;
1143
1144 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 if (!base) {
1146 dev_err(&pdev->dev, "failed to retrieve base register\n");
1147 err = -ENODEV;
1148 goto out;
1149 }
1150
1151 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1152 if (!macen) {
1153 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1154 err = -ENODEV;
1155 goto out;
1156 }
1157
1158 irq = platform_get_irq(pdev, 0);
1159 if (irq < 0) {
1160 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1161 err = -ENODEV;
1162 goto out;
1163 }
1164
1165 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1166 if (!macdma) {
1167 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1168 err = -ENODEV;
1169 goto out;
1170 }
1171
1172 if (!request_mem_region(base->start, resource_size(base),
1173 pdev->name)) {
1174 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1175 err = -ENXIO;
1176 goto out;
1177 }
1178
1179 if (!request_mem_region(macen->start, resource_size(macen),
1180 pdev->name)) {
1181 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1182 err = -ENXIO;
1183 goto err_request;
1184 }
1185
1186 if (!request_mem_region(macdma->start, resource_size(macdma),
1187 pdev->name)) {
1188 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1189 err = -ENXIO;
1190 goto err_macdma;
1191 }
1192
1193 dev = alloc_etherdev(sizeof(struct au1000_private));
1194 if (!dev) {
1195 err = -ENOMEM;
1196 goto err_alloc;
1197 }
1198
1199 SET_NETDEV_DEV(dev, &pdev->dev);
1200 platform_set_drvdata(pdev, dev);
1201 aup = netdev_priv(dev);
1202
1203 spin_lock_init(&aup->lock);
1204 aup->msg_enable = (au1000_debug < 4 ?
1205 AU1000_DEF_MSG_ENABLE : au1000_debug);
1206
1207 /* Allocate the data buffers
1208 * Snooping works fine with eth on all au1xxx
1209 */
1210 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1211 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1212 &aup->dma_addr, 0);
1213 if (!aup->vaddr) {
1214 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1215 err = -ENOMEM;
1216 goto err_vaddr;
1217 }
1218
1219 /* aup->mac is the base address of the MAC's registers */
1220 aup->mac = (struct mac_reg *)
1221 ioremap_nocache(base->start, resource_size(base));
1222 if (!aup->mac) {
1223 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1224 err = -ENXIO;
1225 goto err_remap1;
1226 }
1227
1228 /* Setup some variables for quick register address access */
1229 aup->enable = (u32 *)ioremap_nocache(macen->start,
1230 resource_size(macen));
1231 if (!aup->enable) {
1232 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1233 err = -ENXIO;
1234 goto err_remap2;
1235 }
1236 aup->mac_id = pdev->id;
1237
1238 aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1239 if (!aup->macdma) {
1240 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1241 err = -ENXIO;
1242 goto err_remap3;
1243 }
1244
1245 au1000_setup_hw_rings(aup, aup->macdma);
1246
1247 writel(0, aup->enable);
1248 aup->mac_enabled = 0;
1249
1250 pd = dev_get_platdata(&pdev->dev);
1251 if (!pd) {
1252 dev_info(&pdev->dev, "no platform_data passed,"
1253 " PHY search on MAC0\n");
1254 aup->phy1_search_mac0 = 1;
1255 } else {
1256 if (is_valid_ether_addr(pd->mac)) {
1257 memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
1258 } else {
1259 /* Set a random MAC since no valid provided by platform_data. */
1260 eth_hw_addr_random(dev);
1261 }
1262
1263 aup->phy_static_config = pd->phy_static_config;
1264 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1265 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1266 aup->phy_addr = pd->phy_addr;
1267 aup->phy_busid = pd->phy_busid;
1268 aup->phy_irq = pd->phy_irq;
1269 }
1270
1271 if (aup->phy_busid > 0) {
1272 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1273 err = -ENODEV;
1274 goto err_mdiobus_alloc;
1275 }
1276
1277 aup->mii_bus = mdiobus_alloc();
1278 if (aup->mii_bus == NULL) {
1279 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1280 err = -ENOMEM;
1281 goto err_mdiobus_alloc;
1282 }
1283
1284 aup->mii_bus->priv = dev;
1285 aup->mii_bus->read = au1000_mdiobus_read;
1286 aup->mii_bus->write = au1000_mdiobus_write;
1287 aup->mii_bus->reset = au1000_mdiobus_reset;
1288 aup->mii_bus->name = "au1000_eth_mii";
1289 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1290 pdev->name, aup->mac_id);
1291
1292 /* if known, set corresponding PHY IRQs */
1293 if (aup->phy_static_config)
1294 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1295 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1296
1297 err = mdiobus_register(aup->mii_bus);
1298 if (err) {
1299 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1300 goto err_mdiobus_reg;
1301 }
1302
1303 err = au1000_mii_probe(dev);
1304 if (err != 0)
1305 goto err_out;
1306
1307 pDBfree = NULL;
1308 /* setup the data buffer descriptors and attach a buffer to each one */
1309 pDB = aup->db;
1310 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1311 pDB->pnext = pDBfree;
1312 pDBfree = pDB;
1313 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1314 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1315 pDB++;
1316 }
1317 aup->pDBfree = pDBfree;
1318
1319 err = -ENODEV;
1320 for (i = 0; i < NUM_RX_DMA; i++) {
1321 pDB = au1000_GetFreeDB(aup);
1322 if (!pDB)
1323 goto err_out;
1324
1325 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1326 aup->rx_db_inuse[i] = pDB;
1327 }
1328
1329 err = -ENODEV;
1330 for (i = 0; i < NUM_TX_DMA; i++) {
1331 pDB = au1000_GetFreeDB(aup);
1332 if (!pDB)
1333 goto err_out;
1334
1335 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1336 aup->tx_dma_ring[i]->len = 0;
1337 aup->tx_db_inuse[i] = pDB;
1338 }
1339
1340 dev->base_addr = base->start;
1341 dev->irq = irq;
1342 dev->netdev_ops = &au1000_netdev_ops;
1343 dev->ethtool_ops = &au1000_ethtool_ops;
1344 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1345
1346 /*
1347 * The boot code uses the ethernet controller, so reset it to start
1348 * fresh. au1000_init() expects that the device is in reset state.
1349 */
1350 au1000_reset_mac(dev);
1351
1352 err = register_netdev(dev);
1353 if (err) {
1354 netdev_err(dev, "Cannot register net device, aborting.\n");
1355 goto err_out;
1356 }
1357
1358 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1359 (unsigned long)base->start, irq);
1360
1361 pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1362
1363 return 0;
1364
1365 err_out:
1366 if (aup->mii_bus != NULL)
1367 mdiobus_unregister(aup->mii_bus);
1368
1369 /* here we should have a valid dev plus aup-> register addresses
1370 * so we can reset the mac properly.
1371 */
1372 au1000_reset_mac(dev);
1373
1374 for (i = 0; i < NUM_RX_DMA; i++) {
1375 if (aup->rx_db_inuse[i])
1376 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1377 }
1378 for (i = 0; i < NUM_TX_DMA; i++) {
1379 if (aup->tx_db_inuse[i])
1380 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1381 }
1382 err_mdiobus_reg:
1383 mdiobus_free(aup->mii_bus);
1384 err_mdiobus_alloc:
1385 iounmap(aup->macdma);
1386 err_remap3:
1387 iounmap(aup->enable);
1388 err_remap2:
1389 iounmap(aup->mac);
1390 err_remap1:
1391 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1392 (void *)aup->vaddr, aup->dma_addr);
1393 err_vaddr:
1394 free_netdev(dev);
1395 err_alloc:
1396 release_mem_region(macdma->start, resource_size(macdma));
1397 err_macdma:
1398 release_mem_region(macen->start, resource_size(macen));
1399 err_request:
1400 release_mem_region(base->start, resource_size(base));
1401 out:
1402 return err;
1403 }
1404
1405 static int au1000_remove(struct platform_device *pdev)
1406 {
1407 struct net_device *dev = platform_get_drvdata(pdev);
1408 struct au1000_private *aup = netdev_priv(dev);
1409 int i;
1410 struct resource *base, *macen;
1411
1412 unregister_netdev(dev);
1413 mdiobus_unregister(aup->mii_bus);
1414 mdiobus_free(aup->mii_bus);
1415
1416 for (i = 0; i < NUM_RX_DMA; i++)
1417 if (aup->rx_db_inuse[i])
1418 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1419
1420 for (i = 0; i < NUM_TX_DMA; i++)
1421 if (aup->tx_db_inuse[i])
1422 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1423
1424 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1425 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1426 (void *)aup->vaddr, aup->dma_addr);
1427
1428 iounmap(aup->macdma);
1429 iounmap(aup->mac);
1430 iounmap(aup->enable);
1431
1432 base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1433 release_mem_region(base->start, resource_size(base));
1434
1435 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1436 release_mem_region(base->start, resource_size(base));
1437
1438 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1439 release_mem_region(macen->start, resource_size(macen));
1440
1441 free_netdev(dev);
1442
1443 return 0;
1444 }
1445
1446 static struct platform_driver au1000_eth_driver = {
1447 .probe = au1000_probe,
1448 .remove = au1000_remove,
1449 .driver = {
1450 .name = "au1000-eth",
1451 },
1452 };
1453
1454 module_platform_driver(au1000_eth_driver);
1455
1456 MODULE_ALIAS("platform:au1000-eth");
Linux kernel - Deliverables
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