2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/phy.h>
118 #include <linux/clk.h>
119 #include <linux/bitrev.h>
120 #include <linux/crc32.h>
123 #include "xgbe-common.h"
125 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data
*pdata
,
131 DBGPR("-->xgbe_usec_to_riwt\n");
133 rate
= clk_get_rate(pdata
->sysclk
);
136 * Convert the input usec value to the watchdog timer value. Each
137 * watchdog timer value is equivalent to 256 clock cycles.
138 * Calculate the required value as:
139 * ( usec * ( system_clock_mhz / 10^6 ) / 256
141 ret
= (usec
* (rate
/ 1000000)) / 256;
143 DBGPR("<--xgbe_usec_to_riwt\n");
148 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data
*pdata
,
154 DBGPR("-->xgbe_riwt_to_usec\n");
156 rate
= clk_get_rate(pdata
->sysclk
);
159 * Convert the input watchdog timer value to the usec value. Each
160 * watchdog timer value is equivalent to 256 clock cycles.
161 * Calculate the required value as:
162 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
164 ret
= (riwt
* 256) / (rate
/ 1000000);
166 DBGPR("<--xgbe_riwt_to_usec\n");
171 static int xgbe_config_pblx8(struct xgbe_prv_data
*pdata
)
173 struct xgbe_channel
*channel
;
176 channel
= pdata
->channel
;
177 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++)
178 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_CR
, PBLX8
,
184 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data
*pdata
)
186 return XGMAC_DMA_IOREAD_BITS(pdata
->channel
, DMA_CH_TCR
, PBL
);
189 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data
*pdata
)
191 struct xgbe_channel
*channel
;
194 channel
= pdata
->channel
;
195 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
196 if (!channel
->tx_ring
)
199 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, PBL
,
206 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data
*pdata
)
208 return XGMAC_DMA_IOREAD_BITS(pdata
->channel
, DMA_CH_RCR
, PBL
);
211 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data
*pdata
)
213 struct xgbe_channel
*channel
;
216 channel
= pdata
->channel
;
217 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
218 if (!channel
->rx_ring
)
221 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RCR
, PBL
,
228 static int xgbe_config_osp_mode(struct xgbe_prv_data
*pdata
)
230 struct xgbe_channel
*channel
;
233 channel
= pdata
->channel
;
234 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
235 if (!channel
->tx_ring
)
238 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, OSP
,
245 static int xgbe_config_rsf_mode(struct xgbe_prv_data
*pdata
, unsigned int val
)
249 for (i
= 0; i
< pdata
->rx_q_count
; i
++)
250 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, RSF
, val
);
255 static int xgbe_config_tsf_mode(struct xgbe_prv_data
*pdata
, unsigned int val
)
259 for (i
= 0; i
< pdata
->tx_q_count
; i
++)
260 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_TQOMR
, TSF
, val
);
265 static int xgbe_config_rx_threshold(struct xgbe_prv_data
*pdata
,
270 for (i
= 0; i
< pdata
->rx_q_count
; i
++)
271 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, RTC
, val
);
276 static int xgbe_config_tx_threshold(struct xgbe_prv_data
*pdata
,
281 for (i
= 0; i
< pdata
->tx_q_count
; i
++)
282 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_TQOMR
, TTC
, val
);
287 static int xgbe_config_rx_coalesce(struct xgbe_prv_data
*pdata
)
289 struct xgbe_channel
*channel
;
292 channel
= pdata
->channel
;
293 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
294 if (!channel
->rx_ring
)
297 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RIWT
, RWT
,
304 static int xgbe_config_tx_coalesce(struct xgbe_prv_data
*pdata
)
309 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data
*pdata
)
311 struct xgbe_channel
*channel
;
314 channel
= pdata
->channel
;
315 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
316 if (!channel
->rx_ring
)
319 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RCR
, RBSZ
,
324 static void xgbe_config_tso_mode(struct xgbe_prv_data
*pdata
)
326 struct xgbe_channel
*channel
;
329 channel
= pdata
->channel
;
330 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
331 if (!channel
->tx_ring
)
334 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, TSE
, 1);
338 static void xgbe_config_sph_mode(struct xgbe_prv_data
*pdata
)
340 struct xgbe_channel
*channel
;
343 channel
= pdata
->channel
;
344 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
345 if (!channel
->rx_ring
)
348 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_CR
, SPH
, 1);
351 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, HDSMS
, XGBE_SPH_HDSMS_SIZE
);
354 static int xgbe_write_rss_reg(struct xgbe_prv_data
*pdata
, unsigned int type
,
355 unsigned int index
, unsigned int val
)
360 mutex_lock(&pdata
->rss_mutex
);
362 if (XGMAC_IOREAD_BITS(pdata
, MAC_RSSAR
, OB
)) {
367 XGMAC_IOWRITE(pdata
, MAC_RSSDR
, val
);
369 XGMAC_IOWRITE_BITS(pdata
, MAC_RSSAR
, RSSIA
, index
);
370 XGMAC_IOWRITE_BITS(pdata
, MAC_RSSAR
, ADDRT
, type
);
371 XGMAC_IOWRITE_BITS(pdata
, MAC_RSSAR
, CT
, 0);
372 XGMAC_IOWRITE_BITS(pdata
, MAC_RSSAR
, OB
, 1);
376 if (!XGMAC_IOREAD_BITS(pdata
, MAC_RSSAR
, OB
))
379 usleep_range(1000, 1500);
385 mutex_unlock(&pdata
->rss_mutex
);
390 static int xgbe_write_rss_hash_key(struct xgbe_prv_data
*pdata
)
392 unsigned int key_regs
= sizeof(pdata
->rss_key
) / sizeof(u32
);
393 unsigned int *key
= (unsigned int *)&pdata
->rss_key
;
397 ret
= xgbe_write_rss_reg(pdata
, XGBE_RSS_HASH_KEY_TYPE
,
406 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data
*pdata
)
411 for (i
= 0; i
< ARRAY_SIZE(pdata
->rss_table
); i
++) {
412 ret
= xgbe_write_rss_reg(pdata
,
413 XGBE_RSS_LOOKUP_TABLE_TYPE
, i
,
414 pdata
->rss_table
[i
]);
422 static int xgbe_set_rss_hash_key(struct xgbe_prv_data
*pdata
, const u8
*key
)
424 memcpy(pdata
->rss_key
, key
, sizeof(pdata
->rss_key
));
426 return xgbe_write_rss_hash_key(pdata
);
429 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data
*pdata
,
434 for (i
= 0; i
< ARRAY_SIZE(pdata
->rss_table
); i
++)
435 XGMAC_SET_BITS(pdata
->rss_table
[i
], MAC_RSSDR
, DMCH
, table
[i
]);
437 return xgbe_write_rss_lookup_table(pdata
);
440 static int xgbe_enable_rss(struct xgbe_prv_data
*pdata
)
444 if (!pdata
->hw_feat
.rss
)
447 /* Program the hash key */
448 ret
= xgbe_write_rss_hash_key(pdata
);
452 /* Program the lookup table */
453 ret
= xgbe_write_rss_lookup_table(pdata
);
457 /* Set the RSS options */
458 XGMAC_IOWRITE(pdata
, MAC_RSSCR
, pdata
->rss_options
);
461 XGMAC_IOWRITE_BITS(pdata
, MAC_RSSCR
, RSSE
, 1);
466 static int xgbe_disable_rss(struct xgbe_prv_data
*pdata
)
468 if (!pdata
->hw_feat
.rss
)
471 XGMAC_IOWRITE_BITS(pdata
, MAC_RSSCR
, RSSE
, 0);
476 static void xgbe_config_rss(struct xgbe_prv_data
*pdata
)
480 if (!pdata
->hw_feat
.rss
)
483 if (pdata
->netdev
->features
& NETIF_F_RXHASH
)
484 ret
= xgbe_enable_rss(pdata
);
486 ret
= xgbe_disable_rss(pdata
);
489 netdev_err(pdata
->netdev
,
490 "error configuring RSS, RSS disabled\n");
493 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data
*pdata
)
495 unsigned int max_q_count
, q_count
;
496 unsigned int reg
, reg_val
;
499 /* Clear MTL flow control */
500 for (i
= 0; i
< pdata
->rx_q_count
; i
++)
501 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, EHFC
, 0);
503 /* Clear MAC flow control */
504 max_q_count
= XGMAC_MAX_FLOW_CONTROL_QUEUES
;
505 q_count
= min_t(unsigned int, pdata
->tx_q_count
, max_q_count
);
507 for (i
= 0; i
< q_count
; i
++) {
508 reg_val
= XGMAC_IOREAD(pdata
, reg
);
509 XGMAC_SET_BITS(reg_val
, MAC_Q0TFCR
, TFE
, 0);
510 XGMAC_IOWRITE(pdata
, reg
, reg_val
);
512 reg
+= MAC_QTFCR_INC
;
518 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data
*pdata
)
520 unsigned int max_q_count
, q_count
;
521 unsigned int reg
, reg_val
;
524 /* Set MTL flow control */
525 for (i
= 0; i
< pdata
->rx_q_count
; i
++)
526 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, EHFC
, 1);
528 /* Set MAC flow control */
529 max_q_count
= XGMAC_MAX_FLOW_CONTROL_QUEUES
;
530 q_count
= min_t(unsigned int, pdata
->tx_q_count
, max_q_count
);
532 for (i
= 0; i
< q_count
; i
++) {
533 reg_val
= XGMAC_IOREAD(pdata
, reg
);
535 /* Enable transmit flow control */
536 XGMAC_SET_BITS(reg_val
, MAC_Q0TFCR
, TFE
, 1);
538 XGMAC_SET_BITS(reg_val
, MAC_Q0TFCR
, PT
, 0xffff);
540 XGMAC_IOWRITE(pdata
, reg
, reg_val
);
542 reg
+= MAC_QTFCR_INC
;
548 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data
*pdata
)
550 XGMAC_IOWRITE_BITS(pdata
, MAC_RFCR
, RFE
, 0);
555 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data
*pdata
)
557 XGMAC_IOWRITE_BITS(pdata
, MAC_RFCR
, RFE
, 1);
562 static int xgbe_config_tx_flow_control(struct xgbe_prv_data
*pdata
)
564 struct ieee_pfc
*pfc
= pdata
->pfc
;
566 if (pdata
->tx_pause
|| (pfc
&& pfc
->pfc_en
))
567 xgbe_enable_tx_flow_control(pdata
);
569 xgbe_disable_tx_flow_control(pdata
);
574 static int xgbe_config_rx_flow_control(struct xgbe_prv_data
*pdata
)
576 struct ieee_pfc
*pfc
= pdata
->pfc
;
578 if (pdata
->rx_pause
|| (pfc
&& pfc
->pfc_en
))
579 xgbe_enable_rx_flow_control(pdata
);
581 xgbe_disable_rx_flow_control(pdata
);
586 static void xgbe_config_flow_control(struct xgbe_prv_data
*pdata
)
588 struct ieee_pfc
*pfc
= pdata
->pfc
;
590 xgbe_config_tx_flow_control(pdata
);
591 xgbe_config_rx_flow_control(pdata
);
593 XGMAC_IOWRITE_BITS(pdata
, MAC_RFCR
, PFCE
,
594 (pfc
&& pfc
->pfc_en
) ? 1 : 0);
597 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data
*pdata
)
599 struct xgbe_channel
*channel
;
600 unsigned int dma_ch_isr
, dma_ch_ier
;
603 channel
= pdata
->channel
;
604 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
605 /* Clear all the interrupts which are set */
606 dma_ch_isr
= XGMAC_DMA_IOREAD(channel
, DMA_CH_SR
);
607 XGMAC_DMA_IOWRITE(channel
, DMA_CH_SR
, dma_ch_isr
);
609 /* Clear all interrupt enable bits */
612 /* Enable following interrupts
613 * NIE - Normal Interrupt Summary Enable
614 * AIE - Abnormal Interrupt Summary Enable
615 * FBEE - Fatal Bus Error Enable
617 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, NIE
, 1);
618 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, AIE
, 1);
619 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, FBEE
, 1);
621 if (channel
->tx_ring
) {
622 /* Enable the following Tx interrupts
623 * TIE - Transmit Interrupt Enable (unless using
624 * per channel interrupts)
626 if (!pdata
->per_channel_irq
)
627 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TIE
, 1);
629 if (channel
->rx_ring
) {
630 /* Enable following Rx interrupts
631 * RBUE - Receive Buffer Unavailable Enable
632 * RIE - Receive Interrupt Enable (unless using
633 * per channel interrupts)
635 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RBUE
, 1);
636 if (!pdata
->per_channel_irq
)
637 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RIE
, 1);
640 XGMAC_DMA_IOWRITE(channel
, DMA_CH_IER
, dma_ch_ier
);
644 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data
*pdata
)
646 unsigned int mtl_q_isr
;
647 unsigned int q_count
, i
;
649 q_count
= max(pdata
->hw_feat
.tx_q_cnt
, pdata
->hw_feat
.rx_q_cnt
);
650 for (i
= 0; i
< q_count
; i
++) {
651 /* Clear all the interrupts which are set */
652 mtl_q_isr
= XGMAC_MTL_IOREAD(pdata
, i
, MTL_Q_ISR
);
653 XGMAC_MTL_IOWRITE(pdata
, i
, MTL_Q_ISR
, mtl_q_isr
);
655 /* No MTL interrupts to be enabled */
656 XGMAC_MTL_IOWRITE(pdata
, i
, MTL_Q_IER
, 0);
660 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data
*pdata
)
662 unsigned int mac_ier
= 0;
664 /* Enable Timestamp interrupt */
665 XGMAC_SET_BITS(mac_ier
, MAC_IER
, TSIE
, 1);
667 XGMAC_IOWRITE(pdata
, MAC_IER
, mac_ier
);
669 /* Enable all counter interrupts */
670 XGMAC_IOWRITE_BITS(pdata
, MMC_RIER
, ALL_INTERRUPTS
, 0xffffffff);
671 XGMAC_IOWRITE_BITS(pdata
, MMC_TIER
, ALL_INTERRUPTS
, 0xffffffff);
674 static int xgbe_set_gmii_speed(struct xgbe_prv_data
*pdata
)
676 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, SS
, 0x3);
681 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data
*pdata
)
683 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, SS
, 0x2);
688 static int xgbe_set_xgmii_speed(struct xgbe_prv_data
*pdata
)
690 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, SS
, 0);
695 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data
*pdata
,
698 unsigned int val
= enable
? 1 : 0;
700 if (XGMAC_IOREAD_BITS(pdata
, MAC_PFR
, PR
) == val
)
703 DBGPR(" %s promiscuous mode\n", enable
? "entering" : "leaving");
704 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, PR
, val
);
709 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data
*pdata
,
712 unsigned int val
= enable
? 1 : 0;
714 if (XGMAC_IOREAD_BITS(pdata
, MAC_PFR
, PM
) == val
)
717 DBGPR(" %s allmulti mode\n", enable
? "entering" : "leaving");
718 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, PM
, val
);
723 static void xgbe_set_mac_reg(struct xgbe_prv_data
*pdata
,
724 struct netdev_hw_addr
*ha
, unsigned int *mac_reg
)
726 unsigned int mac_addr_hi
, mac_addr_lo
;
733 mac_addr
= (u8
*)&mac_addr_lo
;
734 mac_addr
[0] = ha
->addr
[0];
735 mac_addr
[1] = ha
->addr
[1];
736 mac_addr
[2] = ha
->addr
[2];
737 mac_addr
[3] = ha
->addr
[3];
738 mac_addr
= (u8
*)&mac_addr_hi
;
739 mac_addr
[0] = ha
->addr
[4];
740 mac_addr
[1] = ha
->addr
[5];
742 DBGPR(" adding mac address %pM at 0x%04x\n", ha
->addr
,
745 XGMAC_SET_BITS(mac_addr_hi
, MAC_MACA1HR
, AE
, 1);
748 XGMAC_IOWRITE(pdata
, *mac_reg
, mac_addr_hi
);
749 *mac_reg
+= MAC_MACA_INC
;
750 XGMAC_IOWRITE(pdata
, *mac_reg
, mac_addr_lo
);
751 *mac_reg
+= MAC_MACA_INC
;
754 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data
*pdata
)
756 struct net_device
*netdev
= pdata
->netdev
;
757 struct netdev_hw_addr
*ha
;
758 unsigned int mac_reg
;
759 unsigned int addn_macs
;
761 mac_reg
= MAC_MACA1HR
;
762 addn_macs
= pdata
->hw_feat
.addn_mac
;
764 if (netdev_uc_count(netdev
) > addn_macs
) {
765 xgbe_set_promiscuous_mode(pdata
, 1);
767 netdev_for_each_uc_addr(ha
, netdev
) {
768 xgbe_set_mac_reg(pdata
, ha
, &mac_reg
);
772 if (netdev_mc_count(netdev
) > addn_macs
) {
773 xgbe_set_all_multicast_mode(pdata
, 1);
775 netdev_for_each_mc_addr(ha
, netdev
) {
776 xgbe_set_mac_reg(pdata
, ha
, &mac_reg
);
782 /* Clear remaining additional MAC address entries */
784 xgbe_set_mac_reg(pdata
, NULL
, &mac_reg
);
787 static void xgbe_set_mac_hash_table(struct xgbe_prv_data
*pdata
)
789 struct net_device
*netdev
= pdata
->netdev
;
790 struct netdev_hw_addr
*ha
;
791 unsigned int hash_reg
;
792 unsigned int hash_table_shift
, hash_table_count
;
793 u32 hash_table
[XGBE_MAC_HASH_TABLE_SIZE
];
797 hash_table_shift
= 26 - (pdata
->hw_feat
.hash_table_size
>> 7);
798 hash_table_count
= pdata
->hw_feat
.hash_table_size
/ 32;
799 memset(hash_table
, 0, sizeof(hash_table
));
801 /* Build the MAC Hash Table register values */
802 netdev_for_each_uc_addr(ha
, netdev
) {
803 crc
= bitrev32(~crc32_le(~0, ha
->addr
, ETH_ALEN
));
804 crc
>>= hash_table_shift
;
805 hash_table
[crc
>> 5] |= (1 << (crc
& 0x1f));
808 netdev_for_each_mc_addr(ha
, netdev
) {
809 crc
= bitrev32(~crc32_le(~0, ha
->addr
, ETH_ALEN
));
810 crc
>>= hash_table_shift
;
811 hash_table
[crc
>> 5] |= (1 << (crc
& 0x1f));
814 /* Set the MAC Hash Table registers */
816 for (i
= 0; i
< hash_table_count
; i
++) {
817 XGMAC_IOWRITE(pdata
, hash_reg
, hash_table
[i
]);
818 hash_reg
+= MAC_HTR_INC
;
822 static int xgbe_add_mac_addresses(struct xgbe_prv_data
*pdata
)
824 if (pdata
->hw_feat
.hash_table_size
)
825 xgbe_set_mac_hash_table(pdata
);
827 xgbe_set_mac_addn_addrs(pdata
);
832 static int xgbe_set_mac_address(struct xgbe_prv_data
*pdata
, u8
*addr
)
834 unsigned int mac_addr_hi
, mac_addr_lo
;
836 mac_addr_hi
= (addr
[5] << 8) | (addr
[4] << 0);
837 mac_addr_lo
= (addr
[3] << 24) | (addr
[2] << 16) |
838 (addr
[1] << 8) | (addr
[0] << 0);
840 XGMAC_IOWRITE(pdata
, MAC_MACA0HR
, mac_addr_hi
);
841 XGMAC_IOWRITE(pdata
, MAC_MACA0LR
, mac_addr_lo
);
846 static int xgbe_read_mmd_regs(struct xgbe_prv_data
*pdata
, int prtad
,
849 unsigned int mmd_address
;
852 if (mmd_reg
& MII_ADDR_C45
)
853 mmd_address
= mmd_reg
& ~MII_ADDR_C45
;
855 mmd_address
= (pdata
->mdio_mmd
<< 16) | (mmd_reg
& 0xffff);
857 /* The PCS registers are accessed using mmio. The underlying APB3
858 * management interface uses indirect addressing to access the MMD
859 * register sets. This requires accessing of the PCS register in two
860 * phases, an address phase and a data phase.
862 * The mmio interface is based on 32-bit offsets and values. All
863 * register offsets must therefore be adjusted by left shifting the
864 * offset 2 bits and reading 32 bits of data.
866 mutex_lock(&pdata
->xpcs_mutex
);
867 XPCS_IOWRITE(pdata
, PCS_MMD_SELECT
<< 2, mmd_address
>> 8);
868 mmd_data
= XPCS_IOREAD(pdata
, (mmd_address
& 0xff) << 2);
869 mutex_unlock(&pdata
->xpcs_mutex
);
874 static void xgbe_write_mmd_regs(struct xgbe_prv_data
*pdata
, int prtad
,
875 int mmd_reg
, int mmd_data
)
877 unsigned int mmd_address
;
879 if (mmd_reg
& MII_ADDR_C45
)
880 mmd_address
= mmd_reg
& ~MII_ADDR_C45
;
882 mmd_address
= (pdata
->mdio_mmd
<< 16) | (mmd_reg
& 0xffff);
884 /* The PCS registers are accessed using mmio. The underlying APB3
885 * management interface uses indirect addressing to access the MMD
886 * register sets. This requires accessing of the PCS register in two
887 * phases, an address phase and a data phase.
889 * The mmio interface is based on 32-bit offsets and values. All
890 * register offsets must therefore be adjusted by left shifting the
891 * offset 2 bits and reading 32 bits of data.
893 mutex_lock(&pdata
->xpcs_mutex
);
894 XPCS_IOWRITE(pdata
, PCS_MMD_SELECT
<< 2, mmd_address
>> 8);
895 XPCS_IOWRITE(pdata
, (mmd_address
& 0xff) << 2, mmd_data
);
896 mutex_unlock(&pdata
->xpcs_mutex
);
899 static int xgbe_tx_complete(struct xgbe_ring_desc
*rdesc
)
901 return !XGMAC_GET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, OWN
);
904 static int xgbe_disable_rx_csum(struct xgbe_prv_data
*pdata
)
906 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, IPC
, 0);
911 static int xgbe_enable_rx_csum(struct xgbe_prv_data
*pdata
)
913 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, IPC
, 1);
918 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data
*pdata
)
920 /* Put the VLAN tag in the Rx descriptor */
921 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, EVLRXS
, 1);
923 /* Don't check the VLAN type */
924 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, DOVLTC
, 1);
926 /* Check only C-TAG (0x8100) packets */
927 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, ERSVLM
, 0);
929 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
930 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, ESVL
, 0);
932 /* Enable VLAN tag stripping */
933 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, EVLS
, 0x3);
938 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data
*pdata
)
940 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, EVLS
, 0);
945 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data
*pdata
)
947 /* Enable VLAN filtering */
948 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, VTFE
, 1);
950 /* Enable VLAN Hash Table filtering */
951 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, VTHM
, 1);
953 /* Disable VLAN tag inverse matching */
954 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, VTIM
, 0);
956 /* Only filter on the lower 12-bits of the VLAN tag */
957 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, ETV
, 1);
959 /* In order for the VLAN Hash Table filtering to be effective,
960 * the VLAN tag identifier in the VLAN Tag Register must not
961 * be zero. Set the VLAN tag identifier to "1" to enable the
962 * VLAN Hash Table filtering. This implies that a VLAN tag of
963 * 1 will always pass filtering.
965 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANTR
, VL
, 1);
970 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data
*pdata
)
972 /* Disable VLAN filtering */
973 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, VTFE
, 0);
979 #define CRCPOLY_LE 0xedb88320
981 static u32
xgbe_vid_crc32_le(__le16 vid_le
)
983 u32 poly
= CRCPOLY_LE
;
986 unsigned char *data
= (unsigned char *)&vid_le
;
987 unsigned char data_byte
= 0;
990 bits
= get_bitmask_order(VLAN_VID_MASK
);
991 for (i
= 0; i
< bits
; i
++) {
993 data_byte
= data
[i
/ 8];
995 temp
= ((crc
& 1) ^ data_byte
) & 1;
1006 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data
*pdata
)
1011 u16 vlan_hash_table
= 0;
1013 /* Generate the VLAN Hash Table value */
1014 for_each_set_bit(vid
, pdata
->active_vlans
, VLAN_N_VID
) {
1015 /* Get the CRC32 value of the VLAN ID */
1016 vid_le
= cpu_to_le16(vid
);
1017 crc
= bitrev32(~xgbe_vid_crc32_le(vid_le
)) >> 28;
1019 vlan_hash_table
|= (1 << crc
);
1022 /* Set the VLAN Hash Table filtering register */
1023 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANHTR
, VLHT
, vlan_hash_table
);
1028 static void xgbe_tx_desc_reset(struct xgbe_ring_data
*rdata
)
1030 struct xgbe_ring_desc
*rdesc
= rdata
->rdesc
;
1032 /* Reset the Tx descriptor
1033 * Set buffer 1 (lo) address to zero
1034 * Set buffer 1 (hi) address to zero
1035 * Reset all other control bits (IC, TTSE, B2L & B1L)
1036 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1043 /* Make sure ownership is written to the descriptor */
1047 static void xgbe_tx_desc_init(struct xgbe_channel
*channel
)
1049 struct xgbe_ring
*ring
= channel
->tx_ring
;
1050 struct xgbe_ring_data
*rdata
;
1052 int start_index
= ring
->cur
;
1054 DBGPR("-->tx_desc_init\n");
1056 /* Initialze all descriptors */
1057 for (i
= 0; i
< ring
->rdesc_count
; i
++) {
1058 rdata
= XGBE_GET_DESC_DATA(ring
, i
);
1060 /* Initialize Tx descriptor */
1061 xgbe_tx_desc_reset(rdata
);
1064 /* Update the total number of Tx descriptors */
1065 XGMAC_DMA_IOWRITE(channel
, DMA_CH_TDRLR
, ring
->rdesc_count
- 1);
1067 /* Update the starting address of descriptor ring */
1068 rdata
= XGBE_GET_DESC_DATA(ring
, start_index
);
1069 XGMAC_DMA_IOWRITE(channel
, DMA_CH_TDLR_HI
,
1070 upper_32_bits(rdata
->rdesc_dma
));
1071 XGMAC_DMA_IOWRITE(channel
, DMA_CH_TDLR_LO
,
1072 lower_32_bits(rdata
->rdesc_dma
));
1074 DBGPR("<--tx_desc_init\n");
1077 static void xgbe_rx_desc_reset(struct xgbe_ring_data
*rdata
)
1079 struct xgbe_ring_desc
*rdesc
= rdata
->rdesc
;
1081 /* Reset the Rx descriptor
1082 * Set buffer 1 (lo) address to header dma address (lo)
1083 * Set buffer 1 (hi) address to header dma address (hi)
1084 * Set buffer 2 (lo) address to buffer dma address (lo)
1085 * Set buffer 2 (hi) address to buffer dma address (hi) and
1086 * set control bits OWN and INTE
1088 rdesc
->desc0
= cpu_to_le32(lower_32_bits(rdata
->rx
.hdr
.dma
));
1089 rdesc
->desc1
= cpu_to_le32(upper_32_bits(rdata
->rx
.hdr
.dma
));
1090 rdesc
->desc2
= cpu_to_le32(lower_32_bits(rdata
->rx
.buf
.dma
));
1091 rdesc
->desc3
= cpu_to_le32(upper_32_bits(rdata
->rx
.buf
.dma
));
1093 XGMAC_SET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, INTE
,
1094 rdata
->interrupt
? 1 : 0);
1096 /* Since the Rx DMA engine is likely running, make sure everything
1097 * is written to the descriptor(s) before setting the OWN bit
1098 * for the descriptor
1102 XGMAC_SET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, OWN
, 1);
1104 /* Make sure ownership is written to the descriptor */
1108 static void xgbe_rx_desc_init(struct xgbe_channel
*channel
)
1110 struct xgbe_prv_data
*pdata
= channel
->pdata
;
1111 struct xgbe_ring
*ring
= channel
->rx_ring
;
1112 struct xgbe_ring_data
*rdata
;
1113 unsigned int start_index
= ring
->cur
;
1114 unsigned int rx_coalesce
, rx_frames
;
1117 DBGPR("-->rx_desc_init\n");
1119 rx_coalesce
= (pdata
->rx_riwt
|| pdata
->rx_frames
) ? 1 : 0;
1120 rx_frames
= pdata
->rx_frames
;
1122 /* Initialize all descriptors */
1123 for (i
= 0; i
< ring
->rdesc_count
; i
++) {
1124 rdata
= XGBE_GET_DESC_DATA(ring
, i
);
1126 /* Set interrupt on completion bit as appropriate */
1127 if (rx_coalesce
&& (!rx_frames
|| ((i
+ 1) % rx_frames
)))
1128 rdata
->interrupt
= 0;
1130 rdata
->interrupt
= 1;
1132 /* Initialize Rx descriptor */
1133 xgbe_rx_desc_reset(rdata
);
1136 /* Update the total number of Rx descriptors */
1137 XGMAC_DMA_IOWRITE(channel
, DMA_CH_RDRLR
, ring
->rdesc_count
- 1);
1139 /* Update the starting address of descriptor ring */
1140 rdata
= XGBE_GET_DESC_DATA(ring
, start_index
);
1141 XGMAC_DMA_IOWRITE(channel
, DMA_CH_RDLR_HI
,
1142 upper_32_bits(rdata
->rdesc_dma
));
1143 XGMAC_DMA_IOWRITE(channel
, DMA_CH_RDLR_LO
,
1144 lower_32_bits(rdata
->rdesc_dma
));
1146 /* Update the Rx Descriptor Tail Pointer */
1147 rdata
= XGBE_GET_DESC_DATA(ring
, start_index
+ ring
->rdesc_count
- 1);
1148 XGMAC_DMA_IOWRITE(channel
, DMA_CH_RDTR_LO
,
1149 lower_32_bits(rdata
->rdesc_dma
));
1151 DBGPR("<--rx_desc_init\n");
1154 static void xgbe_update_tstamp_addend(struct xgbe_prv_data
*pdata
,
1155 unsigned int addend
)
1157 /* Set the addend register value and tell the device */
1158 XGMAC_IOWRITE(pdata
, MAC_TSAR
, addend
);
1159 XGMAC_IOWRITE_BITS(pdata
, MAC_TSCR
, TSADDREG
, 1);
1161 /* Wait for addend update to complete */
1162 while (XGMAC_IOREAD_BITS(pdata
, MAC_TSCR
, TSADDREG
))
1166 static void xgbe_set_tstamp_time(struct xgbe_prv_data
*pdata
, unsigned int sec
,
1169 /* Set the time values and tell the device */
1170 XGMAC_IOWRITE(pdata
, MAC_STSUR
, sec
);
1171 XGMAC_IOWRITE(pdata
, MAC_STNUR
, nsec
);
1172 XGMAC_IOWRITE_BITS(pdata
, MAC_TSCR
, TSINIT
, 1);
1174 /* Wait for time update to complete */
1175 while (XGMAC_IOREAD_BITS(pdata
, MAC_TSCR
, TSINIT
))
1179 static u64
xgbe_get_tstamp_time(struct xgbe_prv_data
*pdata
)
1183 nsec
= XGMAC_IOREAD(pdata
, MAC_STSR
);
1184 nsec
*= NSEC_PER_SEC
;
1185 nsec
+= XGMAC_IOREAD(pdata
, MAC_STNR
);
1190 static u64
xgbe_get_tx_tstamp(struct xgbe_prv_data
*pdata
)
1192 unsigned int tx_snr
;
1195 tx_snr
= XGMAC_IOREAD(pdata
, MAC_TXSNR
);
1196 if (XGMAC_GET_BITS(tx_snr
, MAC_TXSNR
, TXTSSTSMIS
))
1199 nsec
= XGMAC_IOREAD(pdata
, MAC_TXSSR
);
1200 nsec
*= NSEC_PER_SEC
;
1206 static void xgbe_get_rx_tstamp(struct xgbe_packet_data
*packet
,
1207 struct xgbe_ring_desc
*rdesc
)
1211 if (XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_CONTEXT_DESC3
, TSA
) &&
1212 !XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_CONTEXT_DESC3
, TSD
)) {
1213 nsec
= le32_to_cpu(rdesc
->desc1
);
1215 nsec
|= le32_to_cpu(rdesc
->desc0
);
1216 if (nsec
!= 0xffffffffffffffffULL
) {
1217 packet
->rx_tstamp
= nsec
;
1218 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1224 static int xgbe_config_tstamp(struct xgbe_prv_data
*pdata
,
1225 unsigned int mac_tscr
)
1227 /* Set one nano-second accuracy */
1228 XGMAC_SET_BITS(mac_tscr
, MAC_TSCR
, TSCTRLSSR
, 1);
1230 /* Set fine timestamp update */
1231 XGMAC_SET_BITS(mac_tscr
, MAC_TSCR
, TSCFUPDT
, 1);
1233 /* Overwrite earlier timestamps */
1234 XGMAC_SET_BITS(mac_tscr
, MAC_TSCR
, TXTSSTSM
, 1);
1236 XGMAC_IOWRITE(pdata
, MAC_TSCR
, mac_tscr
);
1238 /* Exit if timestamping is not enabled */
1239 if (!XGMAC_GET_BITS(mac_tscr
, MAC_TSCR
, TSENA
))
1242 /* Initialize time registers */
1243 XGMAC_IOWRITE_BITS(pdata
, MAC_SSIR
, SSINC
, XGBE_TSTAMP_SSINC
);
1244 XGMAC_IOWRITE_BITS(pdata
, MAC_SSIR
, SNSINC
, XGBE_TSTAMP_SNSINC
);
1245 xgbe_update_tstamp_addend(pdata
, pdata
->tstamp_addend
);
1246 xgbe_set_tstamp_time(pdata
, 0, 0);
1248 /* Initialize the timecounter */
1249 timecounter_init(&pdata
->tstamp_tc
, &pdata
->tstamp_cc
,
1250 ktime_to_ns(ktime_get_real()));
1255 static void xgbe_config_dcb_tc(struct xgbe_prv_data
*pdata
)
1257 struct ieee_ets
*ets
= pdata
->ets
;
1258 unsigned int total_weight
, min_weight
, weight
;
1264 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1265 * traffic class is using ETS algorithm)
1267 XGMAC_IOWRITE_BITS(pdata
, MTL_OMR
, ETSALG
, MTL_ETSALG_DWRR
);
1269 /* Set Traffic Class algorithms */
1270 total_weight
= pdata
->netdev
->mtu
* pdata
->hw_feat
.tc_cnt
;
1271 min_weight
= total_weight
/ 100;
1275 for (i
= 0; i
< pdata
->hw_feat
.tc_cnt
; i
++) {
1276 switch (ets
->tc_tsa
[i
]) {
1277 case IEEE_8021QAZ_TSA_STRICT
:
1278 DBGPR(" TC%u using SP\n", i
);
1279 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_TC_ETSCR
, TSA
,
1282 case IEEE_8021QAZ_TSA_ETS
:
1283 weight
= total_weight
* ets
->tc_tx_bw
[i
] / 100;
1284 weight
= clamp(weight
, min_weight
, total_weight
);
1286 DBGPR(" TC%u using DWRR (weight %u)\n", i
, weight
);
1287 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_TC_ETSCR
, TSA
,
1289 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_TC_QWR
, QW
,
1296 static void xgbe_config_dcb_pfc(struct xgbe_prv_data
*pdata
)
1298 struct ieee_pfc
*pfc
= pdata
->pfc
;
1299 struct ieee_ets
*ets
= pdata
->ets
;
1300 unsigned int mask
, reg
, reg_val
;
1301 unsigned int tc
, prio
;
1306 for (tc
= 0; tc
< pdata
->hw_feat
.tc_cnt
; tc
++) {
1308 for (prio
= 0; prio
< IEEE_8021QAZ_MAX_TCS
; prio
++) {
1309 if ((pfc
->pfc_en
& (1 << prio
)) &&
1310 (ets
->prio_tc
[prio
] == tc
))
1311 mask
|= (1 << prio
);
1315 DBGPR(" TC%u PFC mask=%#x\n", tc
, mask
);
1316 reg
= MTL_TCPM0R
+ (MTL_TCPM_INC
* (tc
/ MTL_TCPM_TC_PER_REG
));
1317 reg_val
= XGMAC_IOREAD(pdata
, reg
);
1319 reg_val
&= ~(0xff << ((tc
% MTL_TCPM_TC_PER_REG
) << 3));
1320 reg_val
|= (mask
<< ((tc
% MTL_TCPM_TC_PER_REG
) << 3));
1322 XGMAC_IOWRITE(pdata
, reg
, reg_val
);
1325 xgbe_config_flow_control(pdata
);
1328 static void xgbe_dev_xmit(struct xgbe_channel
*channel
)
1330 struct xgbe_prv_data
*pdata
= channel
->pdata
;
1331 struct xgbe_ring
*ring
= channel
->tx_ring
;
1332 struct xgbe_ring_data
*rdata
;
1333 struct xgbe_ring_desc
*rdesc
;
1334 struct xgbe_packet_data
*packet
= &ring
->packet_data
;
1335 unsigned int csum
, tso
, vlan
;
1336 unsigned int tso_context
, vlan_context
;
1337 unsigned int tx_coalesce
, tx_frames
;
1338 int start_index
= ring
->cur
;
1341 DBGPR("-->xgbe_dev_xmit\n");
1343 csum
= XGMAC_GET_BITS(packet
->attributes
, TX_PACKET_ATTRIBUTES
,
1345 tso
= XGMAC_GET_BITS(packet
->attributes
, TX_PACKET_ATTRIBUTES
,
1347 vlan
= XGMAC_GET_BITS(packet
->attributes
, TX_PACKET_ATTRIBUTES
,
1350 if (tso
&& (packet
->mss
!= ring
->tx
.cur_mss
))
1355 if (vlan
&& (packet
->vlan_ctag
!= ring
->tx
.cur_vlan_ctag
))
1360 tx_coalesce
= (pdata
->tx_usecs
|| pdata
->tx_frames
) ? 1 : 0;
1361 tx_frames
= pdata
->tx_frames
;
1362 if (tx_coalesce
&& !channel
->tx_timer_active
)
1363 ring
->coalesce_count
= 0;
1365 rdata
= XGBE_GET_DESC_DATA(ring
, ring
->cur
);
1366 rdesc
= rdata
->rdesc
;
1368 /* Create a context descriptor if this is a TSO packet */
1369 if (tso_context
|| vlan_context
) {
1371 DBGPR(" TSO context descriptor, mss=%u\n",
1374 /* Set the MSS size */
1375 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_CONTEXT_DESC2
,
1378 /* Mark it as a CONTEXT descriptor */
1379 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_CONTEXT_DESC3
,
1382 /* Indicate this descriptor contains the MSS */
1383 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_CONTEXT_DESC3
,
1386 ring
->tx
.cur_mss
= packet
->mss
;
1390 DBGPR(" VLAN context descriptor, ctag=%u\n",
1393 /* Mark it as a CONTEXT descriptor */
1394 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_CONTEXT_DESC3
,
1397 /* Set the VLAN tag */
1398 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_CONTEXT_DESC3
,
1399 VT
, packet
->vlan_ctag
);
1401 /* Indicate this descriptor contains the VLAN tag */
1402 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_CONTEXT_DESC3
,
1405 ring
->tx
.cur_vlan_ctag
= packet
->vlan_ctag
;
1409 rdata
= XGBE_GET_DESC_DATA(ring
, ring
->cur
);
1410 rdesc
= rdata
->rdesc
;
1413 /* Update buffer address (for TSO this is the header) */
1414 rdesc
->desc0
= cpu_to_le32(lower_32_bits(rdata
->skb_dma
));
1415 rdesc
->desc1
= cpu_to_le32(upper_32_bits(rdata
->skb_dma
));
1417 /* Update the buffer length */
1418 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, HL_B1L
,
1419 rdata
->skb_dma_len
);
1421 /* VLAN tag insertion check */
1423 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, VTIR
,
1424 TX_NORMAL_DESC2_VLAN_INSERT
);
1426 /* Timestamp enablement check */
1427 if (XGMAC_GET_BITS(packet
->attributes
, TX_PACKET_ATTRIBUTES
, PTP
))
1428 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, TTSE
, 1);
1430 /* Set IC bit based on Tx coalescing settings */
1431 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, IC
, 1);
1432 if (tx_coalesce
&& (!tx_frames
||
1433 (++ring
->coalesce_count
% tx_frames
)))
1435 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, IC
, 0);
1437 /* Mark it as First Descriptor */
1438 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, FD
, 1);
1440 /* Mark it as a NORMAL descriptor */
1441 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, CTXT
, 0);
1443 /* Set OWN bit if not the first descriptor */
1444 if (ring
->cur
!= start_index
)
1445 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, OWN
, 1);
1449 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, TSE
, 1);
1450 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, TCPPL
,
1451 packet
->tcp_payload_len
);
1452 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, TCPHDRLEN
,
1453 packet
->tcp_header_len
/ 4);
1455 /* Enable CRC and Pad Insertion */
1456 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, CPC
, 0);
1458 /* Enable HW CSUM */
1460 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
,
1463 /* Set the total length to be transmitted */
1464 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, FL
,
1468 for (i
= ring
->cur
- start_index
+ 1; i
< packet
->rdesc_count
; i
++) {
1470 rdata
= XGBE_GET_DESC_DATA(ring
, ring
->cur
);
1471 rdesc
= rdata
->rdesc
;
1473 /* Update buffer address */
1474 rdesc
->desc0
= cpu_to_le32(lower_32_bits(rdata
->skb_dma
));
1475 rdesc
->desc1
= cpu_to_le32(upper_32_bits(rdata
->skb_dma
));
1477 /* Update the buffer length */
1478 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, HL_B1L
,
1479 rdata
->skb_dma_len
);
1481 /* Set IC bit based on Tx coalescing settings */
1482 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, IC
, 1);
1483 if (tx_coalesce
&& (!tx_frames
||
1484 (++ring
->coalesce_count
% tx_frames
)))
1486 XGMAC_SET_BITS_LE(rdesc
->desc2
, TX_NORMAL_DESC2
, IC
, 0);
1489 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, OWN
, 1);
1491 /* Mark it as NORMAL descriptor */
1492 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, CTXT
, 0);
1494 /* Enable HW CSUM */
1496 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
,
1500 /* Set LAST bit for the last descriptor */
1501 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, LD
, 1);
1503 /* In case the Tx DMA engine is running, make sure everything
1504 * is written to the descriptor(s) before setting the OWN bit
1505 * for the first descriptor
1509 /* Set OWN bit for the first descriptor */
1510 rdata
= XGBE_GET_DESC_DATA(ring
, start_index
);
1511 rdesc
= rdata
->rdesc
;
1512 XGMAC_SET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, OWN
, 1);
1514 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1515 xgbe_dump_tx_desc(ring
, start_index
, packet
->rdesc_count
, 1);
1518 /* Make sure ownership is written to the descriptor */
1521 /* Issue a poll command to Tx DMA by writing address
1522 * of next immediate free descriptor */
1524 rdata
= XGBE_GET_DESC_DATA(ring
, ring
->cur
);
1525 XGMAC_DMA_IOWRITE(channel
, DMA_CH_TDTR_LO
,
1526 lower_32_bits(rdata
->rdesc_dma
));
1528 /* Start the Tx coalescing timer */
1529 if (tx_coalesce
&& !channel
->tx_timer_active
) {
1530 channel
->tx_timer_active
= 1;
1531 hrtimer_start(&channel
->tx_timer
,
1532 ktime_set(0, pdata
->tx_usecs
* NSEC_PER_USEC
),
1536 DBGPR(" %s: descriptors %u to %u written\n",
1537 channel
->name
, start_index
& (ring
->rdesc_count
- 1),
1538 (ring
->cur
- 1) & (ring
->rdesc_count
- 1));
1540 DBGPR("<--xgbe_dev_xmit\n");
1543 static int xgbe_dev_read(struct xgbe_channel
*channel
)
1545 struct xgbe_ring
*ring
= channel
->rx_ring
;
1546 struct xgbe_ring_data
*rdata
;
1547 struct xgbe_ring_desc
*rdesc
;
1548 struct xgbe_packet_data
*packet
= &ring
->packet_data
;
1549 struct net_device
*netdev
= channel
->pdata
->netdev
;
1550 unsigned int err
, etlt
, l34t
;
1552 DBGPR("-->xgbe_dev_read: cur = %d\n", ring
->cur
);
1554 rdata
= XGBE_GET_DESC_DATA(ring
, ring
->cur
);
1555 rdesc
= rdata
->rdesc
;
1557 /* Check for data availability */
1558 if (XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, OWN
))
1561 /* Make sure descriptor fields are read after reading the OWN bit */
1564 #ifdef XGMAC_ENABLE_RX_DESC_DUMP
1565 xgbe_dump_rx_desc(ring
, rdesc
, ring
->cur
);
1568 if (XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, CTXT
)) {
1569 /* Timestamp Context Descriptor */
1570 xgbe_get_rx_tstamp(packet
, rdesc
);
1572 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1574 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1579 /* Normal Descriptor, be sure Context Descriptor bit is off */
1580 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
, CONTEXT
, 0);
1582 /* Indicate if a Context Descriptor is next */
1583 if (XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, CDA
))
1584 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1587 /* Get the header length */
1588 if (XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, FD
))
1589 rdata
->rx
.hdr_len
= XGMAC_GET_BITS_LE(rdesc
->desc2
,
1590 RX_NORMAL_DESC2
, HL
);
1592 /* Get the RSS hash */
1593 if (XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, RSV
)) {
1594 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1597 packet
->rss_hash
= le32_to_cpu(rdesc
->desc1
);
1599 l34t
= XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, L34T
);
1601 case RX_DESC3_L34T_IPV4_TCP
:
1602 case RX_DESC3_L34T_IPV4_UDP
:
1603 case RX_DESC3_L34T_IPV6_TCP
:
1604 case RX_DESC3_L34T_IPV6_UDP
:
1605 packet
->rss_hash_type
= PKT_HASH_TYPE_L4
;
1608 packet
->rss_hash_type
= PKT_HASH_TYPE_L3
;
1612 /* Get the packet length */
1613 rdata
->rx
.len
= XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, PL
);
1615 if (!XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, LD
)) {
1616 /* Not all the data has been transferred for this packet */
1617 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1622 /* This is the last of the data for this packet */
1623 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1626 /* Set checksum done indicator as appropriate */
1627 if (channel
->pdata
->netdev
->features
& NETIF_F_RXCSUM
)
1628 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1631 /* Check for errors (only valid in last descriptor) */
1632 err
= XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, ES
);
1633 etlt
= XGMAC_GET_BITS_LE(rdesc
->desc3
, RX_NORMAL_DESC3
, ETLT
);
1634 DBGPR(" err=%u, etlt=%#x\n", err
, etlt
);
1636 if (!err
|| !etlt
) {
1637 /* No error if err is 0 or etlt is 0 */
1638 if ((etlt
== 0x09) &&
1639 (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1640 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1642 packet
->vlan_ctag
= XGMAC_GET_BITS_LE(rdesc
->desc0
,
1645 DBGPR(" vlan-ctag=0x%04x\n", packet
->vlan_ctag
);
1648 if ((etlt
== 0x05) || (etlt
== 0x06))
1649 XGMAC_SET_BITS(packet
->attributes
, RX_PACKET_ATTRIBUTES
,
1652 XGMAC_SET_BITS(packet
->errors
, RX_PACKET_ERRORS
,
1656 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel
->name
,
1657 ring
->cur
& (ring
->rdesc_count
- 1), ring
->cur
);
1662 static int xgbe_is_context_desc(struct xgbe_ring_desc
*rdesc
)
1664 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1665 return XGMAC_GET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, CTXT
);
1668 static int xgbe_is_last_desc(struct xgbe_ring_desc
*rdesc
)
1670 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1671 return XGMAC_GET_BITS_LE(rdesc
->desc3
, TX_NORMAL_DESC3
, LD
);
1674 static int xgbe_enable_int(struct xgbe_channel
*channel
,
1675 enum xgbe_int int_id
)
1677 unsigned int dma_ch_ier
;
1679 dma_ch_ier
= XGMAC_DMA_IOREAD(channel
, DMA_CH_IER
);
1682 case XGMAC_INT_DMA_CH_SR_TI
:
1683 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TIE
, 1);
1685 case XGMAC_INT_DMA_CH_SR_TPS
:
1686 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TXSE
, 1);
1688 case XGMAC_INT_DMA_CH_SR_TBU
:
1689 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TBUE
, 1);
1691 case XGMAC_INT_DMA_CH_SR_RI
:
1692 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RIE
, 1);
1694 case XGMAC_INT_DMA_CH_SR_RBU
:
1695 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RBUE
, 1);
1697 case XGMAC_INT_DMA_CH_SR_RPS
:
1698 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RSE
, 1);
1700 case XGMAC_INT_DMA_CH_SR_TI_RI
:
1701 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TIE
, 1);
1702 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RIE
, 1);
1704 case XGMAC_INT_DMA_CH_SR_FBE
:
1705 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, FBEE
, 1);
1707 case XGMAC_INT_DMA_ALL
:
1708 dma_ch_ier
|= channel
->saved_ier
;
1714 XGMAC_DMA_IOWRITE(channel
, DMA_CH_IER
, dma_ch_ier
);
1719 static int xgbe_disable_int(struct xgbe_channel
*channel
,
1720 enum xgbe_int int_id
)
1722 unsigned int dma_ch_ier
;
1724 dma_ch_ier
= XGMAC_DMA_IOREAD(channel
, DMA_CH_IER
);
1727 case XGMAC_INT_DMA_CH_SR_TI
:
1728 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TIE
, 0);
1730 case XGMAC_INT_DMA_CH_SR_TPS
:
1731 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TXSE
, 0);
1733 case XGMAC_INT_DMA_CH_SR_TBU
:
1734 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TBUE
, 0);
1736 case XGMAC_INT_DMA_CH_SR_RI
:
1737 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RIE
, 0);
1739 case XGMAC_INT_DMA_CH_SR_RBU
:
1740 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RBUE
, 0);
1742 case XGMAC_INT_DMA_CH_SR_RPS
:
1743 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RSE
, 0);
1745 case XGMAC_INT_DMA_CH_SR_TI_RI
:
1746 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, TIE
, 0);
1747 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, RIE
, 0);
1749 case XGMAC_INT_DMA_CH_SR_FBE
:
1750 XGMAC_SET_BITS(dma_ch_ier
, DMA_CH_IER
, FBEE
, 0);
1752 case XGMAC_INT_DMA_ALL
:
1753 channel
->saved_ier
= dma_ch_ier
& XGBE_DMA_INTERRUPT_MASK
;
1754 dma_ch_ier
&= ~XGBE_DMA_INTERRUPT_MASK
;
1760 XGMAC_DMA_IOWRITE(channel
, DMA_CH_IER
, dma_ch_ier
);
1765 static int xgbe_exit(struct xgbe_prv_data
*pdata
)
1767 unsigned int count
= 2000;
1769 DBGPR("-->xgbe_exit\n");
1771 /* Issue a software reset */
1772 XGMAC_IOWRITE_BITS(pdata
, DMA_MR
, SWR
, 1);
1773 usleep_range(10, 15);
1775 /* Poll Until Poll Condition */
1776 while (count
-- && XGMAC_IOREAD_BITS(pdata
, DMA_MR
, SWR
))
1777 usleep_range(500, 600);
1782 DBGPR("<--xgbe_exit\n");
1787 static int xgbe_flush_tx_queues(struct xgbe_prv_data
*pdata
)
1789 unsigned int i
, count
;
1791 if (XGMAC_GET_BITS(pdata
->hw_feat
.version
, MAC_VR
, SNPSVER
) < 0x21)
1794 for (i
= 0; i
< pdata
->tx_q_count
; i
++)
1795 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_TQOMR
, FTQ
, 1);
1797 /* Poll Until Poll Condition */
1798 for (i
= 0; i
< pdata
->tx_q_count
; i
++) {
1800 while (count
-- && XGMAC_MTL_IOREAD_BITS(pdata
, i
,
1802 usleep_range(500, 600);
1811 static void xgbe_config_dma_bus(struct xgbe_prv_data
*pdata
)
1813 /* Set enhanced addressing mode */
1814 XGMAC_IOWRITE_BITS(pdata
, DMA_SBMR
, EAME
, 1);
1816 /* Set the System Bus mode */
1817 XGMAC_IOWRITE_BITS(pdata
, DMA_SBMR
, UNDEF
, 1);
1818 XGMAC_IOWRITE_BITS(pdata
, DMA_SBMR
, BLEN_256
, 1);
1821 static void xgbe_config_dma_cache(struct xgbe_prv_data
*pdata
)
1823 unsigned int arcache
, awcache
;
1826 XGMAC_SET_BITS(arcache
, DMA_AXIARCR
, DRC
, pdata
->arcache
);
1827 XGMAC_SET_BITS(arcache
, DMA_AXIARCR
, DRD
, pdata
->axdomain
);
1828 XGMAC_SET_BITS(arcache
, DMA_AXIARCR
, TEC
, pdata
->arcache
);
1829 XGMAC_SET_BITS(arcache
, DMA_AXIARCR
, TED
, pdata
->axdomain
);
1830 XGMAC_SET_BITS(arcache
, DMA_AXIARCR
, THC
, pdata
->arcache
);
1831 XGMAC_SET_BITS(arcache
, DMA_AXIARCR
, THD
, pdata
->axdomain
);
1832 XGMAC_IOWRITE(pdata
, DMA_AXIARCR
, arcache
);
1835 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, DWC
, pdata
->awcache
);
1836 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, DWD
, pdata
->axdomain
);
1837 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, RPC
, pdata
->awcache
);
1838 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, RPD
, pdata
->axdomain
);
1839 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, RHC
, pdata
->awcache
);
1840 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, RHD
, pdata
->axdomain
);
1841 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, TDC
, pdata
->awcache
);
1842 XGMAC_SET_BITS(awcache
, DMA_AXIAWCR
, TDD
, pdata
->axdomain
);
1843 XGMAC_IOWRITE(pdata
, DMA_AXIAWCR
, awcache
);
1846 static void xgbe_config_mtl_mode(struct xgbe_prv_data
*pdata
)
1850 /* Set Tx to weighted round robin scheduling algorithm */
1851 XGMAC_IOWRITE_BITS(pdata
, MTL_OMR
, ETSALG
, MTL_ETSALG_WRR
);
1853 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1854 for (i
= 0; i
< pdata
->hw_feat
.tc_cnt
; i
++) {
1855 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_TC_ETSCR
, TSA
,
1857 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_TC_QWR
, QW
, 1);
1860 /* Set Rx to strict priority algorithm */
1861 XGMAC_IOWRITE_BITS(pdata
, MTL_OMR
, RAA
, MTL_RAA_SP
);
1864 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size
,
1865 unsigned int queue_count
)
1867 unsigned int q_fifo_size
= 0;
1868 enum xgbe_mtl_fifo_size p_fifo
= XGMAC_MTL_FIFO_SIZE_256
;
1870 /* Calculate Tx/Rx fifo share per queue */
1871 switch (fifo_size
) {
1873 q_fifo_size
= XGBE_FIFO_SIZE_B(128);
1876 q_fifo_size
= XGBE_FIFO_SIZE_B(256);
1879 q_fifo_size
= XGBE_FIFO_SIZE_B(512);
1882 q_fifo_size
= XGBE_FIFO_SIZE_KB(1);
1885 q_fifo_size
= XGBE_FIFO_SIZE_KB(2);
1888 q_fifo_size
= XGBE_FIFO_SIZE_KB(4);
1891 q_fifo_size
= XGBE_FIFO_SIZE_KB(8);
1894 q_fifo_size
= XGBE_FIFO_SIZE_KB(16);
1897 q_fifo_size
= XGBE_FIFO_SIZE_KB(32);
1900 q_fifo_size
= XGBE_FIFO_SIZE_KB(64);
1903 q_fifo_size
= XGBE_FIFO_SIZE_KB(128);
1906 q_fifo_size
= XGBE_FIFO_SIZE_KB(256);
1910 /* The configured value is not the actual amount of fifo RAM */
1911 q_fifo_size
= min_t(unsigned int, XGBE_FIFO_MAX
, q_fifo_size
);
1913 q_fifo_size
= q_fifo_size
/ queue_count
;
1915 /* Set the queue fifo size programmable value */
1916 if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(256))
1917 p_fifo
= XGMAC_MTL_FIFO_SIZE_256K
;
1918 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(128))
1919 p_fifo
= XGMAC_MTL_FIFO_SIZE_128K
;
1920 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(64))
1921 p_fifo
= XGMAC_MTL_FIFO_SIZE_64K
;
1922 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(32))
1923 p_fifo
= XGMAC_MTL_FIFO_SIZE_32K
;
1924 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(16))
1925 p_fifo
= XGMAC_MTL_FIFO_SIZE_16K
;
1926 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(8))
1927 p_fifo
= XGMAC_MTL_FIFO_SIZE_8K
;
1928 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(4))
1929 p_fifo
= XGMAC_MTL_FIFO_SIZE_4K
;
1930 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(2))
1931 p_fifo
= XGMAC_MTL_FIFO_SIZE_2K
;
1932 else if (q_fifo_size
>= XGBE_FIFO_SIZE_KB(1))
1933 p_fifo
= XGMAC_MTL_FIFO_SIZE_1K
;
1934 else if (q_fifo_size
>= XGBE_FIFO_SIZE_B(512))
1935 p_fifo
= XGMAC_MTL_FIFO_SIZE_512
;
1936 else if (q_fifo_size
>= XGBE_FIFO_SIZE_B(256))
1937 p_fifo
= XGMAC_MTL_FIFO_SIZE_256
;
1942 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data
*pdata
)
1944 enum xgbe_mtl_fifo_size fifo_size
;
1947 fifo_size
= xgbe_calculate_per_queue_fifo(pdata
->hw_feat
.tx_fifo_size
,
1950 for (i
= 0; i
< pdata
->tx_q_count
; i
++)
1951 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_TQOMR
, TQS
, fifo_size
);
1953 netdev_notice(pdata
->netdev
, "%d Tx queues, %d byte fifo per queue\n",
1954 pdata
->tx_q_count
, ((fifo_size
+ 1) * 256));
1957 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data
*pdata
)
1959 enum xgbe_mtl_fifo_size fifo_size
;
1962 fifo_size
= xgbe_calculate_per_queue_fifo(pdata
->hw_feat
.rx_fifo_size
,
1965 for (i
= 0; i
< pdata
->rx_q_count
; i
++)
1966 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, RQS
, fifo_size
);
1968 netdev_notice(pdata
->netdev
, "%d Rx queues, %d byte fifo per queue\n",
1969 pdata
->rx_q_count
, ((fifo_size
+ 1) * 256));
1972 static void xgbe_config_queue_mapping(struct xgbe_prv_data
*pdata
)
1974 unsigned int qptc
, qptc_extra
, queue
;
1975 unsigned int prio_queues
;
1976 unsigned int ppq
, ppq_extra
, prio
;
1978 unsigned int i
, j
, reg
, reg_val
;
1980 /* Map the MTL Tx Queues to Traffic Classes
1981 * Note: Tx Queues >= Traffic Classes
1983 qptc
= pdata
->tx_q_count
/ pdata
->hw_feat
.tc_cnt
;
1984 qptc_extra
= pdata
->tx_q_count
% pdata
->hw_feat
.tc_cnt
;
1986 for (i
= 0, queue
= 0; i
< pdata
->hw_feat
.tc_cnt
; i
++) {
1987 for (j
= 0; j
< qptc
; j
++) {
1988 DBGPR(" TXq%u mapped to TC%u\n", queue
, i
);
1989 XGMAC_MTL_IOWRITE_BITS(pdata
, queue
, MTL_Q_TQOMR
,
1991 pdata
->q2tc_map
[queue
++] = i
;
1994 if (i
< qptc_extra
) {
1995 DBGPR(" TXq%u mapped to TC%u\n", queue
, i
);
1996 XGMAC_MTL_IOWRITE_BITS(pdata
, queue
, MTL_Q_TQOMR
,
1998 pdata
->q2tc_map
[queue
++] = i
;
2002 /* Map the 8 VLAN priority values to available MTL Rx queues */
2003 prio_queues
= min_t(unsigned int, IEEE_8021QAZ_MAX_TCS
,
2005 ppq
= IEEE_8021QAZ_MAX_TCS
/ prio_queues
;
2006 ppq_extra
= IEEE_8021QAZ_MAX_TCS
% prio_queues
;
2010 for (i
= 0, prio
= 0; i
< prio_queues
;) {
2012 for (j
= 0; j
< ppq
; j
++) {
2013 DBGPR(" PRIO%u mapped to RXq%u\n", prio
, i
);
2014 mask
|= (1 << prio
);
2015 pdata
->prio2q_map
[prio
++] = i
;
2018 if (i
< ppq_extra
) {
2019 DBGPR(" PRIO%u mapped to RXq%u\n", prio
, i
);
2020 mask
|= (1 << prio
);
2021 pdata
->prio2q_map
[prio
++] = i
;
2024 reg_val
|= (mask
<< ((i
++ % MAC_RQC2_Q_PER_REG
) << 3));
2026 if ((i
% MAC_RQC2_Q_PER_REG
) && (i
!= prio_queues
))
2029 XGMAC_IOWRITE(pdata
, reg
, reg_val
);
2030 reg
+= MAC_RQC2_INC
;
2034 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2037 for (i
= 0; i
< pdata
->rx_q_count
;) {
2038 reg_val
|= (0x80 << ((i
++ % MTL_RQDCM_Q_PER_REG
) << 3));
2040 if ((i
% MTL_RQDCM_Q_PER_REG
) && (i
!= pdata
->rx_q_count
))
2043 XGMAC_IOWRITE(pdata
, reg
, reg_val
);
2045 reg
+= MTL_RQDCM_INC
;
2050 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data
*pdata
)
2054 for (i
= 0; i
< pdata
->rx_q_count
; i
++) {
2055 /* Activate flow control when less than 4k left in fifo */
2056 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, RFA
, 2);
2058 /* De-activate flow control when more than 6k left in fifo */
2059 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_RQOMR
, RFD
, 4);
2063 static void xgbe_config_mac_address(struct xgbe_prv_data
*pdata
)
2065 xgbe_set_mac_address(pdata
, pdata
->netdev
->dev_addr
);
2067 /* Filtering is done using perfect filtering and hash filtering */
2068 if (pdata
->hw_feat
.hash_table_size
) {
2069 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, HPF
, 1);
2070 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, HUC
, 1);
2071 XGMAC_IOWRITE_BITS(pdata
, MAC_PFR
, HMC
, 1);
2075 static void xgbe_config_jumbo_enable(struct xgbe_prv_data
*pdata
)
2079 val
= (pdata
->netdev
->mtu
> XGMAC_STD_PACKET_MTU
) ? 1 : 0;
2081 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, JE
, val
);
2084 static void xgbe_config_checksum_offload(struct xgbe_prv_data
*pdata
)
2086 if (pdata
->netdev
->features
& NETIF_F_RXCSUM
)
2087 xgbe_enable_rx_csum(pdata
);
2089 xgbe_disable_rx_csum(pdata
);
2092 static void xgbe_config_vlan_support(struct xgbe_prv_data
*pdata
)
2094 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2095 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANIR
, CSVL
, 0);
2096 XGMAC_IOWRITE_BITS(pdata
, MAC_VLANIR
, VLTI
, 1);
2098 /* Set the current VLAN Hash Table register value */
2099 xgbe_update_vlan_hash_table(pdata
);
2101 if (pdata
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
)
2102 xgbe_enable_rx_vlan_filtering(pdata
);
2104 xgbe_disable_rx_vlan_filtering(pdata
);
2106 if (pdata
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
2107 xgbe_enable_rx_vlan_stripping(pdata
);
2109 xgbe_disable_rx_vlan_stripping(pdata
);
2112 static u64
xgbe_mmc_read(struct xgbe_prv_data
*pdata
, unsigned int reg_lo
)
2118 /* These registers are always 64 bit */
2119 case MMC_TXOCTETCOUNT_GB_LO
:
2120 case MMC_TXOCTETCOUNT_G_LO
:
2121 case MMC_RXOCTETCOUNT_GB_LO
:
2122 case MMC_RXOCTETCOUNT_G_LO
:
2130 val
= XGMAC_IOREAD(pdata
, reg_lo
);
2133 val
|= ((u64
)XGMAC_IOREAD(pdata
, reg_lo
+ 4) << 32);
2138 static void xgbe_tx_mmc_int(struct xgbe_prv_data
*pdata
)
2140 struct xgbe_mmc_stats
*stats
= &pdata
->mmc_stats
;
2141 unsigned int mmc_isr
= XGMAC_IOREAD(pdata
, MMC_TISR
);
2143 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXOCTETCOUNT_GB
))
2144 stats
->txoctetcount_gb
+=
2145 xgbe_mmc_read(pdata
, MMC_TXOCTETCOUNT_GB_LO
);
2147 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXFRAMECOUNT_GB
))
2148 stats
->txframecount_gb
+=
2149 xgbe_mmc_read(pdata
, MMC_TXFRAMECOUNT_GB_LO
);
2151 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXBROADCASTFRAMES_G
))
2152 stats
->txbroadcastframes_g
+=
2153 xgbe_mmc_read(pdata
, MMC_TXBROADCASTFRAMES_G_LO
);
2155 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXMULTICASTFRAMES_G
))
2156 stats
->txmulticastframes_g
+=
2157 xgbe_mmc_read(pdata
, MMC_TXMULTICASTFRAMES_G_LO
);
2159 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TX64OCTETS_GB
))
2160 stats
->tx64octets_gb
+=
2161 xgbe_mmc_read(pdata
, MMC_TX64OCTETS_GB_LO
);
2163 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TX65TO127OCTETS_GB
))
2164 stats
->tx65to127octets_gb
+=
2165 xgbe_mmc_read(pdata
, MMC_TX65TO127OCTETS_GB_LO
);
2167 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TX128TO255OCTETS_GB
))
2168 stats
->tx128to255octets_gb
+=
2169 xgbe_mmc_read(pdata
, MMC_TX128TO255OCTETS_GB_LO
);
2171 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TX256TO511OCTETS_GB
))
2172 stats
->tx256to511octets_gb
+=
2173 xgbe_mmc_read(pdata
, MMC_TX256TO511OCTETS_GB_LO
);
2175 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TX512TO1023OCTETS_GB
))
2176 stats
->tx512to1023octets_gb
+=
2177 xgbe_mmc_read(pdata
, MMC_TX512TO1023OCTETS_GB_LO
);
2179 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TX1024TOMAXOCTETS_GB
))
2180 stats
->tx1024tomaxoctets_gb
+=
2181 xgbe_mmc_read(pdata
, MMC_TX1024TOMAXOCTETS_GB_LO
);
2183 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXUNICASTFRAMES_GB
))
2184 stats
->txunicastframes_gb
+=
2185 xgbe_mmc_read(pdata
, MMC_TXUNICASTFRAMES_GB_LO
);
2187 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXMULTICASTFRAMES_GB
))
2188 stats
->txmulticastframes_gb
+=
2189 xgbe_mmc_read(pdata
, MMC_TXMULTICASTFRAMES_GB_LO
);
2191 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXBROADCASTFRAMES_GB
))
2192 stats
->txbroadcastframes_g
+=
2193 xgbe_mmc_read(pdata
, MMC_TXBROADCASTFRAMES_GB_LO
);
2195 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXUNDERFLOWERROR
))
2196 stats
->txunderflowerror
+=
2197 xgbe_mmc_read(pdata
, MMC_TXUNDERFLOWERROR_LO
);
2199 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXOCTETCOUNT_G
))
2200 stats
->txoctetcount_g
+=
2201 xgbe_mmc_read(pdata
, MMC_TXOCTETCOUNT_G_LO
);
2203 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXFRAMECOUNT_G
))
2204 stats
->txframecount_g
+=
2205 xgbe_mmc_read(pdata
, MMC_TXFRAMECOUNT_G_LO
);
2207 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXPAUSEFRAMES
))
2208 stats
->txpauseframes
+=
2209 xgbe_mmc_read(pdata
, MMC_TXPAUSEFRAMES_LO
);
2211 if (XGMAC_GET_BITS(mmc_isr
, MMC_TISR
, TXVLANFRAMES_G
))
2212 stats
->txvlanframes_g
+=
2213 xgbe_mmc_read(pdata
, MMC_TXVLANFRAMES_G_LO
);
2216 static void xgbe_rx_mmc_int(struct xgbe_prv_data
*pdata
)
2218 struct xgbe_mmc_stats
*stats
= &pdata
->mmc_stats
;
2219 unsigned int mmc_isr
= XGMAC_IOREAD(pdata
, MMC_RISR
);
2221 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXFRAMECOUNT_GB
))
2222 stats
->rxframecount_gb
+=
2223 xgbe_mmc_read(pdata
, MMC_RXFRAMECOUNT_GB_LO
);
2225 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXOCTETCOUNT_GB
))
2226 stats
->rxoctetcount_gb
+=
2227 xgbe_mmc_read(pdata
, MMC_RXOCTETCOUNT_GB_LO
);
2229 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXOCTETCOUNT_G
))
2230 stats
->rxoctetcount_g
+=
2231 xgbe_mmc_read(pdata
, MMC_RXOCTETCOUNT_G_LO
);
2233 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXBROADCASTFRAMES_G
))
2234 stats
->rxbroadcastframes_g
+=
2235 xgbe_mmc_read(pdata
, MMC_RXBROADCASTFRAMES_G_LO
);
2237 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXMULTICASTFRAMES_G
))
2238 stats
->rxmulticastframes_g
+=
2239 xgbe_mmc_read(pdata
, MMC_RXMULTICASTFRAMES_G_LO
);
2241 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXCRCERROR
))
2242 stats
->rxcrcerror
+=
2243 xgbe_mmc_read(pdata
, MMC_RXCRCERROR_LO
);
2245 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXRUNTERROR
))
2246 stats
->rxrunterror
+=
2247 xgbe_mmc_read(pdata
, MMC_RXRUNTERROR
);
2249 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXJABBERERROR
))
2250 stats
->rxjabbererror
+=
2251 xgbe_mmc_read(pdata
, MMC_RXJABBERERROR
);
2253 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXUNDERSIZE_G
))
2254 stats
->rxundersize_g
+=
2255 xgbe_mmc_read(pdata
, MMC_RXUNDERSIZE_G
);
2257 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXOVERSIZE_G
))
2258 stats
->rxoversize_g
+=
2259 xgbe_mmc_read(pdata
, MMC_RXOVERSIZE_G
);
2261 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RX64OCTETS_GB
))
2262 stats
->rx64octets_gb
+=
2263 xgbe_mmc_read(pdata
, MMC_RX64OCTETS_GB_LO
);
2265 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RX65TO127OCTETS_GB
))
2266 stats
->rx65to127octets_gb
+=
2267 xgbe_mmc_read(pdata
, MMC_RX65TO127OCTETS_GB_LO
);
2269 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RX128TO255OCTETS_GB
))
2270 stats
->rx128to255octets_gb
+=
2271 xgbe_mmc_read(pdata
, MMC_RX128TO255OCTETS_GB_LO
);
2273 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RX256TO511OCTETS_GB
))
2274 stats
->rx256to511octets_gb
+=
2275 xgbe_mmc_read(pdata
, MMC_RX256TO511OCTETS_GB_LO
);
2277 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RX512TO1023OCTETS_GB
))
2278 stats
->rx512to1023octets_gb
+=
2279 xgbe_mmc_read(pdata
, MMC_RX512TO1023OCTETS_GB_LO
);
2281 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RX1024TOMAXOCTETS_GB
))
2282 stats
->rx1024tomaxoctets_gb
+=
2283 xgbe_mmc_read(pdata
, MMC_RX1024TOMAXOCTETS_GB_LO
);
2285 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXUNICASTFRAMES_G
))
2286 stats
->rxunicastframes_g
+=
2287 xgbe_mmc_read(pdata
, MMC_RXUNICASTFRAMES_G_LO
);
2289 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXLENGTHERROR
))
2290 stats
->rxlengtherror
+=
2291 xgbe_mmc_read(pdata
, MMC_RXLENGTHERROR_LO
);
2293 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXOUTOFRANGETYPE
))
2294 stats
->rxoutofrangetype
+=
2295 xgbe_mmc_read(pdata
, MMC_RXOUTOFRANGETYPE_LO
);
2297 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXPAUSEFRAMES
))
2298 stats
->rxpauseframes
+=
2299 xgbe_mmc_read(pdata
, MMC_RXPAUSEFRAMES_LO
);
2301 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXFIFOOVERFLOW
))
2302 stats
->rxfifooverflow
+=
2303 xgbe_mmc_read(pdata
, MMC_RXFIFOOVERFLOW_LO
);
2305 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXVLANFRAMES_GB
))
2306 stats
->rxvlanframes_gb
+=
2307 xgbe_mmc_read(pdata
, MMC_RXVLANFRAMES_GB_LO
);
2309 if (XGMAC_GET_BITS(mmc_isr
, MMC_RISR
, RXWATCHDOGERROR
))
2310 stats
->rxwatchdogerror
+=
2311 xgbe_mmc_read(pdata
, MMC_RXWATCHDOGERROR
);
2314 static void xgbe_read_mmc_stats(struct xgbe_prv_data
*pdata
)
2316 struct xgbe_mmc_stats
*stats
= &pdata
->mmc_stats
;
2318 /* Freeze counters */
2319 XGMAC_IOWRITE_BITS(pdata
, MMC_CR
, MCF
, 1);
2321 stats
->txoctetcount_gb
+=
2322 xgbe_mmc_read(pdata
, MMC_TXOCTETCOUNT_GB_LO
);
2324 stats
->txframecount_gb
+=
2325 xgbe_mmc_read(pdata
, MMC_TXFRAMECOUNT_GB_LO
);
2327 stats
->txbroadcastframes_g
+=
2328 xgbe_mmc_read(pdata
, MMC_TXBROADCASTFRAMES_G_LO
);
2330 stats
->txmulticastframes_g
+=
2331 xgbe_mmc_read(pdata
, MMC_TXMULTICASTFRAMES_G_LO
);
2333 stats
->tx64octets_gb
+=
2334 xgbe_mmc_read(pdata
, MMC_TX64OCTETS_GB_LO
);
2336 stats
->tx65to127octets_gb
+=
2337 xgbe_mmc_read(pdata
, MMC_TX65TO127OCTETS_GB_LO
);
2339 stats
->tx128to255octets_gb
+=
2340 xgbe_mmc_read(pdata
, MMC_TX128TO255OCTETS_GB_LO
);
2342 stats
->tx256to511octets_gb
+=
2343 xgbe_mmc_read(pdata
, MMC_TX256TO511OCTETS_GB_LO
);
2345 stats
->tx512to1023octets_gb
+=
2346 xgbe_mmc_read(pdata
, MMC_TX512TO1023OCTETS_GB_LO
);
2348 stats
->tx1024tomaxoctets_gb
+=
2349 xgbe_mmc_read(pdata
, MMC_TX1024TOMAXOCTETS_GB_LO
);
2351 stats
->txunicastframes_gb
+=
2352 xgbe_mmc_read(pdata
, MMC_TXUNICASTFRAMES_GB_LO
);
2354 stats
->txmulticastframes_gb
+=
2355 xgbe_mmc_read(pdata
, MMC_TXMULTICASTFRAMES_GB_LO
);
2357 stats
->txbroadcastframes_g
+=
2358 xgbe_mmc_read(pdata
, MMC_TXBROADCASTFRAMES_GB_LO
);
2360 stats
->txunderflowerror
+=
2361 xgbe_mmc_read(pdata
, MMC_TXUNDERFLOWERROR_LO
);
2363 stats
->txoctetcount_g
+=
2364 xgbe_mmc_read(pdata
, MMC_TXOCTETCOUNT_G_LO
);
2366 stats
->txframecount_g
+=
2367 xgbe_mmc_read(pdata
, MMC_TXFRAMECOUNT_G_LO
);
2369 stats
->txpauseframes
+=
2370 xgbe_mmc_read(pdata
, MMC_TXPAUSEFRAMES_LO
);
2372 stats
->txvlanframes_g
+=
2373 xgbe_mmc_read(pdata
, MMC_TXVLANFRAMES_G_LO
);
2375 stats
->rxframecount_gb
+=
2376 xgbe_mmc_read(pdata
, MMC_RXFRAMECOUNT_GB_LO
);
2378 stats
->rxoctetcount_gb
+=
2379 xgbe_mmc_read(pdata
, MMC_RXOCTETCOUNT_GB_LO
);
2381 stats
->rxoctetcount_g
+=
2382 xgbe_mmc_read(pdata
, MMC_RXOCTETCOUNT_G_LO
);
2384 stats
->rxbroadcastframes_g
+=
2385 xgbe_mmc_read(pdata
, MMC_RXBROADCASTFRAMES_G_LO
);
2387 stats
->rxmulticastframes_g
+=
2388 xgbe_mmc_read(pdata
, MMC_RXMULTICASTFRAMES_G_LO
);
2390 stats
->rxcrcerror
+=
2391 xgbe_mmc_read(pdata
, MMC_RXCRCERROR_LO
);
2393 stats
->rxrunterror
+=
2394 xgbe_mmc_read(pdata
, MMC_RXRUNTERROR
);
2396 stats
->rxjabbererror
+=
2397 xgbe_mmc_read(pdata
, MMC_RXJABBERERROR
);
2399 stats
->rxundersize_g
+=
2400 xgbe_mmc_read(pdata
, MMC_RXUNDERSIZE_G
);
2402 stats
->rxoversize_g
+=
2403 xgbe_mmc_read(pdata
, MMC_RXOVERSIZE_G
);
2405 stats
->rx64octets_gb
+=
2406 xgbe_mmc_read(pdata
, MMC_RX64OCTETS_GB_LO
);
2408 stats
->rx65to127octets_gb
+=
2409 xgbe_mmc_read(pdata
, MMC_RX65TO127OCTETS_GB_LO
);
2411 stats
->rx128to255octets_gb
+=
2412 xgbe_mmc_read(pdata
, MMC_RX128TO255OCTETS_GB_LO
);
2414 stats
->rx256to511octets_gb
+=
2415 xgbe_mmc_read(pdata
, MMC_RX256TO511OCTETS_GB_LO
);
2417 stats
->rx512to1023octets_gb
+=
2418 xgbe_mmc_read(pdata
, MMC_RX512TO1023OCTETS_GB_LO
);
2420 stats
->rx1024tomaxoctets_gb
+=
2421 xgbe_mmc_read(pdata
, MMC_RX1024TOMAXOCTETS_GB_LO
);
2423 stats
->rxunicastframes_g
+=
2424 xgbe_mmc_read(pdata
, MMC_RXUNICASTFRAMES_G_LO
);
2426 stats
->rxlengtherror
+=
2427 xgbe_mmc_read(pdata
, MMC_RXLENGTHERROR_LO
);
2429 stats
->rxoutofrangetype
+=
2430 xgbe_mmc_read(pdata
, MMC_RXOUTOFRANGETYPE_LO
);
2432 stats
->rxpauseframes
+=
2433 xgbe_mmc_read(pdata
, MMC_RXPAUSEFRAMES_LO
);
2435 stats
->rxfifooverflow
+=
2436 xgbe_mmc_read(pdata
, MMC_RXFIFOOVERFLOW_LO
);
2438 stats
->rxvlanframes_gb
+=
2439 xgbe_mmc_read(pdata
, MMC_RXVLANFRAMES_GB_LO
);
2441 stats
->rxwatchdogerror
+=
2442 xgbe_mmc_read(pdata
, MMC_RXWATCHDOGERROR
);
2444 /* Un-freeze counters */
2445 XGMAC_IOWRITE_BITS(pdata
, MMC_CR
, MCF
, 0);
2448 static void xgbe_config_mmc(struct xgbe_prv_data
*pdata
)
2450 /* Set counters to reset on read */
2451 XGMAC_IOWRITE_BITS(pdata
, MMC_CR
, ROR
, 1);
2453 /* Reset the counters */
2454 XGMAC_IOWRITE_BITS(pdata
, MMC_CR
, CR
, 1);
2457 static void xgbe_prepare_tx_stop(struct xgbe_prv_data
*pdata
,
2458 struct xgbe_channel
*channel
)
2460 unsigned int tx_dsr
, tx_pos
, tx_qidx
;
2461 unsigned int tx_status
;
2462 unsigned long tx_timeout
;
2464 /* Calculate the status register to read and the position within */
2465 if (channel
->queue_index
< DMA_DSRX_FIRST_QUEUE
) {
2467 tx_pos
= (channel
->queue_index
* DMA_DSR_Q_WIDTH
) +
2470 tx_qidx
= channel
->queue_index
- DMA_DSRX_FIRST_QUEUE
;
2472 tx_dsr
= DMA_DSR1
+ ((tx_qidx
/ DMA_DSRX_QPR
) * DMA_DSRX_INC
);
2473 tx_pos
= ((tx_qidx
% DMA_DSRX_QPR
) * DMA_DSR_Q_WIDTH
) +
2477 /* The Tx engine cannot be stopped if it is actively processing
2478 * descriptors. Wait for the Tx engine to enter the stopped or
2479 * suspended state. Don't wait forever though...
2481 tx_timeout
= jiffies
+ (XGBE_DMA_STOP_TIMEOUT
* HZ
);
2482 while (time_before(jiffies
, tx_timeout
)) {
2483 tx_status
= XGMAC_IOREAD(pdata
, tx_dsr
);
2484 tx_status
= GET_BITS(tx_status
, tx_pos
, DMA_DSR_TPS_WIDTH
);
2485 if ((tx_status
== DMA_TPS_STOPPED
) ||
2486 (tx_status
== DMA_TPS_SUSPENDED
))
2489 usleep_range(500, 1000);
2492 if (!time_before(jiffies
, tx_timeout
))
2493 netdev_info(pdata
->netdev
,
2494 "timed out waiting for Tx DMA channel %u to stop\n",
2495 channel
->queue_index
);
2498 static void xgbe_enable_tx(struct xgbe_prv_data
*pdata
)
2500 struct xgbe_channel
*channel
;
2503 /* Enable each Tx DMA channel */
2504 channel
= pdata
->channel
;
2505 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2506 if (!channel
->tx_ring
)
2509 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, ST
, 1);
2512 /* Enable each Tx queue */
2513 for (i
= 0; i
< pdata
->tx_q_count
; i
++)
2514 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_TQOMR
, TXQEN
,
2518 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, TE
, 1);
2521 static void xgbe_disable_tx(struct xgbe_prv_data
*pdata
)
2523 struct xgbe_channel
*channel
;
2526 /* Prepare for Tx DMA channel stop */
2527 channel
= pdata
->channel
;
2528 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2529 if (!channel
->tx_ring
)
2532 xgbe_prepare_tx_stop(pdata
, channel
);
2535 /* Disable MAC Tx */
2536 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, TE
, 0);
2538 /* Disable each Tx queue */
2539 for (i
= 0; i
< pdata
->tx_q_count
; i
++)
2540 XGMAC_MTL_IOWRITE_BITS(pdata
, i
, MTL_Q_TQOMR
, TXQEN
, 0);
2542 /* Disable each Tx DMA channel */
2543 channel
= pdata
->channel
;
2544 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2545 if (!channel
->tx_ring
)
2548 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, ST
, 0);
2552 static void xgbe_enable_rx(struct xgbe_prv_data
*pdata
)
2554 struct xgbe_channel
*channel
;
2555 unsigned int reg_val
, i
;
2557 /* Enable each Rx DMA channel */
2558 channel
= pdata
->channel
;
2559 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2560 if (!channel
->rx_ring
)
2563 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RCR
, SR
, 1);
2566 /* Enable each Rx queue */
2568 for (i
= 0; i
< pdata
->rx_q_count
; i
++)
2569 reg_val
|= (0x02 << (i
<< 1));
2570 XGMAC_IOWRITE(pdata
, MAC_RQC0R
, reg_val
);
2573 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, DCRCC
, 1);
2574 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, CST
, 1);
2575 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, ACS
, 1);
2576 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, RE
, 1);
2579 static void xgbe_disable_rx(struct xgbe_prv_data
*pdata
)
2581 struct xgbe_channel
*channel
;
2584 /* Disable MAC Rx */
2585 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, DCRCC
, 0);
2586 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, CST
, 0);
2587 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, ACS
, 0);
2588 XGMAC_IOWRITE_BITS(pdata
, MAC_RCR
, RE
, 0);
2590 /* Disable each Rx queue */
2591 XGMAC_IOWRITE(pdata
, MAC_RQC0R
, 0);
2593 /* Disable each Rx DMA channel */
2594 channel
= pdata
->channel
;
2595 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2596 if (!channel
->rx_ring
)
2599 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RCR
, SR
, 0);
2603 static void xgbe_powerup_tx(struct xgbe_prv_data
*pdata
)
2605 struct xgbe_channel
*channel
;
2608 /* Enable each Tx DMA channel */
2609 channel
= pdata
->channel
;
2610 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2611 if (!channel
->tx_ring
)
2614 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, ST
, 1);
2618 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, TE
, 1);
2621 static void xgbe_powerdown_tx(struct xgbe_prv_data
*pdata
)
2623 struct xgbe_channel
*channel
;
2626 /* Prepare for Tx DMA channel stop */
2627 channel
= pdata
->channel
;
2628 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2629 if (!channel
->tx_ring
)
2632 xgbe_prepare_tx_stop(pdata
, channel
);
2635 /* Disable MAC Tx */
2636 XGMAC_IOWRITE_BITS(pdata
, MAC_TCR
, TE
, 0);
2638 /* Disable each Tx DMA channel */
2639 channel
= pdata
->channel
;
2640 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2641 if (!channel
->tx_ring
)
2644 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_TCR
, ST
, 0);
2648 static void xgbe_powerup_rx(struct xgbe_prv_data
*pdata
)
2650 struct xgbe_channel
*channel
;
2653 /* Enable each Rx DMA channel */
2654 channel
= pdata
->channel
;
2655 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2656 if (!channel
->rx_ring
)
2659 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RCR
, SR
, 1);
2663 static void xgbe_powerdown_rx(struct xgbe_prv_data
*pdata
)
2665 struct xgbe_channel
*channel
;
2668 /* Disable each Rx DMA channel */
2669 channel
= pdata
->channel
;
2670 for (i
= 0; i
< pdata
->channel_count
; i
++, channel
++) {
2671 if (!channel
->rx_ring
)
2674 XGMAC_DMA_IOWRITE_BITS(channel
, DMA_CH_RCR
, SR
, 0);
2678 static int xgbe_init(struct xgbe_prv_data
*pdata
)
2680 struct xgbe_desc_if
*desc_if
= &pdata
->desc_if
;
2683 DBGPR("-->xgbe_init\n");
2685 /* Flush Tx queues */
2686 ret
= xgbe_flush_tx_queues(pdata
);
2691 * Initialize DMA related features
2693 xgbe_config_dma_bus(pdata
);
2694 xgbe_config_dma_cache(pdata
);
2695 xgbe_config_osp_mode(pdata
);
2696 xgbe_config_pblx8(pdata
);
2697 xgbe_config_tx_pbl_val(pdata
);
2698 xgbe_config_rx_pbl_val(pdata
);
2699 xgbe_config_rx_coalesce(pdata
);
2700 xgbe_config_tx_coalesce(pdata
);
2701 xgbe_config_rx_buffer_size(pdata
);
2702 xgbe_config_tso_mode(pdata
);
2703 xgbe_config_sph_mode(pdata
);
2704 xgbe_config_rss(pdata
);
2705 desc_if
->wrapper_tx_desc_init(pdata
);
2706 desc_if
->wrapper_rx_desc_init(pdata
);
2707 xgbe_enable_dma_interrupts(pdata
);
2710 * Initialize MTL related features
2712 xgbe_config_mtl_mode(pdata
);
2713 xgbe_config_queue_mapping(pdata
);
2714 xgbe_config_tsf_mode(pdata
, pdata
->tx_sf_mode
);
2715 xgbe_config_rsf_mode(pdata
, pdata
->rx_sf_mode
);
2716 xgbe_config_tx_threshold(pdata
, pdata
->tx_threshold
);
2717 xgbe_config_rx_threshold(pdata
, pdata
->rx_threshold
);
2718 xgbe_config_tx_fifo_size(pdata
);
2719 xgbe_config_rx_fifo_size(pdata
);
2720 xgbe_config_flow_control_threshold(pdata
);
2721 /*TODO: Error Packet and undersized good Packet forwarding enable
2724 xgbe_config_dcb_tc(pdata
);
2725 xgbe_config_dcb_pfc(pdata
);
2726 xgbe_enable_mtl_interrupts(pdata
);
2729 * Initialize MAC related features
2731 xgbe_config_mac_address(pdata
);
2732 xgbe_config_jumbo_enable(pdata
);
2733 xgbe_config_flow_control(pdata
);
2734 xgbe_config_checksum_offload(pdata
);
2735 xgbe_config_vlan_support(pdata
);
2736 xgbe_config_mmc(pdata
);
2737 xgbe_enable_mac_interrupts(pdata
);
2739 DBGPR("<--xgbe_init\n");
2744 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if
*hw_if
)
2746 DBGPR("-->xgbe_init_function_ptrs\n");
2748 hw_if
->tx_complete
= xgbe_tx_complete
;
2750 hw_if
->set_promiscuous_mode
= xgbe_set_promiscuous_mode
;
2751 hw_if
->set_all_multicast_mode
= xgbe_set_all_multicast_mode
;
2752 hw_if
->add_mac_addresses
= xgbe_add_mac_addresses
;
2753 hw_if
->set_mac_address
= xgbe_set_mac_address
;
2755 hw_if
->enable_rx_csum
= xgbe_enable_rx_csum
;
2756 hw_if
->disable_rx_csum
= xgbe_disable_rx_csum
;
2758 hw_if
->enable_rx_vlan_stripping
= xgbe_enable_rx_vlan_stripping
;
2759 hw_if
->disable_rx_vlan_stripping
= xgbe_disable_rx_vlan_stripping
;
2760 hw_if
->enable_rx_vlan_filtering
= xgbe_enable_rx_vlan_filtering
;
2761 hw_if
->disable_rx_vlan_filtering
= xgbe_disable_rx_vlan_filtering
;
2762 hw_if
->update_vlan_hash_table
= xgbe_update_vlan_hash_table
;
2764 hw_if
->read_mmd_regs
= xgbe_read_mmd_regs
;
2765 hw_if
->write_mmd_regs
= xgbe_write_mmd_regs
;
2767 hw_if
->set_gmii_speed
= xgbe_set_gmii_speed
;
2768 hw_if
->set_gmii_2500_speed
= xgbe_set_gmii_2500_speed
;
2769 hw_if
->set_xgmii_speed
= xgbe_set_xgmii_speed
;
2771 hw_if
->enable_tx
= xgbe_enable_tx
;
2772 hw_if
->disable_tx
= xgbe_disable_tx
;
2773 hw_if
->enable_rx
= xgbe_enable_rx
;
2774 hw_if
->disable_rx
= xgbe_disable_rx
;
2776 hw_if
->powerup_tx
= xgbe_powerup_tx
;
2777 hw_if
->powerdown_tx
= xgbe_powerdown_tx
;
2778 hw_if
->powerup_rx
= xgbe_powerup_rx
;
2779 hw_if
->powerdown_rx
= xgbe_powerdown_rx
;
2781 hw_if
->dev_xmit
= xgbe_dev_xmit
;
2782 hw_if
->dev_read
= xgbe_dev_read
;
2783 hw_if
->enable_int
= xgbe_enable_int
;
2784 hw_if
->disable_int
= xgbe_disable_int
;
2785 hw_if
->init
= xgbe_init
;
2786 hw_if
->exit
= xgbe_exit
;
2788 /* Descriptor related Sequences have to be initialized here */
2789 hw_if
->tx_desc_init
= xgbe_tx_desc_init
;
2790 hw_if
->rx_desc_init
= xgbe_rx_desc_init
;
2791 hw_if
->tx_desc_reset
= xgbe_tx_desc_reset
;
2792 hw_if
->rx_desc_reset
= xgbe_rx_desc_reset
;
2793 hw_if
->is_last_desc
= xgbe_is_last_desc
;
2794 hw_if
->is_context_desc
= xgbe_is_context_desc
;
2797 hw_if
->config_tx_flow_control
= xgbe_config_tx_flow_control
;
2798 hw_if
->config_rx_flow_control
= xgbe_config_rx_flow_control
;
2800 /* For RX coalescing */
2801 hw_if
->config_rx_coalesce
= xgbe_config_rx_coalesce
;
2802 hw_if
->config_tx_coalesce
= xgbe_config_tx_coalesce
;
2803 hw_if
->usec_to_riwt
= xgbe_usec_to_riwt
;
2804 hw_if
->riwt_to_usec
= xgbe_riwt_to_usec
;
2806 /* For RX and TX threshold config */
2807 hw_if
->config_rx_threshold
= xgbe_config_rx_threshold
;
2808 hw_if
->config_tx_threshold
= xgbe_config_tx_threshold
;
2810 /* For RX and TX Store and Forward Mode config */
2811 hw_if
->config_rsf_mode
= xgbe_config_rsf_mode
;
2812 hw_if
->config_tsf_mode
= xgbe_config_tsf_mode
;
2814 /* For TX DMA Operating on Second Frame config */
2815 hw_if
->config_osp_mode
= xgbe_config_osp_mode
;
2817 /* For RX and TX PBL config */
2818 hw_if
->config_rx_pbl_val
= xgbe_config_rx_pbl_val
;
2819 hw_if
->get_rx_pbl_val
= xgbe_get_rx_pbl_val
;
2820 hw_if
->config_tx_pbl_val
= xgbe_config_tx_pbl_val
;
2821 hw_if
->get_tx_pbl_val
= xgbe_get_tx_pbl_val
;
2822 hw_if
->config_pblx8
= xgbe_config_pblx8
;
2824 /* For MMC statistics support */
2825 hw_if
->tx_mmc_int
= xgbe_tx_mmc_int
;
2826 hw_if
->rx_mmc_int
= xgbe_rx_mmc_int
;
2827 hw_if
->read_mmc_stats
= xgbe_read_mmc_stats
;
2829 /* For PTP config */
2830 hw_if
->config_tstamp
= xgbe_config_tstamp
;
2831 hw_if
->update_tstamp_addend
= xgbe_update_tstamp_addend
;
2832 hw_if
->set_tstamp_time
= xgbe_set_tstamp_time
;
2833 hw_if
->get_tstamp_time
= xgbe_get_tstamp_time
;
2834 hw_if
->get_tx_tstamp
= xgbe_get_tx_tstamp
;
2836 /* For Data Center Bridging config */
2837 hw_if
->config_dcb_tc
= xgbe_config_dcb_tc
;
2838 hw_if
->config_dcb_pfc
= xgbe_config_dcb_pfc
;
2840 /* For Receive Side Scaling */
2841 hw_if
->enable_rss
= xgbe_enable_rss
;
2842 hw_if
->disable_rss
= xgbe_disable_rss
;
2843 hw_if
->set_rss_hash_key
= xgbe_set_rss_hash_key
;
2844 hw_if
->set_rss_lookup_table
= xgbe_set_rss_lookup_table
;
2846 DBGPR("<--xgbe_init_function_ptrs\n");