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amd-xgbe: Move the PHY support into amd-xgbe
[deliverable/linux.git] / drivers / net / ethernet / amd / xgbe / xgbe-dev.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/phy.h>
118 #include <linux/mdio.h>
119 #include <linux/clk.h>
120 #include <linux/bitrev.h>
121 #include <linux/crc32.h>
122
123 #include "xgbe.h"
124 #include "xgbe-common.h"
125
126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
127 unsigned int usec)
128 {
129 unsigned long rate;
130 unsigned int ret;
131
132 DBGPR("-->xgbe_usec_to_riwt\n");
133
134 rate = pdata->sysclk_rate;
135
136 /*
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
141 */
142 ret = (usec * (rate / 1000000)) / 256;
143
144 DBGPR("<--xgbe_usec_to_riwt\n");
145
146 return ret;
147 }
148
149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
150 unsigned int riwt)
151 {
152 unsigned long rate;
153 unsigned int ret;
154
155 DBGPR("-->xgbe_riwt_to_usec\n");
156
157 rate = pdata->sysclk_rate;
158
159 /*
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
164 */
165 ret = (riwt * 256) / (rate / 1000000);
166
167 DBGPR("<--xgbe_riwt_to_usec\n");
168
169 return ret;
170 }
171
172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
173 {
174 struct xgbe_channel *channel;
175 unsigned int i;
176
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
180 pdata->pblx8);
181
182 return 0;
183 }
184
185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
186 {
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
188 }
189
190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
191 {
192 struct xgbe_channel *channel;
193 unsigned int i;
194
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
198 break;
199
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
201 pdata->tx_pbl);
202 }
203
204 return 0;
205 }
206
207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
208 {
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
210 }
211
212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
213 {
214 struct xgbe_channel *channel;
215 unsigned int i;
216
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
220 break;
221
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
223 pdata->rx_pbl);
224 }
225
226 return 0;
227 }
228
229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
230 {
231 struct xgbe_channel *channel;
232 unsigned int i;
233
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
237 break;
238
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
240 pdata->tx_osp_mode);
241 }
242
243 return 0;
244 }
245
246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
247 {
248 unsigned int i;
249
250 for (i = 0; i < pdata->rx_q_count; i++)
251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
252
253 return 0;
254 }
255
256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
257 {
258 unsigned int i;
259
260 for (i = 0; i < pdata->tx_q_count; i++)
261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
262
263 return 0;
264 }
265
266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
267 unsigned int val)
268 {
269 unsigned int i;
270
271 for (i = 0; i < pdata->rx_q_count; i++)
272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
273
274 return 0;
275 }
276
277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
278 unsigned int val)
279 {
280 unsigned int i;
281
282 for (i = 0; i < pdata->tx_q_count; i++)
283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
284
285 return 0;
286 }
287
288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
289 {
290 struct xgbe_channel *channel;
291 unsigned int i;
292
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
296 break;
297
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
299 pdata->rx_riwt);
300 }
301
302 return 0;
303 }
304
305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
306 {
307 return 0;
308 }
309
310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
311 {
312 struct xgbe_channel *channel;
313 unsigned int i;
314
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
318 break;
319
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
321 pdata->rx_buf_size);
322 }
323 }
324
325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
326 {
327 struct xgbe_channel *channel;
328 unsigned int i;
329
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
333 break;
334
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
336 }
337 }
338
339 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
340 {
341 struct xgbe_channel *channel;
342 unsigned int i;
343
344 channel = pdata->channel;
345 for (i = 0; i < pdata->channel_count; i++, channel++) {
346 if (!channel->rx_ring)
347 break;
348
349 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
350 }
351
352 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
353 }
354
355 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
356 unsigned int index, unsigned int val)
357 {
358 unsigned int wait;
359 int ret = 0;
360
361 mutex_lock(&pdata->rss_mutex);
362
363 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
364 ret = -EBUSY;
365 goto unlock;
366 }
367
368 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
369
370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
373 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
374
375 wait = 1000;
376 while (wait--) {
377 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
378 goto unlock;
379
380 usleep_range(1000, 1500);
381 }
382
383 ret = -EBUSY;
384
385 unlock:
386 mutex_unlock(&pdata->rss_mutex);
387
388 return ret;
389 }
390
391 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
392 {
393 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
394 unsigned int *key = (unsigned int *)&pdata->rss_key;
395 int ret;
396
397 while (key_regs--) {
398 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
399 key_regs, *key++);
400 if (ret)
401 return ret;
402 }
403
404 return 0;
405 }
406
407 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
408 {
409 unsigned int i;
410 int ret;
411
412 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
413 ret = xgbe_write_rss_reg(pdata,
414 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
415 pdata->rss_table[i]);
416 if (ret)
417 return ret;
418 }
419
420 return 0;
421 }
422
423 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
424 {
425 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
426
427 return xgbe_write_rss_hash_key(pdata);
428 }
429
430 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
431 const u32 *table)
432 {
433 unsigned int i;
434
435 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
436 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
437
438 return xgbe_write_rss_lookup_table(pdata);
439 }
440
441 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
442 {
443 int ret;
444
445 if (!pdata->hw_feat.rss)
446 return -EOPNOTSUPP;
447
448 /* Program the hash key */
449 ret = xgbe_write_rss_hash_key(pdata);
450 if (ret)
451 return ret;
452
453 /* Program the lookup table */
454 ret = xgbe_write_rss_lookup_table(pdata);
455 if (ret)
456 return ret;
457
458 /* Set the RSS options */
459 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
460
461 /* Enable RSS */
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
463
464 return 0;
465 }
466
467 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
468 {
469 if (!pdata->hw_feat.rss)
470 return -EOPNOTSUPP;
471
472 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
473
474 return 0;
475 }
476
477 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
478 {
479 int ret;
480
481 if (!pdata->hw_feat.rss)
482 return;
483
484 if (pdata->netdev->features & NETIF_F_RXHASH)
485 ret = xgbe_enable_rss(pdata);
486 else
487 ret = xgbe_disable_rss(pdata);
488
489 if (ret)
490 netdev_err(pdata->netdev,
491 "error configuring RSS, RSS disabled\n");
492 }
493
494 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
495 {
496 unsigned int max_q_count, q_count;
497 unsigned int reg, reg_val;
498 unsigned int i;
499
500 /* Clear MTL flow control */
501 for (i = 0; i < pdata->rx_q_count; i++)
502 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
503
504 /* Clear MAC flow control */
505 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
506 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
507 reg = MAC_Q0TFCR;
508 for (i = 0; i < q_count; i++) {
509 reg_val = XGMAC_IOREAD(pdata, reg);
510 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
511 XGMAC_IOWRITE(pdata, reg, reg_val);
512
513 reg += MAC_QTFCR_INC;
514 }
515
516 return 0;
517 }
518
519 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
520 {
521 unsigned int max_q_count, q_count;
522 unsigned int reg, reg_val;
523 unsigned int i;
524
525 /* Set MTL flow control */
526 for (i = 0; i < pdata->rx_q_count; i++)
527 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
528
529 /* Set MAC flow control */
530 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
531 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
532 reg = MAC_Q0TFCR;
533 for (i = 0; i < q_count; i++) {
534 reg_val = XGMAC_IOREAD(pdata, reg);
535
536 /* Enable transmit flow control */
537 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
538 /* Set pause time */
539 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
540
541 XGMAC_IOWRITE(pdata, reg, reg_val);
542
543 reg += MAC_QTFCR_INC;
544 }
545
546 return 0;
547 }
548
549 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
550 {
551 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
552
553 return 0;
554 }
555
556 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
557 {
558 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
559
560 return 0;
561 }
562
563 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
564 {
565 struct ieee_pfc *pfc = pdata->pfc;
566
567 if (pdata->tx_pause || (pfc && pfc->pfc_en))
568 xgbe_enable_tx_flow_control(pdata);
569 else
570 xgbe_disable_tx_flow_control(pdata);
571
572 return 0;
573 }
574
575 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
576 {
577 struct ieee_pfc *pfc = pdata->pfc;
578
579 if (pdata->rx_pause || (pfc && pfc->pfc_en))
580 xgbe_enable_rx_flow_control(pdata);
581 else
582 xgbe_disable_rx_flow_control(pdata);
583
584 return 0;
585 }
586
587 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
588 {
589 struct ieee_pfc *pfc = pdata->pfc;
590
591 xgbe_config_tx_flow_control(pdata);
592 xgbe_config_rx_flow_control(pdata);
593
594 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
595 (pfc && pfc->pfc_en) ? 1 : 0);
596 }
597
598 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
599 {
600 struct xgbe_channel *channel;
601 unsigned int dma_ch_isr, dma_ch_ier;
602 unsigned int i;
603
604 channel = pdata->channel;
605 for (i = 0; i < pdata->channel_count; i++, channel++) {
606 /* Clear all the interrupts which are set */
607 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
608 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
609
610 /* Clear all interrupt enable bits */
611 dma_ch_ier = 0;
612
613 /* Enable following interrupts
614 * NIE - Normal Interrupt Summary Enable
615 * AIE - Abnormal Interrupt Summary Enable
616 * FBEE - Fatal Bus Error Enable
617 */
618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
620 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
621
622 if (channel->tx_ring) {
623 /* Enable the following Tx interrupts
624 * TIE - Transmit Interrupt Enable (unless using
625 * per channel interrupts)
626 */
627 if (!pdata->per_channel_irq)
628 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
629 }
630 if (channel->rx_ring) {
631 /* Enable following Rx interrupts
632 * RBUE - Receive Buffer Unavailable Enable
633 * RIE - Receive Interrupt Enable (unless using
634 * per channel interrupts)
635 */
636 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
637 if (!pdata->per_channel_irq)
638 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
639 }
640
641 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
642 }
643 }
644
645 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
646 {
647 unsigned int mtl_q_isr;
648 unsigned int q_count, i;
649
650 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
651 for (i = 0; i < q_count; i++) {
652 /* Clear all the interrupts which are set */
653 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
654 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
655
656 /* No MTL interrupts to be enabled */
657 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
658 }
659 }
660
661 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
662 {
663 unsigned int mac_ier = 0;
664
665 /* Enable Timestamp interrupt */
666 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
667
668 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
669
670 /* Enable all counter interrupts */
671 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
672 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
673 }
674
675 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
676 {
677 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3)
678 return 0;
679
680 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
681
682 return 0;
683 }
684
685 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
686 {
687 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2)
688 return 0;
689
690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
691
692 return 0;
693 }
694
695 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
696 {
697 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0)
698 return 0;
699
700 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
701
702 return 0;
703 }
704
705 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
706 unsigned int enable)
707 {
708 unsigned int val = enable ? 1 : 0;
709
710 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
711 return 0;
712
713 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
714 enable ? "entering" : "leaving");
715 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
716
717 return 0;
718 }
719
720 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
721 unsigned int enable)
722 {
723 unsigned int val = enable ? 1 : 0;
724
725 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
726 return 0;
727
728 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
729 enable ? "entering" : "leaving");
730 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
731
732 return 0;
733 }
734
735 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
736 struct netdev_hw_addr *ha, unsigned int *mac_reg)
737 {
738 unsigned int mac_addr_hi, mac_addr_lo;
739 u8 *mac_addr;
740
741 mac_addr_lo = 0;
742 mac_addr_hi = 0;
743
744 if (ha) {
745 mac_addr = (u8 *)&mac_addr_lo;
746 mac_addr[0] = ha->addr[0];
747 mac_addr[1] = ha->addr[1];
748 mac_addr[2] = ha->addr[2];
749 mac_addr[3] = ha->addr[3];
750 mac_addr = (u8 *)&mac_addr_hi;
751 mac_addr[0] = ha->addr[4];
752 mac_addr[1] = ha->addr[5];
753
754 netif_dbg(pdata, drv, pdata->netdev,
755 "adding mac address %pM at %#x\n",
756 ha->addr, *mac_reg);
757
758 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
759 }
760
761 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
762 *mac_reg += MAC_MACA_INC;
763 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
764 *mac_reg += MAC_MACA_INC;
765 }
766
767 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
768 {
769 struct net_device *netdev = pdata->netdev;
770 struct netdev_hw_addr *ha;
771 unsigned int mac_reg;
772 unsigned int addn_macs;
773
774 mac_reg = MAC_MACA1HR;
775 addn_macs = pdata->hw_feat.addn_mac;
776
777 if (netdev_uc_count(netdev) > addn_macs) {
778 xgbe_set_promiscuous_mode(pdata, 1);
779 } else {
780 netdev_for_each_uc_addr(ha, netdev) {
781 xgbe_set_mac_reg(pdata, ha, &mac_reg);
782 addn_macs--;
783 }
784
785 if (netdev_mc_count(netdev) > addn_macs) {
786 xgbe_set_all_multicast_mode(pdata, 1);
787 } else {
788 netdev_for_each_mc_addr(ha, netdev) {
789 xgbe_set_mac_reg(pdata, ha, &mac_reg);
790 addn_macs--;
791 }
792 }
793 }
794
795 /* Clear remaining additional MAC address entries */
796 while (addn_macs--)
797 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
798 }
799
800 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
801 {
802 struct net_device *netdev = pdata->netdev;
803 struct netdev_hw_addr *ha;
804 unsigned int hash_reg;
805 unsigned int hash_table_shift, hash_table_count;
806 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
807 u32 crc;
808 unsigned int i;
809
810 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
811 hash_table_count = pdata->hw_feat.hash_table_size / 32;
812 memset(hash_table, 0, sizeof(hash_table));
813
814 /* Build the MAC Hash Table register values */
815 netdev_for_each_uc_addr(ha, netdev) {
816 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
817 crc >>= hash_table_shift;
818 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
819 }
820
821 netdev_for_each_mc_addr(ha, netdev) {
822 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
823 crc >>= hash_table_shift;
824 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
825 }
826
827 /* Set the MAC Hash Table registers */
828 hash_reg = MAC_HTR0;
829 for (i = 0; i < hash_table_count; i++) {
830 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
831 hash_reg += MAC_HTR_INC;
832 }
833 }
834
835 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
836 {
837 if (pdata->hw_feat.hash_table_size)
838 xgbe_set_mac_hash_table(pdata);
839 else
840 xgbe_set_mac_addn_addrs(pdata);
841
842 return 0;
843 }
844
845 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
846 {
847 unsigned int mac_addr_hi, mac_addr_lo;
848
849 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
850 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
851 (addr[1] << 8) | (addr[0] << 0);
852
853 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
854 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
855
856 return 0;
857 }
858
859 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
860 {
861 struct net_device *netdev = pdata->netdev;
862 unsigned int pr_mode, am_mode;
863
864 pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
865 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
866
867 xgbe_set_promiscuous_mode(pdata, pr_mode);
868 xgbe_set_all_multicast_mode(pdata, am_mode);
869
870 xgbe_add_mac_addresses(pdata);
871
872 return 0;
873 }
874
875 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
876 int mmd_reg)
877 {
878 unsigned int mmd_address;
879 int mmd_data;
880
881 if (mmd_reg & MII_ADDR_C45)
882 mmd_address = mmd_reg & ~MII_ADDR_C45;
883 else
884 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
885
886 /* The PCS registers are accessed using mmio. The underlying APB3
887 * management interface uses indirect addressing to access the MMD
888 * register sets. This requires accessing of the PCS register in two
889 * phases, an address phase and a data phase.
890 *
891 * The mmio interface is based on 32-bit offsets and values. All
892 * register offsets must therefore be adjusted by left shifting the
893 * offset 2 bits and reading 32 bits of data.
894 */
895 mutex_lock(&pdata->xpcs_mutex);
896 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
897 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
898 mutex_unlock(&pdata->xpcs_mutex);
899
900 return mmd_data;
901 }
902
903 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
904 int mmd_reg, int mmd_data)
905 {
906 unsigned int mmd_address;
907
908 if (mmd_reg & MII_ADDR_C45)
909 mmd_address = mmd_reg & ~MII_ADDR_C45;
910 else
911 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
912
913 /* The PCS registers are accessed using mmio. The underlying APB3
914 * management interface uses indirect addressing to access the MMD
915 * register sets. This requires accessing of the PCS register in two
916 * phases, an address phase and a data phase.
917 *
918 * The mmio interface is based on 32-bit offsets and values. All
919 * register offsets must therefore be adjusted by left shifting the
920 * offset 2 bits and reading 32 bits of data.
921 */
922 mutex_lock(&pdata->xpcs_mutex);
923 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
924 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
925 mutex_unlock(&pdata->xpcs_mutex);
926 }
927
928 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
929 {
930 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
931 }
932
933 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
934 {
935 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
936
937 return 0;
938 }
939
940 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
941 {
942 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
943
944 return 0;
945 }
946
947 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
948 {
949 /* Put the VLAN tag in the Rx descriptor */
950 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
951
952 /* Don't check the VLAN type */
953 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
954
955 /* Check only C-TAG (0x8100) packets */
956 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
957
958 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
959 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
960
961 /* Enable VLAN tag stripping */
962 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
963
964 return 0;
965 }
966
967 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
968 {
969 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
970
971 return 0;
972 }
973
974 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
975 {
976 /* Enable VLAN filtering */
977 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
978
979 /* Enable VLAN Hash Table filtering */
980 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
981
982 /* Disable VLAN tag inverse matching */
983 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
984
985 /* Only filter on the lower 12-bits of the VLAN tag */
986 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
987
988 /* In order for the VLAN Hash Table filtering to be effective,
989 * the VLAN tag identifier in the VLAN Tag Register must not
990 * be zero. Set the VLAN tag identifier to "1" to enable the
991 * VLAN Hash Table filtering. This implies that a VLAN tag of
992 * 1 will always pass filtering.
993 */
994 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
995
996 return 0;
997 }
998
999 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
1000 {
1001 /* Disable VLAN filtering */
1002 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
1003
1004 return 0;
1005 }
1006
1007 #ifndef CRCPOLY_LE
1008 #define CRCPOLY_LE 0xedb88320
1009 #endif
1010 static u32 xgbe_vid_crc32_le(__le16 vid_le)
1011 {
1012 u32 poly = CRCPOLY_LE;
1013 u32 crc = ~0;
1014 u32 temp = 0;
1015 unsigned char *data = (unsigned char *)&vid_le;
1016 unsigned char data_byte = 0;
1017 int i, bits;
1018
1019 bits = get_bitmask_order(VLAN_VID_MASK);
1020 for (i = 0; i < bits; i++) {
1021 if ((i % 8) == 0)
1022 data_byte = data[i / 8];
1023
1024 temp = ((crc & 1) ^ data_byte) & 1;
1025 crc >>= 1;
1026 data_byte >>= 1;
1027
1028 if (temp)
1029 crc ^= poly;
1030 }
1031
1032 return crc;
1033 }
1034
1035 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
1036 {
1037 u32 crc;
1038 u16 vid;
1039 __le16 vid_le;
1040 u16 vlan_hash_table = 0;
1041
1042 /* Generate the VLAN Hash Table value */
1043 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
1044 /* Get the CRC32 value of the VLAN ID */
1045 vid_le = cpu_to_le16(vid);
1046 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
1047
1048 vlan_hash_table |= (1 << crc);
1049 }
1050
1051 /* Set the VLAN Hash Table filtering register */
1052 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
1053
1054 return 0;
1055 }
1056
1057 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1058 {
1059 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1060
1061 /* Reset the Tx descriptor
1062 * Set buffer 1 (lo) address to zero
1063 * Set buffer 1 (hi) address to zero
1064 * Reset all other control bits (IC, TTSE, B2L & B1L)
1065 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1066 */
1067 rdesc->desc0 = 0;
1068 rdesc->desc1 = 0;
1069 rdesc->desc2 = 0;
1070 rdesc->desc3 = 0;
1071
1072 /* Make sure ownership is written to the descriptor */
1073 dma_wmb();
1074 }
1075
1076 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1077 {
1078 struct xgbe_ring *ring = channel->tx_ring;
1079 struct xgbe_ring_data *rdata;
1080 int i;
1081 int start_index = ring->cur;
1082
1083 DBGPR("-->tx_desc_init\n");
1084
1085 /* Initialze all descriptors */
1086 for (i = 0; i < ring->rdesc_count; i++) {
1087 rdata = XGBE_GET_DESC_DATA(ring, i);
1088
1089 /* Initialize Tx descriptor */
1090 xgbe_tx_desc_reset(rdata);
1091 }
1092
1093 /* Update the total number of Tx descriptors */
1094 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1095
1096 /* Update the starting address of descriptor ring */
1097 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1098 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1099 upper_32_bits(rdata->rdesc_dma));
1100 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1101 lower_32_bits(rdata->rdesc_dma));
1102
1103 DBGPR("<--tx_desc_init\n");
1104 }
1105
1106 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1107 struct xgbe_ring_data *rdata, unsigned int index)
1108 {
1109 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1110 unsigned int rx_usecs = pdata->rx_usecs;
1111 unsigned int rx_frames = pdata->rx_frames;
1112 unsigned int inte;
1113
1114 if (!rx_usecs && !rx_frames) {
1115 /* No coalescing, interrupt for every descriptor */
1116 inte = 1;
1117 } else {
1118 /* Set interrupt based on Rx frame coalescing setting */
1119 if (rx_frames && !((index + 1) % rx_frames))
1120 inte = 1;
1121 else
1122 inte = 0;
1123 }
1124
1125 /* Reset the Rx descriptor
1126 * Set buffer 1 (lo) address to header dma address (lo)
1127 * Set buffer 1 (hi) address to header dma address (hi)
1128 * Set buffer 2 (lo) address to buffer dma address (lo)
1129 * Set buffer 2 (hi) address to buffer dma address (hi) and
1130 * set control bits OWN and INTE
1131 */
1132 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma));
1133 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma));
1134 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma));
1135 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma));
1136
1137 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
1138
1139 /* Since the Rx DMA engine is likely running, make sure everything
1140 * is written to the descriptor(s) before setting the OWN bit
1141 * for the descriptor
1142 */
1143 dma_wmb();
1144
1145 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1146
1147 /* Make sure ownership is written to the descriptor */
1148 dma_wmb();
1149 }
1150
1151 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1152 {
1153 struct xgbe_prv_data *pdata = channel->pdata;
1154 struct xgbe_ring *ring = channel->rx_ring;
1155 struct xgbe_ring_data *rdata;
1156 unsigned int start_index = ring->cur;
1157 unsigned int i;
1158
1159 DBGPR("-->rx_desc_init\n");
1160
1161 /* Initialize all descriptors */
1162 for (i = 0; i < ring->rdesc_count; i++) {
1163 rdata = XGBE_GET_DESC_DATA(ring, i);
1164
1165 /* Initialize Rx descriptor */
1166 xgbe_rx_desc_reset(pdata, rdata, i);
1167 }
1168
1169 /* Update the total number of Rx descriptors */
1170 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1171
1172 /* Update the starting address of descriptor ring */
1173 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1174 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1175 upper_32_bits(rdata->rdesc_dma));
1176 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1177 lower_32_bits(rdata->rdesc_dma));
1178
1179 /* Update the Rx Descriptor Tail Pointer */
1180 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1181 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1182 lower_32_bits(rdata->rdesc_dma));
1183
1184 DBGPR("<--rx_desc_init\n");
1185 }
1186
1187 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1188 unsigned int addend)
1189 {
1190 /* Set the addend register value and tell the device */
1191 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1192 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1193
1194 /* Wait for addend update to complete */
1195 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1196 udelay(5);
1197 }
1198
1199 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1200 unsigned int nsec)
1201 {
1202 /* Set the time values and tell the device */
1203 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1204 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1205 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1206
1207 /* Wait for time update to complete */
1208 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1209 udelay(5);
1210 }
1211
1212 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1213 {
1214 u64 nsec;
1215
1216 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1217 nsec *= NSEC_PER_SEC;
1218 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1219
1220 return nsec;
1221 }
1222
1223 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1224 {
1225 unsigned int tx_snr;
1226 u64 nsec;
1227
1228 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1229 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1230 return 0;
1231
1232 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1233 nsec *= NSEC_PER_SEC;
1234 nsec += tx_snr;
1235
1236 return nsec;
1237 }
1238
1239 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1240 struct xgbe_ring_desc *rdesc)
1241 {
1242 u64 nsec;
1243
1244 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1245 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1246 nsec = le32_to_cpu(rdesc->desc1);
1247 nsec <<= 32;
1248 nsec |= le32_to_cpu(rdesc->desc0);
1249 if (nsec != 0xffffffffffffffffULL) {
1250 packet->rx_tstamp = nsec;
1251 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1252 RX_TSTAMP, 1);
1253 }
1254 }
1255 }
1256
1257 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1258 unsigned int mac_tscr)
1259 {
1260 /* Set one nano-second accuracy */
1261 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1262
1263 /* Set fine timestamp update */
1264 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1265
1266 /* Overwrite earlier timestamps */
1267 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1268
1269 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1270
1271 /* Exit if timestamping is not enabled */
1272 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1273 return 0;
1274
1275 /* Initialize time registers */
1276 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1277 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1278 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1279 xgbe_set_tstamp_time(pdata, 0, 0);
1280
1281 /* Initialize the timecounter */
1282 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1283 ktime_to_ns(ktime_get_real()));
1284
1285 return 0;
1286 }
1287
1288 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1289 {
1290 struct ieee_ets *ets = pdata->ets;
1291 unsigned int total_weight, min_weight, weight;
1292 unsigned int i;
1293
1294 if (!ets)
1295 return;
1296
1297 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1298 * traffic class is using ETS algorithm)
1299 */
1300 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1301
1302 /* Set Traffic Class algorithms */
1303 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1304 min_weight = total_weight / 100;
1305 if (!min_weight)
1306 min_weight = 1;
1307
1308 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1309 switch (ets->tc_tsa[i]) {
1310 case IEEE_8021QAZ_TSA_STRICT:
1311 netif_dbg(pdata, drv, pdata->netdev,
1312 "TC%u using SP\n", i);
1313 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1314 MTL_TSA_SP);
1315 break;
1316 case IEEE_8021QAZ_TSA_ETS:
1317 weight = total_weight * ets->tc_tx_bw[i] / 100;
1318 weight = clamp(weight, min_weight, total_weight);
1319
1320 netif_dbg(pdata, drv, pdata->netdev,
1321 "TC%u using DWRR (weight %u)\n", i, weight);
1322 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1323 MTL_TSA_ETS);
1324 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1325 weight);
1326 break;
1327 }
1328 }
1329 }
1330
1331 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1332 {
1333 struct ieee_pfc *pfc = pdata->pfc;
1334 struct ieee_ets *ets = pdata->ets;
1335 unsigned int mask, reg, reg_val;
1336 unsigned int tc, prio;
1337
1338 if (!pfc || !ets)
1339 return;
1340
1341 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1342 mask = 0;
1343 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1344 if ((pfc->pfc_en & (1 << prio)) &&
1345 (ets->prio_tc[prio] == tc))
1346 mask |= (1 << prio);
1347 }
1348 mask &= 0xff;
1349
1350 netif_dbg(pdata, drv, pdata->netdev, "TC%u PFC mask=%#x\n",
1351 tc, mask);
1352 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1353 reg_val = XGMAC_IOREAD(pdata, reg);
1354
1355 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1356 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1357
1358 XGMAC_IOWRITE(pdata, reg, reg_val);
1359 }
1360
1361 xgbe_config_flow_control(pdata);
1362 }
1363
1364 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1365 struct xgbe_ring *ring)
1366 {
1367 struct xgbe_prv_data *pdata = channel->pdata;
1368 struct xgbe_ring_data *rdata;
1369
1370 /* Make sure everything is written before the register write */
1371 wmb();
1372
1373 /* Issue a poll command to Tx DMA by writing address
1374 * of next immediate free descriptor */
1375 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1376 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1377 lower_32_bits(rdata->rdesc_dma));
1378
1379 /* Start the Tx timer */
1380 if (pdata->tx_usecs && !channel->tx_timer_active) {
1381 channel->tx_timer_active = 1;
1382 mod_timer(&channel->tx_timer,
1383 jiffies + usecs_to_jiffies(pdata->tx_usecs));
1384 }
1385
1386 ring->tx.xmit_more = 0;
1387 }
1388
1389 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1390 {
1391 struct xgbe_prv_data *pdata = channel->pdata;
1392 struct xgbe_ring *ring = channel->tx_ring;
1393 struct xgbe_ring_data *rdata;
1394 struct xgbe_ring_desc *rdesc;
1395 struct xgbe_packet_data *packet = &ring->packet_data;
1396 unsigned int csum, tso, vlan;
1397 unsigned int tso_context, vlan_context;
1398 unsigned int tx_set_ic;
1399 int start_index = ring->cur;
1400 int cur_index = ring->cur;
1401 int i;
1402
1403 DBGPR("-->xgbe_dev_xmit\n");
1404
1405 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1406 CSUM_ENABLE);
1407 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1408 TSO_ENABLE);
1409 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1410 VLAN_CTAG);
1411
1412 if (tso && (packet->mss != ring->tx.cur_mss))
1413 tso_context = 1;
1414 else
1415 tso_context = 0;
1416
1417 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1418 vlan_context = 1;
1419 else
1420 vlan_context = 0;
1421
1422 /* Determine if an interrupt should be generated for this Tx:
1423 * Interrupt:
1424 * - Tx frame count exceeds the frame count setting
1425 * - Addition of Tx frame count to the frame count since the
1426 * last interrupt was set exceeds the frame count setting
1427 * No interrupt:
1428 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1429 * - Addition of Tx frame count to the frame count since the
1430 * last interrupt was set does not exceed the frame count setting
1431 */
1432 ring->coalesce_count += packet->tx_packets;
1433 if (!pdata->tx_frames)
1434 tx_set_ic = 0;
1435 else if (packet->tx_packets > pdata->tx_frames)
1436 tx_set_ic = 1;
1437 else if ((ring->coalesce_count % pdata->tx_frames) <
1438 packet->tx_packets)
1439 tx_set_ic = 1;
1440 else
1441 tx_set_ic = 0;
1442
1443 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1444 rdesc = rdata->rdesc;
1445
1446 /* Create a context descriptor if this is a TSO packet */
1447 if (tso_context || vlan_context) {
1448 if (tso_context) {
1449 netif_dbg(pdata, tx_queued, pdata->netdev,
1450 "TSO context descriptor, mss=%u\n",
1451 packet->mss);
1452
1453 /* Set the MSS size */
1454 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1455 MSS, packet->mss);
1456
1457 /* Mark it as a CONTEXT descriptor */
1458 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1459 CTXT, 1);
1460
1461 /* Indicate this descriptor contains the MSS */
1462 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1463 TCMSSV, 1);
1464
1465 ring->tx.cur_mss = packet->mss;
1466 }
1467
1468 if (vlan_context) {
1469 netif_dbg(pdata, tx_queued, pdata->netdev,
1470 "VLAN context descriptor, ctag=%u\n",
1471 packet->vlan_ctag);
1472
1473 /* Mark it as a CONTEXT descriptor */
1474 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1475 CTXT, 1);
1476
1477 /* Set the VLAN tag */
1478 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1479 VT, packet->vlan_ctag);
1480
1481 /* Indicate this descriptor contains the VLAN tag */
1482 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1483 VLTV, 1);
1484
1485 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1486 }
1487
1488 cur_index++;
1489 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1490 rdesc = rdata->rdesc;
1491 }
1492
1493 /* Update buffer address (for TSO this is the header) */
1494 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1495 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1496
1497 /* Update the buffer length */
1498 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1499 rdata->skb_dma_len);
1500
1501 /* VLAN tag insertion check */
1502 if (vlan)
1503 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1504 TX_NORMAL_DESC2_VLAN_INSERT);
1505
1506 /* Timestamp enablement check */
1507 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1508 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1509
1510 /* Mark it as First Descriptor */
1511 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1512
1513 /* Mark it as a NORMAL descriptor */
1514 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1515
1516 /* Set OWN bit if not the first descriptor */
1517 if (cur_index != start_index)
1518 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1519
1520 if (tso) {
1521 /* Enable TSO */
1522 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1523 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1524 packet->tcp_payload_len);
1525 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1526 packet->tcp_header_len / 4);
1527
1528 pdata->ext_stats.tx_tso_packets++;
1529 } else {
1530 /* Enable CRC and Pad Insertion */
1531 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1532
1533 /* Enable HW CSUM */
1534 if (csum)
1535 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1536 CIC, 0x3);
1537
1538 /* Set the total length to be transmitted */
1539 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1540 packet->length);
1541 }
1542
1543 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1544 cur_index++;
1545 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1546 rdesc = rdata->rdesc;
1547
1548 /* Update buffer address */
1549 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1550 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1551
1552 /* Update the buffer length */
1553 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1554 rdata->skb_dma_len);
1555
1556 /* Set OWN bit */
1557 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1558
1559 /* Mark it as NORMAL descriptor */
1560 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1561
1562 /* Enable HW CSUM */
1563 if (csum)
1564 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1565 CIC, 0x3);
1566 }
1567
1568 /* Set LAST bit for the last descriptor */
1569 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1570
1571 /* Set IC bit based on Tx coalescing settings */
1572 if (tx_set_ic)
1573 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1574
1575 /* Save the Tx info to report back during cleanup */
1576 rdata->tx.packets = packet->tx_packets;
1577 rdata->tx.bytes = packet->tx_bytes;
1578
1579 /* In case the Tx DMA engine is running, make sure everything
1580 * is written to the descriptor(s) before setting the OWN bit
1581 * for the first descriptor
1582 */
1583 dma_wmb();
1584
1585 /* Set OWN bit for the first descriptor */
1586 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1587 rdesc = rdata->rdesc;
1588 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1589
1590 if (netif_msg_tx_queued(pdata))
1591 xgbe_dump_tx_desc(pdata, ring, start_index,
1592 packet->rdesc_count, 1);
1593
1594 /* Make sure ownership is written to the descriptor */
1595 dma_wmb();
1596
1597 ring->cur = cur_index + 1;
1598 if (!packet->skb->xmit_more ||
1599 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1600 channel->queue_index)))
1601 xgbe_tx_start_xmit(channel, ring);
1602 else
1603 ring->tx.xmit_more = 1;
1604
1605 DBGPR(" %s: descriptors %u to %u written\n",
1606 channel->name, start_index & (ring->rdesc_count - 1),
1607 (ring->cur - 1) & (ring->rdesc_count - 1));
1608
1609 DBGPR("<--xgbe_dev_xmit\n");
1610 }
1611
1612 static int xgbe_dev_read(struct xgbe_channel *channel)
1613 {
1614 struct xgbe_prv_data *pdata = channel->pdata;
1615 struct xgbe_ring *ring = channel->rx_ring;
1616 struct xgbe_ring_data *rdata;
1617 struct xgbe_ring_desc *rdesc;
1618 struct xgbe_packet_data *packet = &ring->packet_data;
1619 struct net_device *netdev = pdata->netdev;
1620 unsigned int err, etlt, l34t;
1621
1622 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1623
1624 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1625 rdesc = rdata->rdesc;
1626
1627 /* Check for data availability */
1628 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1629 return 1;
1630
1631 /* Make sure descriptor fields are read after reading the OWN bit */
1632 dma_rmb();
1633
1634 if (netif_msg_rx_status(pdata))
1635 xgbe_dump_rx_desc(pdata, ring, ring->cur);
1636
1637 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1638 /* Timestamp Context Descriptor */
1639 xgbe_get_rx_tstamp(packet, rdesc);
1640
1641 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1642 CONTEXT, 1);
1643 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1644 CONTEXT_NEXT, 0);
1645 return 0;
1646 }
1647
1648 /* Normal Descriptor, be sure Context Descriptor bit is off */
1649 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1650
1651 /* Indicate if a Context Descriptor is next */
1652 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1653 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1654 CONTEXT_NEXT, 1);
1655
1656 /* Get the header length */
1657 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
1658 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1659 RX_NORMAL_DESC2, HL);
1660 if (rdata->rx.hdr_len)
1661 pdata->ext_stats.rx_split_header_packets++;
1662 }
1663
1664 /* Get the RSS hash */
1665 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1666 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1667 RSS_HASH, 1);
1668
1669 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1670
1671 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1672 switch (l34t) {
1673 case RX_DESC3_L34T_IPV4_TCP:
1674 case RX_DESC3_L34T_IPV4_UDP:
1675 case RX_DESC3_L34T_IPV6_TCP:
1676 case RX_DESC3_L34T_IPV6_UDP:
1677 packet->rss_hash_type = PKT_HASH_TYPE_L4;
1678 break;
1679 default:
1680 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1681 }
1682 }
1683
1684 /* Get the packet length */
1685 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1686
1687 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1688 /* Not all the data has been transferred for this packet */
1689 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1690 INCOMPLETE, 1);
1691 return 0;
1692 }
1693
1694 /* This is the last of the data for this packet */
1695 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1696 INCOMPLETE, 0);
1697
1698 /* Set checksum done indicator as appropriate */
1699 if (netdev->features & NETIF_F_RXCSUM)
1700 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1701 CSUM_DONE, 1);
1702
1703 /* Check for errors (only valid in last descriptor) */
1704 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1705 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1706 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
1707
1708 if (!err || !etlt) {
1709 /* No error if err is 0 or etlt is 0 */
1710 if ((etlt == 0x09) &&
1711 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1712 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1713 VLAN_CTAG, 1);
1714 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1715 RX_NORMAL_DESC0,
1716 OVT);
1717 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
1718 packet->vlan_ctag);
1719 }
1720 } else {
1721 if ((etlt == 0x05) || (etlt == 0x06))
1722 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1723 CSUM_DONE, 0);
1724 else
1725 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1726 FRAME, 1);
1727 }
1728
1729 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1730 ring->cur & (ring->rdesc_count - 1), ring->cur);
1731
1732 return 0;
1733 }
1734
1735 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1736 {
1737 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1738 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1739 }
1740
1741 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1742 {
1743 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1744 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1745 }
1746
1747 static int xgbe_enable_int(struct xgbe_channel *channel,
1748 enum xgbe_int int_id)
1749 {
1750 unsigned int dma_ch_ier;
1751
1752 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1753
1754 switch (int_id) {
1755 case XGMAC_INT_DMA_CH_SR_TI:
1756 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1757 break;
1758 case XGMAC_INT_DMA_CH_SR_TPS:
1759 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1760 break;
1761 case XGMAC_INT_DMA_CH_SR_TBU:
1762 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1763 break;
1764 case XGMAC_INT_DMA_CH_SR_RI:
1765 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1766 break;
1767 case XGMAC_INT_DMA_CH_SR_RBU:
1768 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1769 break;
1770 case XGMAC_INT_DMA_CH_SR_RPS:
1771 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1772 break;
1773 case XGMAC_INT_DMA_CH_SR_TI_RI:
1774 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1775 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1776 break;
1777 case XGMAC_INT_DMA_CH_SR_FBE:
1778 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1779 break;
1780 case XGMAC_INT_DMA_ALL:
1781 dma_ch_ier |= channel->saved_ier;
1782 break;
1783 default:
1784 return -1;
1785 }
1786
1787 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1788
1789 return 0;
1790 }
1791
1792 static int xgbe_disable_int(struct xgbe_channel *channel,
1793 enum xgbe_int int_id)
1794 {
1795 unsigned int dma_ch_ier;
1796
1797 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1798
1799 switch (int_id) {
1800 case XGMAC_INT_DMA_CH_SR_TI:
1801 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1802 break;
1803 case XGMAC_INT_DMA_CH_SR_TPS:
1804 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1805 break;
1806 case XGMAC_INT_DMA_CH_SR_TBU:
1807 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1808 break;
1809 case XGMAC_INT_DMA_CH_SR_RI:
1810 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1811 break;
1812 case XGMAC_INT_DMA_CH_SR_RBU:
1813 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1814 break;
1815 case XGMAC_INT_DMA_CH_SR_RPS:
1816 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1817 break;
1818 case XGMAC_INT_DMA_CH_SR_TI_RI:
1819 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1820 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1821 break;
1822 case XGMAC_INT_DMA_CH_SR_FBE:
1823 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1824 break;
1825 case XGMAC_INT_DMA_ALL:
1826 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1827 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1828 break;
1829 default:
1830 return -1;
1831 }
1832
1833 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1834
1835 return 0;
1836 }
1837
1838 static int xgbe_exit(struct xgbe_prv_data *pdata)
1839 {
1840 unsigned int count = 2000;
1841
1842 DBGPR("-->xgbe_exit\n");
1843
1844 /* Issue a software reset */
1845 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1846 usleep_range(10, 15);
1847
1848 /* Poll Until Poll Condition */
1849 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1850 usleep_range(500, 600);
1851
1852 if (!count)
1853 return -EBUSY;
1854
1855 DBGPR("<--xgbe_exit\n");
1856
1857 return 0;
1858 }
1859
1860 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1861 {
1862 unsigned int i, count;
1863
1864 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1865 return 0;
1866
1867 for (i = 0; i < pdata->tx_q_count; i++)
1868 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1869
1870 /* Poll Until Poll Condition */
1871 for (i = 0; i < pdata->tx_q_count; i++) {
1872 count = 2000;
1873 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1874 MTL_Q_TQOMR, FTQ))
1875 usleep_range(500, 600);
1876
1877 if (!count)
1878 return -EBUSY;
1879 }
1880
1881 return 0;
1882 }
1883
1884 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1885 {
1886 /* Set enhanced addressing mode */
1887 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1888
1889 /* Set the System Bus mode */
1890 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1891 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1892 }
1893
1894 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1895 {
1896 unsigned int arcache, awcache;
1897
1898 arcache = 0;
1899 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1900 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1901 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1902 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1903 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1904 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1905 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1906
1907 awcache = 0;
1908 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1909 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1910 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1911 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1912 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1913 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1914 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1915 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1916 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1917 }
1918
1919 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1920 {
1921 unsigned int i;
1922
1923 /* Set Tx to weighted round robin scheduling algorithm */
1924 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1925
1926 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1927 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1928 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1929 MTL_TSA_ETS);
1930 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1931 }
1932
1933 /* Set Rx to strict priority algorithm */
1934 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1935 }
1936
1937 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1938 unsigned int queue_count)
1939 {
1940 unsigned int q_fifo_size = 0;
1941 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1942
1943 /* Calculate Tx/Rx fifo share per queue */
1944 switch (fifo_size) {
1945 case 0:
1946 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1947 break;
1948 case 1:
1949 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1950 break;
1951 case 2:
1952 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1953 break;
1954 case 3:
1955 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1956 break;
1957 case 4:
1958 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1959 break;
1960 case 5:
1961 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1962 break;
1963 case 6:
1964 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1965 break;
1966 case 7:
1967 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1968 break;
1969 case 8:
1970 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1971 break;
1972 case 9:
1973 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1974 break;
1975 case 10:
1976 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1977 break;
1978 case 11:
1979 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1980 break;
1981 }
1982
1983 /* The configured value is not the actual amount of fifo RAM */
1984 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1985
1986 q_fifo_size = q_fifo_size / queue_count;
1987
1988 /* Set the queue fifo size programmable value */
1989 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1990 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1991 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1992 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1993 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1994 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1995 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1996 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
1997 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
1998 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
1999 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
2000 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
2001 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
2002 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
2003 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
2004 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
2005 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
2006 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
2007 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
2008 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
2009 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
2010 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
2011
2012 return p_fifo;
2013 }
2014
2015 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
2016 {
2017 enum xgbe_mtl_fifo_size fifo_size;
2018 unsigned int i;
2019
2020 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
2021 pdata->tx_q_count);
2022
2023 for (i = 0; i < pdata->tx_q_count; i++)
2024 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
2025
2026 netif_info(pdata, drv, pdata->netdev,
2027 "%d Tx hardware queues, %d byte fifo per queue\n",
2028 pdata->tx_q_count, ((fifo_size + 1) * 256));
2029 }
2030
2031 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2032 {
2033 enum xgbe_mtl_fifo_size fifo_size;
2034 unsigned int i;
2035
2036 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
2037 pdata->rx_q_count);
2038
2039 for (i = 0; i < pdata->rx_q_count; i++)
2040 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
2041
2042 netif_info(pdata, drv, pdata->netdev,
2043 "%d Rx hardware queues, %d byte fifo per queue\n",
2044 pdata->rx_q_count, ((fifo_size + 1) * 256));
2045 }
2046
2047 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2048 {
2049 unsigned int qptc, qptc_extra, queue;
2050 unsigned int prio_queues;
2051 unsigned int ppq, ppq_extra, prio;
2052 unsigned int mask;
2053 unsigned int i, j, reg, reg_val;
2054
2055 /* Map the MTL Tx Queues to Traffic Classes
2056 * Note: Tx Queues >= Traffic Classes
2057 */
2058 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2059 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2060
2061 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2062 for (j = 0; j < qptc; j++) {
2063 netif_dbg(pdata, drv, pdata->netdev,
2064 "TXq%u mapped to TC%u\n", queue, i);
2065 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2066 Q2TCMAP, i);
2067 pdata->q2tc_map[queue++] = i;
2068 }
2069
2070 if (i < qptc_extra) {
2071 netif_dbg(pdata, drv, pdata->netdev,
2072 "TXq%u mapped to TC%u\n", queue, i);
2073 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2074 Q2TCMAP, i);
2075 pdata->q2tc_map[queue++] = i;
2076 }
2077 }
2078
2079 /* Map the 8 VLAN priority values to available MTL Rx queues */
2080 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
2081 pdata->rx_q_count);
2082 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2083 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2084
2085 reg = MAC_RQC2R;
2086 reg_val = 0;
2087 for (i = 0, prio = 0; i < prio_queues;) {
2088 mask = 0;
2089 for (j = 0; j < ppq; j++) {
2090 netif_dbg(pdata, drv, pdata->netdev,
2091 "PRIO%u mapped to RXq%u\n", prio, i);
2092 mask |= (1 << prio);
2093 pdata->prio2q_map[prio++] = i;
2094 }
2095
2096 if (i < ppq_extra) {
2097 netif_dbg(pdata, drv, pdata->netdev,
2098 "PRIO%u mapped to RXq%u\n", prio, i);
2099 mask |= (1 << prio);
2100 pdata->prio2q_map[prio++] = i;
2101 }
2102
2103 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2104
2105 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2106 continue;
2107
2108 XGMAC_IOWRITE(pdata, reg, reg_val);
2109 reg += MAC_RQC2_INC;
2110 reg_val = 0;
2111 }
2112
2113 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2114 reg = MTL_RQDCM0R;
2115 reg_val = 0;
2116 for (i = 0; i < pdata->rx_q_count;) {
2117 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2118
2119 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2120 continue;
2121
2122 XGMAC_IOWRITE(pdata, reg, reg_val);
2123
2124 reg += MTL_RQDCM_INC;
2125 reg_val = 0;
2126 }
2127 }
2128
2129 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2130 {
2131 unsigned int i;
2132
2133 for (i = 0; i < pdata->rx_q_count; i++) {
2134 /* Activate flow control when less than 4k left in fifo */
2135 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
2136
2137 /* De-activate flow control when more than 6k left in fifo */
2138 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
2139 }
2140 }
2141
2142 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2143 {
2144 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2145
2146 /* Filtering is done using perfect filtering and hash filtering */
2147 if (pdata->hw_feat.hash_table_size) {
2148 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2149 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2150 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2151 }
2152 }
2153
2154 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2155 {
2156 unsigned int val;
2157
2158 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2159
2160 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2161 }
2162
2163 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2164 {
2165 switch (pdata->phy_speed) {
2166 case SPEED_10000:
2167 xgbe_set_xgmii_speed(pdata);
2168 break;
2169
2170 case SPEED_2500:
2171 xgbe_set_gmii_2500_speed(pdata);
2172 break;
2173
2174 case SPEED_1000:
2175 xgbe_set_gmii_speed(pdata);
2176 break;
2177 }
2178 }
2179
2180 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2181 {
2182 if (pdata->netdev->features & NETIF_F_RXCSUM)
2183 xgbe_enable_rx_csum(pdata);
2184 else
2185 xgbe_disable_rx_csum(pdata);
2186 }
2187
2188 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2189 {
2190 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2191 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2192 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2193
2194 /* Set the current VLAN Hash Table register value */
2195 xgbe_update_vlan_hash_table(pdata);
2196
2197 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2198 xgbe_enable_rx_vlan_filtering(pdata);
2199 else
2200 xgbe_disable_rx_vlan_filtering(pdata);
2201
2202 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2203 xgbe_enable_rx_vlan_stripping(pdata);
2204 else
2205 xgbe_disable_rx_vlan_stripping(pdata);
2206 }
2207
2208 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2209 {
2210 bool read_hi;
2211 u64 val;
2212
2213 switch (reg_lo) {
2214 /* These registers are always 64 bit */
2215 case MMC_TXOCTETCOUNT_GB_LO:
2216 case MMC_TXOCTETCOUNT_G_LO:
2217 case MMC_RXOCTETCOUNT_GB_LO:
2218 case MMC_RXOCTETCOUNT_G_LO:
2219 read_hi = true;
2220 break;
2221
2222 default:
2223 read_hi = false;
2224 };
2225
2226 val = XGMAC_IOREAD(pdata, reg_lo);
2227
2228 if (read_hi)
2229 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2230
2231 return val;
2232 }
2233
2234 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2235 {
2236 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2237 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2238
2239 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2240 stats->txoctetcount_gb +=
2241 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2242
2243 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2244 stats->txframecount_gb +=
2245 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2246
2247 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2248 stats->txbroadcastframes_g +=
2249 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2250
2251 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2252 stats->txmulticastframes_g +=
2253 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2254
2255 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2256 stats->tx64octets_gb +=
2257 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2258
2259 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2260 stats->tx65to127octets_gb +=
2261 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2262
2263 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2264 stats->tx128to255octets_gb +=
2265 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2266
2267 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2268 stats->tx256to511octets_gb +=
2269 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2270
2271 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2272 stats->tx512to1023octets_gb +=
2273 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2274
2275 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2276 stats->tx1024tomaxoctets_gb +=
2277 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2278
2279 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2280 stats->txunicastframes_gb +=
2281 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2282
2283 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2284 stats->txmulticastframes_gb +=
2285 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2286
2287 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2288 stats->txbroadcastframes_g +=
2289 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2290
2291 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2292 stats->txunderflowerror +=
2293 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2294
2295 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2296 stats->txoctetcount_g +=
2297 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2298
2299 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2300 stats->txframecount_g +=
2301 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2302
2303 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2304 stats->txpauseframes +=
2305 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2306
2307 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2308 stats->txvlanframes_g +=
2309 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2310 }
2311
2312 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2313 {
2314 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2315 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2316
2317 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2318 stats->rxframecount_gb +=
2319 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2320
2321 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2322 stats->rxoctetcount_gb +=
2323 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2324
2325 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2326 stats->rxoctetcount_g +=
2327 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2328
2329 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2330 stats->rxbroadcastframes_g +=
2331 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2332
2333 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2334 stats->rxmulticastframes_g +=
2335 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2336
2337 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2338 stats->rxcrcerror +=
2339 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2340
2341 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2342 stats->rxrunterror +=
2343 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2344
2345 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2346 stats->rxjabbererror +=
2347 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2348
2349 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2350 stats->rxundersize_g +=
2351 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2352
2353 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2354 stats->rxoversize_g +=
2355 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2356
2357 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2358 stats->rx64octets_gb +=
2359 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2360
2361 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2362 stats->rx65to127octets_gb +=
2363 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2364
2365 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2366 stats->rx128to255octets_gb +=
2367 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2368
2369 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2370 stats->rx256to511octets_gb +=
2371 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2372
2373 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2374 stats->rx512to1023octets_gb +=
2375 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2376
2377 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2378 stats->rx1024tomaxoctets_gb +=
2379 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2380
2381 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2382 stats->rxunicastframes_g +=
2383 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2384
2385 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2386 stats->rxlengtherror +=
2387 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2388
2389 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2390 stats->rxoutofrangetype +=
2391 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2392
2393 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2394 stats->rxpauseframes +=
2395 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2396
2397 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2398 stats->rxfifooverflow +=
2399 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2400
2401 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2402 stats->rxvlanframes_gb +=
2403 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2404
2405 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2406 stats->rxwatchdogerror +=
2407 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2408 }
2409
2410 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2411 {
2412 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2413
2414 /* Freeze counters */
2415 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2416
2417 stats->txoctetcount_gb +=
2418 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2419
2420 stats->txframecount_gb +=
2421 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2422
2423 stats->txbroadcastframes_g +=
2424 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2425
2426 stats->txmulticastframes_g +=
2427 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2428
2429 stats->tx64octets_gb +=
2430 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2431
2432 stats->tx65to127octets_gb +=
2433 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2434
2435 stats->tx128to255octets_gb +=
2436 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2437
2438 stats->tx256to511octets_gb +=
2439 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2440
2441 stats->tx512to1023octets_gb +=
2442 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2443
2444 stats->tx1024tomaxoctets_gb +=
2445 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2446
2447 stats->txunicastframes_gb +=
2448 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2449
2450 stats->txmulticastframes_gb +=
2451 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2452
2453 stats->txbroadcastframes_g +=
2454 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2455
2456 stats->txunderflowerror +=
2457 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2458
2459 stats->txoctetcount_g +=
2460 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2461
2462 stats->txframecount_g +=
2463 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2464
2465 stats->txpauseframes +=
2466 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2467
2468 stats->txvlanframes_g +=
2469 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2470
2471 stats->rxframecount_gb +=
2472 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2473
2474 stats->rxoctetcount_gb +=
2475 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2476
2477 stats->rxoctetcount_g +=
2478 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2479
2480 stats->rxbroadcastframes_g +=
2481 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2482
2483 stats->rxmulticastframes_g +=
2484 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2485
2486 stats->rxcrcerror +=
2487 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2488
2489 stats->rxrunterror +=
2490 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2491
2492 stats->rxjabbererror +=
2493 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2494
2495 stats->rxundersize_g +=
2496 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2497
2498 stats->rxoversize_g +=
2499 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2500
2501 stats->rx64octets_gb +=
2502 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2503
2504 stats->rx65to127octets_gb +=
2505 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2506
2507 stats->rx128to255octets_gb +=
2508 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2509
2510 stats->rx256to511octets_gb +=
2511 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2512
2513 stats->rx512to1023octets_gb +=
2514 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2515
2516 stats->rx1024tomaxoctets_gb +=
2517 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2518
2519 stats->rxunicastframes_g +=
2520 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2521
2522 stats->rxlengtherror +=
2523 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2524
2525 stats->rxoutofrangetype +=
2526 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2527
2528 stats->rxpauseframes +=
2529 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2530
2531 stats->rxfifooverflow +=
2532 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2533
2534 stats->rxvlanframes_gb +=
2535 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2536
2537 stats->rxwatchdogerror +=
2538 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2539
2540 /* Un-freeze counters */
2541 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2542 }
2543
2544 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2545 {
2546 /* Set counters to reset on read */
2547 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2548
2549 /* Reset the counters */
2550 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2551 }
2552
2553 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
2554 struct xgbe_channel *channel)
2555 {
2556 unsigned int tx_dsr, tx_pos, tx_qidx;
2557 unsigned int tx_status;
2558 unsigned long tx_timeout;
2559
2560 /* Calculate the status register to read and the position within */
2561 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
2562 tx_dsr = DMA_DSR0;
2563 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
2564 DMA_DSR0_TPS_START;
2565 } else {
2566 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
2567
2568 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
2569 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
2570 DMA_DSRX_TPS_START;
2571 }
2572
2573 /* The Tx engine cannot be stopped if it is actively processing
2574 * descriptors. Wait for the Tx engine to enter the stopped or
2575 * suspended state. Don't wait forever though...
2576 */
2577 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2578 while (time_before(jiffies, tx_timeout)) {
2579 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2580 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
2581 if ((tx_status == DMA_TPS_STOPPED) ||
2582 (tx_status == DMA_TPS_SUSPENDED))
2583 break;
2584
2585 usleep_range(500, 1000);
2586 }
2587
2588 if (!time_before(jiffies, tx_timeout))
2589 netdev_info(pdata->netdev,
2590 "timed out waiting for Tx DMA channel %u to stop\n",
2591 channel->queue_index);
2592 }
2593
2594 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2595 {
2596 struct xgbe_channel *channel;
2597 unsigned int i;
2598
2599 /* Enable each Tx DMA channel */
2600 channel = pdata->channel;
2601 for (i = 0; i < pdata->channel_count; i++, channel++) {
2602 if (!channel->tx_ring)
2603 break;
2604
2605 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2606 }
2607
2608 /* Enable each Tx queue */
2609 for (i = 0; i < pdata->tx_q_count; i++)
2610 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2611 MTL_Q_ENABLED);
2612
2613 /* Enable MAC Tx */
2614 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2615 }
2616
2617 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2618 {
2619 struct xgbe_channel *channel;
2620 unsigned int i;
2621
2622 /* Prepare for Tx DMA channel stop */
2623 channel = pdata->channel;
2624 for (i = 0; i < pdata->channel_count; i++, channel++) {
2625 if (!channel->tx_ring)
2626 break;
2627
2628 xgbe_prepare_tx_stop(pdata, channel);
2629 }
2630
2631 /* Disable MAC Tx */
2632 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2633
2634 /* Disable each Tx queue */
2635 for (i = 0; i < pdata->tx_q_count; i++)
2636 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2637
2638 /* Disable each Tx DMA channel */
2639 channel = pdata->channel;
2640 for (i = 0; i < pdata->channel_count; i++, channel++) {
2641 if (!channel->tx_ring)
2642 break;
2643
2644 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2645 }
2646 }
2647
2648 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2649 {
2650 struct xgbe_channel *channel;
2651 unsigned int reg_val, i;
2652
2653 /* Enable each Rx DMA channel */
2654 channel = pdata->channel;
2655 for (i = 0; i < pdata->channel_count; i++, channel++) {
2656 if (!channel->rx_ring)
2657 break;
2658
2659 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2660 }
2661
2662 /* Enable each Rx queue */
2663 reg_val = 0;
2664 for (i = 0; i < pdata->rx_q_count; i++)
2665 reg_val |= (0x02 << (i << 1));
2666 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2667
2668 /* Enable MAC Rx */
2669 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2670 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2671 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2672 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2673 }
2674
2675 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2676 {
2677 struct xgbe_channel *channel;
2678 unsigned int i;
2679
2680 /* Disable MAC Rx */
2681 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2682 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2683 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2684 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2685
2686 /* Disable each Rx queue */
2687 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2688
2689 /* Disable each Rx DMA channel */
2690 channel = pdata->channel;
2691 for (i = 0; i < pdata->channel_count; i++, channel++) {
2692 if (!channel->rx_ring)
2693 break;
2694
2695 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2696 }
2697 }
2698
2699 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2700 {
2701 struct xgbe_channel *channel;
2702 unsigned int i;
2703
2704 /* Enable each Tx DMA channel */
2705 channel = pdata->channel;
2706 for (i = 0; i < pdata->channel_count; i++, channel++) {
2707 if (!channel->tx_ring)
2708 break;
2709
2710 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2711 }
2712
2713 /* Enable MAC Tx */
2714 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2715 }
2716
2717 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2718 {
2719 struct xgbe_channel *channel;
2720 unsigned int i;
2721
2722 /* Prepare for Tx DMA channel stop */
2723 channel = pdata->channel;
2724 for (i = 0; i < pdata->channel_count; i++, channel++) {
2725 if (!channel->tx_ring)
2726 break;
2727
2728 xgbe_prepare_tx_stop(pdata, channel);
2729 }
2730
2731 /* Disable MAC Tx */
2732 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2733
2734 /* Disable each Tx DMA channel */
2735 channel = pdata->channel;
2736 for (i = 0; i < pdata->channel_count; i++, channel++) {
2737 if (!channel->tx_ring)
2738 break;
2739
2740 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2741 }
2742 }
2743
2744 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2745 {
2746 struct xgbe_channel *channel;
2747 unsigned int i;
2748
2749 /* Enable each Rx DMA channel */
2750 channel = pdata->channel;
2751 for (i = 0; i < pdata->channel_count; i++, channel++) {
2752 if (!channel->rx_ring)
2753 break;
2754
2755 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2756 }
2757 }
2758
2759 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2760 {
2761 struct xgbe_channel *channel;
2762 unsigned int i;
2763
2764 /* Disable each Rx DMA channel */
2765 channel = pdata->channel;
2766 for (i = 0; i < pdata->channel_count; i++, channel++) {
2767 if (!channel->rx_ring)
2768 break;
2769
2770 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2771 }
2772 }
2773
2774 static int xgbe_init(struct xgbe_prv_data *pdata)
2775 {
2776 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2777 int ret;
2778
2779 DBGPR("-->xgbe_init\n");
2780
2781 /* Flush Tx queues */
2782 ret = xgbe_flush_tx_queues(pdata);
2783 if (ret)
2784 return ret;
2785
2786 /*
2787 * Initialize DMA related features
2788 */
2789 xgbe_config_dma_bus(pdata);
2790 xgbe_config_dma_cache(pdata);
2791 xgbe_config_osp_mode(pdata);
2792 xgbe_config_pblx8(pdata);
2793 xgbe_config_tx_pbl_val(pdata);
2794 xgbe_config_rx_pbl_val(pdata);
2795 xgbe_config_rx_coalesce(pdata);
2796 xgbe_config_tx_coalesce(pdata);
2797 xgbe_config_rx_buffer_size(pdata);
2798 xgbe_config_tso_mode(pdata);
2799 xgbe_config_sph_mode(pdata);
2800 xgbe_config_rss(pdata);
2801 desc_if->wrapper_tx_desc_init(pdata);
2802 desc_if->wrapper_rx_desc_init(pdata);
2803 xgbe_enable_dma_interrupts(pdata);
2804
2805 /*
2806 * Initialize MTL related features
2807 */
2808 xgbe_config_mtl_mode(pdata);
2809 xgbe_config_queue_mapping(pdata);
2810 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2811 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2812 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2813 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2814 xgbe_config_tx_fifo_size(pdata);
2815 xgbe_config_rx_fifo_size(pdata);
2816 xgbe_config_flow_control_threshold(pdata);
2817 /*TODO: Error Packet and undersized good Packet forwarding enable
2818 (FEP and FUP)
2819 */
2820 xgbe_config_dcb_tc(pdata);
2821 xgbe_config_dcb_pfc(pdata);
2822 xgbe_enable_mtl_interrupts(pdata);
2823
2824 /*
2825 * Initialize MAC related features
2826 */
2827 xgbe_config_mac_address(pdata);
2828 xgbe_config_rx_mode(pdata);
2829 xgbe_config_jumbo_enable(pdata);
2830 xgbe_config_flow_control(pdata);
2831 xgbe_config_mac_speed(pdata);
2832 xgbe_config_checksum_offload(pdata);
2833 xgbe_config_vlan_support(pdata);
2834 xgbe_config_mmc(pdata);
2835 xgbe_enable_mac_interrupts(pdata);
2836
2837 DBGPR("<--xgbe_init\n");
2838
2839 return 0;
2840 }
2841
2842 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2843 {
2844 DBGPR("-->xgbe_init_function_ptrs\n");
2845
2846 hw_if->tx_complete = xgbe_tx_complete;
2847
2848 hw_if->set_mac_address = xgbe_set_mac_address;
2849 hw_if->config_rx_mode = xgbe_config_rx_mode;
2850
2851 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2852 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2853
2854 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2855 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2856 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2857 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2858 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2859
2860 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2861 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2862
2863 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2864 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2865 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2866
2867 hw_if->enable_tx = xgbe_enable_tx;
2868 hw_if->disable_tx = xgbe_disable_tx;
2869 hw_if->enable_rx = xgbe_enable_rx;
2870 hw_if->disable_rx = xgbe_disable_rx;
2871
2872 hw_if->powerup_tx = xgbe_powerup_tx;
2873 hw_if->powerdown_tx = xgbe_powerdown_tx;
2874 hw_if->powerup_rx = xgbe_powerup_rx;
2875 hw_if->powerdown_rx = xgbe_powerdown_rx;
2876
2877 hw_if->dev_xmit = xgbe_dev_xmit;
2878 hw_if->dev_read = xgbe_dev_read;
2879 hw_if->enable_int = xgbe_enable_int;
2880 hw_if->disable_int = xgbe_disable_int;
2881 hw_if->init = xgbe_init;
2882 hw_if->exit = xgbe_exit;
2883
2884 /* Descriptor related Sequences have to be initialized here */
2885 hw_if->tx_desc_init = xgbe_tx_desc_init;
2886 hw_if->rx_desc_init = xgbe_rx_desc_init;
2887 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2888 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2889 hw_if->is_last_desc = xgbe_is_last_desc;
2890 hw_if->is_context_desc = xgbe_is_context_desc;
2891 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
2892
2893 /* For FLOW ctrl */
2894 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2895 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2896
2897 /* For RX coalescing */
2898 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2899 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2900 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2901 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2902
2903 /* For RX and TX threshold config */
2904 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2905 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2906
2907 /* For RX and TX Store and Forward Mode config */
2908 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2909 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2910
2911 /* For TX DMA Operating on Second Frame config */
2912 hw_if->config_osp_mode = xgbe_config_osp_mode;
2913
2914 /* For RX and TX PBL config */
2915 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2916 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2917 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2918 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2919 hw_if->config_pblx8 = xgbe_config_pblx8;
2920
2921 /* For MMC statistics support */
2922 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2923 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2924 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2925
2926 /* For PTP config */
2927 hw_if->config_tstamp = xgbe_config_tstamp;
2928 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2929 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2930 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2931 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2932
2933 /* For Data Center Bridging config */
2934 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2935 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2936
2937 /* For Receive Side Scaling */
2938 hw_if->enable_rss = xgbe_enable_rss;
2939 hw_if->disable_rss = xgbe_disable_rss;
2940 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2941 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
2942
2943 DBGPR("<--xgbe_init_function_ptrs\n");
2944 }
Linux kernel - Deliverables
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