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amd-xgbe: Rework the Rx path SKB allocation
[deliverable/linux.git] / drivers / net / ethernet / amd / xgbe / xgbe-drv.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/platform_device.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <net/busy_poll.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
126
127 #include "xgbe.h"
128 #include "xgbe-common.h"
129
130 static int xgbe_one_poll(struct napi_struct *, int);
131 static int xgbe_all_poll(struct napi_struct *, int);
132
133 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
134 {
135 struct xgbe_channel *channel_mem, *channel;
136 struct xgbe_ring *tx_ring, *rx_ring;
137 unsigned int count, i;
138 int ret = -ENOMEM;
139
140 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
141
142 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
143 if (!channel_mem)
144 goto err_channel;
145
146 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
147 GFP_KERNEL);
148 if (!tx_ring)
149 goto err_tx_ring;
150
151 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
152 GFP_KERNEL);
153 if (!rx_ring)
154 goto err_rx_ring;
155
156 for (i = 0, channel = channel_mem; i < count; i++, channel++) {
157 snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
158 channel->pdata = pdata;
159 channel->queue_index = i;
160 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
161 (DMA_CH_INC * i);
162
163 if (pdata->per_channel_irq) {
164 /* Get the DMA interrupt (offset 1) */
165 ret = platform_get_irq(pdata->pdev, i + 1);
166 if (ret < 0) {
167 netdev_err(pdata->netdev,
168 "platform_get_irq %u failed\n",
169 i + 1);
170 goto err_irq;
171 }
172
173 channel->dma_irq = ret;
174 }
175
176 if (i < pdata->tx_ring_count) {
177 spin_lock_init(&tx_ring->lock);
178 channel->tx_ring = tx_ring++;
179 }
180
181 if (i < pdata->rx_ring_count) {
182 spin_lock_init(&rx_ring->lock);
183 channel->rx_ring = rx_ring++;
184 }
185
186 netif_dbg(pdata, drv, pdata->netdev,
187 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
188 channel->name, channel->dma_regs, channel->dma_irq,
189 channel->tx_ring, channel->rx_ring);
190 }
191
192 pdata->channel = channel_mem;
193 pdata->channel_count = count;
194
195 return 0;
196
197 err_irq:
198 kfree(rx_ring);
199
200 err_rx_ring:
201 kfree(tx_ring);
202
203 err_tx_ring:
204 kfree(channel_mem);
205
206 err_channel:
207 return ret;
208 }
209
210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
211 {
212 if (!pdata->channel)
213 return;
214
215 kfree(pdata->channel->rx_ring);
216 kfree(pdata->channel->tx_ring);
217 kfree(pdata->channel);
218
219 pdata->channel = NULL;
220 pdata->channel_count = 0;
221 }
222
223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
224 {
225 return (ring->rdesc_count - (ring->cur - ring->dirty));
226 }
227
228 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
229 {
230 return (ring->cur - ring->dirty);
231 }
232
233 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
234 struct xgbe_ring *ring, unsigned int count)
235 {
236 struct xgbe_prv_data *pdata = channel->pdata;
237
238 if (count > xgbe_tx_avail_desc(ring)) {
239 netif_info(pdata, drv, pdata->netdev,
240 "Tx queue stopped, not enough descriptors available\n");
241 netif_stop_subqueue(pdata->netdev, channel->queue_index);
242 ring->tx.queue_stopped = 1;
243
244 /* If we haven't notified the hardware because of xmit_more
245 * support, tell it now
246 */
247 if (ring->tx.xmit_more)
248 pdata->hw_if.tx_start_xmit(channel, ring);
249
250 return NETDEV_TX_BUSY;
251 }
252
253 return 0;
254 }
255
256 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
257 {
258 unsigned int rx_buf_size;
259
260 if (mtu > XGMAC_JUMBO_PACKET_MTU) {
261 netdev_alert(netdev, "MTU exceeds maximum supported value\n");
262 return -EINVAL;
263 }
264
265 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
266 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
267
268 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
269 ~(XGBE_RX_BUF_ALIGN - 1);
270
271 return rx_buf_size;
272 }
273
274 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
275 {
276 struct xgbe_hw_if *hw_if = &pdata->hw_if;
277 struct xgbe_channel *channel;
278 enum xgbe_int int_id;
279 unsigned int i;
280
281 channel = pdata->channel;
282 for (i = 0; i < pdata->channel_count; i++, channel++) {
283 if (channel->tx_ring && channel->rx_ring)
284 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
285 else if (channel->tx_ring)
286 int_id = XGMAC_INT_DMA_CH_SR_TI;
287 else if (channel->rx_ring)
288 int_id = XGMAC_INT_DMA_CH_SR_RI;
289 else
290 continue;
291
292 hw_if->enable_int(channel, int_id);
293 }
294 }
295
296 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
297 {
298 struct xgbe_hw_if *hw_if = &pdata->hw_if;
299 struct xgbe_channel *channel;
300 enum xgbe_int int_id;
301 unsigned int i;
302
303 channel = pdata->channel;
304 for (i = 0; i < pdata->channel_count; i++, channel++) {
305 if (channel->tx_ring && channel->rx_ring)
306 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
307 else if (channel->tx_ring)
308 int_id = XGMAC_INT_DMA_CH_SR_TI;
309 else if (channel->rx_ring)
310 int_id = XGMAC_INT_DMA_CH_SR_RI;
311 else
312 continue;
313
314 hw_if->disable_int(channel, int_id);
315 }
316 }
317
318 static irqreturn_t xgbe_isr(int irq, void *data)
319 {
320 struct xgbe_prv_data *pdata = data;
321 struct xgbe_hw_if *hw_if = &pdata->hw_if;
322 struct xgbe_channel *channel;
323 unsigned int dma_isr, dma_ch_isr;
324 unsigned int mac_isr, mac_tssr;
325 unsigned int i;
326
327 /* The DMA interrupt status register also reports MAC and MTL
328 * interrupts. So for polling mode, we just need to check for
329 * this register to be non-zero
330 */
331 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
332 if (!dma_isr)
333 goto isr_done;
334
335 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
336
337 for (i = 0; i < pdata->channel_count; i++) {
338 if (!(dma_isr & (1 << i)))
339 continue;
340
341 channel = pdata->channel + i;
342
343 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
344 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
345 i, dma_ch_isr);
346
347 /* The TI or RI interrupt bits may still be set even if using
348 * per channel DMA interrupts. Check to be sure those are not
349 * enabled before using the private data napi structure.
350 */
351 if (!pdata->per_channel_irq &&
352 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
353 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
354 if (napi_schedule_prep(&pdata->napi)) {
355 /* Disable Tx and Rx interrupts */
356 xgbe_disable_rx_tx_ints(pdata);
357
358 /* Turn on polling */
359 __napi_schedule(&pdata->napi);
360 }
361 }
362
363 /* Restart the device on a Fatal Bus Error */
364 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
365 schedule_work(&pdata->restart_work);
366
367 /* Clear all interrupt signals */
368 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
369 }
370
371 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
372 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
373
374 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
375 hw_if->tx_mmc_int(pdata);
376
377 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
378 hw_if->rx_mmc_int(pdata);
379
380 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
381 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
382
383 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
384 /* Read Tx Timestamp to clear interrupt */
385 pdata->tx_tstamp =
386 hw_if->get_tx_tstamp(pdata);
387 schedule_work(&pdata->tx_tstamp_work);
388 }
389 }
390 }
391
392 isr_done:
393 return IRQ_HANDLED;
394 }
395
396 static irqreturn_t xgbe_dma_isr(int irq, void *data)
397 {
398 struct xgbe_channel *channel = data;
399
400 /* Per channel DMA interrupts are enabled, so we use the per
401 * channel napi structure and not the private data napi structure
402 */
403 if (napi_schedule_prep(&channel->napi)) {
404 /* Disable Tx and Rx interrupts */
405 disable_irq_nosync(channel->dma_irq);
406
407 /* Turn on polling */
408 __napi_schedule(&channel->napi);
409 }
410
411 return IRQ_HANDLED;
412 }
413
414 static void xgbe_tx_timer(unsigned long data)
415 {
416 struct xgbe_channel *channel = (struct xgbe_channel *)data;
417 struct xgbe_prv_data *pdata = channel->pdata;
418 struct napi_struct *napi;
419
420 DBGPR("-->xgbe_tx_timer\n");
421
422 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
423
424 if (napi_schedule_prep(napi)) {
425 /* Disable Tx and Rx interrupts */
426 if (pdata->per_channel_irq)
427 disable_irq(channel->dma_irq);
428 else
429 xgbe_disable_rx_tx_ints(pdata);
430
431 /* Turn on polling */
432 __napi_schedule(napi);
433 }
434
435 channel->tx_timer_active = 0;
436
437 DBGPR("<--xgbe_tx_timer\n");
438 }
439
440 static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
441 {
442 struct xgbe_channel *channel;
443 unsigned int i;
444
445 DBGPR("-->xgbe_init_tx_timers\n");
446
447 channel = pdata->channel;
448 for (i = 0; i < pdata->channel_count; i++, channel++) {
449 if (!channel->tx_ring)
450 break;
451
452 setup_timer(&channel->tx_timer, xgbe_tx_timer,
453 (unsigned long)channel);
454 }
455
456 DBGPR("<--xgbe_init_tx_timers\n");
457 }
458
459 static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata)
460 {
461 struct xgbe_channel *channel;
462 unsigned int i;
463
464 DBGPR("-->xgbe_stop_tx_timers\n");
465
466 channel = pdata->channel;
467 for (i = 0; i < pdata->channel_count; i++, channel++) {
468 if (!channel->tx_ring)
469 break;
470
471 del_timer_sync(&channel->tx_timer);
472 }
473
474 DBGPR("<--xgbe_stop_tx_timers\n");
475 }
476
477 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
478 {
479 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
480 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
481
482 DBGPR("-->xgbe_get_all_hw_features\n");
483
484 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
485 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
486 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
487
488 memset(hw_feat, 0, sizeof(*hw_feat));
489
490 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
491
492 /* Hardware feature register 0 */
493 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
494 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
495 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
496 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
497 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
498 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
499 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
500 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
501 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
502 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
503 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
504 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
505 ADDMACADRSEL);
506 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
507 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
508
509 /* Hardware feature register 1 */
510 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
511 RXFIFOSIZE);
512 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
513 TXFIFOSIZE);
514 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
515 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
516 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
517 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
518 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
519 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
520 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
521 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
522 HASHTBLSZ);
523 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
524 L3L4FNUM);
525
526 /* Hardware feature register 2 */
527 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
528 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
529 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
530 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
531 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
532 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
533
534 /* Translate the Hash Table size into actual number */
535 switch (hw_feat->hash_table_size) {
536 case 0:
537 break;
538 case 1:
539 hw_feat->hash_table_size = 64;
540 break;
541 case 2:
542 hw_feat->hash_table_size = 128;
543 break;
544 case 3:
545 hw_feat->hash_table_size = 256;
546 break;
547 }
548
549 /* Translate the address width setting into actual number */
550 switch (hw_feat->dma_width) {
551 case 0:
552 hw_feat->dma_width = 32;
553 break;
554 case 1:
555 hw_feat->dma_width = 40;
556 break;
557 case 2:
558 hw_feat->dma_width = 48;
559 break;
560 default:
561 hw_feat->dma_width = 32;
562 }
563
564 /* The Queue, Channel and TC counts are zero based so increment them
565 * to get the actual number
566 */
567 hw_feat->rx_q_cnt++;
568 hw_feat->tx_q_cnt++;
569 hw_feat->rx_ch_cnt++;
570 hw_feat->tx_ch_cnt++;
571 hw_feat->tc_cnt++;
572
573 DBGPR("<--xgbe_get_all_hw_features\n");
574 }
575
576 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
577 {
578 struct xgbe_channel *channel;
579 unsigned int i;
580
581 if (pdata->per_channel_irq) {
582 channel = pdata->channel;
583 for (i = 0; i < pdata->channel_count; i++, channel++) {
584 if (add)
585 netif_napi_add(pdata->netdev, &channel->napi,
586 xgbe_one_poll, NAPI_POLL_WEIGHT);
587
588 napi_enable(&channel->napi);
589 }
590 } else {
591 if (add)
592 netif_napi_add(pdata->netdev, &pdata->napi,
593 xgbe_all_poll, NAPI_POLL_WEIGHT);
594
595 napi_enable(&pdata->napi);
596 }
597 }
598
599 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
600 {
601 struct xgbe_channel *channel;
602 unsigned int i;
603
604 if (pdata->per_channel_irq) {
605 channel = pdata->channel;
606 for (i = 0; i < pdata->channel_count; i++, channel++) {
607 napi_disable(&channel->napi);
608
609 if (del)
610 netif_napi_del(&channel->napi);
611 }
612 } else {
613 napi_disable(&pdata->napi);
614
615 if (del)
616 netif_napi_del(&pdata->napi);
617 }
618 }
619
620 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
621 {
622 struct xgbe_channel *channel;
623 struct net_device *netdev = pdata->netdev;
624 unsigned int i;
625 int ret;
626
627 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
628 netdev->name, pdata);
629 if (ret) {
630 netdev_alert(netdev, "error requesting irq %d\n",
631 pdata->dev_irq);
632 return ret;
633 }
634
635 if (!pdata->per_channel_irq)
636 return 0;
637
638 channel = pdata->channel;
639 for (i = 0; i < pdata->channel_count; i++, channel++) {
640 snprintf(channel->dma_irq_name,
641 sizeof(channel->dma_irq_name) - 1,
642 "%s-TxRx-%u", netdev_name(netdev),
643 channel->queue_index);
644
645 ret = devm_request_irq(pdata->dev, channel->dma_irq,
646 xgbe_dma_isr, 0,
647 channel->dma_irq_name, channel);
648 if (ret) {
649 netdev_alert(netdev, "error requesting irq %d\n",
650 channel->dma_irq);
651 goto err_irq;
652 }
653 }
654
655 return 0;
656
657 err_irq:
658 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
659 for (i--, channel--; i < pdata->channel_count; i--, channel--)
660 devm_free_irq(pdata->dev, channel->dma_irq, channel);
661
662 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
663
664 return ret;
665 }
666
667 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
668 {
669 struct xgbe_channel *channel;
670 unsigned int i;
671
672 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
673
674 if (!pdata->per_channel_irq)
675 return;
676
677 channel = pdata->channel;
678 for (i = 0; i < pdata->channel_count; i++, channel++)
679 devm_free_irq(pdata->dev, channel->dma_irq, channel);
680 }
681
682 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
683 {
684 struct xgbe_hw_if *hw_if = &pdata->hw_if;
685
686 DBGPR("-->xgbe_init_tx_coalesce\n");
687
688 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
689 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
690
691 hw_if->config_tx_coalesce(pdata);
692
693 DBGPR("<--xgbe_init_tx_coalesce\n");
694 }
695
696 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
697 {
698 struct xgbe_hw_if *hw_if = &pdata->hw_if;
699
700 DBGPR("-->xgbe_init_rx_coalesce\n");
701
702 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
703 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
704 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
705
706 hw_if->config_rx_coalesce(pdata);
707
708 DBGPR("<--xgbe_init_rx_coalesce\n");
709 }
710
711 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
712 {
713 struct xgbe_desc_if *desc_if = &pdata->desc_if;
714 struct xgbe_channel *channel;
715 struct xgbe_ring *ring;
716 struct xgbe_ring_data *rdata;
717 unsigned int i, j;
718
719 DBGPR("-->xgbe_free_tx_data\n");
720
721 channel = pdata->channel;
722 for (i = 0; i < pdata->channel_count; i++, channel++) {
723 ring = channel->tx_ring;
724 if (!ring)
725 break;
726
727 for (j = 0; j < ring->rdesc_count; j++) {
728 rdata = XGBE_GET_DESC_DATA(ring, j);
729 desc_if->unmap_rdata(pdata, rdata);
730 }
731 }
732
733 DBGPR("<--xgbe_free_tx_data\n");
734 }
735
736 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
737 {
738 struct xgbe_desc_if *desc_if = &pdata->desc_if;
739 struct xgbe_channel *channel;
740 struct xgbe_ring *ring;
741 struct xgbe_ring_data *rdata;
742 unsigned int i, j;
743
744 DBGPR("-->xgbe_free_rx_data\n");
745
746 channel = pdata->channel;
747 for (i = 0; i < pdata->channel_count; i++, channel++) {
748 ring = channel->rx_ring;
749 if (!ring)
750 break;
751
752 for (j = 0; j < ring->rdesc_count; j++) {
753 rdata = XGBE_GET_DESC_DATA(ring, j);
754 desc_if->unmap_rdata(pdata, rdata);
755 }
756 }
757
758 DBGPR("<--xgbe_free_rx_data\n");
759 }
760
761 static void xgbe_adjust_link(struct net_device *netdev)
762 {
763 struct xgbe_prv_data *pdata = netdev_priv(netdev);
764 struct xgbe_hw_if *hw_if = &pdata->hw_if;
765 struct phy_device *phydev = pdata->phydev;
766 int new_state = 0;
767
768 if (!phydev)
769 return;
770
771 if (phydev->link) {
772 /* Flow control support */
773 if (pdata->pause_autoneg) {
774 if (phydev->pause || phydev->asym_pause) {
775 pdata->tx_pause = 1;
776 pdata->rx_pause = 1;
777 } else {
778 pdata->tx_pause = 0;
779 pdata->rx_pause = 0;
780 }
781 }
782
783 if (pdata->tx_pause != pdata->phy_tx_pause) {
784 hw_if->config_tx_flow_control(pdata);
785 pdata->phy_tx_pause = pdata->tx_pause;
786 }
787
788 if (pdata->rx_pause != pdata->phy_rx_pause) {
789 hw_if->config_rx_flow_control(pdata);
790 pdata->phy_rx_pause = pdata->rx_pause;
791 }
792
793 /* Speed support */
794 if (phydev->speed != pdata->phy_speed) {
795 new_state = 1;
796
797 switch (phydev->speed) {
798 case SPEED_10000:
799 hw_if->set_xgmii_speed(pdata);
800 break;
801
802 case SPEED_2500:
803 hw_if->set_gmii_2500_speed(pdata);
804 break;
805
806 case SPEED_1000:
807 hw_if->set_gmii_speed(pdata);
808 break;
809 }
810 pdata->phy_speed = phydev->speed;
811 }
812
813 if (phydev->link != pdata->phy_link) {
814 new_state = 1;
815 pdata->phy_link = 1;
816 }
817 } else if (pdata->phy_link) {
818 new_state = 1;
819 pdata->phy_link = 0;
820 pdata->phy_speed = SPEED_UNKNOWN;
821 }
822
823 if (new_state)
824 phy_print_status(phydev);
825 }
826
827 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
828 {
829 struct net_device *netdev = pdata->netdev;
830 struct phy_device *phydev = pdata->phydev;
831 int ret;
832
833 pdata->phy_link = -1;
834 pdata->phy_speed = SPEED_UNKNOWN;
835 pdata->phy_tx_pause = pdata->tx_pause;
836 pdata->phy_rx_pause = pdata->rx_pause;
837
838 ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link,
839 pdata->phy_mode);
840 if (ret) {
841 netdev_err(netdev, "phy_connect_direct failed\n");
842 return ret;
843 }
844
845 if (!phydev->drv || (phydev->drv->phy_id == 0)) {
846 netdev_err(netdev, "phy_id not valid\n");
847 ret = -ENODEV;
848 goto err_phy_connect;
849 }
850 netif_dbg(pdata, ifup, pdata->netdev,
851 "phy_connect_direct succeeded for PHY %s\n",
852 dev_name(&phydev->dev));
853
854 return 0;
855
856 err_phy_connect:
857 phy_disconnect(phydev);
858
859 return ret;
860 }
861
862 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
863 {
864 if (!pdata->phydev)
865 return;
866
867 phy_disconnect(pdata->phydev);
868 }
869
870 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
871 {
872 struct xgbe_prv_data *pdata = netdev_priv(netdev);
873 struct xgbe_hw_if *hw_if = &pdata->hw_if;
874 unsigned long flags;
875
876 DBGPR("-->xgbe_powerdown\n");
877
878 if (!netif_running(netdev) ||
879 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
880 netdev_alert(netdev, "Device is already powered down\n");
881 DBGPR("<--xgbe_powerdown\n");
882 return -EINVAL;
883 }
884
885 spin_lock_irqsave(&pdata->lock, flags);
886
887 if (caller == XGMAC_DRIVER_CONTEXT)
888 netif_device_detach(netdev);
889
890 netif_tx_stop_all_queues(netdev);
891
892 hw_if->powerdown_tx(pdata);
893 hw_if->powerdown_rx(pdata);
894
895 xgbe_napi_disable(pdata, 0);
896
897 phy_stop(pdata->phydev);
898
899 pdata->power_down = 1;
900
901 spin_unlock_irqrestore(&pdata->lock, flags);
902
903 DBGPR("<--xgbe_powerdown\n");
904
905 return 0;
906 }
907
908 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
909 {
910 struct xgbe_prv_data *pdata = netdev_priv(netdev);
911 struct xgbe_hw_if *hw_if = &pdata->hw_if;
912 unsigned long flags;
913
914 DBGPR("-->xgbe_powerup\n");
915
916 if (!netif_running(netdev) ||
917 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
918 netdev_alert(netdev, "Device is already powered up\n");
919 DBGPR("<--xgbe_powerup\n");
920 return -EINVAL;
921 }
922
923 spin_lock_irqsave(&pdata->lock, flags);
924
925 pdata->power_down = 0;
926
927 phy_start(pdata->phydev);
928
929 xgbe_napi_enable(pdata, 0);
930
931 hw_if->powerup_tx(pdata);
932 hw_if->powerup_rx(pdata);
933
934 if (caller == XGMAC_DRIVER_CONTEXT)
935 netif_device_attach(netdev);
936
937 netif_tx_start_all_queues(netdev);
938
939 spin_unlock_irqrestore(&pdata->lock, flags);
940
941 DBGPR("<--xgbe_powerup\n");
942
943 return 0;
944 }
945
946 static int xgbe_start(struct xgbe_prv_data *pdata)
947 {
948 struct xgbe_hw_if *hw_if = &pdata->hw_if;
949 struct net_device *netdev = pdata->netdev;
950 int ret;
951
952 DBGPR("-->xgbe_start\n");
953
954 hw_if->init(pdata);
955
956 phy_start(pdata->phydev);
957
958 xgbe_napi_enable(pdata, 1);
959
960 ret = xgbe_request_irqs(pdata);
961 if (ret)
962 goto err_napi;
963
964 hw_if->enable_tx(pdata);
965 hw_if->enable_rx(pdata);
966
967 xgbe_init_tx_timers(pdata);
968
969 netif_tx_start_all_queues(netdev);
970
971 DBGPR("<--xgbe_start\n");
972
973 return 0;
974
975 err_napi:
976 xgbe_napi_disable(pdata, 1);
977
978 phy_stop(pdata->phydev);
979
980 hw_if->exit(pdata);
981
982 return ret;
983 }
984
985 static void xgbe_stop(struct xgbe_prv_data *pdata)
986 {
987 struct xgbe_hw_if *hw_if = &pdata->hw_if;
988 struct xgbe_channel *channel;
989 struct net_device *netdev = pdata->netdev;
990 struct netdev_queue *txq;
991 unsigned int i;
992
993 DBGPR("-->xgbe_stop\n");
994
995 netif_tx_stop_all_queues(netdev);
996
997 xgbe_stop_tx_timers(pdata);
998
999 hw_if->disable_tx(pdata);
1000 hw_if->disable_rx(pdata);
1001
1002 xgbe_free_irqs(pdata);
1003
1004 xgbe_napi_disable(pdata, 1);
1005
1006 phy_stop(pdata->phydev);
1007
1008 hw_if->exit(pdata);
1009
1010 channel = pdata->channel;
1011 for (i = 0; i < pdata->channel_count; i++, channel++) {
1012 if (!channel->tx_ring)
1013 continue;
1014
1015 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1016 netdev_tx_reset_queue(txq);
1017 }
1018
1019 DBGPR("<--xgbe_stop\n");
1020 }
1021
1022 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1023 {
1024 DBGPR("-->xgbe_restart_dev\n");
1025
1026 /* If not running, "restart" will happen on open */
1027 if (!netif_running(pdata->netdev))
1028 return;
1029
1030 xgbe_stop(pdata);
1031
1032 xgbe_free_tx_data(pdata);
1033 xgbe_free_rx_data(pdata);
1034
1035 xgbe_start(pdata);
1036
1037 DBGPR("<--xgbe_restart_dev\n");
1038 }
1039
1040 static void xgbe_restart(struct work_struct *work)
1041 {
1042 struct xgbe_prv_data *pdata = container_of(work,
1043 struct xgbe_prv_data,
1044 restart_work);
1045
1046 rtnl_lock();
1047
1048 xgbe_restart_dev(pdata);
1049
1050 rtnl_unlock();
1051 }
1052
1053 static void xgbe_tx_tstamp(struct work_struct *work)
1054 {
1055 struct xgbe_prv_data *pdata = container_of(work,
1056 struct xgbe_prv_data,
1057 tx_tstamp_work);
1058 struct skb_shared_hwtstamps hwtstamps;
1059 u64 nsec;
1060 unsigned long flags;
1061
1062 if (pdata->tx_tstamp) {
1063 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1064 pdata->tx_tstamp);
1065
1066 memset(&hwtstamps, 0, sizeof(hwtstamps));
1067 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1068 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1069 }
1070
1071 dev_kfree_skb_any(pdata->tx_tstamp_skb);
1072
1073 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1074 pdata->tx_tstamp_skb = NULL;
1075 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1076 }
1077
1078 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1079 struct ifreq *ifreq)
1080 {
1081 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1082 sizeof(pdata->tstamp_config)))
1083 return -EFAULT;
1084
1085 return 0;
1086 }
1087
1088 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1089 struct ifreq *ifreq)
1090 {
1091 struct hwtstamp_config config;
1092 unsigned int mac_tscr;
1093
1094 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1095 return -EFAULT;
1096
1097 if (config.flags)
1098 return -EINVAL;
1099
1100 mac_tscr = 0;
1101
1102 switch (config.tx_type) {
1103 case HWTSTAMP_TX_OFF:
1104 break;
1105
1106 case HWTSTAMP_TX_ON:
1107 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1108 break;
1109
1110 default:
1111 return -ERANGE;
1112 }
1113
1114 switch (config.rx_filter) {
1115 case HWTSTAMP_FILTER_NONE:
1116 break;
1117
1118 case HWTSTAMP_FILTER_ALL:
1119 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1120 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1121 break;
1122
1123 /* PTP v2, UDP, any kind of event packet */
1124 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1125 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1126 /* PTP v1, UDP, any kind of event packet */
1127 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1128 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1129 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1130 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1131 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1132 break;
1133
1134 /* PTP v2, UDP, Sync packet */
1135 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1136 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1137 /* PTP v1, UDP, Sync packet */
1138 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1139 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1140 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1141 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1142 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1143 break;
1144
1145 /* PTP v2, UDP, Delay_req packet */
1146 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1147 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1148 /* PTP v1, UDP, Delay_req packet */
1149 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1150 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1151 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1152 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1153 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1154 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1155 break;
1156
1157 /* 802.AS1, Ethernet, any kind of event packet */
1158 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1159 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1160 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1161 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1162 break;
1163
1164 /* 802.AS1, Ethernet, Sync packet */
1165 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1166 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1167 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1168 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1169 break;
1170
1171 /* 802.AS1, Ethernet, Delay_req packet */
1172 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1173 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1174 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1175 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1176 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1177 break;
1178
1179 /* PTP v2/802.AS1, any layer, any kind of event packet */
1180 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1181 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1182 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1183 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1184 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1185 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1186 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1187 break;
1188
1189 /* PTP v2/802.AS1, any layer, Sync packet */
1190 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1191 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1192 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1193 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1194 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1195 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1196 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1197 break;
1198
1199 /* PTP v2/802.AS1, any layer, Delay_req packet */
1200 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1201 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1202 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1203 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1204 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1205 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1206 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1207 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1208 break;
1209
1210 default:
1211 return -ERANGE;
1212 }
1213
1214 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1215
1216 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1217
1218 return 0;
1219 }
1220
1221 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1222 struct sk_buff *skb,
1223 struct xgbe_packet_data *packet)
1224 {
1225 unsigned long flags;
1226
1227 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1228 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1229 if (pdata->tx_tstamp_skb) {
1230 /* Another timestamp in progress, ignore this one */
1231 XGMAC_SET_BITS(packet->attributes,
1232 TX_PACKET_ATTRIBUTES, PTP, 0);
1233 } else {
1234 pdata->tx_tstamp_skb = skb_get(skb);
1235 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1236 }
1237 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1238 }
1239
1240 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1241 skb_tx_timestamp(skb);
1242 }
1243
1244 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1245 {
1246 if (skb_vlan_tag_present(skb))
1247 packet->vlan_ctag = skb_vlan_tag_get(skb);
1248 }
1249
1250 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1251 {
1252 int ret;
1253
1254 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1255 TSO_ENABLE))
1256 return 0;
1257
1258 ret = skb_cow_head(skb, 0);
1259 if (ret)
1260 return ret;
1261
1262 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1263 packet->tcp_header_len = tcp_hdrlen(skb);
1264 packet->tcp_payload_len = skb->len - packet->header_len;
1265 packet->mss = skb_shinfo(skb)->gso_size;
1266 DBGPR(" packet->header_len=%u\n", packet->header_len);
1267 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1268 packet->tcp_header_len, packet->tcp_payload_len);
1269 DBGPR(" packet->mss=%u\n", packet->mss);
1270
1271 /* Update the number of packets that will ultimately be transmitted
1272 * along with the extra bytes for each extra packet
1273 */
1274 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1275 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1276
1277 return 0;
1278 }
1279
1280 static int xgbe_is_tso(struct sk_buff *skb)
1281 {
1282 if (skb->ip_summed != CHECKSUM_PARTIAL)
1283 return 0;
1284
1285 if (!skb_is_gso(skb))
1286 return 0;
1287
1288 DBGPR(" TSO packet to be processed\n");
1289
1290 return 1;
1291 }
1292
1293 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1294 struct xgbe_ring *ring, struct sk_buff *skb,
1295 struct xgbe_packet_data *packet)
1296 {
1297 struct skb_frag_struct *frag;
1298 unsigned int context_desc;
1299 unsigned int len;
1300 unsigned int i;
1301
1302 packet->skb = skb;
1303
1304 context_desc = 0;
1305 packet->rdesc_count = 0;
1306
1307 packet->tx_packets = 1;
1308 packet->tx_bytes = skb->len;
1309
1310 if (xgbe_is_tso(skb)) {
1311 /* TSO requires an extra descriptor if mss is different */
1312 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1313 context_desc = 1;
1314 packet->rdesc_count++;
1315 }
1316
1317 /* TSO requires an extra descriptor for TSO header */
1318 packet->rdesc_count++;
1319
1320 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1321 TSO_ENABLE, 1);
1322 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1323 CSUM_ENABLE, 1);
1324 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1325 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1326 CSUM_ENABLE, 1);
1327
1328 if (skb_vlan_tag_present(skb)) {
1329 /* VLAN requires an extra descriptor if tag is different */
1330 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1331 /* We can share with the TSO context descriptor */
1332 if (!context_desc) {
1333 context_desc = 1;
1334 packet->rdesc_count++;
1335 }
1336
1337 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1338 VLAN_CTAG, 1);
1339 }
1340
1341 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1342 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1343 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1344 PTP, 1);
1345
1346 for (len = skb_headlen(skb); len;) {
1347 packet->rdesc_count++;
1348 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1349 }
1350
1351 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1352 frag = &skb_shinfo(skb)->frags[i];
1353 for (len = skb_frag_size(frag); len; ) {
1354 packet->rdesc_count++;
1355 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1356 }
1357 }
1358 }
1359
1360 static int xgbe_open(struct net_device *netdev)
1361 {
1362 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1363 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1364 int ret;
1365
1366 DBGPR("-->xgbe_open\n");
1367
1368 /* Initialize the phy */
1369 ret = xgbe_phy_init(pdata);
1370 if (ret)
1371 return ret;
1372
1373 /* Enable the clocks */
1374 ret = clk_prepare_enable(pdata->sysclk);
1375 if (ret) {
1376 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1377 goto err_phy_init;
1378 }
1379
1380 ret = clk_prepare_enable(pdata->ptpclk);
1381 if (ret) {
1382 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1383 goto err_sysclk;
1384 }
1385
1386 /* Calculate the Rx buffer size before allocating rings */
1387 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1388 if (ret < 0)
1389 goto err_ptpclk;
1390 pdata->rx_buf_size = ret;
1391
1392 /* Allocate the channel and ring structures */
1393 ret = xgbe_alloc_channels(pdata);
1394 if (ret)
1395 goto err_ptpclk;
1396
1397 /* Allocate the ring descriptors and buffers */
1398 ret = desc_if->alloc_ring_resources(pdata);
1399 if (ret)
1400 goto err_channels;
1401
1402 /* Initialize the device restart and Tx timestamp work struct */
1403 INIT_WORK(&pdata->restart_work, xgbe_restart);
1404 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1405
1406 ret = xgbe_start(pdata);
1407 if (ret)
1408 goto err_rings;
1409
1410 DBGPR("<--xgbe_open\n");
1411
1412 return 0;
1413
1414 err_rings:
1415 desc_if->free_ring_resources(pdata);
1416
1417 err_channels:
1418 xgbe_free_channels(pdata);
1419
1420 err_ptpclk:
1421 clk_disable_unprepare(pdata->ptpclk);
1422
1423 err_sysclk:
1424 clk_disable_unprepare(pdata->sysclk);
1425
1426 err_phy_init:
1427 xgbe_phy_exit(pdata);
1428
1429 return ret;
1430 }
1431
1432 static int xgbe_close(struct net_device *netdev)
1433 {
1434 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1435 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1436
1437 DBGPR("-->xgbe_close\n");
1438
1439 /* Stop the device */
1440 xgbe_stop(pdata);
1441
1442 /* Free the ring descriptors and buffers */
1443 desc_if->free_ring_resources(pdata);
1444
1445 /* Free the channel and ring structures */
1446 xgbe_free_channels(pdata);
1447
1448 /* Disable the clocks */
1449 clk_disable_unprepare(pdata->ptpclk);
1450 clk_disable_unprepare(pdata->sysclk);
1451
1452 /* Release the phy */
1453 xgbe_phy_exit(pdata);
1454
1455 DBGPR("<--xgbe_close\n");
1456
1457 return 0;
1458 }
1459
1460 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1461 {
1462 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1463 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1464 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1465 struct xgbe_channel *channel;
1466 struct xgbe_ring *ring;
1467 struct xgbe_packet_data *packet;
1468 struct netdev_queue *txq;
1469 int ret;
1470
1471 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1472
1473 channel = pdata->channel + skb->queue_mapping;
1474 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1475 ring = channel->tx_ring;
1476 packet = &ring->packet_data;
1477
1478 ret = NETDEV_TX_OK;
1479
1480 if (skb->len == 0) {
1481 netif_err(pdata, tx_err, netdev,
1482 "empty skb received from stack\n");
1483 dev_kfree_skb_any(skb);
1484 goto tx_netdev_return;
1485 }
1486
1487 /* Calculate preliminary packet info */
1488 memset(packet, 0, sizeof(*packet));
1489 xgbe_packet_info(pdata, ring, skb, packet);
1490
1491 /* Check that there are enough descriptors available */
1492 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1493 if (ret)
1494 goto tx_netdev_return;
1495
1496 ret = xgbe_prep_tso(skb, packet);
1497 if (ret) {
1498 netif_err(pdata, tx_err, netdev,
1499 "error processing TSO packet\n");
1500 dev_kfree_skb_any(skb);
1501 goto tx_netdev_return;
1502 }
1503 xgbe_prep_vlan(skb, packet);
1504
1505 if (!desc_if->map_tx_skb(channel, skb)) {
1506 dev_kfree_skb_any(skb);
1507 goto tx_netdev_return;
1508 }
1509
1510 xgbe_prep_tx_tstamp(pdata, skb, packet);
1511
1512 /* Report on the actual number of bytes (to be) sent */
1513 netdev_tx_sent_queue(txq, packet->tx_bytes);
1514
1515 /* Configure required descriptor fields for transmission */
1516 hw_if->dev_xmit(channel);
1517
1518 if (netif_msg_pktdata(pdata))
1519 xgbe_print_pkt(netdev, skb, true);
1520
1521 /* Stop the queue in advance if there may not be enough descriptors */
1522 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1523
1524 ret = NETDEV_TX_OK;
1525
1526 tx_netdev_return:
1527 return ret;
1528 }
1529
1530 static void xgbe_set_rx_mode(struct net_device *netdev)
1531 {
1532 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1533 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1534
1535 DBGPR("-->xgbe_set_rx_mode\n");
1536
1537 hw_if->config_rx_mode(pdata);
1538
1539 DBGPR("<--xgbe_set_rx_mode\n");
1540 }
1541
1542 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1543 {
1544 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1545 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1546 struct sockaddr *saddr = addr;
1547
1548 DBGPR("-->xgbe_set_mac_address\n");
1549
1550 if (!is_valid_ether_addr(saddr->sa_data))
1551 return -EADDRNOTAVAIL;
1552
1553 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1554
1555 hw_if->set_mac_address(pdata, netdev->dev_addr);
1556
1557 DBGPR("<--xgbe_set_mac_address\n");
1558
1559 return 0;
1560 }
1561
1562 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1563 {
1564 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1565 int ret;
1566
1567 switch (cmd) {
1568 case SIOCGHWTSTAMP:
1569 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1570 break;
1571
1572 case SIOCSHWTSTAMP:
1573 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1574 break;
1575
1576 default:
1577 ret = -EOPNOTSUPP;
1578 }
1579
1580 return ret;
1581 }
1582
1583 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1584 {
1585 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1586 int ret;
1587
1588 DBGPR("-->xgbe_change_mtu\n");
1589
1590 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1591 if (ret < 0)
1592 return ret;
1593
1594 pdata->rx_buf_size = ret;
1595 netdev->mtu = mtu;
1596
1597 xgbe_restart_dev(pdata);
1598
1599 DBGPR("<--xgbe_change_mtu\n");
1600
1601 return 0;
1602 }
1603
1604 static void xgbe_tx_timeout(struct net_device *netdev)
1605 {
1606 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1607
1608 netdev_warn(netdev, "tx timeout, device restarting\n");
1609 schedule_work(&pdata->restart_work);
1610 }
1611
1612 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1613 struct rtnl_link_stats64 *s)
1614 {
1615 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1616 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1617
1618 DBGPR("-->%s\n", __func__);
1619
1620 pdata->hw_if.read_mmc_stats(pdata);
1621
1622 s->rx_packets = pstats->rxframecount_gb;
1623 s->rx_bytes = pstats->rxoctetcount_gb;
1624 s->rx_errors = pstats->rxframecount_gb -
1625 pstats->rxbroadcastframes_g -
1626 pstats->rxmulticastframes_g -
1627 pstats->rxunicastframes_g;
1628 s->multicast = pstats->rxmulticastframes_g;
1629 s->rx_length_errors = pstats->rxlengtherror;
1630 s->rx_crc_errors = pstats->rxcrcerror;
1631 s->rx_fifo_errors = pstats->rxfifooverflow;
1632
1633 s->tx_packets = pstats->txframecount_gb;
1634 s->tx_bytes = pstats->txoctetcount_gb;
1635 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1636 s->tx_dropped = netdev->stats.tx_dropped;
1637
1638 DBGPR("<--%s\n", __func__);
1639
1640 return s;
1641 }
1642
1643 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1644 u16 vid)
1645 {
1646 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1647 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1648
1649 DBGPR("-->%s\n", __func__);
1650
1651 set_bit(vid, pdata->active_vlans);
1652 hw_if->update_vlan_hash_table(pdata);
1653
1654 DBGPR("<--%s\n", __func__);
1655
1656 return 0;
1657 }
1658
1659 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1660 u16 vid)
1661 {
1662 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1663 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1664
1665 DBGPR("-->%s\n", __func__);
1666
1667 clear_bit(vid, pdata->active_vlans);
1668 hw_if->update_vlan_hash_table(pdata);
1669
1670 DBGPR("<--%s\n", __func__);
1671
1672 return 0;
1673 }
1674
1675 #ifdef CONFIG_NET_POLL_CONTROLLER
1676 static void xgbe_poll_controller(struct net_device *netdev)
1677 {
1678 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1679 struct xgbe_channel *channel;
1680 unsigned int i;
1681
1682 DBGPR("-->xgbe_poll_controller\n");
1683
1684 if (pdata->per_channel_irq) {
1685 channel = pdata->channel;
1686 for (i = 0; i < pdata->channel_count; i++, channel++)
1687 xgbe_dma_isr(channel->dma_irq, channel);
1688 } else {
1689 disable_irq(pdata->dev_irq);
1690 xgbe_isr(pdata->dev_irq, pdata);
1691 enable_irq(pdata->dev_irq);
1692 }
1693
1694 DBGPR("<--xgbe_poll_controller\n");
1695 }
1696 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1697
1698 static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
1699 {
1700 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1701 unsigned int offset, queue;
1702 u8 i;
1703
1704 if (tc && (tc != pdata->hw_feat.tc_cnt))
1705 return -EINVAL;
1706
1707 if (tc) {
1708 netdev_set_num_tc(netdev, tc);
1709 for (i = 0, queue = 0, offset = 0; i < tc; i++) {
1710 while ((queue < pdata->tx_q_count) &&
1711 (pdata->q2tc_map[queue] == i))
1712 queue++;
1713
1714 netif_dbg(pdata, drv, netdev, "TC%u using TXq%u-%u\n",
1715 i, offset, queue - 1);
1716 netdev_set_tc_queue(netdev, i, queue - offset, offset);
1717 offset = queue;
1718 }
1719 } else {
1720 netdev_reset_tc(netdev);
1721 }
1722
1723 return 0;
1724 }
1725
1726 static int xgbe_set_features(struct net_device *netdev,
1727 netdev_features_t features)
1728 {
1729 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1730 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1731 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1732 int ret = 0;
1733
1734 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1735 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1736 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1737 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1738
1739 if ((features & NETIF_F_RXHASH) && !rxhash)
1740 ret = hw_if->enable_rss(pdata);
1741 else if (!(features & NETIF_F_RXHASH) && rxhash)
1742 ret = hw_if->disable_rss(pdata);
1743 if (ret)
1744 return ret;
1745
1746 if ((features & NETIF_F_RXCSUM) && !rxcsum)
1747 hw_if->enable_rx_csum(pdata);
1748 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1749 hw_if->disable_rx_csum(pdata);
1750
1751 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1752 hw_if->enable_rx_vlan_stripping(pdata);
1753 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1754 hw_if->disable_rx_vlan_stripping(pdata);
1755
1756 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1757 hw_if->enable_rx_vlan_filtering(pdata);
1758 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1759 hw_if->disable_rx_vlan_filtering(pdata);
1760
1761 pdata->netdev_features = features;
1762
1763 DBGPR("<--xgbe_set_features\n");
1764
1765 return 0;
1766 }
1767
1768 static const struct net_device_ops xgbe_netdev_ops = {
1769 .ndo_open = xgbe_open,
1770 .ndo_stop = xgbe_close,
1771 .ndo_start_xmit = xgbe_xmit,
1772 .ndo_set_rx_mode = xgbe_set_rx_mode,
1773 .ndo_set_mac_address = xgbe_set_mac_address,
1774 .ndo_validate_addr = eth_validate_addr,
1775 .ndo_do_ioctl = xgbe_ioctl,
1776 .ndo_change_mtu = xgbe_change_mtu,
1777 .ndo_tx_timeout = xgbe_tx_timeout,
1778 .ndo_get_stats64 = xgbe_get_stats64,
1779 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
1780 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
1781 #ifdef CONFIG_NET_POLL_CONTROLLER
1782 .ndo_poll_controller = xgbe_poll_controller,
1783 #endif
1784 .ndo_setup_tc = xgbe_setup_tc,
1785 .ndo_set_features = xgbe_set_features,
1786 };
1787
1788 struct net_device_ops *xgbe_get_netdev_ops(void)
1789 {
1790 return (struct net_device_ops *)&xgbe_netdev_ops;
1791 }
1792
1793 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1794 {
1795 struct xgbe_prv_data *pdata = channel->pdata;
1796 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1797 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1798 struct xgbe_ring *ring = channel->rx_ring;
1799 struct xgbe_ring_data *rdata;
1800
1801 while (ring->dirty != ring->cur) {
1802 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1803
1804 /* Reset rdata values */
1805 desc_if->unmap_rdata(pdata, rdata);
1806
1807 if (desc_if->map_rx_buffer(pdata, ring, rdata))
1808 break;
1809
1810 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
1811
1812 ring->dirty++;
1813 }
1814
1815 /* Make sure everything is written before the register write */
1816 wmb();
1817
1818 /* Update the Rx Tail Pointer Register with address of
1819 * the last cleaned entry */
1820 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
1821 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1822 lower_32_bits(rdata->rdesc_dma));
1823 }
1824
1825 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1826 struct napi_struct *napi,
1827 struct xgbe_ring_data *rdata,
1828 unsigned int len)
1829 {
1830 struct sk_buff *skb;
1831 u8 *packet;
1832 unsigned int copy_len;
1833
1834 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
1835 if (!skb)
1836 return NULL;
1837
1838 /* Start with the header buffer which may contain just the header
1839 * or the header plus data
1840 */
1841 dma_sync_single_for_cpu(pdata->dev, rdata->rx.hdr.dma,
1842 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
1843
1844 packet = page_address(rdata->rx.hdr.pa.pages) +
1845 rdata->rx.hdr.pa.pages_offset;
1846 copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len;
1847 copy_len = min(rdata->rx.hdr.dma_len, copy_len);
1848 skb_copy_to_linear_data(skb, packet, copy_len);
1849 skb_put(skb, copy_len);
1850
1851 len -= copy_len;
1852 if (len) {
1853 /* Add the remaining data as a frag */
1854 dma_sync_single_for_cpu(pdata->dev, rdata->rx.buf.dma,
1855 rdata->rx.buf.dma_len, DMA_FROM_DEVICE);
1856
1857 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1858 rdata->rx.buf.pa.pages,
1859 rdata->rx.buf.pa.pages_offset,
1860 len, rdata->rx.buf.dma_len);
1861 rdata->rx.buf.pa.pages = NULL;
1862 }
1863
1864 return skb;
1865 }
1866
1867 static int xgbe_tx_poll(struct xgbe_channel *channel)
1868 {
1869 struct xgbe_prv_data *pdata = channel->pdata;
1870 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1871 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1872 struct xgbe_ring *ring = channel->tx_ring;
1873 struct xgbe_ring_data *rdata;
1874 struct xgbe_ring_desc *rdesc;
1875 struct net_device *netdev = pdata->netdev;
1876 struct netdev_queue *txq;
1877 int processed = 0;
1878 unsigned int tx_packets = 0, tx_bytes = 0;
1879
1880 DBGPR("-->xgbe_tx_poll\n");
1881
1882 /* Nothing to do if there isn't a Tx ring for this channel */
1883 if (!ring)
1884 return 0;
1885
1886 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1887
1888 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1889 (ring->dirty != ring->cur)) {
1890 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1891 rdesc = rdata->rdesc;
1892
1893 if (!hw_if->tx_complete(rdesc))
1894 break;
1895
1896 /* Make sure descriptor fields are read after reading the OWN
1897 * bit */
1898 dma_rmb();
1899
1900 if (netif_msg_tx_done(pdata))
1901 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
1902
1903 if (hw_if->is_last_desc(rdesc)) {
1904 tx_packets += rdata->tx.packets;
1905 tx_bytes += rdata->tx.bytes;
1906 }
1907
1908 /* Free the SKB and reset the descriptor for re-use */
1909 desc_if->unmap_rdata(pdata, rdata);
1910 hw_if->tx_desc_reset(rdata);
1911
1912 processed++;
1913 ring->dirty++;
1914 }
1915
1916 if (!processed)
1917 return 0;
1918
1919 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1920
1921 if ((ring->tx.queue_stopped == 1) &&
1922 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1923 ring->tx.queue_stopped = 0;
1924 netif_tx_wake_queue(txq);
1925 }
1926
1927 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1928
1929 return processed;
1930 }
1931
1932 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1933 {
1934 struct xgbe_prv_data *pdata = channel->pdata;
1935 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1936 struct xgbe_ring *ring = channel->rx_ring;
1937 struct xgbe_ring_data *rdata;
1938 struct xgbe_packet_data *packet;
1939 struct net_device *netdev = pdata->netdev;
1940 struct napi_struct *napi;
1941 struct sk_buff *skb;
1942 struct skb_shared_hwtstamps *hwtstamps;
1943 unsigned int incomplete, error, context_next, context;
1944 unsigned int len, rdesc_len, max_len;
1945 unsigned int received = 0;
1946 int packet_count = 0;
1947
1948 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1949
1950 /* Nothing to do if there isn't a Rx ring for this channel */
1951 if (!ring)
1952 return 0;
1953
1954 incomplete = 0;
1955 context_next = 0;
1956
1957 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1958
1959 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1960 packet = &ring->packet_data;
1961 while (packet_count < budget) {
1962 DBGPR(" cur = %d\n", ring->cur);
1963
1964 /* First time in loop see if we need to restore state */
1965 if (!received && rdata->state_saved) {
1966 skb = rdata->state.skb;
1967 error = rdata->state.error;
1968 len = rdata->state.len;
1969 } else {
1970 memset(packet, 0, sizeof(*packet));
1971 skb = NULL;
1972 error = 0;
1973 len = 0;
1974 }
1975
1976 read_again:
1977 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1978
1979 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
1980 xgbe_rx_refresh(channel);
1981
1982 if (hw_if->dev_read(channel))
1983 break;
1984
1985 received++;
1986 ring->cur++;
1987
1988 incomplete = XGMAC_GET_BITS(packet->attributes,
1989 RX_PACKET_ATTRIBUTES,
1990 INCOMPLETE);
1991 context_next = XGMAC_GET_BITS(packet->attributes,
1992 RX_PACKET_ATTRIBUTES,
1993 CONTEXT_NEXT);
1994 context = XGMAC_GET_BITS(packet->attributes,
1995 RX_PACKET_ATTRIBUTES,
1996 CONTEXT);
1997
1998 /* Earlier error, just drain the remaining data */
1999 if ((incomplete || context_next) && error)
2000 goto read_again;
2001
2002 if (error || packet->errors) {
2003 if (packet->errors)
2004 netif_err(pdata, rx_err, netdev,
2005 "error in received packet\n");
2006 dev_kfree_skb(skb);
2007 goto next_packet;
2008 }
2009
2010 if (!context) {
2011 /* Length is cumulative, get this descriptor's length */
2012 rdesc_len = rdata->rx.len - len;
2013 len += rdesc_len;
2014
2015 if (rdesc_len && !skb) {
2016 skb = xgbe_create_skb(pdata, napi, rdata,
2017 rdesc_len);
2018 if (!skb)
2019 error = 1;
2020 } else if (rdesc_len) {
2021 dma_sync_single_for_cpu(pdata->dev,
2022 rdata->rx.buf.dma,
2023 rdata->rx.buf.dma_len,
2024 DMA_FROM_DEVICE);
2025
2026 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2027 rdata->rx.buf.pa.pages,
2028 rdata->rx.buf.pa.pages_offset,
2029 rdesc_len,
2030 rdata->rx.buf.dma_len);
2031 rdata->rx.buf.pa.pages = NULL;
2032 }
2033 }
2034
2035 if (incomplete || context_next)
2036 goto read_again;
2037
2038 if (!skb)
2039 goto next_packet;
2040
2041 /* Be sure we don't exceed the configured MTU */
2042 max_len = netdev->mtu + ETH_HLEN;
2043 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2044 (skb->protocol == htons(ETH_P_8021Q)))
2045 max_len += VLAN_HLEN;
2046
2047 if (skb->len > max_len) {
2048 netif_err(pdata, rx_err, netdev,
2049 "packet length exceeds configured MTU\n");
2050 dev_kfree_skb(skb);
2051 goto next_packet;
2052 }
2053
2054 if (netif_msg_pktdata(pdata))
2055 xgbe_print_pkt(netdev, skb, false);
2056
2057 skb_checksum_none_assert(skb);
2058 if (XGMAC_GET_BITS(packet->attributes,
2059 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2060 skb->ip_summed = CHECKSUM_UNNECESSARY;
2061
2062 if (XGMAC_GET_BITS(packet->attributes,
2063 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2064 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2065 packet->vlan_ctag);
2066
2067 if (XGMAC_GET_BITS(packet->attributes,
2068 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2069 u64 nsec;
2070
2071 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2072 packet->rx_tstamp);
2073 hwtstamps = skb_hwtstamps(skb);
2074 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2075 }
2076
2077 if (XGMAC_GET_BITS(packet->attributes,
2078 RX_PACKET_ATTRIBUTES, RSS_HASH))
2079 skb_set_hash(skb, packet->rss_hash,
2080 packet->rss_hash_type);
2081
2082 skb->dev = netdev;
2083 skb->protocol = eth_type_trans(skb, netdev);
2084 skb_record_rx_queue(skb, channel->queue_index);
2085 skb_mark_napi_id(skb, napi);
2086
2087 napi_gro_receive(napi, skb);
2088
2089 next_packet:
2090 packet_count++;
2091 }
2092
2093 /* Check if we need to save state before leaving */
2094 if (received && (incomplete || context_next)) {
2095 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2096 rdata->state_saved = 1;
2097 rdata->state.skb = skb;
2098 rdata->state.len = len;
2099 rdata->state.error = error;
2100 }
2101
2102 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2103
2104 return packet_count;
2105 }
2106
2107 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2108 {
2109 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2110 napi);
2111 int processed = 0;
2112
2113 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2114
2115 /* Cleanup Tx ring first */
2116 xgbe_tx_poll(channel);
2117
2118 /* Process Rx ring next */
2119 processed = xgbe_rx_poll(channel, budget);
2120
2121 /* If we processed everything, we are done */
2122 if (processed < budget) {
2123 /* Turn off polling */
2124 napi_complete(napi);
2125
2126 /* Enable Tx and Rx interrupts */
2127 enable_irq(channel->dma_irq);
2128 }
2129
2130 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2131
2132 return processed;
2133 }
2134
2135 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2136 {
2137 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2138 napi);
2139 struct xgbe_channel *channel;
2140 int ring_budget;
2141 int processed, last_processed;
2142 unsigned int i;
2143
2144 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2145
2146 processed = 0;
2147 ring_budget = budget / pdata->rx_ring_count;
2148 do {
2149 last_processed = processed;
2150
2151 channel = pdata->channel;
2152 for (i = 0; i < pdata->channel_count; i++, channel++) {
2153 /* Cleanup Tx ring first */
2154 xgbe_tx_poll(channel);
2155
2156 /* Process Rx ring next */
2157 if (ring_budget > (budget - processed))
2158 ring_budget = budget - processed;
2159 processed += xgbe_rx_poll(channel, ring_budget);
2160 }
2161 } while ((processed < budget) && (processed != last_processed));
2162
2163 /* If we processed everything, we are done */
2164 if (processed < budget) {
2165 /* Turn off polling */
2166 napi_complete(napi);
2167
2168 /* Enable Tx and Rx interrupts */
2169 xgbe_enable_rx_tx_ints(pdata);
2170 }
2171
2172 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2173
2174 return processed;
2175 }
2176
2177 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2178 unsigned int idx, unsigned int count, unsigned int flag)
2179 {
2180 struct xgbe_ring_data *rdata;
2181 struct xgbe_ring_desc *rdesc;
2182
2183 while (count--) {
2184 rdata = XGBE_GET_DESC_DATA(ring, idx);
2185 rdesc = rdata->rdesc;
2186 netdev_dbg(pdata->netdev,
2187 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2188 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2189 le32_to_cpu(rdesc->desc0),
2190 le32_to_cpu(rdesc->desc1),
2191 le32_to_cpu(rdesc->desc2),
2192 le32_to_cpu(rdesc->desc3));
2193 idx++;
2194 }
2195 }
2196
2197 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2198 unsigned int idx)
2199 {
2200 struct xgbe_ring_data *rdata;
2201 struct xgbe_ring_desc *rdesc;
2202
2203 rdata = XGBE_GET_DESC_DATA(ring, idx);
2204 rdesc = rdata->rdesc;
2205 netdev_dbg(pdata->netdev,
2206 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2207 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2208 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2209 }
2210
2211 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2212 {
2213 struct ethhdr *eth = (struct ethhdr *)skb->data;
2214 unsigned char *buf = skb->data;
2215 unsigned char buffer[128];
2216 unsigned int i, j;
2217
2218 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2219
2220 netdev_dbg(netdev, "%s packet of %d bytes\n",
2221 (tx_rx ? "TX" : "RX"), skb->len);
2222
2223 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2224 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2225 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2226
2227 for (i = 0, j = 0; i < skb->len;) {
2228 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2229 buf[i++]);
2230
2231 if ((i % 32) == 0) {
2232 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer);
2233 j = 0;
2234 } else if ((i % 16) == 0) {
2235 buffer[j++] = ' ';
2236 buffer[j++] = ' ';
2237 } else if ((i % 4) == 0) {
2238 buffer[j++] = ' ';
2239 }
2240 }
2241 if (i % 32)
2242 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer);
2243
2244 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2245 }
Linux kernel - Deliverables
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