drivers/net/ethernet/amd/xgbe/xgbe.h

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #ifndef __XGBE_H__
 118 #define __XGBE_H__
 119
 120 #include <linux/dma-mapping.h>
 121 #include <linux/netdevice.h>
 122 #include <linux/workqueue.h>
 123 #include <linux/phy.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/bitops.h>
 126 #include <linux/ptp_clock_kernel.h>
 127 #include <linux/clocksource.h>
 128 #include <linux/net_tstamp.h>
 129 #include <net/dcbnl.h>
 130
 131 #define XGBE_DRV_NAME           "amd-xgbe"
 132 #define XGBE_DRV_VERSION        "1.0.0-a"
 133 #define XGBE_DRV_DESC           "AMD 10 Gigabit Ethernet Driver"
 134
 135 /* Descriptor related defines */
 136 #define XGBE_TX_DESC_CNT        512
 137 #define XGBE_TX_DESC_MIN_FREE   (XGBE_TX_DESC_CNT >> 3)
 138 #define XGBE_TX_DESC_MAX_PROC   (XGBE_TX_DESC_CNT >> 1)
 139 #define XGBE_RX_DESC_CNT        512
 140
 141 #define XGBE_TX_MAX_BUF_SIZE    (0x3fff & ~(64 - 1))
 142
 143 #define XGBE_RX_MIN_BUF_SIZE    (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 144 #define XGBE_RX_BUF_ALIGN       64
 145 #define XGBE_SKB_ALLOC_SIZE     256
 146 #define XGBE_SPH_HDSMS_SIZE     2       /* Keep in sync with SKB_ALLOC_SIZE */
 147
 148 #define XGBE_MAX_DMA_CHANNELS   16
 149 #define XGBE_MAX_QUEUES         16
 150
 151 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 152 #define XGBE_DMA_OS_AXDOMAIN    0x2
 153 #define XGBE_DMA_OS_ARCACHE     0xb
 154 #define XGBE_DMA_OS_AWCACHE     0xf
 155
 156 /* DMA cache settings - System, no caches used */
 157 #define XGBE_DMA_SYS_AXDOMAIN   0x3
 158 #define XGBE_DMA_SYS_ARCACHE    0x0
 159 #define XGBE_DMA_SYS_AWCACHE    0x0
 160
 161 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
 162
 163 #define XGMAC_MIN_PACKET        60
 164 #define XGMAC_STD_PACKET_MTU    1500
 165 #define XGMAC_MAX_STD_PACKET    1518
 166 #define XGMAC_JUMBO_PACKET_MTU  9000
 167 #define XGMAC_MAX_JUMBO_PACKET  9018
 168
 169 /* MDIO bus phy name */
 170 #define XGBE_PHY_NAME           "amd_xgbe_phy"
 171 #define XGBE_PRTAD              0
 172
 173 /* Device-tree clock names */
 174 #define XGBE_DMA_CLOCK          "dma_clk"
 175 #define XGBE_PTP_CLOCK          "ptp_clk"
 176
 177 /* Timestamp support - values based on 50MHz PTP clock
 178  *   50MHz => 20 nsec
 179  */
 180 #define XGBE_TSTAMP_SSINC       20
 181 #define XGBE_TSTAMP_SNSINC      0
 182
 183 /* Driver PMT macros */
 184 #define XGMAC_DRIVER_CONTEXT    1
 185 #define XGMAC_IOCTL_CONTEXT     2
 186
 187 #define XGBE_FIFO_MAX           81920
 188 #define XGBE_FIFO_SIZE_B(x)     (x)
 189 #define XGBE_FIFO_SIZE_KB(x)    (x * 1024)
 190
 191 #define XGBE_TC_MIN_QUANTUM     10
 192
 193 /* Helper macro for descriptor handling
 194  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
 195  *  since the index is free-running and needs to be and-ed
 196  *  with the descriptor count value of the ring to index to
 197  *  the proper descriptor data.
 198  */
 199 #define XGBE_GET_DESC_DATA(_ring, _idx)                         \
 200         ((_ring)->rdata +                                       \
 201          ((_idx) & ((_ring)->rdesc_count - 1)))
 202
 203 /* Default coalescing parameters */
 204 #define XGMAC_INIT_DMA_TX_USECS         50
 205 #define XGMAC_INIT_DMA_TX_FRAMES        25
 206
 207 #define XGMAC_MAX_DMA_RIWT              0xff
 208 #define XGMAC_INIT_DMA_RX_USECS         30
 209 #define XGMAC_INIT_DMA_RX_FRAMES        25
 210
 211 /* Flow control queue count */
 212 #define XGMAC_MAX_FLOW_CONTROL_QUEUES   8
 213
 214 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
 215 #define XGBE_MAC_HASH_TABLE_SIZE        8
 216
 217 struct xgbe_prv_data;
 218
 219 struct xgbe_packet_data {
 220         unsigned int attributes;
 221
 222         unsigned int errors;
 223
 224         unsigned int rdesc_count;
 225         unsigned int length;
 226
 227         unsigned int header_len;
 228         unsigned int tcp_header_len;
 229         unsigned int tcp_payload_len;
 230         unsigned short mss;
 231
 232         unsigned short vlan_ctag;
 233
 234         u64 rx_tstamp;
 235 };
 236
 237 /* Common Rx and Tx descriptor mapping */
 238 struct xgbe_ring_desc {
 239         u32 desc0;
 240         u32 desc1;
 241         u32 desc2;
 242         u32 desc3;
 243 };
 244
 245 /* Page allocation related values */
 246 struct xgbe_page_alloc {
 247         struct page *pages;
 248         unsigned int pages_len;
 249         unsigned int pages_offset;
 250
 251         dma_addr_t pages_dma;
 252 };
 253
 254 /* Ring entry buffer data */
 255 struct xgbe_buffer_data {
 256         struct xgbe_page_alloc pa;
 257         struct xgbe_page_alloc pa_unmap;
 258
 259         dma_addr_t dma;
 260         unsigned int dma_len;
 261 };
 262
 263 /* Structure used to hold information related to the descriptor
 264  * and the packet associated with the descriptor (always use
 265  * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
 266  */
 267 struct xgbe_ring_data {
 268         struct xgbe_ring_desc *rdesc;   /* Virtual address of descriptor */
 269         dma_addr_t rdesc_dma;           /* DMA address of descriptor */
 270
 271         struct sk_buff *skb;            /* Virtual address of SKB */
 272         dma_addr_t skb_dma;             /* DMA address of SKB data */
 273         unsigned int skb_dma_len;       /* Length of SKB DMA area */
 274         unsigned int tso_header;        /* TSO header indicator */
 275
 276         struct xgbe_buffer_data rx_hdr; /* Header locations */
 277         struct xgbe_buffer_data rx_buf; /* Payload locations */
 278
 279         unsigned short hdr_len;         /* Length of received header */
 280         unsigned short len;             /* Length of received Rx packet */
 281
 282         unsigned int interrupt;         /* Interrupt indicator */
 283
 284         unsigned int mapped_as_page;
 285
 286         /* Incomplete receive save location.  If the budget is exhausted
 287          * or the last descriptor (last normal descriptor or a following
 288          * context descriptor) has not been DMA'd yet the current state
 289          * of the receive processing needs to be saved.
 290          */
 291         unsigned int state_saved;
 292         struct {
 293                 unsigned int incomplete;
 294                 unsigned int context_next;
 295                 struct sk_buff *skb;
 296                 unsigned int len;
 297                 unsigned int error;
 298         } state;
 299 };
 300
 301 struct xgbe_ring {
 302         /* Ring lock - used just for TX rings at the moment */
 303         spinlock_t lock;
 304
 305         /* Per packet related information */
 306         struct xgbe_packet_data packet_data;
 307
 308         /* Virtual/DMA addresses and count of allocated descriptor memory */
 309         struct xgbe_ring_desc *rdesc;
 310         dma_addr_t rdesc_dma;
 311         unsigned int rdesc_count;
 312
 313         /* Array of descriptor data corresponding the descriptor memory
 314          * (always use the XGBE_GET_DESC_DATA macro to access this data)
 315          */
 316         struct xgbe_ring_data *rdata;
 317
 318         /* Page allocation for RX buffers */
 319         struct xgbe_page_alloc rx_hdr_pa;
 320         struct xgbe_page_alloc rx_buf_pa;
 321
 322         /* Ring index values
 323          *  cur   - Tx: index of descriptor to be used for current transfer
 324          *          Rx: index of descriptor to check for packet availability
 325          *  dirty - Tx: index of descriptor to check for transfer complete
 326          *          Rx: count of descriptors in which a packet has been received
 327          *              (used with skb_realloc_index to refresh the ring)
 328          */
 329         unsigned int cur;
 330         unsigned int dirty;
 331
 332         /* Coalesce frame count used for interrupt bit setting */
 333         unsigned int coalesce_count;
 334
 335         union {
 336                 struct {
 337                         unsigned int queue_stopped;
 338                         unsigned short cur_mss;
 339                         unsigned short cur_vlan_ctag;
 340                 } tx;
 341
 342                 struct {
 343                         unsigned int realloc_index;
 344                         unsigned int realloc_threshold;
 345                 } rx;
 346         };
 347 } ____cacheline_aligned;
 348
 349 /* Structure used to describe the descriptor rings associated with
 350  * a DMA channel.
 351  */
 352 struct xgbe_channel {
 353         char name[16];
 354
 355         /* Address of private data area for device */
 356         struct xgbe_prv_data *pdata;
 357
 358         /* Queue index and base address of queue's DMA registers */
 359         unsigned int queue_index;
 360         void __iomem *dma_regs;
 361
 362         unsigned int saved_ier;
 363
 364         unsigned int tx_timer_active;
 365         struct hrtimer tx_timer;
 366
 367         struct xgbe_ring *tx_ring;
 368         struct xgbe_ring *rx_ring;
 369 } ____cacheline_aligned;
 370
 371 enum xgbe_int {
 372         XGMAC_INT_DMA_CH_SR_TI,
 373         XGMAC_INT_DMA_CH_SR_TPS,
 374         XGMAC_INT_DMA_CH_SR_TBU,
 375         XGMAC_INT_DMA_CH_SR_RI,
 376         XGMAC_INT_DMA_CH_SR_RBU,
 377         XGMAC_INT_DMA_CH_SR_RPS,
 378         XGMAC_INT_DMA_CH_SR_TI_RI,
 379         XGMAC_INT_DMA_CH_SR_FBE,
 380         XGMAC_INT_DMA_ALL,
 381 };
 382
 383 enum xgbe_int_state {
 384         XGMAC_INT_STATE_SAVE,
 385         XGMAC_INT_STATE_RESTORE,
 386 };
 387
 388 enum xgbe_mtl_fifo_size {
 389         XGMAC_MTL_FIFO_SIZE_256  = 0x00,
 390         XGMAC_MTL_FIFO_SIZE_512  = 0x01,
 391         XGMAC_MTL_FIFO_SIZE_1K   = 0x03,
 392         XGMAC_MTL_FIFO_SIZE_2K   = 0x07,
 393         XGMAC_MTL_FIFO_SIZE_4K   = 0x0f,
 394         XGMAC_MTL_FIFO_SIZE_8K   = 0x1f,
 395         XGMAC_MTL_FIFO_SIZE_16K  = 0x3f,
 396         XGMAC_MTL_FIFO_SIZE_32K  = 0x7f,
 397         XGMAC_MTL_FIFO_SIZE_64K  = 0xff,
 398         XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
 399         XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
 400 };
 401
 402 struct xgbe_mmc_stats {
 403         /* Tx Stats */
 404         u64 txoctetcount_gb;
 405         u64 txframecount_gb;
 406         u64 txbroadcastframes_g;
 407         u64 txmulticastframes_g;
 408         u64 tx64octets_gb;
 409         u64 tx65to127octets_gb;
 410         u64 tx128to255octets_gb;
 411         u64 tx256to511octets_gb;
 412         u64 tx512to1023octets_gb;
 413         u64 tx1024tomaxoctets_gb;
 414         u64 txunicastframes_gb;
 415         u64 txmulticastframes_gb;
 416         u64 txbroadcastframes_gb;
 417         u64 txunderflowerror;
 418         u64 txoctetcount_g;
 419         u64 txframecount_g;
 420         u64 txpauseframes;
 421         u64 txvlanframes_g;
 422
 423         /* Rx Stats */
 424         u64 rxframecount_gb;
 425         u64 rxoctetcount_gb;
 426         u64 rxoctetcount_g;
 427         u64 rxbroadcastframes_g;
 428         u64 rxmulticastframes_g;
 429         u64 rxcrcerror;
 430         u64 rxrunterror;
 431         u64 rxjabbererror;
 432         u64 rxundersize_g;
 433         u64 rxoversize_g;
 434         u64 rx64octets_gb;
 435         u64 rx65to127octets_gb;
 436         u64 rx128to255octets_gb;
 437         u64 rx256to511octets_gb;
 438         u64 rx512to1023octets_gb;
 439         u64 rx1024tomaxoctets_gb;
 440         u64 rxunicastframes_g;
 441         u64 rxlengtherror;
 442         u64 rxoutofrangetype;
 443         u64 rxpauseframes;
 444         u64 rxfifooverflow;
 445         u64 rxvlanframes_gb;
 446         u64 rxwatchdogerror;
 447 };
 448
 449 struct xgbe_hw_if {
 450         int (*tx_complete)(struct xgbe_ring_desc *);
 451
 452         int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
 453         int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
 454         int (*add_mac_addresses)(struct xgbe_prv_data *);
 455         int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
 456
 457         int (*enable_rx_csum)(struct xgbe_prv_data *);
 458         int (*disable_rx_csum)(struct xgbe_prv_data *);
 459
 460         int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
 461         int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
 462         int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
 463         int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
 464         int (*update_vlan_hash_table)(struct xgbe_prv_data *);
 465
 466         int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
 467         void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
 468         int (*set_gmii_speed)(struct xgbe_prv_data *);
 469         int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
 470         int (*set_xgmii_speed)(struct xgbe_prv_data *);
 471
 472         void (*enable_tx)(struct xgbe_prv_data *);
 473         void (*disable_tx)(struct xgbe_prv_data *);
 474         void (*enable_rx)(struct xgbe_prv_data *);
 475         void (*disable_rx)(struct xgbe_prv_data *);
 476
 477         void (*powerup_tx)(struct xgbe_prv_data *);
 478         void (*powerdown_tx)(struct xgbe_prv_data *);
 479         void (*powerup_rx)(struct xgbe_prv_data *);
 480         void (*powerdown_rx)(struct xgbe_prv_data *);
 481
 482         int (*init)(struct xgbe_prv_data *);
 483         int (*exit)(struct xgbe_prv_data *);
 484
 485         int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
 486         int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
 487         void (*dev_xmit)(struct xgbe_channel *);
 488         int (*dev_read)(struct xgbe_channel *);
 489         void (*tx_desc_init)(struct xgbe_channel *);
 490         void (*rx_desc_init)(struct xgbe_channel *);
 491         void (*rx_desc_reset)(struct xgbe_ring_data *);
 492         void (*tx_desc_reset)(struct xgbe_ring_data *);
 493         int (*is_last_desc)(struct xgbe_ring_desc *);
 494         int (*is_context_desc)(struct xgbe_ring_desc *);
 495
 496         /* For FLOW ctrl */
 497         int (*config_tx_flow_control)(struct xgbe_prv_data *);
 498         int (*config_rx_flow_control)(struct xgbe_prv_data *);
 499
 500         /* For RX coalescing */
 501         int (*config_rx_coalesce)(struct xgbe_prv_data *);
 502         int (*config_tx_coalesce)(struct xgbe_prv_data *);
 503         unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
 504         unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
 505
 506         /* For RX and TX threshold config */
 507         int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
 508         int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
 509
 510         /* For RX and TX Store and Forward Mode config */
 511         int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
 512         int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
 513
 514         /* For TX DMA Operate on Second Frame config */
 515         int (*config_osp_mode)(struct xgbe_prv_data *);
 516
 517         /* For RX and TX PBL config */
 518         int (*config_rx_pbl_val)(struct xgbe_prv_data *);
 519         int (*get_rx_pbl_val)(struct xgbe_prv_data *);
 520         int (*config_tx_pbl_val)(struct xgbe_prv_data *);
 521         int (*get_tx_pbl_val)(struct xgbe_prv_data *);
 522         int (*config_pblx8)(struct xgbe_prv_data *);
 523
 524         /* For MMC statistics */
 525         void (*rx_mmc_int)(struct xgbe_prv_data *);
 526         void (*tx_mmc_int)(struct xgbe_prv_data *);
 527         void (*read_mmc_stats)(struct xgbe_prv_data *);
 528
 529         /* For Timestamp config */
 530         int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
 531         void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
 532         void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
 533                                 unsigned int nsec);
 534         u64 (*get_tstamp_time)(struct xgbe_prv_data *);
 535         u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
 536
 537         /* For Data Center Bridging config */
 538         void (*config_dcb_tc)(struct xgbe_prv_data *);
 539         void (*config_dcb_pfc)(struct xgbe_prv_data *);
 540 };
 541
 542 struct xgbe_desc_if {
 543         int (*alloc_ring_resources)(struct xgbe_prv_data *);
 544         void (*free_ring_resources)(struct xgbe_prv_data *);
 545         int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
 546         void (*realloc_rx_buffer)(struct xgbe_channel *);
 547         void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
 548         void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
 549         void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
 550 };
 551
 552 /* This structure contains flags that indicate what hardware features
 553  * or configurations are present in the device.
 554  */
 555 struct xgbe_hw_features {
 556         /* HW Version */
 557         unsigned int version;
 558
 559         /* HW Feature Register0 */
 560         unsigned int gmii;              /* 1000 Mbps support */
 561         unsigned int vlhash;            /* VLAN Hash Filter */
 562         unsigned int sma;               /* SMA(MDIO) Interface */
 563         unsigned int rwk;               /* PMT remote wake-up packet */
 564         unsigned int mgk;               /* PMT magic packet */
 565         unsigned int mmc;               /* RMON module */
 566         unsigned int aoe;               /* ARP Offload */
 567         unsigned int ts;                /* IEEE 1588-2008 Adavanced Timestamp */
 568         unsigned int eee;               /* Energy Efficient Ethernet */
 569         unsigned int tx_coe;            /* Tx Checksum Offload */
 570         unsigned int rx_coe;            /* Rx Checksum Offload */
 571         unsigned int addn_mac;          /* Additional MAC Addresses */
 572         unsigned int ts_src;            /* Timestamp Source */
 573         unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 574
 575         /* HW Feature Register1 */
 576         unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 577         unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 578         unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 579         unsigned int dcb;               /* DCB Feature */
 580         unsigned int sph;               /* Split Header Feature */
 581         unsigned int tso;               /* TCP Segmentation Offload */
 582         unsigned int dma_debug;         /* DMA Debug Registers */
 583         unsigned int rss;               /* Receive Side Scaling */
 584         unsigned int tc_cnt;            /* Number of Traffic Classes */
 585         unsigned int hash_table_size;   /* Hash Table Size */
 586         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 587
 588         /* HW Feature Register2 */
 589         unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 590         unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 591         unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 592         unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 593         unsigned int pps_out_num;       /* Number of PPS outputs */
 594         unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 595 };
 596
 597 struct xgbe_prv_data {
 598         struct net_device *netdev;
 599         struct platform_device *pdev;
 600         struct device *dev;
 601
 602         /* XGMAC/XPCS related mmio registers */
 603         void __iomem *xgmac_regs;       /* XGMAC CSRs */
 604         void __iomem *xpcs_regs;        /* XPCS MMD registers */
 605
 606         /* Overall device lock */
 607         spinlock_t lock;
 608
 609         /* XPCS indirect addressing mutex */
 610         struct mutex xpcs_mutex;
 611
 612         int irq_number;
 613
 614         struct xgbe_hw_if hw_if;
 615         struct xgbe_desc_if desc_if;
 616
 617         /* AXI DMA settings */
 618         unsigned int axdomain;
 619         unsigned int arcache;
 620         unsigned int awcache;
 621
 622         /* Rings for Tx/Rx on a DMA channel */
 623         struct xgbe_channel *channel;
 624         unsigned int channel_count;
 625         unsigned int tx_ring_count;
 626         unsigned int tx_desc_count;
 627         unsigned int rx_ring_count;
 628         unsigned int rx_desc_count;
 629
 630         unsigned int tx_q_count;
 631         unsigned int rx_q_count;
 632
 633         /* Tx/Rx common settings */
 634         unsigned int pblx8;
 635
 636         /* Tx settings */
 637         unsigned int tx_sf_mode;
 638         unsigned int tx_threshold;
 639         unsigned int tx_pbl;
 640         unsigned int tx_osp_mode;
 641
 642         /* Rx settings */
 643         unsigned int rx_sf_mode;
 644         unsigned int rx_threshold;
 645         unsigned int rx_pbl;
 646
 647         /* Tx coalescing settings */
 648         unsigned int tx_usecs;
 649         unsigned int tx_frames;
 650
 651         /* Rx coalescing settings */
 652         unsigned int rx_riwt;
 653         unsigned int rx_frames;
 654
 655         /* Current Rx buffer size */
 656         unsigned int rx_buf_size;
 657
 658         /* Flow control settings */
 659         unsigned int pause_autoneg;
 660         unsigned int tx_pause;
 661         unsigned int rx_pause;
 662
 663         /* MDIO settings */
 664         struct module *phy_module;
 665         char *mii_bus_id;
 666         struct mii_bus *mii;
 667         int mdio_mmd;
 668         struct phy_device *phydev;
 669         int default_autoneg;
 670         int default_speed;
 671
 672         /* Current PHY settings */
 673         phy_interface_t phy_mode;
 674         int phy_link;
 675         int phy_speed;
 676         unsigned int phy_tx_pause;
 677         unsigned int phy_rx_pause;
 678
 679         /* Netdev related settings */
 680         netdev_features_t netdev_features;
 681         struct napi_struct napi;
 682         struct xgbe_mmc_stats mmc_stats;
 683
 684         /* Filtering support */
 685         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 686
 687         /* Device clocks */
 688         struct clk *sysclk;
 689         struct clk *ptpclk;
 690
 691         /* Timestamp support */
 692         spinlock_t tstamp_lock;
 693         struct ptp_clock_info ptp_clock_info;
 694         struct ptp_clock *ptp_clock;
 695         struct hwtstamp_config tstamp_config;
 696         struct cyclecounter tstamp_cc;
 697         struct timecounter tstamp_tc;
 698         unsigned int tstamp_addend;
 699         struct work_struct tx_tstamp_work;
 700         struct sk_buff *tx_tstamp_skb;
 701         u64 tx_tstamp;
 702
 703         /* DCB support */
 704         struct ieee_ets *ets;
 705         struct ieee_pfc *pfc;
 706         unsigned int q2tc_map[XGBE_MAX_QUEUES];
 707         unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
 708
 709         /* Hardware features of the device */
 710         struct xgbe_hw_features hw_feat;
 711
 712         /* Device restart work structure */
 713         struct work_struct restart_work;
 714
 715         /* Keeps track of power mode */
 716         unsigned int power_down;
 717
 718 #ifdef CONFIG_DEBUG_FS
 719         struct dentry *xgbe_debugfs;
 720
 721         unsigned int debugfs_xgmac_reg;
 722
 723         unsigned int debugfs_xpcs_mmd;
 724         unsigned int debugfs_xpcs_reg;
 725 #endif
 726 };
 727
 728 /* Function prototypes*/
 729
 730 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 731 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
 732 struct net_device_ops *xgbe_get_netdev_ops(void);
 733 struct ethtool_ops *xgbe_get_ethtool_ops(void);
 734 #ifdef CONFIG_AMD_XGBE_DCB
 735 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
 736 #endif
 737
 738 int xgbe_mdio_register(struct xgbe_prv_data *);
 739 void xgbe_mdio_unregister(struct xgbe_prv_data *);
 740 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
 741 void xgbe_ptp_register(struct xgbe_prv_data *);
 742 void xgbe_ptp_unregister(struct xgbe_prv_data *);
 743 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
 744                        unsigned int);
 745 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
 746                        unsigned int);
 747 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
 748 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
 749 int xgbe_powerup(struct net_device *, unsigned int);
 750 int xgbe_powerdown(struct net_device *, unsigned int);
 751 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
 752 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
 753
 754 #ifdef CONFIG_DEBUG_FS
 755 void xgbe_debugfs_init(struct xgbe_prv_data *);
 756 void xgbe_debugfs_exit(struct xgbe_prv_data *);
 757 #else
 758 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
 759 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
 760 #endif /* CONFIG_DEBUG_FS */
 761
 762 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
 763 #if 0
 764 #define XGMAC_ENABLE_TX_DESC_DUMP
 765 #define XGMAC_ENABLE_RX_DESC_DUMP
 766 #endif
 767
 768 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
 769 #if 0
 770 #define XGMAC_ENABLE_TX_PKT_DUMP
 771 #define XGMAC_ENABLE_RX_PKT_DUMP
 772 #endif
 773
 774 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
 775 #if 0
 776 #define YDEBUG
 777 #define YDEBUG_MDIO
 778 #endif
 779
 780 /* For debug prints */
 781 #ifdef YDEBUG
 782 #define DBGPR(x...) pr_alert(x)
 783 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
 784 #else
 785 #define DBGPR(x...) do { } while (0)
 786 #define DBGPHY_REGS(x...) do { } while (0)
 787 #endif
 788
 789 #ifdef YDEBUG_MDIO
 790 #define DBGPR_MDIO(x...) pr_alert(x)
 791 #else
 792 #define DBGPR_MDIO(x...) do { } while (0)
 793 #endif
 794
 795 #endif