drivers/net/ethernet/amd/xgbe/xgbe.h

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #ifndef __XGBE_H__
 118 #define __XGBE_H__
 119
 120 #include <linux/dma-mapping.h>
 121 #include <linux/netdevice.h>
 122 #include <linux/workqueue.h>
 123 #include <linux/phy.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/bitops.h>
 126 #include <linux/ptp_clock_kernel.h>
 127 #include <linux/clocksource.h>
 128 #include <linux/net_tstamp.h>
 129 #include <net/dcbnl.h>
 130
 131 #define XGBE_DRV_NAME           "amd-xgbe"
 132 #define XGBE_DRV_VERSION        "1.0.0-a"
 133 #define XGBE_DRV_DESC           "AMD 10 Gigabit Ethernet Driver"
 134
 135 /* Descriptor related defines */
 136 #define XGBE_TX_DESC_CNT        512
 137 #define XGBE_TX_DESC_MIN_FREE   (XGBE_TX_DESC_CNT >> 3)
 138 #define XGBE_TX_DESC_MAX_PROC   (XGBE_TX_DESC_CNT >> 1)
 139 #define XGBE_RX_DESC_CNT        512
 140
 141 #define XGBE_TX_MAX_BUF_SIZE    (0x3fff & ~(64 - 1))
 142
 143 #define XGBE_RX_MIN_BUF_SIZE    (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 144 #define XGBE_RX_BUF_ALIGN       64
 145 #define XGBE_SKB_ALLOC_SIZE     256
 146 #define XGBE_SPH_HDSMS_SIZE     2       /* Keep in sync with SKB_ALLOC_SIZE */
 147
 148 #define XGBE_MAX_DMA_CHANNELS   16
 149 #define XGBE_MAX_QUEUES         16
 150 #define XGBE_DMA_STOP_TIMEOUT   5
 151
 152 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 153 #define XGBE_DMA_OS_AXDOMAIN    0x2
 154 #define XGBE_DMA_OS_ARCACHE     0xb
 155 #define XGBE_DMA_OS_AWCACHE     0xf
 156
 157 /* DMA cache settings - System, no caches used */
 158 #define XGBE_DMA_SYS_AXDOMAIN   0x3
 159 #define XGBE_DMA_SYS_ARCACHE    0x0
 160 #define XGBE_DMA_SYS_AWCACHE    0x0
 161
 162 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
 163
 164 #define XGMAC_MIN_PACKET        60
 165 #define XGMAC_STD_PACKET_MTU    1500
 166 #define XGMAC_MAX_STD_PACKET    1518
 167 #define XGMAC_JUMBO_PACKET_MTU  9000
 168 #define XGMAC_MAX_JUMBO_PACKET  9018
 169
 170 /* MDIO bus phy name */
 171 #define XGBE_PHY_NAME           "amd_xgbe_phy"
 172 #define XGBE_PRTAD              0
 173
 174 /* Device-tree clock names */
 175 #define XGBE_DMA_CLOCK          "dma_clk"
 176 #define XGBE_PTP_CLOCK          "ptp_clk"
 177 #define XGBE_DMA_IRQS           "amd,per-channel-interrupt"
 178
 179 /* Timestamp support - values based on 50MHz PTP clock
 180  *   50MHz => 20 nsec
 181  */
 182 #define XGBE_TSTAMP_SSINC       20
 183 #define XGBE_TSTAMP_SNSINC      0
 184
 185 /* Driver PMT macros */
 186 #define XGMAC_DRIVER_CONTEXT    1
 187 #define XGMAC_IOCTL_CONTEXT     2
 188
 189 #define XGBE_FIFO_MAX           81920
 190 #define XGBE_FIFO_SIZE_B(x)     (x)
 191 #define XGBE_FIFO_SIZE_KB(x)    (x * 1024)
 192
 193 #define XGBE_TC_MIN_QUANTUM     10
 194
 195 /* Helper macro for descriptor handling
 196  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
 197  *  since the index is free-running and needs to be and-ed
 198  *  with the descriptor count value of the ring to index to
 199  *  the proper descriptor data.
 200  */
 201 #define XGBE_GET_DESC_DATA(_ring, _idx)                         \
 202         ((_ring)->rdata +                                       \
 203          ((_idx) & ((_ring)->rdesc_count - 1)))
 204
 205 /* Default coalescing parameters */
 206 #define XGMAC_INIT_DMA_TX_USECS         50
 207 #define XGMAC_INIT_DMA_TX_FRAMES        25
 208
 209 #define XGMAC_MAX_DMA_RIWT              0xff
 210 #define XGMAC_INIT_DMA_RX_USECS         30
 211 #define XGMAC_INIT_DMA_RX_FRAMES        25
 212
 213 /* Flow control queue count */
 214 #define XGMAC_MAX_FLOW_CONTROL_QUEUES   8
 215
 216 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
 217 #define XGBE_MAC_HASH_TABLE_SIZE        8
 218
 219 /* Receive Side Scaling */
 220 #define XGBE_RSS_HASH_KEY_SIZE          40
 221 #define XGBE_RSS_MAX_TABLE_SIZE         256
 222 #define XGBE_RSS_LOOKUP_TABLE_TYPE      0
 223 #define XGBE_RSS_HASH_KEY_TYPE          1
 224
 225 struct xgbe_prv_data;
 226
 227 struct xgbe_packet_data {
 228         unsigned int attributes;
 229
 230         unsigned int errors;
 231
 232         unsigned int rdesc_count;
 233         unsigned int length;
 234
 235         unsigned int header_len;
 236         unsigned int tcp_header_len;
 237         unsigned int tcp_payload_len;
 238         unsigned short mss;
 239
 240         unsigned short vlan_ctag;
 241
 242         u64 rx_tstamp;
 243
 244         u32 rss_hash;
 245         enum pkt_hash_types rss_hash_type;
 246
 247         unsigned int tx_packets;
 248         unsigned int tx_bytes;
 249 };
 250
 251 /* Common Rx and Tx descriptor mapping */
 252 struct xgbe_ring_desc {
 253         __le32 desc0;
 254         __le32 desc1;
 255         __le32 desc2;
 256         __le32 desc3;
 257 };
 258
 259 /* Page allocation related values */
 260 struct xgbe_page_alloc {
 261         struct page *pages;
 262         unsigned int pages_len;
 263         unsigned int pages_offset;
 264
 265         dma_addr_t pages_dma;
 266 };
 267
 268 /* Ring entry buffer data */
 269 struct xgbe_buffer_data {
 270         struct xgbe_page_alloc pa;
 271         struct xgbe_page_alloc pa_unmap;
 272
 273         dma_addr_t dma;
 274         unsigned int dma_len;
 275 };
 276
 277 /* Tx-related ring data */
 278 struct xgbe_tx_ring_data {
 279         unsigned int tso_header;        /* TSO header indicator */
 280         unsigned int packets;           /* BQL packet count */
 281         unsigned int bytes;             /* BQL byte count */
 282 };
 283
 284 /* Rx-related ring data */
 285 struct xgbe_rx_ring_data {
 286         struct xgbe_buffer_data hdr;    /* Header locations */
 287         struct xgbe_buffer_data buf;    /* Payload locations */
 288
 289         unsigned short hdr_len;         /* Length of received header */
 290         unsigned short len;             /* Length of received packet */
 291 };
 292
 293 /* Structure used to hold information related to the descriptor
 294  * and the packet associated with the descriptor (always use
 295  * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
 296  */
 297 struct xgbe_ring_data {
 298         struct xgbe_ring_desc *rdesc;   /* Virtual address of descriptor */
 299         dma_addr_t rdesc_dma;           /* DMA address of descriptor */
 300
 301         struct sk_buff *skb;            /* Virtual address of SKB */
 302         dma_addr_t skb_dma;             /* DMA address of SKB data */
 303         unsigned int skb_dma_len;       /* Length of SKB DMA area */
 304
 305         struct xgbe_tx_ring_data tx;    /* Tx-related data */
 306         struct xgbe_rx_ring_data rx;    /* Rx-related data */
 307
 308         unsigned int interrupt;         /* Interrupt indicator */
 309
 310         unsigned int mapped_as_page;
 311
 312         /* Incomplete receive save location.  If the budget is exhausted
 313          * or the last descriptor (last normal descriptor or a following
 314          * context descriptor) has not been DMA'd yet the current state
 315          * of the receive processing needs to be saved.
 316          */
 317         unsigned int state_saved;
 318         struct {
 319                 unsigned int incomplete;
 320                 unsigned int context_next;
 321                 struct sk_buff *skb;
 322                 unsigned int len;
 323                 unsigned int error;
 324         } state;
 325 };
 326
 327 struct xgbe_ring {
 328         /* Ring lock - used just for TX rings at the moment */
 329         spinlock_t lock;
 330
 331         /* Per packet related information */
 332         struct xgbe_packet_data packet_data;
 333
 334         /* Virtual/DMA addresses and count of allocated descriptor memory */
 335         struct xgbe_ring_desc *rdesc;
 336         dma_addr_t rdesc_dma;
 337         unsigned int rdesc_count;
 338
 339         /* Array of descriptor data corresponding the descriptor memory
 340          * (always use the XGBE_GET_DESC_DATA macro to access this data)
 341          */
 342         struct xgbe_ring_data *rdata;
 343
 344         /* Page allocation for RX buffers */
 345         struct xgbe_page_alloc rx_hdr_pa;
 346         struct xgbe_page_alloc rx_buf_pa;
 347
 348         /* Ring index values
 349          *  cur   - Tx: index of descriptor to be used for current transfer
 350          *          Rx: index of descriptor to check for packet availability
 351          *  dirty - Tx: index of descriptor to check for transfer complete
 352          *          Rx: count of descriptors in which a packet has been received
 353          *              (used with skb_realloc_index to refresh the ring)
 354          */
 355         unsigned int cur;
 356         unsigned int dirty;
 357
 358         /* Coalesce frame count used for interrupt bit setting */
 359         unsigned int coalesce_count;
 360
 361         union {
 362                 struct {
 363                         unsigned int queue_stopped;
 364                         unsigned short cur_mss;
 365                         unsigned short cur_vlan_ctag;
 366                 } tx;
 367
 368                 struct {
 369                         unsigned int realloc_index;
 370                         unsigned int realloc_threshold;
 371                 } rx;
 372         };
 373 } ____cacheline_aligned;
 374
 375 /* Structure used to describe the descriptor rings associated with
 376  * a DMA channel.
 377  */
 378 struct xgbe_channel {
 379         char name[16];
 380
 381         /* Address of private data area for device */
 382         struct xgbe_prv_data *pdata;
 383
 384         /* Queue index and base address of queue's DMA registers */
 385         unsigned int queue_index;
 386         void __iomem *dma_regs;
 387
 388         /* Per channel interrupt irq number */
 389         int dma_irq;
 390
 391         /* Netdev related settings */
 392         struct napi_struct napi;
 393
 394         unsigned int saved_ier;
 395
 396         unsigned int tx_timer_active;
 397         struct hrtimer tx_timer;
 398
 399         struct xgbe_ring *tx_ring;
 400         struct xgbe_ring *rx_ring;
 401 } ____cacheline_aligned;
 402
 403 enum xgbe_int {
 404         XGMAC_INT_DMA_CH_SR_TI,
 405         XGMAC_INT_DMA_CH_SR_TPS,
 406         XGMAC_INT_DMA_CH_SR_TBU,
 407         XGMAC_INT_DMA_CH_SR_RI,
 408         XGMAC_INT_DMA_CH_SR_RBU,
 409         XGMAC_INT_DMA_CH_SR_RPS,
 410         XGMAC_INT_DMA_CH_SR_TI_RI,
 411         XGMAC_INT_DMA_CH_SR_FBE,
 412         XGMAC_INT_DMA_ALL,
 413 };
 414
 415 enum xgbe_int_state {
 416         XGMAC_INT_STATE_SAVE,
 417         XGMAC_INT_STATE_RESTORE,
 418 };
 419
 420 enum xgbe_mtl_fifo_size {
 421         XGMAC_MTL_FIFO_SIZE_256  = 0x00,
 422         XGMAC_MTL_FIFO_SIZE_512  = 0x01,
 423         XGMAC_MTL_FIFO_SIZE_1K   = 0x03,
 424         XGMAC_MTL_FIFO_SIZE_2K   = 0x07,
 425         XGMAC_MTL_FIFO_SIZE_4K   = 0x0f,
 426         XGMAC_MTL_FIFO_SIZE_8K   = 0x1f,
 427         XGMAC_MTL_FIFO_SIZE_16K  = 0x3f,
 428         XGMAC_MTL_FIFO_SIZE_32K  = 0x7f,
 429         XGMAC_MTL_FIFO_SIZE_64K  = 0xff,
 430         XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
 431         XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
 432 };
 433
 434 struct xgbe_mmc_stats {
 435         /* Tx Stats */
 436         u64 txoctetcount_gb;
 437         u64 txframecount_gb;
 438         u64 txbroadcastframes_g;
 439         u64 txmulticastframes_g;
 440         u64 tx64octets_gb;
 441         u64 tx65to127octets_gb;
 442         u64 tx128to255octets_gb;
 443         u64 tx256to511octets_gb;
 444         u64 tx512to1023octets_gb;
 445         u64 tx1024tomaxoctets_gb;
 446         u64 txunicastframes_gb;
 447         u64 txmulticastframes_gb;
 448         u64 txbroadcastframes_gb;
 449         u64 txunderflowerror;
 450         u64 txoctetcount_g;
 451         u64 txframecount_g;
 452         u64 txpauseframes;
 453         u64 txvlanframes_g;
 454
 455         /* Rx Stats */
 456         u64 rxframecount_gb;
 457         u64 rxoctetcount_gb;
 458         u64 rxoctetcount_g;
 459         u64 rxbroadcastframes_g;
 460         u64 rxmulticastframes_g;
 461         u64 rxcrcerror;
 462         u64 rxrunterror;
 463         u64 rxjabbererror;
 464         u64 rxundersize_g;
 465         u64 rxoversize_g;
 466         u64 rx64octets_gb;
 467         u64 rx65to127octets_gb;
 468         u64 rx128to255octets_gb;
 469         u64 rx256to511octets_gb;
 470         u64 rx512to1023octets_gb;
 471         u64 rx1024tomaxoctets_gb;
 472         u64 rxunicastframes_g;
 473         u64 rxlengtherror;
 474         u64 rxoutofrangetype;
 475         u64 rxpauseframes;
 476         u64 rxfifooverflow;
 477         u64 rxvlanframes_gb;
 478         u64 rxwatchdogerror;
 479 };
 480
 481 struct xgbe_hw_if {
 482         int (*tx_complete)(struct xgbe_ring_desc *);
 483
 484         int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
 485         int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
 486         int (*add_mac_addresses)(struct xgbe_prv_data *);
 487         int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
 488
 489         int (*enable_rx_csum)(struct xgbe_prv_data *);
 490         int (*disable_rx_csum)(struct xgbe_prv_data *);
 491
 492         int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
 493         int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
 494         int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
 495         int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
 496         int (*update_vlan_hash_table)(struct xgbe_prv_data *);
 497
 498         int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
 499         void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
 500         int (*set_gmii_speed)(struct xgbe_prv_data *);
 501         int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
 502         int (*set_xgmii_speed)(struct xgbe_prv_data *);
 503
 504         void (*enable_tx)(struct xgbe_prv_data *);
 505         void (*disable_tx)(struct xgbe_prv_data *);
 506         void (*enable_rx)(struct xgbe_prv_data *);
 507         void (*disable_rx)(struct xgbe_prv_data *);
 508
 509         void (*powerup_tx)(struct xgbe_prv_data *);
 510         void (*powerdown_tx)(struct xgbe_prv_data *);
 511         void (*powerup_rx)(struct xgbe_prv_data *);
 512         void (*powerdown_rx)(struct xgbe_prv_data *);
 513
 514         int (*init)(struct xgbe_prv_data *);
 515         int (*exit)(struct xgbe_prv_data *);
 516
 517         int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
 518         int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
 519         void (*dev_xmit)(struct xgbe_channel *);
 520         int (*dev_read)(struct xgbe_channel *);
 521         void (*tx_desc_init)(struct xgbe_channel *);
 522         void (*rx_desc_init)(struct xgbe_channel *);
 523         void (*rx_desc_reset)(struct xgbe_ring_data *);
 524         void (*tx_desc_reset)(struct xgbe_ring_data *);
 525         int (*is_last_desc)(struct xgbe_ring_desc *);
 526         int (*is_context_desc)(struct xgbe_ring_desc *);
 527
 528         /* For FLOW ctrl */
 529         int (*config_tx_flow_control)(struct xgbe_prv_data *);
 530         int (*config_rx_flow_control)(struct xgbe_prv_data *);
 531
 532         /* For RX coalescing */
 533         int (*config_rx_coalesce)(struct xgbe_prv_data *);
 534         int (*config_tx_coalesce)(struct xgbe_prv_data *);
 535         unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
 536         unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
 537
 538         /* For RX and TX threshold config */
 539         int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
 540         int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
 541
 542         /* For RX and TX Store and Forward Mode config */
 543         int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
 544         int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
 545
 546         /* For TX DMA Operate on Second Frame config */
 547         int (*config_osp_mode)(struct xgbe_prv_data *);
 548
 549         /* For RX and TX PBL config */
 550         int (*config_rx_pbl_val)(struct xgbe_prv_data *);
 551         int (*get_rx_pbl_val)(struct xgbe_prv_data *);
 552         int (*config_tx_pbl_val)(struct xgbe_prv_data *);
 553         int (*get_tx_pbl_val)(struct xgbe_prv_data *);
 554         int (*config_pblx8)(struct xgbe_prv_data *);
 555
 556         /* For MMC statistics */
 557         void (*rx_mmc_int)(struct xgbe_prv_data *);
 558         void (*tx_mmc_int)(struct xgbe_prv_data *);
 559         void (*read_mmc_stats)(struct xgbe_prv_data *);
 560
 561         /* For Timestamp config */
 562         int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
 563         void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
 564         void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
 565                                 unsigned int nsec);
 566         u64 (*get_tstamp_time)(struct xgbe_prv_data *);
 567         u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
 568
 569         /* For Data Center Bridging config */
 570         void (*config_dcb_tc)(struct xgbe_prv_data *);
 571         void (*config_dcb_pfc)(struct xgbe_prv_data *);
 572
 573         /* For Receive Side Scaling */
 574         int (*enable_rss)(struct xgbe_prv_data *);
 575         int (*disable_rss)(struct xgbe_prv_data *);
 576         int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
 577         int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
 578 };
 579
 580 struct xgbe_desc_if {
 581         int (*alloc_ring_resources)(struct xgbe_prv_data *);
 582         void (*free_ring_resources)(struct xgbe_prv_data *);
 583         int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
 584         void (*realloc_rx_buffer)(struct xgbe_channel *);
 585         void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
 586         void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
 587         void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
 588 };
 589
 590 /* This structure contains flags that indicate what hardware features
 591  * or configurations are present in the device.
 592  */
 593 struct xgbe_hw_features {
 594         /* HW Version */
 595         unsigned int version;
 596
 597         /* HW Feature Register0 */
 598         unsigned int gmii;              /* 1000 Mbps support */
 599         unsigned int vlhash;            /* VLAN Hash Filter */
 600         unsigned int sma;               /* SMA(MDIO) Interface */
 601         unsigned int rwk;               /* PMT remote wake-up packet */
 602         unsigned int mgk;               /* PMT magic packet */
 603         unsigned int mmc;               /* RMON module */
 604         unsigned int aoe;               /* ARP Offload */
 605         unsigned int ts;                /* IEEE 1588-2008 Adavanced Timestamp */
 606         unsigned int eee;               /* Energy Efficient Ethernet */
 607         unsigned int tx_coe;            /* Tx Checksum Offload */
 608         unsigned int rx_coe;            /* Rx Checksum Offload */
 609         unsigned int addn_mac;          /* Additional MAC Addresses */
 610         unsigned int ts_src;            /* Timestamp Source */
 611         unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 612
 613         /* HW Feature Register1 */
 614         unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 615         unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 616         unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 617         unsigned int dcb;               /* DCB Feature */
 618         unsigned int sph;               /* Split Header Feature */
 619         unsigned int tso;               /* TCP Segmentation Offload */
 620         unsigned int dma_debug;         /* DMA Debug Registers */
 621         unsigned int rss;               /* Receive Side Scaling */
 622         unsigned int tc_cnt;            /* Number of Traffic Classes */
 623         unsigned int hash_table_size;   /* Hash Table Size */
 624         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 625
 626         /* HW Feature Register2 */
 627         unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 628         unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 629         unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 630         unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 631         unsigned int pps_out_num;       /* Number of PPS outputs */
 632         unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 633 };
 634
 635 struct xgbe_prv_data {
 636         struct net_device *netdev;
 637         struct platform_device *pdev;
 638         struct device *dev;
 639
 640         /* XGMAC/XPCS related mmio registers */
 641         void __iomem *xgmac_regs;       /* XGMAC CSRs */
 642         void __iomem *xpcs_regs;        /* XPCS MMD registers */
 643
 644         /* Overall device lock */
 645         spinlock_t lock;
 646
 647         /* XPCS indirect addressing mutex */
 648         struct mutex xpcs_mutex;
 649
 650         /* RSS addressing mutex */
 651         struct mutex rss_mutex;
 652
 653         int dev_irq;
 654         unsigned int per_channel_irq;
 655
 656         struct xgbe_hw_if hw_if;
 657         struct xgbe_desc_if desc_if;
 658
 659         /* AXI DMA settings */
 660         unsigned int axdomain;
 661         unsigned int arcache;
 662         unsigned int awcache;
 663
 664         /* Rings for Tx/Rx on a DMA channel */
 665         struct xgbe_channel *channel;
 666         unsigned int channel_count;
 667         unsigned int tx_ring_count;
 668         unsigned int tx_desc_count;
 669         unsigned int rx_ring_count;
 670         unsigned int rx_desc_count;
 671
 672         unsigned int tx_q_count;
 673         unsigned int rx_q_count;
 674
 675         /* Tx/Rx common settings */
 676         unsigned int pblx8;
 677
 678         /* Tx settings */
 679         unsigned int tx_sf_mode;
 680         unsigned int tx_threshold;
 681         unsigned int tx_pbl;
 682         unsigned int tx_osp_mode;
 683
 684         /* Rx settings */
 685         unsigned int rx_sf_mode;
 686         unsigned int rx_threshold;
 687         unsigned int rx_pbl;
 688
 689         /* Tx coalescing settings */
 690         unsigned int tx_usecs;
 691         unsigned int tx_frames;
 692
 693         /* Rx coalescing settings */
 694         unsigned int rx_riwt;
 695         unsigned int rx_frames;
 696
 697         /* Current Rx buffer size */
 698         unsigned int rx_buf_size;
 699
 700         /* Flow control settings */
 701         unsigned int pause_autoneg;
 702         unsigned int tx_pause;
 703         unsigned int rx_pause;
 704
 705         /* Receive Side Scaling settings */
 706         u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
 707         u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
 708         u32 rss_options;
 709
 710         /* MDIO settings */
 711         struct module *phy_module;
 712         char *mii_bus_id;
 713         struct mii_bus *mii;
 714         int mdio_mmd;
 715         struct phy_device *phydev;
 716         int default_autoneg;
 717         int default_speed;
 718
 719         /* Current PHY settings */
 720         phy_interface_t phy_mode;
 721         int phy_link;
 722         int phy_speed;
 723         unsigned int phy_tx_pause;
 724         unsigned int phy_rx_pause;
 725
 726         /* Netdev related settings */
 727         netdev_features_t netdev_features;
 728         struct napi_struct napi;
 729         struct xgbe_mmc_stats mmc_stats;
 730
 731         /* Filtering support */
 732         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 733
 734         /* Device clocks */
 735         struct clk *sysclk;
 736         struct clk *ptpclk;
 737
 738         /* Timestamp support */
 739         spinlock_t tstamp_lock;
 740         struct ptp_clock_info ptp_clock_info;
 741         struct ptp_clock *ptp_clock;
 742         struct hwtstamp_config tstamp_config;
 743         struct cyclecounter tstamp_cc;
 744         struct timecounter tstamp_tc;
 745         unsigned int tstamp_addend;
 746         struct work_struct tx_tstamp_work;
 747         struct sk_buff *tx_tstamp_skb;
 748         u64 tx_tstamp;
 749
 750         /* DCB support */
 751         struct ieee_ets *ets;
 752         struct ieee_pfc *pfc;
 753         unsigned int q2tc_map[XGBE_MAX_QUEUES];
 754         unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
 755
 756         /* Hardware features of the device */
 757         struct xgbe_hw_features hw_feat;
 758
 759         /* Device restart work structure */
 760         struct work_struct restart_work;
 761
 762         /* Keeps track of power mode */
 763         unsigned int power_down;
 764
 765 #ifdef CONFIG_DEBUG_FS
 766         struct dentry *xgbe_debugfs;
 767
 768         unsigned int debugfs_xgmac_reg;
 769
 770         unsigned int debugfs_xpcs_mmd;
 771         unsigned int debugfs_xpcs_reg;
 772 #endif
 773 };
 774
 775 /* Function prototypes*/
 776
 777 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 778 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
 779 struct net_device_ops *xgbe_get_netdev_ops(void);
 780 struct ethtool_ops *xgbe_get_ethtool_ops(void);
 781 #ifdef CONFIG_AMD_XGBE_DCB
 782 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
 783 #endif
 784
 785 int xgbe_mdio_register(struct xgbe_prv_data *);
 786 void xgbe_mdio_unregister(struct xgbe_prv_data *);
 787 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
 788 void xgbe_ptp_register(struct xgbe_prv_data *);
 789 void xgbe_ptp_unregister(struct xgbe_prv_data *);
 790 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
 791                        unsigned int);
 792 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
 793                        unsigned int);
 794 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
 795 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
 796 int xgbe_powerup(struct net_device *, unsigned int);
 797 int xgbe_powerdown(struct net_device *, unsigned int);
 798 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
 799 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
 800
 801 #ifdef CONFIG_DEBUG_FS
 802 void xgbe_debugfs_init(struct xgbe_prv_data *);
 803 void xgbe_debugfs_exit(struct xgbe_prv_data *);
 804 #else
 805 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
 806 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
 807 #endif /* CONFIG_DEBUG_FS */
 808
 809 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
 810 #if 0
 811 #define XGMAC_ENABLE_TX_DESC_DUMP
 812 #define XGMAC_ENABLE_RX_DESC_DUMP
 813 #endif
 814
 815 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
 816 #if 0
 817 #define XGMAC_ENABLE_TX_PKT_DUMP
 818 #define XGMAC_ENABLE_RX_PKT_DUMP
 819 #endif
 820
 821 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
 822 #if 0
 823 #define YDEBUG
 824 #define YDEBUG_MDIO
 825 #endif
 826
 827 /* For debug prints */
 828 #ifdef YDEBUG
 829 #define DBGPR(x...) pr_alert(x)
 830 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
 831 #else
 832 #define DBGPR(x...) do { } while (0)
 833 #define DBGPHY_REGS(x...) do { } while (0)
 834 #endif
 835
 836 #ifdef YDEBUG_MDIO
 837 #define DBGPR_MDIO(x...) pr_alert(x)
 838 #else
 839 #define DBGPR_MDIO(x...) do { } while (0)
 840 #endif
 841
 842 #endif