drivers/net/ethernet/amd/xgbe/xgbe.h

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #ifndef __XGBE_H__
 118 #define __XGBE_H__
 119
 120 #include <linux/dma-mapping.h>
 121 #include <linux/netdevice.h>
 122 #include <linux/workqueue.h>
 123 #include <linux/phy.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/bitops.h>
 126 #include <linux/ptp_clock_kernel.h>
 127 #include <linux/timecounter.h>
 128 #include <linux/net_tstamp.h>
 129 #include <net/dcbnl.h>
 130
 131 #define XGBE_DRV_NAME           "amd-xgbe"
 132 #define XGBE_DRV_VERSION        "1.0.1"
 133 #define XGBE_DRV_DESC           "AMD 10 Gigabit Ethernet Driver"
 134
 135 /* Descriptor related defines */
 136 #define XGBE_TX_DESC_CNT        512
 137 #define XGBE_TX_DESC_MIN_FREE   (XGBE_TX_DESC_CNT >> 3)
 138 #define XGBE_TX_DESC_MAX_PROC   (XGBE_TX_DESC_CNT >> 1)
 139 #define XGBE_RX_DESC_CNT        512
 140
 141 #define XGBE_TX_MAX_BUF_SIZE    (0x3fff & ~(64 - 1))
 142
 143 /* Descriptors required for maximum contigous TSO/GSO packet */
 144 #define XGBE_TX_MAX_SPLIT       ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
 145
 146 /* Maximum possible descriptors needed for an SKB:
 147  * - Maximum number of SKB frags
 148  * - Maximum descriptors for contiguous TSO/GSO packet
 149  * - Possible context descriptor
 150  * - Possible TSO header descriptor
 151  */
 152 #define XGBE_TX_MAX_DESCS       (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
 153
 154 #define XGBE_RX_MIN_BUF_SIZE    (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 155 #define XGBE_RX_BUF_ALIGN       64
 156 #define XGBE_SKB_ALLOC_SIZE     256
 157 #define XGBE_SPH_HDSMS_SIZE     2       /* Keep in sync with SKB_ALLOC_SIZE */
 158
 159 #define XGBE_MAX_DMA_CHANNELS   16
 160 #define XGBE_MAX_QUEUES         16
 161 #define XGBE_DMA_STOP_TIMEOUT   5
 162
 163 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 164 #define XGBE_DMA_OS_AXDOMAIN    0x2
 165 #define XGBE_DMA_OS_ARCACHE     0xb
 166 #define XGBE_DMA_OS_AWCACHE     0xf
 167
 168 /* DMA cache settings - System, no caches used */
 169 #define XGBE_DMA_SYS_AXDOMAIN   0x3
 170 #define XGBE_DMA_SYS_ARCACHE    0x0
 171 #define XGBE_DMA_SYS_AWCACHE    0x0
 172
 173 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
 174
 175 #define XGMAC_MIN_PACKET        60
 176 #define XGMAC_STD_PACKET_MTU    1500
 177 #define XGMAC_MAX_STD_PACKET    1518
 178 #define XGMAC_JUMBO_PACKET_MTU  9000
 179 #define XGMAC_MAX_JUMBO_PACKET  9018
 180
 181 /* Common property names */
 182 #define XGBE_MAC_ADDR_PROPERTY  "mac-address"
 183 #define XGBE_PHY_MODE_PROPERTY  "phy-mode"
 184 #define XGBE_DMA_IRQS_PROPERTY  "amd,per-channel-interrupt"
 185 #define XGBE_SPEEDSET_PROPERTY  "amd,speed-set"
 186 #define XGBE_BLWC_PROPERTY      "amd,serdes-blwc"
 187 #define XGBE_CDR_RATE_PROPERTY  "amd,serdes-cdr-rate"
 188 #define XGBE_PQ_SKEW_PROPERTY   "amd,serdes-pq-skew"
 189 #define XGBE_TX_AMP_PROPERTY    "amd,serdes-tx-amp"
 190 #define XGBE_DFE_CFG_PROPERTY   "amd,serdes-dfe-tap-config"
 191 #define XGBE_DFE_ENA_PROPERTY   "amd,serdes-dfe-tap-enable"
 192
 193 /* Device-tree clock names */
 194 #define XGBE_DMA_CLOCK          "dma_clk"
 195 #define XGBE_PTP_CLOCK          "ptp_clk"
 196
 197 /* ACPI property names */
 198 #define XGBE_ACPI_DMA_FREQ      "amd,dma-freq"
 199 #define XGBE_ACPI_PTP_FREQ      "amd,ptp-freq"
 200
 201 /* Timestamp support - values based on 50MHz PTP clock
 202  *   50MHz => 20 nsec
 203  */
 204 #define XGBE_TSTAMP_SSINC       20
 205 #define XGBE_TSTAMP_SNSINC      0
 206
 207 /* Driver PMT macros */
 208 #define XGMAC_DRIVER_CONTEXT    1
 209 #define XGMAC_IOCTL_CONTEXT     2
 210
 211 #define XGBE_FIFO_MAX           81920
 212 #define XGBE_FIFO_SIZE_B(x)     (x)
 213 #define XGBE_FIFO_SIZE_KB(x)    (x * 1024)
 214
 215 #define XGBE_TC_MIN_QUANTUM     10
 216
 217 /* Helper macro for descriptor handling
 218  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
 219  *  since the index is free-running and needs to be and-ed
 220  *  with the descriptor count value of the ring to index to
 221  *  the proper descriptor data.
 222  */
 223 #define XGBE_GET_DESC_DATA(_ring, _idx)                         \
 224         ((_ring)->rdata +                                       \
 225          ((_idx) & ((_ring)->rdesc_count - 1)))
 226
 227 /* Default coalescing parameters */
 228 #define XGMAC_INIT_DMA_TX_USECS         1000
 229 #define XGMAC_INIT_DMA_TX_FRAMES        25
 230
 231 #define XGMAC_MAX_DMA_RIWT              0xff
 232 #define XGMAC_INIT_DMA_RX_USECS         30
 233 #define XGMAC_INIT_DMA_RX_FRAMES        25
 234
 235 /* Flow control queue count */
 236 #define XGMAC_MAX_FLOW_CONTROL_QUEUES   8
 237
 238 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
 239 #define XGBE_MAC_HASH_TABLE_SIZE        8
 240
 241 /* Receive Side Scaling */
 242 #define XGBE_RSS_HASH_KEY_SIZE          40
 243 #define XGBE_RSS_MAX_TABLE_SIZE         256
 244 #define XGBE_RSS_LOOKUP_TABLE_TYPE      0
 245 #define XGBE_RSS_HASH_KEY_TYPE          1
 246
 247 /* Auto-negotiation */
 248 #define XGBE_AN_MS_TIMEOUT              500
 249 #define XGBE_LINK_TIMEOUT               10
 250
 251 #define XGBE_AN_INT_CMPLT               0x01
 252 #define XGBE_AN_INC_LINK                0x02
 253 #define XGBE_AN_PG_RCV                  0x04
 254 #define XGBE_AN_INT_MASK                0x07
 255
 256 /* Rate-change complete wait/retry count */
 257 #define XGBE_RATECHANGE_COUNT           500
 258
 259 /* Default SerDes settings */
 260 #define XGBE_SPEED_10000_BLWC           0
 261 #define XGBE_SPEED_10000_CDR            0x7
 262 #define XGBE_SPEED_10000_PLL            0x1
 263 #define XGBE_SPEED_10000_PQ             0x12
 264 #define XGBE_SPEED_10000_RATE           0x0
 265 #define XGBE_SPEED_10000_TXAMP          0xa
 266 #define XGBE_SPEED_10000_WORD           0x7
 267 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
 268 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
 269
 270 #define XGBE_SPEED_2500_BLWC            1
 271 #define XGBE_SPEED_2500_CDR             0x2
 272 #define XGBE_SPEED_2500_PLL             0x0
 273 #define XGBE_SPEED_2500_PQ              0xa
 274 #define XGBE_SPEED_2500_RATE            0x1
 275 #define XGBE_SPEED_2500_TXAMP           0xf
 276 #define XGBE_SPEED_2500_WORD            0x1
 277 #define XGBE_SPEED_2500_DFE_TAP_CONFIG  0x3
 278 #define XGBE_SPEED_2500_DFE_TAP_ENABLE  0x0
 279
 280 #define XGBE_SPEED_1000_BLWC            1
 281 #define XGBE_SPEED_1000_CDR             0x2
 282 #define XGBE_SPEED_1000_PLL             0x0
 283 #define XGBE_SPEED_1000_PQ              0xa
 284 #define XGBE_SPEED_1000_RATE            0x3
 285 #define XGBE_SPEED_1000_TXAMP           0xf
 286 #define XGBE_SPEED_1000_WORD            0x1
 287 #define XGBE_SPEED_1000_DFE_TAP_CONFIG  0x3
 288 #define XGBE_SPEED_1000_DFE_TAP_ENABLE  0x0
 289
 290 struct xgbe_prv_data;
 291
 292 struct xgbe_packet_data {
 293         struct sk_buff *skb;
 294
 295         unsigned int attributes;
 296
 297         unsigned int errors;
 298
 299         unsigned int rdesc_count;
 300         unsigned int length;
 301
 302         unsigned int header_len;
 303         unsigned int tcp_header_len;
 304         unsigned int tcp_payload_len;
 305         unsigned short mss;
 306
 307         unsigned short vlan_ctag;
 308
 309         u64 rx_tstamp;
 310
 311         u32 rss_hash;
 312         enum pkt_hash_types rss_hash_type;
 313
 314         unsigned int tx_packets;
 315         unsigned int tx_bytes;
 316 };
 317
 318 /* Common Rx and Tx descriptor mapping */
 319 struct xgbe_ring_desc {
 320         __le32 desc0;
 321         __le32 desc1;
 322         __le32 desc2;
 323         __le32 desc3;
 324 };
 325
 326 /* Page allocation related values */
 327 struct xgbe_page_alloc {
 328         struct page *pages;
 329         unsigned int pages_len;
 330         unsigned int pages_offset;
 331
 332         dma_addr_t pages_dma;
 333 };
 334
 335 /* Ring entry buffer data */
 336 struct xgbe_buffer_data {
 337         struct xgbe_page_alloc pa;
 338         struct xgbe_page_alloc pa_unmap;
 339
 340         dma_addr_t dma;
 341         unsigned int dma_len;
 342 };
 343
 344 /* Tx-related ring data */
 345 struct xgbe_tx_ring_data {
 346         unsigned int packets;           /* BQL packet count */
 347         unsigned int bytes;             /* BQL byte count */
 348 };
 349
 350 /* Rx-related ring data */
 351 struct xgbe_rx_ring_data {
 352         struct xgbe_buffer_data hdr;    /* Header locations */
 353         struct xgbe_buffer_data buf;    /* Payload locations */
 354
 355         unsigned short hdr_len;         /* Length of received header */
 356         unsigned short len;             /* Length of received packet */
 357 };
 358
 359 /* Structure used to hold information related to the descriptor
 360  * and the packet associated with the descriptor (always use
 361  * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
 362  */
 363 struct xgbe_ring_data {
 364         struct xgbe_ring_desc *rdesc;   /* Virtual address of descriptor */
 365         dma_addr_t rdesc_dma;           /* DMA address of descriptor */
 366
 367         struct sk_buff *skb;            /* Virtual address of SKB */
 368         dma_addr_t skb_dma;             /* DMA address of SKB data */
 369         unsigned int skb_dma_len;       /* Length of SKB DMA area */
 370
 371         struct xgbe_tx_ring_data tx;    /* Tx-related data */
 372         struct xgbe_rx_ring_data rx;    /* Rx-related data */
 373
 374         unsigned int mapped_as_page;
 375
 376         /* Incomplete receive save location.  If the budget is exhausted
 377          * or the last descriptor (last normal descriptor or a following
 378          * context descriptor) has not been DMA'd yet the current state
 379          * of the receive processing needs to be saved.
 380          */
 381         unsigned int state_saved;
 382         struct {
 383                 struct sk_buff *skb;
 384                 unsigned int len;
 385                 unsigned int error;
 386         } state;
 387 };
 388
 389 struct xgbe_ring {
 390         /* Ring lock - used just for TX rings at the moment */
 391         spinlock_t lock;
 392
 393         /* Per packet related information */
 394         struct xgbe_packet_data packet_data;
 395
 396         /* Virtual/DMA addresses and count of allocated descriptor memory */
 397         struct xgbe_ring_desc *rdesc;
 398         dma_addr_t rdesc_dma;
 399         unsigned int rdesc_count;
 400
 401         /* Array of descriptor data corresponding the descriptor memory
 402          * (always use the XGBE_GET_DESC_DATA macro to access this data)
 403          */
 404         struct xgbe_ring_data *rdata;
 405
 406         /* Page allocation for RX buffers */
 407         struct xgbe_page_alloc rx_hdr_pa;
 408         struct xgbe_page_alloc rx_buf_pa;
 409
 410         /* Ring index values
 411          *  cur   - Tx: index of descriptor to be used for current transfer
 412          *          Rx: index of descriptor to check for packet availability
 413          *  dirty - Tx: index of descriptor to check for transfer complete
 414          *          Rx: index of descriptor to check for buffer reallocation
 415          */
 416         unsigned int cur;
 417         unsigned int dirty;
 418
 419         /* Coalesce frame count used for interrupt bit setting */
 420         unsigned int coalesce_count;
 421
 422         union {
 423                 struct {
 424                         unsigned int queue_stopped;
 425                         unsigned int xmit_more;
 426                         unsigned short cur_mss;
 427                         unsigned short cur_vlan_ctag;
 428                 } tx;
 429         };
 430 } ____cacheline_aligned;
 431
 432 /* Structure used to describe the descriptor rings associated with
 433  * a DMA channel.
 434  */
 435 struct xgbe_channel {
 436         char name[16];
 437
 438         /* Address of private data area for device */
 439         struct xgbe_prv_data *pdata;
 440
 441         /* Queue index and base address of queue's DMA registers */
 442         unsigned int queue_index;
 443         void __iomem *dma_regs;
 444
 445         /* Per channel interrupt irq number */
 446         int dma_irq;
 447         char dma_irq_name[IFNAMSIZ + 32];
 448
 449         /* Netdev related settings */
 450         struct napi_struct napi;
 451
 452         unsigned int saved_ier;
 453
 454         unsigned int tx_timer_active;
 455         struct timer_list tx_timer;
 456
 457         struct xgbe_ring *tx_ring;
 458         struct xgbe_ring *rx_ring;
 459 } ____cacheline_aligned;
 460
 461 enum xgbe_state {
 462         XGBE_DOWN,
 463         XGBE_LINK,
 464         XGBE_LINK_INIT,
 465         XGBE_LINK_ERR,
 466 };
 467
 468 enum xgbe_int {
 469         XGMAC_INT_DMA_CH_SR_TI,
 470         XGMAC_INT_DMA_CH_SR_TPS,
 471         XGMAC_INT_DMA_CH_SR_TBU,
 472         XGMAC_INT_DMA_CH_SR_RI,
 473         XGMAC_INT_DMA_CH_SR_RBU,
 474         XGMAC_INT_DMA_CH_SR_RPS,
 475         XGMAC_INT_DMA_CH_SR_TI_RI,
 476         XGMAC_INT_DMA_CH_SR_FBE,
 477         XGMAC_INT_DMA_ALL,
 478 };
 479
 480 enum xgbe_int_state {
 481         XGMAC_INT_STATE_SAVE,
 482         XGMAC_INT_STATE_RESTORE,
 483 };
 484
 485 enum xgbe_mtl_fifo_size {
 486         XGMAC_MTL_FIFO_SIZE_256  = 0x00,
 487         XGMAC_MTL_FIFO_SIZE_512  = 0x01,
 488         XGMAC_MTL_FIFO_SIZE_1K   = 0x03,
 489         XGMAC_MTL_FIFO_SIZE_2K   = 0x07,
 490         XGMAC_MTL_FIFO_SIZE_4K   = 0x0f,
 491         XGMAC_MTL_FIFO_SIZE_8K   = 0x1f,
 492         XGMAC_MTL_FIFO_SIZE_16K  = 0x3f,
 493         XGMAC_MTL_FIFO_SIZE_32K  = 0x7f,
 494         XGMAC_MTL_FIFO_SIZE_64K  = 0xff,
 495         XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
 496         XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
 497 };
 498
 499 enum xgbe_speed {
 500         XGBE_SPEED_1000 = 0,
 501         XGBE_SPEED_2500,
 502         XGBE_SPEED_10000,
 503         XGBE_SPEEDS,
 504 };
 505
 506 enum xgbe_an {
 507         XGBE_AN_READY = 0,
 508         XGBE_AN_PAGE_RECEIVED,
 509         XGBE_AN_INCOMPAT_LINK,
 510         XGBE_AN_COMPLETE,
 511         XGBE_AN_NO_LINK,
 512         XGBE_AN_ERROR,
 513 };
 514
 515 enum xgbe_rx {
 516         XGBE_RX_BPA = 0,
 517         XGBE_RX_XNP,
 518         XGBE_RX_COMPLETE,
 519         XGBE_RX_ERROR,
 520 };
 521
 522 enum xgbe_mode {
 523         XGBE_MODE_KR = 0,
 524         XGBE_MODE_KX,
 525 };
 526
 527 enum xgbe_speedset {
 528         XGBE_SPEEDSET_1000_10000 = 0,
 529         XGBE_SPEEDSET_2500_10000,
 530 };
 531
 532 struct xgbe_phy {
 533         u32 supported;
 534         u32 advertising;
 535         u32 lp_advertising;
 536
 537         int address;
 538
 539         int autoneg;
 540         int speed;
 541         int duplex;
 542         int pause;
 543         int asym_pause;
 544
 545         int link;
 546 };
 547
 548 struct xgbe_mmc_stats {
 549         /* Tx Stats */
 550         u64 txoctetcount_gb;
 551         u64 txframecount_gb;
 552         u64 txbroadcastframes_g;
 553         u64 txmulticastframes_g;
 554         u64 tx64octets_gb;
 555         u64 tx65to127octets_gb;
 556         u64 tx128to255octets_gb;
 557         u64 tx256to511octets_gb;
 558         u64 tx512to1023octets_gb;
 559         u64 tx1024tomaxoctets_gb;
 560         u64 txunicastframes_gb;
 561         u64 txmulticastframes_gb;
 562         u64 txbroadcastframes_gb;
 563         u64 txunderflowerror;
 564         u64 txoctetcount_g;
 565         u64 txframecount_g;
 566         u64 txpauseframes;
 567         u64 txvlanframes_g;
 568
 569         /* Rx Stats */
 570         u64 rxframecount_gb;
 571         u64 rxoctetcount_gb;
 572         u64 rxoctetcount_g;
 573         u64 rxbroadcastframes_g;
 574         u64 rxmulticastframes_g;
 575         u64 rxcrcerror;
 576         u64 rxrunterror;
 577         u64 rxjabbererror;
 578         u64 rxundersize_g;
 579         u64 rxoversize_g;
 580         u64 rx64octets_gb;
 581         u64 rx65to127octets_gb;
 582         u64 rx128to255octets_gb;
 583         u64 rx256to511octets_gb;
 584         u64 rx512to1023octets_gb;
 585         u64 rx1024tomaxoctets_gb;
 586         u64 rxunicastframes_g;
 587         u64 rxlengtherror;
 588         u64 rxoutofrangetype;
 589         u64 rxpauseframes;
 590         u64 rxfifooverflow;
 591         u64 rxvlanframes_gb;
 592         u64 rxwatchdogerror;
 593 };
 594
 595 struct xgbe_ext_stats {
 596         u64 tx_tso_packets;
 597         u64 rx_split_header_packets;
 598 };
 599
 600 struct xgbe_hw_if {
 601         int (*tx_complete)(struct xgbe_ring_desc *);
 602
 603         int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
 604         int (*config_rx_mode)(struct xgbe_prv_data *);
 605
 606         int (*enable_rx_csum)(struct xgbe_prv_data *);
 607         int (*disable_rx_csum)(struct xgbe_prv_data *);
 608
 609         int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
 610         int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
 611         int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
 612         int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
 613         int (*update_vlan_hash_table)(struct xgbe_prv_data *);
 614
 615         int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
 616         void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
 617         int (*set_gmii_speed)(struct xgbe_prv_data *);
 618         int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
 619         int (*set_xgmii_speed)(struct xgbe_prv_data *);
 620
 621         void (*enable_tx)(struct xgbe_prv_data *);
 622         void (*disable_tx)(struct xgbe_prv_data *);
 623         void (*enable_rx)(struct xgbe_prv_data *);
 624         void (*disable_rx)(struct xgbe_prv_data *);
 625
 626         void (*powerup_tx)(struct xgbe_prv_data *);
 627         void (*powerdown_tx)(struct xgbe_prv_data *);
 628         void (*powerup_rx)(struct xgbe_prv_data *);
 629         void (*powerdown_rx)(struct xgbe_prv_data *);
 630
 631         int (*init)(struct xgbe_prv_data *);
 632         int (*exit)(struct xgbe_prv_data *);
 633
 634         int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
 635         int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
 636         void (*dev_xmit)(struct xgbe_channel *);
 637         int (*dev_read)(struct xgbe_channel *);
 638         void (*tx_desc_init)(struct xgbe_channel *);
 639         void (*rx_desc_init)(struct xgbe_channel *);
 640         void (*tx_desc_reset)(struct xgbe_ring_data *);
 641         void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
 642                               unsigned int);
 643         int (*is_last_desc)(struct xgbe_ring_desc *);
 644         int (*is_context_desc)(struct xgbe_ring_desc *);
 645         void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
 646
 647         /* For FLOW ctrl */
 648         int (*config_tx_flow_control)(struct xgbe_prv_data *);
 649         int (*config_rx_flow_control)(struct xgbe_prv_data *);
 650
 651         /* For RX coalescing */
 652         int (*config_rx_coalesce)(struct xgbe_prv_data *);
 653         int (*config_tx_coalesce)(struct xgbe_prv_data *);
 654         unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
 655         unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
 656
 657         /* For RX and TX threshold config */
 658         int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
 659         int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
 660
 661         /* For RX and TX Store and Forward Mode config */
 662         int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
 663         int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
 664
 665         /* For TX DMA Operate on Second Frame config */
 666         int (*config_osp_mode)(struct xgbe_prv_data *);
 667
 668         /* For RX and TX PBL config */
 669         int (*config_rx_pbl_val)(struct xgbe_prv_data *);
 670         int (*get_rx_pbl_val)(struct xgbe_prv_data *);
 671         int (*config_tx_pbl_val)(struct xgbe_prv_data *);
 672         int (*get_tx_pbl_val)(struct xgbe_prv_data *);
 673         int (*config_pblx8)(struct xgbe_prv_data *);
 674
 675         /* For MMC statistics */
 676         void (*rx_mmc_int)(struct xgbe_prv_data *);
 677         void (*tx_mmc_int)(struct xgbe_prv_data *);
 678         void (*read_mmc_stats)(struct xgbe_prv_data *);
 679
 680         /* For Timestamp config */
 681         int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
 682         void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
 683         void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
 684                                 unsigned int nsec);
 685         u64 (*get_tstamp_time)(struct xgbe_prv_data *);
 686         u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
 687
 688         /* For Data Center Bridging config */
 689         void (*config_dcb_tc)(struct xgbe_prv_data *);
 690         void (*config_dcb_pfc)(struct xgbe_prv_data *);
 691
 692         /* For Receive Side Scaling */
 693         int (*enable_rss)(struct xgbe_prv_data *);
 694         int (*disable_rss)(struct xgbe_prv_data *);
 695         int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
 696         int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
 697 };
 698
 699 struct xgbe_phy_if {
 700         /* For initial PHY setup */
 701         void (*phy_init)(struct xgbe_prv_data *);
 702
 703         /* For PHY support when setting device up/down */
 704         int (*phy_reset)(struct xgbe_prv_data *);
 705         int (*phy_start)(struct xgbe_prv_data *);
 706         void (*phy_stop)(struct xgbe_prv_data *);
 707
 708         /* For PHY support while device is up */
 709         void (*phy_status)(struct xgbe_prv_data *);
 710         int (*phy_config_aneg)(struct xgbe_prv_data *);
 711 };
 712
 713 struct xgbe_desc_if {
 714         int (*alloc_ring_resources)(struct xgbe_prv_data *);
 715         void (*free_ring_resources)(struct xgbe_prv_data *);
 716         int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
 717         int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
 718                              struct xgbe_ring_data *);
 719         void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
 720         void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
 721         void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
 722 };
 723
 724 /* This structure contains flags that indicate what hardware features
 725  * or configurations are present in the device.
 726  */
 727 struct xgbe_hw_features {
 728         /* HW Version */
 729         unsigned int version;
 730
 731         /* HW Feature Register0 */
 732         unsigned int gmii;              /* 1000 Mbps support */
 733         unsigned int vlhash;            /* VLAN Hash Filter */
 734         unsigned int sma;               /* SMA(MDIO) Interface */
 735         unsigned int rwk;               /* PMT remote wake-up packet */
 736         unsigned int mgk;               /* PMT magic packet */
 737         unsigned int mmc;               /* RMON module */
 738         unsigned int aoe;               /* ARP Offload */
 739         unsigned int ts;                /* IEEE 1588-2008 Advanced Timestamp */
 740         unsigned int eee;               /* Energy Efficient Ethernet */
 741         unsigned int tx_coe;            /* Tx Checksum Offload */
 742         unsigned int rx_coe;            /* Rx Checksum Offload */
 743         unsigned int addn_mac;          /* Additional MAC Addresses */
 744         unsigned int ts_src;            /* Timestamp Source */
 745         unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 746
 747         /* HW Feature Register1 */
 748         unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 749         unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 750         unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 751         unsigned int dma_width;         /* DMA width */
 752         unsigned int dcb;               /* DCB Feature */
 753         unsigned int sph;               /* Split Header Feature */
 754         unsigned int tso;               /* TCP Segmentation Offload */
 755         unsigned int dma_debug;         /* DMA Debug Registers */
 756         unsigned int rss;               /* Receive Side Scaling */
 757         unsigned int tc_cnt;            /* Number of Traffic Classes */
 758         unsigned int hash_table_size;   /* Hash Table Size */
 759         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 760
 761         /* HW Feature Register2 */
 762         unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 763         unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 764         unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 765         unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 766         unsigned int pps_out_num;       /* Number of PPS outputs */
 767         unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 768 };
 769
 770 struct xgbe_prv_data {
 771         struct net_device *netdev;
 772         struct platform_device *pdev;
 773         struct acpi_device *adev;
 774         struct device *dev;
 775
 776         /* ACPI or DT flag */
 777         unsigned int use_acpi;
 778
 779         /* XGMAC/XPCS related mmio registers */
 780         void __iomem *xgmac_regs;       /* XGMAC CSRs */
 781         void __iomem *xpcs_regs;        /* XPCS MMD registers */
 782         void __iomem *rxtx_regs;        /* SerDes Rx/Tx CSRs */
 783         void __iomem *sir0_regs;        /* SerDes integration registers (1/2) */
 784         void __iomem *sir1_regs;        /* SerDes integration registers (2/2) */
 785
 786         /* Overall device lock */
 787         spinlock_t lock;
 788
 789         /* XPCS indirect addressing mutex */
 790         struct mutex xpcs_mutex;
 791
 792         /* RSS addressing mutex */
 793         struct mutex rss_mutex;
 794
 795         /* Flags representing xgbe_state */
 796         unsigned long dev_state;
 797
 798         int dev_irq;
 799         unsigned int per_channel_irq;
 800
 801         struct xgbe_hw_if hw_if;
 802         struct xgbe_phy_if phy_if;
 803         struct xgbe_desc_if desc_if;
 804
 805         /* AXI DMA settings */
 806         unsigned int coherent;
 807         unsigned int axdomain;
 808         unsigned int arcache;
 809         unsigned int awcache;
 810
 811         /* Service routine support */
 812         struct workqueue_struct *dev_workqueue;
 813         struct work_struct service_work;
 814         struct timer_list service_timer;
 815
 816         /* Rings for Tx/Rx on a DMA channel */
 817         struct xgbe_channel *channel;
 818         unsigned int channel_count;
 819         unsigned int tx_ring_count;
 820         unsigned int tx_desc_count;
 821         unsigned int rx_ring_count;
 822         unsigned int rx_desc_count;
 823
 824         unsigned int tx_q_count;
 825         unsigned int rx_q_count;
 826
 827         /* Tx/Rx common settings */
 828         unsigned int pblx8;
 829
 830         /* Tx settings */
 831         unsigned int tx_sf_mode;
 832         unsigned int tx_threshold;
 833         unsigned int tx_pbl;
 834         unsigned int tx_osp_mode;
 835
 836         /* Rx settings */
 837         unsigned int rx_sf_mode;
 838         unsigned int rx_threshold;
 839         unsigned int rx_pbl;
 840
 841         /* Tx coalescing settings */
 842         unsigned int tx_usecs;
 843         unsigned int tx_frames;
 844
 845         /* Rx coalescing settings */
 846         unsigned int rx_riwt;
 847         unsigned int rx_usecs;
 848         unsigned int rx_frames;
 849
 850         /* Current Rx buffer size */
 851         unsigned int rx_buf_size;
 852
 853         /* Flow control settings */
 854         unsigned int pause_autoneg;
 855         unsigned int tx_pause;
 856         unsigned int rx_pause;
 857
 858         /* Receive Side Scaling settings */
 859         u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
 860         u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
 861         u32 rss_options;
 862
 863         /* Netdev related settings */
 864         unsigned char mac_addr[ETH_ALEN];
 865         netdev_features_t netdev_features;
 866         struct napi_struct napi;
 867         struct xgbe_mmc_stats mmc_stats;
 868         struct xgbe_ext_stats ext_stats;
 869
 870         /* Filtering support */
 871         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 872
 873         /* Device clocks */
 874         struct clk *sysclk;
 875         unsigned long sysclk_rate;
 876         struct clk *ptpclk;
 877         unsigned long ptpclk_rate;
 878
 879         /* Timestamp support */
 880         spinlock_t tstamp_lock;
 881         struct ptp_clock_info ptp_clock_info;
 882         struct ptp_clock *ptp_clock;
 883         struct hwtstamp_config tstamp_config;
 884         struct cyclecounter tstamp_cc;
 885         struct timecounter tstamp_tc;
 886         unsigned int tstamp_addend;
 887         struct work_struct tx_tstamp_work;
 888         struct sk_buff *tx_tstamp_skb;
 889         u64 tx_tstamp;
 890
 891         /* DCB support */
 892         struct ieee_ets *ets;
 893         struct ieee_pfc *pfc;
 894         unsigned int q2tc_map[XGBE_MAX_QUEUES];
 895         unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
 896
 897         /* Hardware features of the device */
 898         struct xgbe_hw_features hw_feat;
 899
 900         /* Device restart work structure */
 901         struct work_struct restart_work;
 902
 903         /* Keeps track of power mode */
 904         unsigned int power_down;
 905
 906         /* Network interface message level setting */
 907         u32 msg_enable;
 908
 909         /* Current PHY settings */
 910         phy_interface_t phy_mode;
 911         int phy_link;
 912         int phy_speed;
 913         unsigned int phy_tx_pause;
 914         unsigned int phy_rx_pause;
 915
 916         /* MDIO/PHY related settings */
 917         struct xgbe_phy phy;
 918         int mdio_mmd;
 919         unsigned long link_check;
 920
 921         char an_name[IFNAMSIZ + 32];
 922         struct workqueue_struct *an_workqueue;
 923
 924         int an_irq;
 925         struct work_struct an_irq_work;
 926
 927         unsigned int speed_set;
 928
 929         /* SerDes UEFI configurable settings.
 930          *   Switching between modes/speeds requires new values for some
 931          *   SerDes settings.  The values can be supplied as device
 932          *   properties in array format.  The first array entry is for
 933          *   1GbE, second for 2.5GbE and third for 10GbE
 934          */
 935         u32 serdes_blwc[XGBE_SPEEDS];
 936         u32 serdes_cdr_rate[XGBE_SPEEDS];
 937         u32 serdes_pq_skew[XGBE_SPEEDS];
 938         u32 serdes_tx_amp[XGBE_SPEEDS];
 939         u32 serdes_dfe_tap_cfg[XGBE_SPEEDS];
 940         u32 serdes_dfe_tap_ena[XGBE_SPEEDS];
 941
 942         /* Auto-negotiation state machine support */
 943         struct mutex an_mutex;
 944         enum xgbe_an an_result;
 945         enum xgbe_an an_state;
 946         enum xgbe_rx kr_state;
 947         enum xgbe_rx kx_state;
 948         struct work_struct an_work;
 949         unsigned int an_supported;
 950         unsigned int parallel_detect;
 951         unsigned int fec_ability;
 952         unsigned long an_start;
 953
 954         unsigned int lpm_ctrl;          /* CTRL1 for resume */
 955
 956 #ifdef CONFIG_DEBUG_FS
 957         struct dentry *xgbe_debugfs;
 958
 959         unsigned int debugfs_xgmac_reg;
 960
 961         unsigned int debugfs_xpcs_mmd;
 962         unsigned int debugfs_xpcs_reg;
 963 #endif
 964 };
 965
 966 /* Function prototypes*/
 967
 968 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 969 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
 970 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
 971 struct net_device_ops *xgbe_get_netdev_ops(void);
 972 struct ethtool_ops *xgbe_get_ethtool_ops(void);
 973 #ifdef CONFIG_AMD_XGBE_DCB
 974 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
 975 #endif
 976
 977 void xgbe_ptp_register(struct xgbe_prv_data *);
 978 void xgbe_ptp_unregister(struct xgbe_prv_data *);
 979 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
 980                        unsigned int, unsigned int, unsigned int);
 981 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
 982                        unsigned int);
 983 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
 984 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
 985 int xgbe_powerup(struct net_device *, unsigned int);
 986 int xgbe_powerdown(struct net_device *, unsigned int);
 987 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
 988 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
 989
 990 #ifdef CONFIG_DEBUG_FS
 991 void xgbe_debugfs_init(struct xgbe_prv_data *);
 992 void xgbe_debugfs_exit(struct xgbe_prv_data *);
 993 #else
 994 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
 995 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
 996 #endif /* CONFIG_DEBUG_FS */
 997
 998 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
 999 #if 0
1000 #define YDEBUG
1001 #define YDEBUG_MDIO
1002 #endif
1003
1004 /* For debug prints */
1005 #ifdef YDEBUG
1006 #define DBGPR(x...) pr_alert(x)
1007 #else
1008 #define DBGPR(x...) do { } while (0)
1009 #endif
1010
1011 #ifdef YDEBUG_MDIO
1012 #define DBGPR_MDIO(x...) pr_alert(x)
1013 #else
1014 #define DBGPR_MDIO(x...) do { } while (0)
1015 #endif
1016
1017 #endif