1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __XGENE_ENET_HW_H__
23 #define __XGENE_ENET_HW_H__
25 #include "xgene_enet_main.h"
27 struct xgene_enet_pdata
;
28 struct xgene_enet_stats
;
30 /* clears and then set bits */
31 static inline void xgene_set_bits(u32
*dst
, u32 val
, u32 start
, u32 len
)
33 u32 end
= start
+ len
- 1;
34 u32 mask
= GENMASK(end
, start
);
37 *dst
|= (val
<< start
) & mask
;
40 static inline u32
xgene_get_bits(u32 val
, u32 start
, u32 end
)
42 return (val
& GENMASK(end
, start
)) >> start
;
51 #define CSR_RING_ID 0x0008
52 #define OVERWRITE BIT(31)
53 #define IS_BUFFER_POOL BIT(20)
54 #define PREFETCH_BUF_EN BIT(21)
55 #define CSR_RING_ID_BUF 0x000c
56 #define CSR_RING_NE_INT_MODE 0x017c
57 #define CSR_RING_CONFIG 0x006c
58 #define CSR_RING_WR_BASE 0x0070
59 #define NUM_RING_CONFIG 5
60 #define BUFPOOL_MODE 3
61 #define INC_DEC_CMD_ADDR 0x002c
62 #define UDP_HDR_SIZE 2
63 #define BUF_LEN_CODE_2K 0x5000
65 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
66 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
68 /* Empty slot soft signature */
69 #define EMPTY_SLOT_INDEX 1
70 #define EMPTY_SLOT ~0ULL
72 #define WORK_DESC_SIZE 32
73 #define BUFPOOL_DESC_SIZE 16
75 #define RING_OWNER_MASK GENMASK(9, 6)
76 #define RING_BUFNUM_MASK GENMASK(5, 0)
78 #define SELTHRSH_POS 3
79 #define SELTHRSH_LEN 3
80 #define RINGADDRL_POS 5
81 #define RINGADDRL_LEN 27
82 #define RINGADDRH_POS 0
83 #define RINGADDRH_LEN 6
84 #define RINGSIZE_POS 23
85 #define RINGSIZE_LEN 3
86 #define RINGTYPE_POS 19
87 #define RINGTYPE_LEN 2
88 #define RINGMODE_POS 20
89 #define RINGMODE_LEN 3
90 #define RECOMTIMEOUTL_POS 28
91 #define RECOMTIMEOUTL_LEN 3
92 #define RECOMTIMEOUTH_POS 0
93 #define RECOMTIMEOUTH_LEN 2
94 #define NUMMSGSINQ_POS 1
95 #define NUMMSGSINQ_LEN 16
96 #define ACCEPTLERR BIT(19)
97 #define QCOHERENT BIT(4)
98 #define RECOMBBUF BIT(27)
100 #define BLOCK_ETH_CSR_OFFSET 0x2000
101 #define BLOCK_ETH_RING_IF_OFFSET 0x9000
102 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
104 #define BLOCK_ETH_MAC_OFFSET 0x0000
105 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
107 #define MAC_ADDR_REG_OFFSET 0x00
108 #define MAC_COMMAND_REG_OFFSET 0x04
109 #define MAC_WRITE_REG_OFFSET 0x08
110 #define MAC_READ_REG_OFFSET 0x0c
111 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
113 #define MII_MGMT_CONFIG_ADDR 0x20
114 #define MII_MGMT_COMMAND_ADDR 0x24
115 #define MII_MGMT_ADDRESS_ADDR 0x28
116 #define MII_MGMT_CONTROL_ADDR 0x2c
117 #define MII_MGMT_STATUS_ADDR 0x30
118 #define MII_MGMT_INDICATORS_ADDR 0x34
120 #define BUSY_MASK BIT(0)
121 #define READ_CYCLE_MASK BIT(0)
122 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
124 #define ENET_SPARE_CFG_REG_ADDR 0x0750
125 #define RSIF_CONFIG_REG_ADDR 0x0010
126 #define RSIF_RAM_DBG_REG0_ADDR 0x0048
127 #define RGMII_REG_0_ADDR 0x07e0
128 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
129 #define DEBUG_REG_ADDR 0x0700
130 #define CFG_BYPASS_ADDR 0x0294
131 #define CLE_BYPASS_REG0_0_ADDR 0x0490
132 #define CLE_BYPASS_REG1_0_ADDR 0x0494
133 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
134 #define RESUME_TX BIT(0)
135 #define CFG_SPEED_1250 BIT(24)
136 #define TX_PORT0 BIT(0)
137 #define CFG_BYPASS_UNISEC_TX BIT(2)
138 #define CFG_BYPASS_UNISEC_RX BIT(1)
139 #define CFG_CLE_BYPASS_EN0 BIT(31)
140 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
142 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
143 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
144 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
145 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
146 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
147 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0))
148 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16))
149 #define ICM_CONFIG0_REG_0_ADDR 0x0400
150 #define ICM_CONFIG2_REG_0_ADDR 0x0410
151 #define RX_DV_GATE_REG_0_ADDR 0x05fc
152 #define TX_DV_GATE_EN0 BIT(2)
153 #define RX_DV_GATE_EN0 BIT(1)
154 #define RESUME_RX0 BIT(0)
155 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
156 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
157 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
158 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
159 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
160 #define ENET_BLOCK_MEM_RDY_ADDR 0x74
161 #define MAC_CONFIG_1_ADDR 0x00
162 #define MAC_CONFIG_2_ADDR 0x04
163 #define MAX_FRAME_LEN_ADDR 0x10
164 #define INTERFACE_CONTROL_ADDR 0x38
165 #define STATION_ADDR0_ADDR 0x40
166 #define STATION_ADDR1_ADDR 0x44
167 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
168 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
169 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
170 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
171 #define SOFT_RESET1 BIT(31)
174 #define ENET_LHD_MODE BIT(25)
175 #define ENET_GHD_MODE BIT(26)
176 #define FULL_DUPLEX2 BIT(0)
177 #define SCAN_AUTO_INCR BIT(5)
178 #define TBYT_ADDR 0x38
179 #define TPKT_ADDR 0x39
180 #define TDRP_ADDR 0x45
181 #define TFCS_ADDR 0x47
182 #define TUND_ADDR 0x4a
184 #define TSO_IPPROTO_TCP 1
186 #define USERINFO_POS 0
187 #define USERINFO_LEN 32
188 #define FPQNUM_POS 32
189 #define FPQNUM_LEN 12
194 #define BUFDATALEN_POS 48
195 #define BUFDATALEN_LEN 12
196 #define DATAADDR_POS 0
197 #define DATAADDR_LEN 42
198 #define COHERENT_POS 63
199 #define HENQNUM_POS 48
200 #define HENQNUM_LEN 12
201 #define TYPESEL_POS 44
202 #define TYPESEL_LEN 4
203 #define ETHHDR_POS 12
205 #define IC_POS 35 /* Insert CRC */
210 #define EC_POS 22 /* Enable checksum */
212 #define IS_POS 24 /* IP protocol select */
214 #define TYPE_ETH_WORK_MESSAGE_POS 44
216 struct xgene_enet_raw_desc
{
223 struct xgene_enet_raw_desc16
{
228 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr
)
230 __le64
*desc_slot
= desc_slot_ptr
;
232 desc_slot
[EMPTY_SLOT_INDEX
] = cpu_to_le64(EMPTY_SLOT
);
235 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr
)
237 __le64
*desc_slot
= desc_slot_ptr
;
239 return (desc_slot
[EMPTY_SLOT_INDEX
] == cpu_to_le64(EMPTY_SLOT
));
242 enum xgene_enet_ring_cfgsize
{
251 enum xgene_enet_ring_type
{
257 enum xgene_ring_owner
{
263 enum xgene_enet_ring_bufnum
{
264 RING_BUFNUM_REGULAR
= 0x0,
265 RING_BUFNUM_BUFPOOL
= 0x20,
269 enum xgene_enet_cmd
{
270 XGENE_ENET_WR_CMD
= BIT(31),
271 XGENE_ENET_RD_CMD
= BIT(30)
274 enum xgene_enet_err_code
{
278 BUFPOOL_TIMEOUT
= 15,
280 INGRESS_CHECKSUM
= 17,
281 INGRESS_TRUNC_FRAME
= 18,
282 INGRESS_PKT_LEN
= 19,
283 INGRESS_PKT_UNDER
= 20,
284 INGRESS_FIFO_OVERRUN
= 21,
285 INGRESS_CHECKSUM_COMPUTE
= 26,
289 static inline enum xgene_ring_owner
xgene_enet_ring_owner(u16 id
)
291 return (id
& RING_OWNER_MASK
) >> 6;
294 static inline u8
xgene_enet_ring_bufnum(u16 id
)
296 return id
& RING_BUFNUM_MASK
;
299 static inline bool xgene_enet_is_bufpool(u16 id
)
301 return ((id
& RING_BUFNUM_MASK
) >= 0x20) ? true : false;
304 static inline u16
xgene_enet_get_numslots(u16 id
, u32 size
)
306 bool is_bufpool
= xgene_enet_is_bufpool(id
);
308 return (is_bufpool
) ? size
/ BUFPOOL_DESC_SIZE
:
309 size
/ WORK_DESC_SIZE
;
312 struct xgene_enet_desc_ring
*xgene_enet_setup_ring(
313 struct xgene_enet_desc_ring
*ring
);
314 void xgene_enet_clear_ring(struct xgene_enet_desc_ring
*ring
);
315 void xgene_enet_parse_error(struct xgene_enet_desc_ring
*ring
,
316 struct xgene_enet_pdata
*pdata
,
317 enum xgene_enet_err_code status
);
319 int xgene_enet_mdio_config(struct xgene_enet_pdata
*pdata
);
320 void xgene_enet_mdio_remove(struct xgene_enet_pdata
*pdata
);
322 extern struct xgene_mac_ops xgene_gmac_ops
;
323 extern struct xgene_port_ops xgene_gport_ops
;
325 #endif /* __XGENE_ENET_HW_H__ */