drivers/net/ethernet/apm/xgene/xgene_enet_main.h

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Ravi Patel <rapatel@apm.com>
   6  *          Keyur Chudgar <kchudgar@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef __XGENE_ENET_MAIN_H__
  23 #define __XGENE_ENET_MAIN_H__
  24
  25 #include <linux/acpi.h>
  26 #include <linux/clk.h>
  27 #include <linux/efi.h>
  28 #include <linux/io.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/of_net.h>
  31 #include <linux/of_mdio.h>
  32 #include <linux/module.h>
  33 #include <net/ip.h>
  34 #include <linux/prefetch.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/phy.h>
  37 #include "xgene_enet_hw.h"
  38 #include "xgene_enet_ring2.h"
  39
  40 #define XGENE_DRV_VERSION       "v1.0"
  41 #define XGENE_ENET_MAX_MTU      1536
  42 #define SKB_BUFFER_SIZE         (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
  43 #define NUM_PKT_BUF     64
  44 #define NUM_BUFPOOL     32
  45
  46 #define START_CPU_BUFNUM_0      0
  47 #define START_ETH_BUFNUM_0      2
  48 #define START_BP_BUFNUM_0       0x22
  49 #define START_RING_NUM_0        8
  50 #define START_CPU_BUFNUM_1      12
  51 #define START_ETH_BUFNUM_1      10
  52 #define START_BP_BUFNUM_1       0x2A
  53 #define START_RING_NUM_1        264
  54
  55 #define X2_START_CPU_BUFNUM_0   0
  56 #define X2_START_ETH_BUFNUM_0   0
  57 #define X2_START_BP_BUFNUM_0    0x20
  58 #define X2_START_RING_NUM_0     0
  59 #define X2_START_CPU_BUFNUM_1   0xc
  60 #define X2_START_ETH_BUFNUM_1   0
  61 #define X2_START_BP_BUFNUM_1    0x20
  62 #define X2_START_RING_NUM_1     256
  63
  64 #define IRQ_ID_SIZE             16
  65 #define XGENE_MAX_TXC_RINGS     1
  66
  67 #define PHY_POLL_LINK_ON        (10 * HZ)
  68 #define PHY_POLL_LINK_OFF       (PHY_POLL_LINK_ON / 5)
  69
  70 enum xgene_enet_id {
  71         XGENE_ENET1 = 1,
  72         XGENE_ENET2
  73 };
  74
  75 /* software context of a descriptor ring */
  76 struct xgene_enet_desc_ring {
  77         struct net_device *ndev;
  78         u16 id;
  79         u16 num;
  80         u16 head;
  81         u16 tail;
  82         u16 slots;
  83         u16 irq;
  84         char irq_name[IRQ_ID_SIZE];
  85         u32 size;
  86         u32 state[X2_NUM_RING_CONFIG];
  87         void __iomem *cmd_base;
  88         void __iomem *cmd;
  89         dma_addr_t dma;
  90         dma_addr_t irq_mbox_dma;
  91         void *irq_mbox_addr;
  92         u16 dst_ring_num;
  93         u8 nbufpool;
  94         struct sk_buff *(*rx_skb);
  95         struct sk_buff *(*cp_skb);
  96         enum xgene_enet_ring_cfgsize cfgsize;
  97         struct xgene_enet_desc_ring *cp_ring;
  98         struct xgene_enet_desc_ring *buf_pool;
  99         struct napi_struct napi;
 100         union {
 101                 void *desc_addr;
 102                 struct xgene_enet_raw_desc *raw_desc;
 103                 struct xgene_enet_raw_desc16 *raw_desc16;
 104         };
 105 };
 106
 107 struct xgene_mac_ops {
 108         void (*init)(struct xgene_enet_pdata *pdata);
 109         void (*reset)(struct xgene_enet_pdata *pdata);
 110         void (*tx_enable)(struct xgene_enet_pdata *pdata);
 111         void (*rx_enable)(struct xgene_enet_pdata *pdata);
 112         void (*tx_disable)(struct xgene_enet_pdata *pdata);
 113         void (*rx_disable)(struct xgene_enet_pdata *pdata);
 114         void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
 115         void (*link_state)(struct work_struct *work);
 116 };
 117
 118 struct xgene_port_ops {
 119         int (*reset)(struct xgene_enet_pdata *pdata);
 120         void (*cle_bypass)(struct xgene_enet_pdata *pdata,
 121                            u32 dst_ring_num, u16 bufpool_id);
 122         void (*shutdown)(struct xgene_enet_pdata *pdata);
 123 };
 124
 125 struct xgene_ring_ops {
 126         u8 num_ring_config;
 127         u8 num_ring_id_shift;
 128         struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
 129         void (*clear)(struct xgene_enet_desc_ring *);
 130         void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
 131         u32 (*len)(struct xgene_enet_desc_ring *);
 132 };
 133
 134 /* ethernet private data */
 135 struct xgene_enet_pdata {
 136         struct net_device *ndev;
 137         struct mii_bus *mdio_bus;
 138         struct phy_device *phy_dev;
 139         int phy_speed;
 140         struct clk *clk;
 141         struct platform_device *pdev;
 142         enum xgene_enet_id enet_id;
 143         struct xgene_enet_desc_ring *tx_ring;
 144         struct xgene_enet_desc_ring *rx_ring;
 145         char *dev_name;
 146         u32 rx_buff_cnt;
 147         u32 tx_qcnt_hi;
 148         u32 cp_qcnt_hi;
 149         u32 cp_qcnt_low;
 150         u32 rx_irq;
 151         u32 txc_irq;
 152         u8 cq_cnt;
 153         void __iomem *eth_csr_addr;
 154         void __iomem *eth_ring_if_addr;
 155         void __iomem *eth_diag_csr_addr;
 156         void __iomem *mcx_mac_addr;
 157         void __iomem *mcx_mac_csr_addr;
 158         void __iomem *base_addr;
 159         void __iomem *ring_csr_addr;
 160         void __iomem *ring_cmd_addr;
 161         int phy_mode;
 162         enum xgene_enet_rm rm;
 163         struct rtnl_link_stats64 stats;
 164         struct xgene_mac_ops *mac_ops;
 165         struct xgene_port_ops *port_ops;
 166         struct xgene_ring_ops *ring_ops;
 167         struct delayed_work link_work;
 168         u32 port_id;
 169         u8 cpu_bufnum;
 170         u8 eth_bufnum;
 171         u8 bp_bufnum;
 172         u16 ring_num;
 173 };
 174
 175 struct xgene_indirect_ctl {
 176         void __iomem *addr;
 177         void __iomem *ctl;
 178         void __iomem *cmd;
 179         void __iomem *cmd_done;
 180 };
 181
 182 /* Set the specified value into a bit-field defined by its starting position
 183  * and length within a single u64.
 184  */
 185 static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
 186 {
 187         return (val & ((1ULL << len) - 1)) << pos;
 188 }
 189
 190 #define SET_VAL(field, val) \
 191                 xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
 192
 193 #define SET_BIT(field) \
 194                 xgene_enet_set_field_value(field ## _POS, 1, 1)
 195
 196 /* Get the value from a bit-field defined by its starting position
 197  * and length within the specified u64.
 198  */
 199 static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
 200 {
 201         return (src >> pos) & ((1ULL << len) - 1);
 202 }
 203
 204 #define GET_VAL(field, src) \
 205                 xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
 206
 207 static inline struct device *ndev_to_dev(struct net_device *ndev)
 208 {
 209         return ndev->dev.parent;
 210 }
 211
 212 void xgene_enet_set_ethtool_ops(struct net_device *netdev);
 213
 214 #endif /* __XGENE_ENET_MAIN_H__ */