projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*
[deliverable/linux.git] / drivers / net / ethernet / atheros / atl1e / atl1e_main.c
1 /*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "atl1e.h"
23
24 #define DRV_VERSION "1.0.0.7-NAPI"
25
26 char atl1e_driver_name[] = "ATL1E";
27 char atl1e_driver_version[] = DRV_VERSION;
28 #define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29 /*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38 static DEFINE_PCI_DEVICE_TABLE(atl1e_pci_tbl) = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1066)},
41 /* required last entry */
42 { 0 }
43 };
44 MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
45
46 MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
47 MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
48 MODULE_LICENSE("GPL");
49 MODULE_VERSION(DRV_VERSION);
50
51 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
52
53 static const u16
54 atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
55 {
56 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
57 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
58 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
59 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
60 };
61
62 static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
63 {
64 REG_RXF0_BASE_ADDR_HI,
65 REG_RXF1_BASE_ADDR_HI,
66 REG_RXF2_BASE_ADDR_HI,
67 REG_RXF3_BASE_ADDR_HI
68 };
69
70 static const u16
71 atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
72 {
73 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
74 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
75 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
76 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
77 };
78
79 static const u16
80 atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
81 {
82 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
83 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
84 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
85 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
86 };
87
88 static const u16 atl1e_pay_load_size[] = {
89 128, 256, 512, 1024, 2048, 4096,
90 };
91
92 /**
93 * atl1e_irq_enable - Enable default interrupt generation settings
94 * @adapter: board private structure
95 */
96 static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
97 {
98 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
99 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
100 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
101 AT_WRITE_FLUSH(&adapter->hw);
102 }
103 }
104
105 /**
106 * atl1e_irq_disable - Mask off interrupt generation on the NIC
107 * @adapter: board private structure
108 */
109 static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
110 {
111 atomic_inc(&adapter->irq_sem);
112 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
113 AT_WRITE_FLUSH(&adapter->hw);
114 synchronize_irq(adapter->pdev->irq);
115 }
116
117 /**
118 * atl1e_irq_reset - reset interrupt confiure on the NIC
119 * @adapter: board private structure
120 */
121 static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
122 {
123 atomic_set(&adapter->irq_sem, 0);
124 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
125 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
126 AT_WRITE_FLUSH(&adapter->hw);
127 }
128
129 /**
130 * atl1e_phy_config - Timer Call-back
131 * @data: pointer to netdev cast into an unsigned long
132 */
133 static void atl1e_phy_config(unsigned long data)
134 {
135 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
136 struct atl1e_hw *hw = &adapter->hw;
137 unsigned long flags;
138
139 spin_lock_irqsave(&adapter->mdio_lock, flags);
140 atl1e_restart_autoneg(hw);
141 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
142 }
143
144 void atl1e_reinit_locked(struct atl1e_adapter *adapter)
145 {
146
147 WARN_ON(in_interrupt());
148 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
149 msleep(1);
150 atl1e_down(adapter);
151 atl1e_up(adapter);
152 clear_bit(__AT_RESETTING, &adapter->flags);
153 }
154
155 static void atl1e_reset_task(struct work_struct *work)
156 {
157 struct atl1e_adapter *adapter;
158 adapter = container_of(work, struct atl1e_adapter, reset_task);
159
160 atl1e_reinit_locked(adapter);
161 }
162
163 static int atl1e_check_link(struct atl1e_adapter *adapter)
164 {
165 struct atl1e_hw *hw = &adapter->hw;
166 struct net_device *netdev = adapter->netdev;
167 int err = 0;
168 u16 speed, duplex, phy_data;
169
170 /* MII_BMSR must read twice */
171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 if ((phy_data & BMSR_LSTATUS) == 0) {
174 /* link down */
175 if (netif_carrier_ok(netdev)) { /* old link state: Up */
176 u32 value;
177 /* disable rx */
178 value = AT_READ_REG(hw, REG_MAC_CTRL);
179 value &= ~MAC_CTRL_RX_EN;
180 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
181 adapter->link_speed = SPEED_0;
182 netif_carrier_off(netdev);
183 netif_stop_queue(netdev);
184 }
185 } else {
186 /* Link Up */
187 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
188 if (unlikely(err))
189 return err;
190
191 /* link result is our setting */
192 if (adapter->link_speed != speed ||
193 adapter->link_duplex != duplex) {
194 adapter->link_speed = speed;
195 adapter->link_duplex = duplex;
196 atl1e_setup_mac_ctrl(adapter);
197 netdev_info(netdev,
198 "NIC Link is Up <%d Mbps %s Duplex>\n",
199 adapter->link_speed,
200 adapter->link_duplex == FULL_DUPLEX ?
201 "Full" : "Half");
202 }
203
204 if (!netif_carrier_ok(netdev)) {
205 /* Link down -> Up */
206 netif_carrier_on(netdev);
207 netif_wake_queue(netdev);
208 }
209 }
210 return 0;
211 }
212
213 /**
214 * atl1e_link_chg_task - deal with link change event Out of interrupt context
215 * @netdev: network interface device structure
216 */
217 static void atl1e_link_chg_task(struct work_struct *work)
218 {
219 struct atl1e_adapter *adapter;
220 unsigned long flags;
221
222 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
223 spin_lock_irqsave(&adapter->mdio_lock, flags);
224 atl1e_check_link(adapter);
225 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
226 }
227
228 static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
229 {
230 struct net_device *netdev = adapter->netdev;
231 u16 phy_data = 0;
232 u16 link_up = 0;
233
234 spin_lock(&adapter->mdio_lock);
235 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
236 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
237 spin_unlock(&adapter->mdio_lock);
238 link_up = phy_data & BMSR_LSTATUS;
239 /* notify upper layer link down ASAP */
240 if (!link_up) {
241 if (netif_carrier_ok(netdev)) {
242 /* old link state: Up */
243 netdev_info(netdev, "NIC Link is Down\n");
244 adapter->link_speed = SPEED_0;
245 netif_stop_queue(netdev);
246 }
247 }
248 schedule_work(&adapter->link_chg_task);
249 }
250
251 static void atl1e_del_timer(struct atl1e_adapter *adapter)
252 {
253 del_timer_sync(&adapter->phy_config_timer);
254 }
255
256 static void atl1e_cancel_work(struct atl1e_adapter *adapter)
257 {
258 cancel_work_sync(&adapter->reset_task);
259 cancel_work_sync(&adapter->link_chg_task);
260 }
261
262 /**
263 * atl1e_tx_timeout - Respond to a Tx Hang
264 * @netdev: network interface device structure
265 */
266 static void atl1e_tx_timeout(struct net_device *netdev)
267 {
268 struct atl1e_adapter *adapter = netdev_priv(netdev);
269
270 /* Do the reset outside of interrupt context */
271 schedule_work(&adapter->reset_task);
272 }
273
274 /**
275 * atl1e_set_multi - Multicast and Promiscuous mode set
276 * @netdev: network interface device structure
277 *
278 * The set_multi entry point is called whenever the multicast address
279 * list or the network interface flags are updated. This routine is
280 * responsible for configuring the hardware for proper multicast,
281 * promiscuous mode, and all-multi behavior.
282 */
283 static void atl1e_set_multi(struct net_device *netdev)
284 {
285 struct atl1e_adapter *adapter = netdev_priv(netdev);
286 struct atl1e_hw *hw = &adapter->hw;
287 struct netdev_hw_addr *ha;
288 u32 mac_ctrl_data = 0;
289 u32 hash_value;
290
291 /* Check for Promiscuous and All Multicast modes */
292 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
293
294 if (netdev->flags & IFF_PROMISC) {
295 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
296 } else if (netdev->flags & IFF_ALLMULTI) {
297 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
298 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
299 } else {
300 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
301 }
302
303 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
304
305 /* clear the old settings from the multicast hash table */
306 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
307 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
308
309 /* comoute mc addresses' hash value ,and put it into hash table */
310 netdev_for_each_mc_addr(ha, netdev) {
311 hash_value = atl1e_hash_mc_addr(hw, ha->addr);
312 atl1e_hash_set(hw, hash_value);
313 }
314 }
315
316 static void __atl1e_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
317 {
318 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
319 /* enable VLAN tag insert/strip */
320 *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
321 } else {
322 /* disable VLAN tag insert/strip */
323 *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
324 }
325 }
326
327 static void atl1e_vlan_mode(struct net_device *netdev,
328 netdev_features_t features)
329 {
330 struct atl1e_adapter *adapter = netdev_priv(netdev);
331 u32 mac_ctrl_data = 0;
332
333 netdev_dbg(adapter->netdev, "%s\n", __func__);
334
335 atl1e_irq_disable(adapter);
336 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
337 __atl1e_vlan_mode(features, &mac_ctrl_data);
338 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
339 atl1e_irq_enable(adapter);
340 }
341
342 static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
343 {
344 netdev_dbg(adapter->netdev, "%s\n", __func__);
345 atl1e_vlan_mode(adapter->netdev, adapter->netdev->features);
346 }
347
348 /**
349 * atl1e_set_mac - Change the Ethernet Address of the NIC
350 * @netdev: network interface device structure
351 * @p: pointer to an address structure
352 *
353 * Returns 0 on success, negative on failure
354 */
355 static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
356 {
357 struct atl1e_adapter *adapter = netdev_priv(netdev);
358 struct sockaddr *addr = p;
359
360 if (!is_valid_ether_addr(addr->sa_data))
361 return -EADDRNOTAVAIL;
362
363 if (netif_running(netdev))
364 return -EBUSY;
365
366 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
367 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
368
369 atl1e_hw_set_mac_addr(&adapter->hw);
370
371 return 0;
372 }
373
374 static netdev_features_t atl1e_fix_features(struct net_device *netdev,
375 netdev_features_t features)
376 {
377 /*
378 * Since there is no support for separate rx/tx vlan accel
379 * enable/disable make sure tx flag is always in same state as rx.
380 */
381 if (features & NETIF_F_HW_VLAN_CTAG_RX)
382 features |= NETIF_F_HW_VLAN_CTAG_TX;
383 else
384 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
385
386 return features;
387 }
388
389 static int atl1e_set_features(struct net_device *netdev,
390 netdev_features_t features)
391 {
392 netdev_features_t changed = netdev->features ^ features;
393
394 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
395 atl1e_vlan_mode(netdev, features);
396
397 return 0;
398 }
399
400 /**
401 * atl1e_change_mtu - Change the Maximum Transfer Unit
402 * @netdev: network interface device structure
403 * @new_mtu: new value for maximum frame size
404 *
405 * Returns 0 on success, negative on failure
406 */
407 static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
408 {
409 struct atl1e_adapter *adapter = netdev_priv(netdev);
410 int old_mtu = netdev->mtu;
411 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
412
413 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
414 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
415 netdev_warn(adapter->netdev, "invalid MTU setting\n");
416 return -EINVAL;
417 }
418 /* set MTU */
419 if (old_mtu != new_mtu && netif_running(netdev)) {
420 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
421 msleep(1);
422 netdev->mtu = new_mtu;
423 adapter->hw.max_frame_size = new_mtu;
424 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
425 atl1e_down(adapter);
426 atl1e_up(adapter);
427 clear_bit(__AT_RESETTING, &adapter->flags);
428 }
429 return 0;
430 }
431
432 /*
433 * caller should hold mdio_lock
434 */
435 static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
436 {
437 struct atl1e_adapter *adapter = netdev_priv(netdev);
438 u16 result;
439
440 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
441 return result;
442 }
443
444 static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
445 int reg_num, int val)
446 {
447 struct atl1e_adapter *adapter = netdev_priv(netdev);
448
449 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
450 }
451
452 static int atl1e_mii_ioctl(struct net_device *netdev,
453 struct ifreq *ifr, int cmd)
454 {
455 struct atl1e_adapter *adapter = netdev_priv(netdev);
456 struct mii_ioctl_data *data = if_mii(ifr);
457 unsigned long flags;
458 int retval = 0;
459
460 if (!netif_running(netdev))
461 return -EINVAL;
462
463 spin_lock_irqsave(&adapter->mdio_lock, flags);
464 switch (cmd) {
465 case SIOCGMIIPHY:
466 data->phy_id = 0;
467 break;
468
469 case SIOCGMIIREG:
470 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
471 &data->val_out)) {
472 retval = -EIO;
473 goto out;
474 }
475 break;
476
477 case SIOCSMIIREG:
478 if (data->reg_num & ~(0x1F)) {
479 retval = -EFAULT;
480 goto out;
481 }
482
483 netdev_dbg(adapter->netdev, "<atl1e_mii_ioctl> write %x %x\n",
484 data->reg_num, data->val_in);
485 if (atl1e_write_phy_reg(&adapter->hw,
486 data->reg_num, data->val_in)) {
487 retval = -EIO;
488 goto out;
489 }
490 break;
491
492 default:
493 retval = -EOPNOTSUPP;
494 break;
495 }
496 out:
497 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
498 return retval;
499
500 }
501
502 static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
503 {
504 switch (cmd) {
505 case SIOCGMIIPHY:
506 case SIOCGMIIREG:
507 case SIOCSMIIREG:
508 return atl1e_mii_ioctl(netdev, ifr, cmd);
509 default:
510 return -EOPNOTSUPP;
511 }
512 }
513
514 static void atl1e_setup_pcicmd(struct pci_dev *pdev)
515 {
516 u16 cmd;
517
518 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
519 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
520 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
521 pci_write_config_word(pdev, PCI_COMMAND, cmd);
522
523 /*
524 * some motherboards BIOS(PXE/EFI) driver may set PME
525 * while they transfer control to OS (Windows/Linux)
526 * so we should clear this bit before NIC work normally
527 */
528 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
529 msleep(1);
530 }
531
532 /**
533 * atl1e_alloc_queues - Allocate memory for all rings
534 * @adapter: board private structure to initialize
535 *
536 */
537 static int atl1e_alloc_queues(struct atl1e_adapter *adapter)
538 {
539 return 0;
540 }
541
542 /**
543 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
544 * @adapter: board private structure to initialize
545 *
546 * atl1e_sw_init initializes the Adapter private data structure.
547 * Fields are initialized based on PCI device information and
548 * OS network device settings (MTU size).
549 */
550 static int atl1e_sw_init(struct atl1e_adapter *adapter)
551 {
552 struct atl1e_hw *hw = &adapter->hw;
553 struct pci_dev *pdev = adapter->pdev;
554 u32 phy_status_data = 0;
555
556 adapter->wol = 0;
557 adapter->link_speed = SPEED_0; /* hardware init */
558 adapter->link_duplex = FULL_DUPLEX;
559 adapter->num_rx_queues = 1;
560
561 /* PCI config space info */
562 hw->vendor_id = pdev->vendor;
563 hw->device_id = pdev->device;
564 hw->subsystem_vendor_id = pdev->subsystem_vendor;
565 hw->subsystem_id = pdev->subsystem_device;
566 hw->revision_id = pdev->revision;
567
568 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
569
570 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
571 /* nic type */
572 if (hw->revision_id >= 0xF0) {
573 hw->nic_type = athr_l2e_revB;
574 } else {
575 if (phy_status_data & PHY_STATUS_100M)
576 hw->nic_type = athr_l1e;
577 else
578 hw->nic_type = athr_l2e_revA;
579 }
580
581 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
582
583 if (phy_status_data & PHY_STATUS_EMI_CA)
584 hw->emi_ca = true;
585 else
586 hw->emi_ca = false;
587
588 hw->phy_configured = false;
589 hw->preamble_len = 7;
590 hw->max_frame_size = adapter->netdev->mtu;
591 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
592 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
593
594 hw->rrs_type = atl1e_rrs_disable;
595 hw->indirect_tab = 0;
596 hw->base_cpu = 0;
597
598 /* need confirm */
599
600 hw->ict = 50000; /* 100ms */
601 hw->smb_timer = 200000; /* 200ms */
602 hw->tpd_burst = 5;
603 hw->rrd_thresh = 1;
604 hw->tpd_thresh = adapter->tx_ring.count / 2;
605 hw->rx_count_down = 4; /* 2us resolution */
606 hw->tx_count_down = hw->imt * 4 / 3;
607 hw->dmar_block = atl1e_dma_req_1024;
608 hw->dmaw_block = atl1e_dma_req_1024;
609 hw->dmar_dly_cnt = 15;
610 hw->dmaw_dly_cnt = 4;
611
612 if (atl1e_alloc_queues(adapter)) {
613 netdev_err(adapter->netdev, "Unable to allocate memory for queues\n");
614 return -ENOMEM;
615 }
616
617 atomic_set(&adapter->irq_sem, 1);
618 spin_lock_init(&adapter->mdio_lock);
619 spin_lock_init(&adapter->tx_lock);
620
621 set_bit(__AT_DOWN, &adapter->flags);
622
623 return 0;
624 }
625
626 /**
627 * atl1e_clean_tx_ring - Free Tx-skb
628 * @adapter: board private structure
629 */
630 static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
631 {
632 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
633 struct atl1e_tx_buffer *tx_buffer = NULL;
634 struct pci_dev *pdev = adapter->pdev;
635 u16 index, ring_count;
636
637 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
638 return;
639
640 ring_count = tx_ring->count;
641 /* first unmmap dma */
642 for (index = 0; index < ring_count; index++) {
643 tx_buffer = &tx_ring->tx_buffer[index];
644 if (tx_buffer->dma) {
645 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
646 pci_unmap_single(pdev, tx_buffer->dma,
647 tx_buffer->length, PCI_DMA_TODEVICE);
648 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
649 pci_unmap_page(pdev, tx_buffer->dma,
650 tx_buffer->length, PCI_DMA_TODEVICE);
651 tx_buffer->dma = 0;
652 }
653 }
654 /* second free skb */
655 for (index = 0; index < ring_count; index++) {
656 tx_buffer = &tx_ring->tx_buffer[index];
657 if (tx_buffer->skb) {
658 dev_kfree_skb_any(tx_buffer->skb);
659 tx_buffer->skb = NULL;
660 }
661 }
662 /* Zero out Tx-buffers */
663 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
664 ring_count);
665 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
666 ring_count);
667 }
668
669 /**
670 * atl1e_clean_rx_ring - Free rx-reservation skbs
671 * @adapter: board private structure
672 */
673 static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
674 {
675 struct atl1e_rx_ring *rx_ring =
676 &adapter->rx_ring;
677 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
678 u16 i, j;
679
680
681 if (adapter->ring_vir_addr == NULL)
682 return;
683 /* Zero out the descriptor ring */
684 for (i = 0; i < adapter->num_rx_queues; i++) {
685 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
686 if (rx_page_desc[i].rx_page[j].addr != NULL) {
687 memset(rx_page_desc[i].rx_page[j].addr, 0,
688 rx_ring->real_page_size);
689 }
690 }
691 }
692 }
693
694 static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
695 {
696 *ring_size = ((u32)(adapter->tx_ring.count *
697 sizeof(struct atl1e_tpd_desc) + 7
698 /* tx ring, qword align */
699 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
700 adapter->num_rx_queues + 31
701 /* rx ring, 32 bytes align */
702 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
703 sizeof(u32) + 3));
704 /* tx, rx cmd, dword align */
705 }
706
707 static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
708 {
709 struct atl1e_rx_ring *rx_ring = NULL;
710
711 rx_ring = &adapter->rx_ring;
712
713 rx_ring->real_page_size = adapter->rx_ring.page_size
714 + adapter->hw.max_frame_size
715 + ETH_HLEN + VLAN_HLEN
716 + ETH_FCS_LEN;
717 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
718 atl1e_cal_ring_size(adapter, &adapter->ring_size);
719
720 adapter->ring_vir_addr = NULL;
721 adapter->rx_ring.desc = NULL;
722 rwlock_init(&adapter->tx_ring.tx_lock);
723 }
724
725 /*
726 * Read / Write Ptr Initialize:
727 */
728 static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
729 {
730 struct atl1e_tx_ring *tx_ring = NULL;
731 struct atl1e_rx_ring *rx_ring = NULL;
732 struct atl1e_rx_page_desc *rx_page_desc = NULL;
733 int i, j;
734
735 tx_ring = &adapter->tx_ring;
736 rx_ring = &adapter->rx_ring;
737 rx_page_desc = rx_ring->rx_page_desc;
738
739 tx_ring->next_to_use = 0;
740 atomic_set(&tx_ring->next_to_clean, 0);
741
742 for (i = 0; i < adapter->num_rx_queues; i++) {
743 rx_page_desc[i].rx_using = 0;
744 rx_page_desc[i].rx_nxseq = 0;
745 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
746 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
747 rx_page_desc[i].rx_page[j].read_offset = 0;
748 }
749 }
750 }
751
752 /**
753 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
754 * @adapter: board private structure
755 *
756 * Free all transmit software resources
757 */
758 static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
759 {
760 struct pci_dev *pdev = adapter->pdev;
761
762 atl1e_clean_tx_ring(adapter);
763 atl1e_clean_rx_ring(adapter);
764
765 if (adapter->ring_vir_addr) {
766 pci_free_consistent(pdev, adapter->ring_size,
767 adapter->ring_vir_addr, adapter->ring_dma);
768 adapter->ring_vir_addr = NULL;
769 }
770
771 if (adapter->tx_ring.tx_buffer) {
772 kfree(adapter->tx_ring.tx_buffer);
773 adapter->tx_ring.tx_buffer = NULL;
774 }
775 }
776
777 /**
778 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
779 * @adapter: board private structure
780 *
781 * Return 0 on success, negative on failure
782 */
783 static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
784 {
785 struct pci_dev *pdev = adapter->pdev;
786 struct atl1e_tx_ring *tx_ring;
787 struct atl1e_rx_ring *rx_ring;
788 struct atl1e_rx_page_desc *rx_page_desc;
789 int size, i, j;
790 u32 offset = 0;
791 int err = 0;
792
793 if (adapter->ring_vir_addr != NULL)
794 return 0; /* alloced already */
795
796 tx_ring = &adapter->tx_ring;
797 rx_ring = &adapter->rx_ring;
798
799 /* real ring DMA buffer */
800
801 size = adapter->ring_size;
802 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
803 adapter->ring_size, &adapter->ring_dma);
804
805 if (adapter->ring_vir_addr == NULL) {
806 netdev_err(adapter->netdev,
807 "pci_alloc_consistent failed, size = D%d\n", size);
808 return -ENOMEM;
809 }
810
811 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
812
813 rx_page_desc = rx_ring->rx_page_desc;
814
815 /* Init TPD Ring */
816 tx_ring->dma = roundup(adapter->ring_dma, 8);
817 offset = tx_ring->dma - adapter->ring_dma;
818 tx_ring->desc = adapter->ring_vir_addr + offset;
819 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
820 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
821 if (tx_ring->tx_buffer == NULL) {
822 err = -ENOMEM;
823 goto failed;
824 }
825
826 /* Init RXF-Pages */
827 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
828 offset = roundup(offset, 32);
829
830 for (i = 0; i < adapter->num_rx_queues; i++) {
831 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
832 rx_page_desc[i].rx_page[j].dma =
833 adapter->ring_dma + offset;
834 rx_page_desc[i].rx_page[j].addr =
835 adapter->ring_vir_addr + offset;
836 offset += rx_ring->real_page_size;
837 }
838 }
839
840 /* Init CMB dma address */
841 tx_ring->cmb_dma = adapter->ring_dma + offset;
842 tx_ring->cmb = adapter->ring_vir_addr + offset;
843 offset += sizeof(u32);
844
845 for (i = 0; i < adapter->num_rx_queues; i++) {
846 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
847 rx_page_desc[i].rx_page[j].write_offset_dma =
848 adapter->ring_dma + offset;
849 rx_page_desc[i].rx_page[j].write_offset_addr =
850 adapter->ring_vir_addr + offset;
851 offset += sizeof(u32);
852 }
853 }
854
855 if (unlikely(offset > adapter->ring_size)) {
856 netdev_err(adapter->netdev, "offset(%d) > ring size(%d) !!\n",
857 offset, adapter->ring_size);
858 err = -1;
859 goto failed;
860 }
861
862 return 0;
863 failed:
864 if (adapter->ring_vir_addr != NULL) {
865 pci_free_consistent(pdev, adapter->ring_size,
866 adapter->ring_vir_addr, adapter->ring_dma);
867 adapter->ring_vir_addr = NULL;
868 }
869 return err;
870 }
871
872 static inline void atl1e_configure_des_ring(struct atl1e_adapter *adapter)
873 {
874
875 struct atl1e_hw *hw = &adapter->hw;
876 struct atl1e_rx_ring *rx_ring = &adapter->rx_ring;
877 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
878 struct atl1e_rx_page_desc *rx_page_desc = NULL;
879 int i, j;
880
881 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
882 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
883 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
884 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
885 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
886 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
887 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
888
889 rx_page_desc = rx_ring->rx_page_desc;
890 /* RXF Page Physical address / Page Length */
891 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
892 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
893 (u32)((adapter->ring_dma &
894 AT_DMA_HI_ADDR_MASK) >> 32));
895 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
896 u32 page_phy_addr;
897 u32 offset_phy_addr;
898
899 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
900 offset_phy_addr =
901 rx_page_desc[i].rx_page[j].write_offset_dma;
902
903 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
904 page_phy_addr & AT_DMA_LO_ADDR_MASK);
905 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
906 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
907 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
908 }
909 }
910 /* Page Length */
911 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
912 /* Load all of base address above */
913 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
914 }
915
916 static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
917 {
918 struct atl1e_hw *hw = &adapter->hw;
919 u32 dev_ctrl_data = 0;
920 u32 max_pay_load = 0;
921 u32 jumbo_thresh = 0;
922 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
923
924 /* configure TXQ param */
925 if (hw->nic_type != athr_l2e_revB) {
926 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
927 if (hw->max_frame_size <= 1500) {
928 jumbo_thresh = hw->max_frame_size + extra_size;
929 } else if (hw->max_frame_size < 6*1024) {
930 jumbo_thresh =
931 (hw->max_frame_size + extra_size) * 2 / 3;
932 } else {
933 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
934 }
935 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
936 }
937
938 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
939
940 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
941 DEVICE_CTRL_MAX_PAYLOAD_MASK;
942
943 hw->dmaw_block = min_t(u32, max_pay_load, hw->dmaw_block);
944
945 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
946 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
947 hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
948
949 if (hw->nic_type != athr_l2e_revB)
950 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
951 atl1e_pay_load_size[hw->dmar_block]);
952 /* enable TXQ */
953 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
954 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
955 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
956 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
957 }
958
959 static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
960 {
961 struct atl1e_hw *hw = &adapter->hw;
962 u32 rxf_len = 0;
963 u32 rxf_low = 0;
964 u32 rxf_high = 0;
965 u32 rxf_thresh_data = 0;
966 u32 rxq_ctrl_data = 0;
967
968 if (hw->nic_type != athr_l2e_revB) {
969 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
970 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
971 RXQ_JMBOSZ_TH_SHIFT |
972 (1 & RXQ_JMBO_LKAH_MASK) <<
973 RXQ_JMBO_LKAH_SHIFT));
974
975 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
976 rxf_high = rxf_len * 4 / 5;
977 rxf_low = rxf_len / 5;
978 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
979 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
980 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
981 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
982
983 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
984 }
985
986 /* RRS */
987 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
988 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
989
990 if (hw->rrs_type & atl1e_rrs_ipv4)
991 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
992
993 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
994 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
995
996 if (hw->rrs_type & atl1e_rrs_ipv6)
997 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
998
999 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
1000 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
1001
1002 if (hw->rrs_type != atl1e_rrs_disable)
1003 rxq_ctrl_data |=
1004 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1005
1006 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1007 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1008
1009 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1010 }
1011
1012 static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1013 {
1014 struct atl1e_hw *hw = &adapter->hw;
1015 u32 dma_ctrl_data = 0;
1016
1017 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1018 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1019 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1020 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1021 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1022 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1023 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1024 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1025 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1026 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1027
1028 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1029 }
1030
1031 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
1032 {
1033 u32 value;
1034 struct atl1e_hw *hw = &adapter->hw;
1035 struct net_device *netdev = adapter->netdev;
1036
1037 /* Config MAC CTRL Register */
1038 value = MAC_CTRL_TX_EN |
1039 MAC_CTRL_RX_EN ;
1040
1041 if (FULL_DUPLEX == adapter->link_duplex)
1042 value |= MAC_CTRL_DUPLX;
1043
1044 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1045 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1046 MAC_CTRL_SPEED_SHIFT);
1047 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1048
1049 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1050 value |= (((u32)adapter->hw.preamble_len &
1051 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1052
1053 __atl1e_vlan_mode(netdev->features, &value);
1054
1055 value |= MAC_CTRL_BC_EN;
1056 if (netdev->flags & IFF_PROMISC)
1057 value |= MAC_CTRL_PROMIS_EN;
1058 if (netdev->flags & IFF_ALLMULTI)
1059 value |= MAC_CTRL_MC_ALL_EN;
1060
1061 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1062 }
1063
1064 /**
1065 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1066 * @adapter: board private structure
1067 *
1068 * Configure the Tx /Rx unit of the MAC after a reset.
1069 */
1070 static int atl1e_configure(struct atl1e_adapter *adapter)
1071 {
1072 struct atl1e_hw *hw = &adapter->hw;
1073
1074 u32 intr_status_data = 0;
1075
1076 /* clear interrupt status */
1077 AT_WRITE_REG(hw, REG_ISR, ~0);
1078
1079 /* 1. set MAC Address */
1080 atl1e_hw_set_mac_addr(hw);
1081
1082 /* 2. Init the Multicast HASH table done by set_muti */
1083
1084 /* 3. Clear any WOL status */
1085 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1086
1087 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1088 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1089 * High 32bits memory */
1090 atl1e_configure_des_ring(adapter);
1091
1092 /* 5. set Interrupt Moderator Timer */
1093 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1094 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1095 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1096 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1097
1098 /* 6. rx/tx threshold to trig interrupt */
1099 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1100 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1101 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1102 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1103
1104 /* 7. set Interrupt Clear Timer */
1105 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1106
1107 /* 8. set MTU */
1108 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1109 VLAN_HLEN + ETH_FCS_LEN);
1110
1111 /* 9. config TXQ early tx threshold */
1112 atl1e_configure_tx(adapter);
1113
1114 /* 10. config RXQ */
1115 atl1e_configure_rx(adapter);
1116
1117 /* 11. config DMA Engine */
1118 atl1e_configure_dma(adapter);
1119
1120 /* 12. smb timer to trig interrupt */
1121 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1122
1123 intr_status_data = AT_READ_REG(hw, REG_ISR);
1124 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1125 netdev_err(adapter->netdev,
1126 "atl1e_configure failed, PCIE phy link down\n");
1127 return -1;
1128 }
1129
1130 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1131 return 0;
1132 }
1133
1134 /**
1135 * atl1e_get_stats - Get System Network Statistics
1136 * @netdev: network interface device structure
1137 *
1138 * Returns the address of the device statistics structure.
1139 * The statistics are actually updated from the timer callback.
1140 */
1141 static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1142 {
1143 struct atl1e_adapter *adapter = netdev_priv(netdev);
1144 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1145 struct net_device_stats *net_stats = &netdev->stats;
1146
1147 net_stats->rx_packets = hw_stats->rx_ok;
1148 net_stats->tx_packets = hw_stats->tx_ok;
1149 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1150 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1151 net_stats->multicast = hw_stats->rx_mcast;
1152 net_stats->collisions = hw_stats->tx_1_col +
1153 hw_stats->tx_2_col * 2 +
1154 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1155
1156 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1157 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1158 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1159 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1160 net_stats->rx_length_errors = hw_stats->rx_len_err;
1161 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1162 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1163 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1164
1165 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1166
1167 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1168 hw_stats->tx_underrun + hw_stats->tx_trunc;
1169 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1170 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1171 net_stats->tx_window_errors = hw_stats->tx_late_col;
1172
1173 return net_stats;
1174 }
1175
1176 static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1177 {
1178 u16 hw_reg_addr = 0;
1179 unsigned long *stats_item = NULL;
1180
1181 /* update rx status */
1182 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1183 stats_item = &adapter->hw_stats.rx_ok;
1184 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1185 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1186 stats_item++;
1187 hw_reg_addr += 4;
1188 }
1189 /* update tx status */
1190 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1191 stats_item = &adapter->hw_stats.tx_ok;
1192 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1193 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1194 stats_item++;
1195 hw_reg_addr += 4;
1196 }
1197 }
1198
1199 static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1200 {
1201 u16 phy_data;
1202
1203 spin_lock(&adapter->mdio_lock);
1204 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1205 spin_unlock(&adapter->mdio_lock);
1206 }
1207
1208 static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1209 {
1210 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1211 struct atl1e_tx_buffer *tx_buffer = NULL;
1212 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1213 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1214
1215 while (next_to_clean != hw_next_to_clean) {
1216 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1217 if (tx_buffer->dma) {
1218 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
1219 pci_unmap_single(adapter->pdev, tx_buffer->dma,
1220 tx_buffer->length, PCI_DMA_TODEVICE);
1221 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
1222 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1223 tx_buffer->length, PCI_DMA_TODEVICE);
1224 tx_buffer->dma = 0;
1225 }
1226
1227 if (tx_buffer->skb) {
1228 dev_kfree_skb_irq(tx_buffer->skb);
1229 tx_buffer->skb = NULL;
1230 }
1231
1232 if (++next_to_clean == tx_ring->count)
1233 next_to_clean = 0;
1234 }
1235
1236 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1237
1238 if (netif_queue_stopped(adapter->netdev) &&
1239 netif_carrier_ok(adapter->netdev)) {
1240 netif_wake_queue(adapter->netdev);
1241 }
1242
1243 return true;
1244 }
1245
1246 /**
1247 * atl1e_intr - Interrupt Handler
1248 * @irq: interrupt number
1249 * @data: pointer to a network interface device structure
1250 */
1251 static irqreturn_t atl1e_intr(int irq, void *data)
1252 {
1253 struct net_device *netdev = data;
1254 struct atl1e_adapter *adapter = netdev_priv(netdev);
1255 struct atl1e_hw *hw = &adapter->hw;
1256 int max_ints = AT_MAX_INT_WORK;
1257 int handled = IRQ_NONE;
1258 u32 status;
1259
1260 do {
1261 status = AT_READ_REG(hw, REG_ISR);
1262 if ((status & IMR_NORMAL_MASK) == 0 ||
1263 (status & ISR_DIS_INT) != 0) {
1264 if (max_ints != AT_MAX_INT_WORK)
1265 handled = IRQ_HANDLED;
1266 break;
1267 }
1268 /* link event */
1269 if (status & ISR_GPHY)
1270 atl1e_clear_phy_int(adapter);
1271 /* Ack ISR */
1272 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1273
1274 handled = IRQ_HANDLED;
1275 /* check if PCIE PHY Link down */
1276 if (status & ISR_PHY_LINKDOWN) {
1277 netdev_err(adapter->netdev,
1278 "pcie phy linkdown %x\n", status);
1279 if (netif_running(adapter->netdev)) {
1280 /* reset MAC */
1281 atl1e_irq_reset(adapter);
1282 schedule_work(&adapter->reset_task);
1283 break;
1284 }
1285 }
1286
1287 /* check if DMA read/write error */
1288 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1289 netdev_err(adapter->netdev,
1290 "PCIE DMA RW error (status = 0x%x)\n",
1291 status);
1292 atl1e_irq_reset(adapter);
1293 schedule_work(&adapter->reset_task);
1294 break;
1295 }
1296
1297 if (status & ISR_SMB)
1298 atl1e_update_hw_stats(adapter);
1299
1300 /* link event */
1301 if (status & (ISR_GPHY | ISR_MANUAL)) {
1302 netdev->stats.tx_carrier_errors++;
1303 atl1e_link_chg_event(adapter);
1304 break;
1305 }
1306
1307 /* transmit event */
1308 if (status & ISR_TX_EVENT)
1309 atl1e_clean_tx_irq(adapter);
1310
1311 if (status & ISR_RX_EVENT) {
1312 /*
1313 * disable rx interrupts, without
1314 * the synchronize_irq bit
1315 */
1316 AT_WRITE_REG(hw, REG_IMR,
1317 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1318 AT_WRITE_FLUSH(hw);
1319 if (likely(napi_schedule_prep(
1320 &adapter->napi)))
1321 __napi_schedule(&adapter->napi);
1322 }
1323 } while (--max_ints > 0);
1324 /* re-enable Interrupt*/
1325 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1326
1327 return handled;
1328 }
1329
1330 static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1331 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1332 {
1333 u8 *packet = (u8 *)(prrs + 1);
1334 struct iphdr *iph;
1335 u16 head_len = ETH_HLEN;
1336 u16 pkt_flags;
1337 u16 err_flags;
1338
1339 skb_checksum_none_assert(skb);
1340 pkt_flags = prrs->pkt_flag;
1341 err_flags = prrs->err_flag;
1342 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1343 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1344 if (pkt_flags & RRS_IS_IPV4) {
1345 if (pkt_flags & RRS_IS_802_3)
1346 head_len += 8;
1347 iph = (struct iphdr *) (packet + head_len);
1348 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1349 goto hw_xsum;
1350 }
1351 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1352 skb->ip_summed = CHECKSUM_UNNECESSARY;
1353 return;
1354 }
1355 }
1356
1357 hw_xsum :
1358 return;
1359 }
1360
1361 static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1362 u8 que)
1363 {
1364 struct atl1e_rx_page_desc *rx_page_desc =
1365 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1366 u8 rx_using = rx_page_desc[que].rx_using;
1367
1368 return &(rx_page_desc[que].rx_page[rx_using]);
1369 }
1370
1371 static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1372 int *work_done, int work_to_do)
1373 {
1374 struct net_device *netdev = adapter->netdev;
1375 struct atl1e_rx_ring *rx_ring = &adapter->rx_ring;
1376 struct atl1e_rx_page_desc *rx_page_desc =
1377 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1378 struct sk_buff *skb = NULL;
1379 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1380 u32 packet_size, write_offset;
1381 struct atl1e_recv_ret_status *prrs;
1382
1383 write_offset = *(rx_page->write_offset_addr);
1384 if (likely(rx_page->read_offset < write_offset)) {
1385 do {
1386 if (*work_done >= work_to_do)
1387 break;
1388 (*work_done)++;
1389 /* get new packet's rrs */
1390 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1391 rx_page->read_offset);
1392 /* check sequence number */
1393 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1394 netdev_err(netdev,
1395 "rx sequence number error (rx=%d) (expect=%d)\n",
1396 prrs->seq_num,
1397 rx_page_desc[que].rx_nxseq);
1398 rx_page_desc[que].rx_nxseq++;
1399 /* just for debug use */
1400 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1401 (((u32)prrs->seq_num) << 16) |
1402 rx_page_desc[que].rx_nxseq);
1403 goto fatal_err;
1404 }
1405 rx_page_desc[que].rx_nxseq++;
1406
1407 /* error packet */
1408 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1409 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1410 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1411 RRS_ERR_TRUNC)) {
1412 /* hardware error, discard this packet*/
1413 netdev_err(netdev,
1414 "rx packet desc error %x\n",
1415 *((u32 *)prrs + 1));
1416 goto skip_pkt;
1417 }
1418 }
1419
1420 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1421 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1422 skb = netdev_alloc_skb_ip_align(netdev, packet_size);
1423 if (skb == NULL)
1424 goto skip_pkt;
1425
1426 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1427 skb_put(skb, packet_size);
1428 skb->protocol = eth_type_trans(skb, netdev);
1429 atl1e_rx_checksum(adapter, skb, prrs);
1430
1431 if (prrs->pkt_flag & RRS_IS_VLAN_TAG) {
1432 u16 vlan_tag = (prrs->vtag >> 4) |
1433 ((prrs->vtag & 7) << 13) |
1434 ((prrs->vtag & 8) << 9);
1435 netdev_dbg(netdev,
1436 "RXD VLAN TAG<RRD>=0x%04x\n",
1437 prrs->vtag);
1438 __vlan_hwaccel_put_tag(skb, vlan_tag);
1439 }
1440 netif_receive_skb(skb);
1441
1442 skip_pkt:
1443 /* skip current packet whether it's ok or not. */
1444 rx_page->read_offset +=
1445 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1446 RRS_PKT_SIZE_MASK) +
1447 sizeof(struct atl1e_recv_ret_status) + 31) &
1448 0xFFFFFFE0);
1449
1450 if (rx_page->read_offset >= rx_ring->page_size) {
1451 /* mark this page clean */
1452 u16 reg_addr;
1453 u8 rx_using;
1454
1455 rx_page->read_offset =
1456 *(rx_page->write_offset_addr) = 0;
1457 rx_using = rx_page_desc[que].rx_using;
1458 reg_addr =
1459 atl1e_rx_page_vld_regs[que][rx_using];
1460 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1461 rx_page_desc[que].rx_using ^= 1;
1462 rx_page = atl1e_get_rx_page(adapter, que);
1463 }
1464 write_offset = *(rx_page->write_offset_addr);
1465 } while (rx_page->read_offset < write_offset);
1466 }
1467
1468 return;
1469
1470 fatal_err:
1471 if (!test_bit(__AT_DOWN, &adapter->flags))
1472 schedule_work(&adapter->reset_task);
1473 }
1474
1475 /**
1476 * atl1e_clean - NAPI Rx polling callback
1477 */
1478 static int atl1e_clean(struct napi_struct *napi, int budget)
1479 {
1480 struct atl1e_adapter *adapter =
1481 container_of(napi, struct atl1e_adapter, napi);
1482 u32 imr_data;
1483 int work_done = 0;
1484
1485 /* Keep link state information with original netdev */
1486 if (!netif_carrier_ok(adapter->netdev))
1487 goto quit_polling;
1488
1489 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1490
1491 /* If no Tx and not enough Rx work done, exit the polling mode */
1492 if (work_done < budget) {
1493 quit_polling:
1494 napi_complete(napi);
1495 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1496 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1497 /* test debug */
1498 if (test_bit(__AT_DOWN, &adapter->flags)) {
1499 atomic_dec(&adapter->irq_sem);
1500 netdev_err(adapter->netdev,
1501 "atl1e_clean is called when AT_DOWN\n");
1502 }
1503 /* reenable RX intr */
1504 /*atl1e_irq_enable(adapter); */
1505
1506 }
1507 return work_done;
1508 }
1509
1510 #ifdef CONFIG_NET_POLL_CONTROLLER
1511
1512 /*
1513 * Polling 'interrupt' - used by things like netconsole to send skbs
1514 * without having to re-enable interrupts. It's not called while
1515 * the interrupt routine is executing.
1516 */
1517 static void atl1e_netpoll(struct net_device *netdev)
1518 {
1519 struct atl1e_adapter *adapter = netdev_priv(netdev);
1520
1521 disable_irq(adapter->pdev->irq);
1522 atl1e_intr(adapter->pdev->irq, netdev);
1523 enable_irq(adapter->pdev->irq);
1524 }
1525 #endif
1526
1527 static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1528 {
1529 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1530 u16 next_to_use = 0;
1531 u16 next_to_clean = 0;
1532
1533 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1534 next_to_use = tx_ring->next_to_use;
1535
1536 return (u16)(next_to_clean > next_to_use) ?
1537 (next_to_clean - next_to_use - 1) :
1538 (tx_ring->count + next_to_clean - next_to_use - 1);
1539 }
1540
1541 /*
1542 * get next usable tpd
1543 * Note: should call atl1e_tdp_avail to make sure
1544 * there is enough tpd to use
1545 */
1546 static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1547 {
1548 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1549 u16 next_to_use = 0;
1550
1551 next_to_use = tx_ring->next_to_use;
1552 if (++tx_ring->next_to_use == tx_ring->count)
1553 tx_ring->next_to_use = 0;
1554
1555 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1556 return &tx_ring->desc[next_to_use];
1557 }
1558
1559 static struct atl1e_tx_buffer *
1560 atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1561 {
1562 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1563
1564 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1565 }
1566
1567 /* Calculate the transmit packet descript needed*/
1568 static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1569 {
1570 int i = 0;
1571 u16 tpd_req = 1;
1572 u16 fg_size = 0;
1573 u16 proto_hdr_len = 0;
1574
1575 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1576 fg_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
1577 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1578 }
1579
1580 if (skb_is_gso(skb)) {
1581 if (skb->protocol == htons(ETH_P_IP) ||
1582 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1583 proto_hdr_len = skb_transport_offset(skb) +
1584 tcp_hdrlen(skb);
1585 if (proto_hdr_len < skb_headlen(skb)) {
1586 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1587 MAX_TX_BUF_LEN - 1) >>
1588 MAX_TX_BUF_SHIFT);
1589 }
1590 }
1591
1592 }
1593 return tpd_req;
1594 }
1595
1596 static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1597 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1598 {
1599 u8 hdr_len;
1600 u32 real_len;
1601 unsigned short offload_type;
1602 int err;
1603
1604 if (skb_is_gso(skb)) {
1605 if (skb_header_cloned(skb)) {
1606 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1607 if (unlikely(err))
1608 return -1;
1609 }
1610 offload_type = skb_shinfo(skb)->gso_type;
1611
1612 if (offload_type & SKB_GSO_TCPV4) {
1613 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1614 + ntohs(ip_hdr(skb)->tot_len));
1615
1616 if (real_len < skb->len)
1617 pskb_trim(skb, real_len);
1618
1619 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1620 if (unlikely(skb->len == hdr_len)) {
1621 /* only xsum need */
1622 netdev_warn(adapter->netdev,
1623 "IPV4 tso with zero data??\n");
1624 goto check_sum;
1625 } else {
1626 ip_hdr(skb)->check = 0;
1627 ip_hdr(skb)->tot_len = 0;
1628 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1629 ip_hdr(skb)->saddr,
1630 ip_hdr(skb)->daddr,
1631 0, IPPROTO_TCP, 0);
1632 tpd->word3 |= (ip_hdr(skb)->ihl &
1633 TDP_V4_IPHL_MASK) <<
1634 TPD_V4_IPHL_SHIFT;
1635 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1636 TPD_TCPHDRLEN_MASK) <<
1637 TPD_TCPHDRLEN_SHIFT;
1638 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1639 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1640 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1641 }
1642 return 0;
1643 }
1644 }
1645
1646 check_sum:
1647 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1648 u8 css, cso;
1649
1650 cso = skb_checksum_start_offset(skb);
1651 if (unlikely(cso & 0x1)) {
1652 netdev_err(adapter->netdev,
1653 "payload offset should not ant event number\n");
1654 return -1;
1655 } else {
1656 css = cso + skb->csum_offset;
1657 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1658 TPD_PLOADOFFSET_SHIFT;
1659 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1660 TPD_CCSUMOFFSET_SHIFT;
1661 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1662 }
1663 }
1664
1665 return 0;
1666 }
1667
1668 static void atl1e_tx_map(struct atl1e_adapter *adapter,
1669 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1670 {
1671 struct atl1e_tpd_desc *use_tpd = NULL;
1672 struct atl1e_tx_buffer *tx_buffer = NULL;
1673 u16 buf_len = skb_headlen(skb);
1674 u16 map_len = 0;
1675 u16 mapped_len = 0;
1676 u16 hdr_len = 0;
1677 u16 nr_frags;
1678 u16 f;
1679 int segment;
1680
1681 nr_frags = skb_shinfo(skb)->nr_frags;
1682 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1683 if (segment) {
1684 /* TSO */
1685 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1686 use_tpd = tpd;
1687
1688 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1689 tx_buffer->length = map_len;
1690 tx_buffer->dma = pci_map_single(adapter->pdev,
1691 skb->data, hdr_len, PCI_DMA_TODEVICE);
1692 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1693 mapped_len += map_len;
1694 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1695 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1696 ((cpu_to_le32(tx_buffer->length) &
1697 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1698 }
1699
1700 while (mapped_len < buf_len) {
1701 /* mapped_len == 0, means we should use the first tpd,
1702 which is given by caller */
1703 if (mapped_len == 0) {
1704 use_tpd = tpd;
1705 } else {
1706 use_tpd = atl1e_get_tpd(adapter);
1707 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1708 }
1709 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1710 tx_buffer->skb = NULL;
1711
1712 tx_buffer->length = map_len =
1713 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1714 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1715 tx_buffer->dma =
1716 pci_map_single(adapter->pdev, skb->data + mapped_len,
1717 map_len, PCI_DMA_TODEVICE);
1718 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1719 mapped_len += map_len;
1720 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1721 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1722 ((cpu_to_le32(tx_buffer->length) &
1723 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1724 }
1725
1726 for (f = 0; f < nr_frags; f++) {
1727 const struct skb_frag_struct *frag;
1728 u16 i;
1729 u16 seg_num;
1730
1731 frag = &skb_shinfo(skb)->frags[f];
1732 buf_len = skb_frag_size(frag);
1733
1734 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1735 for (i = 0; i < seg_num; i++) {
1736 use_tpd = atl1e_get_tpd(adapter);
1737 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1738
1739 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1740 BUG_ON(tx_buffer->skb);
1741
1742 tx_buffer->skb = NULL;
1743 tx_buffer->length =
1744 (buf_len > MAX_TX_BUF_LEN) ?
1745 MAX_TX_BUF_LEN : buf_len;
1746 buf_len -= tx_buffer->length;
1747
1748 tx_buffer->dma = skb_frag_dma_map(&adapter->pdev->dev,
1749 frag,
1750 (i * MAX_TX_BUF_LEN),
1751 tx_buffer->length,
1752 DMA_TO_DEVICE);
1753 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_PAGE);
1754 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1755 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1756 ((cpu_to_le32(tx_buffer->length) &
1757 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1758 }
1759 }
1760
1761 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1762 /* note this one is a tcp header */
1763 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1764 /* The last tpd */
1765
1766 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1767 /* The last buffer info contain the skb address,
1768 so it will be free after unmap */
1769 tx_buffer->skb = skb;
1770 }
1771
1772 static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1773 struct atl1e_tpd_desc *tpd)
1774 {
1775 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1776 /* Force memory writes to complete before letting h/w
1777 * know there are new descriptors to fetch. (Only
1778 * applicable for weak-ordered memory model archs,
1779 * such as IA-64). */
1780 wmb();
1781 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1782 }
1783
1784 static netdev_tx_t atl1e_xmit_frame(struct sk_buff *skb,
1785 struct net_device *netdev)
1786 {
1787 struct atl1e_adapter *adapter = netdev_priv(netdev);
1788 unsigned long flags;
1789 u16 tpd_req = 1;
1790 struct atl1e_tpd_desc *tpd;
1791
1792 if (test_bit(__AT_DOWN, &adapter->flags)) {
1793 dev_kfree_skb_any(skb);
1794 return NETDEV_TX_OK;
1795 }
1796
1797 if (unlikely(skb->len <= 0)) {
1798 dev_kfree_skb_any(skb);
1799 return NETDEV_TX_OK;
1800 }
1801 tpd_req = atl1e_cal_tdp_req(skb);
1802 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1803 return NETDEV_TX_LOCKED;
1804
1805 if (atl1e_tpd_avail(adapter) < tpd_req) {
1806 /* no enough descriptor, just stop queue */
1807 netif_stop_queue(netdev);
1808 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1809 return NETDEV_TX_BUSY;
1810 }
1811
1812 tpd = atl1e_get_tpd(adapter);
1813
1814 if (vlan_tx_tag_present(skb)) {
1815 u16 vlan_tag = vlan_tx_tag_get(skb);
1816 u16 atl1e_vlan_tag;
1817
1818 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1819 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1820 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1821 TPD_VLAN_SHIFT;
1822 }
1823
1824 if (skb->protocol == htons(ETH_P_8021Q))
1825 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1826
1827 if (skb_network_offset(skb) != ETH_HLEN)
1828 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1829
1830 /* do TSO and check sum */
1831 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1832 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1833 dev_kfree_skb_any(skb);
1834 return NETDEV_TX_OK;
1835 }
1836
1837 atl1e_tx_map(adapter, skb, tpd);
1838 atl1e_tx_queue(adapter, tpd_req, tpd);
1839
1840 netdev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1841 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1842 return NETDEV_TX_OK;
1843 }
1844
1845 static void atl1e_free_irq(struct atl1e_adapter *adapter)
1846 {
1847 struct net_device *netdev = adapter->netdev;
1848
1849 free_irq(adapter->pdev->irq, netdev);
1850 }
1851
1852 static int atl1e_request_irq(struct atl1e_adapter *adapter)
1853 {
1854 struct pci_dev *pdev = adapter->pdev;
1855 struct net_device *netdev = adapter->netdev;
1856 int err = 0;
1857
1858 err = request_irq(pdev->irq, atl1e_intr, IRQF_SHARED, netdev->name,
1859 netdev);
1860 if (err) {
1861 netdev_dbg(adapter->netdev,
1862 "Unable to allocate interrupt Error: %d\n", err);
1863 return err;
1864 }
1865 netdev_dbg(netdev, "atl1e_request_irq OK\n");
1866 return err;
1867 }
1868
1869 int atl1e_up(struct atl1e_adapter *adapter)
1870 {
1871 struct net_device *netdev = adapter->netdev;
1872 int err = 0;
1873 u32 val;
1874
1875 /* hardware has been reset, we need to reload some things */
1876 err = atl1e_init_hw(&adapter->hw);
1877 if (err) {
1878 err = -EIO;
1879 return err;
1880 }
1881 atl1e_init_ring_ptrs(adapter);
1882 atl1e_set_multi(netdev);
1883 atl1e_restore_vlan(adapter);
1884
1885 if (atl1e_configure(adapter)) {
1886 err = -EIO;
1887 goto err_up;
1888 }
1889
1890 clear_bit(__AT_DOWN, &adapter->flags);
1891 napi_enable(&adapter->napi);
1892 atl1e_irq_enable(adapter);
1893 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1894 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1895 val | MASTER_CTRL_MANUAL_INT);
1896
1897 err_up:
1898 return err;
1899 }
1900
1901 void atl1e_down(struct atl1e_adapter *adapter)
1902 {
1903 struct net_device *netdev = adapter->netdev;
1904
1905 /* signal that we're down so the interrupt handler does not
1906 * reschedule our watchdog timer */
1907 set_bit(__AT_DOWN, &adapter->flags);
1908
1909 netif_stop_queue(netdev);
1910
1911 /* reset MAC to disable all RX/TX */
1912 atl1e_reset_hw(&adapter->hw);
1913 msleep(1);
1914
1915 napi_disable(&adapter->napi);
1916 atl1e_del_timer(adapter);
1917 atl1e_irq_disable(adapter);
1918
1919 netif_carrier_off(netdev);
1920 adapter->link_speed = SPEED_0;
1921 adapter->link_duplex = -1;
1922 atl1e_clean_tx_ring(adapter);
1923 atl1e_clean_rx_ring(adapter);
1924 }
1925
1926 /**
1927 * atl1e_open - Called when a network interface is made active
1928 * @netdev: network interface device structure
1929 *
1930 * Returns 0 on success, negative value on failure
1931 *
1932 * The open entry point is called when a network interface is made
1933 * active by the system (IFF_UP). At this point all resources needed
1934 * for transmit and receive operations are allocated, the interrupt
1935 * handler is registered with the OS, the watchdog timer is started,
1936 * and the stack is notified that the interface is ready.
1937 */
1938 static int atl1e_open(struct net_device *netdev)
1939 {
1940 struct atl1e_adapter *adapter = netdev_priv(netdev);
1941 int err;
1942
1943 /* disallow open during test */
1944 if (test_bit(__AT_TESTING, &adapter->flags))
1945 return -EBUSY;
1946
1947 /* allocate rx/tx dma buffer & descriptors */
1948 atl1e_init_ring_resources(adapter);
1949 err = atl1e_setup_ring_resources(adapter);
1950 if (unlikely(err))
1951 return err;
1952
1953 err = atl1e_request_irq(adapter);
1954 if (unlikely(err))
1955 goto err_req_irq;
1956
1957 err = atl1e_up(adapter);
1958 if (unlikely(err))
1959 goto err_up;
1960
1961 return 0;
1962
1963 err_up:
1964 atl1e_free_irq(adapter);
1965 err_req_irq:
1966 atl1e_free_ring_resources(adapter);
1967 atl1e_reset_hw(&adapter->hw);
1968
1969 return err;
1970 }
1971
1972 /**
1973 * atl1e_close - Disables a network interface
1974 * @netdev: network interface device structure
1975 *
1976 * Returns 0, this is not allowed to fail
1977 *
1978 * The close entry point is called when an interface is de-activated
1979 * by the OS. The hardware is still under the drivers control, but
1980 * needs to be disabled. A global MAC reset is issued to stop the
1981 * hardware, and all transmit and receive resources are freed.
1982 */
1983 static int atl1e_close(struct net_device *netdev)
1984 {
1985 struct atl1e_adapter *adapter = netdev_priv(netdev);
1986
1987 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
1988 atl1e_down(adapter);
1989 atl1e_free_irq(adapter);
1990 atl1e_free_ring_resources(adapter);
1991
1992 return 0;
1993 }
1994
1995 static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
1996 {
1997 struct net_device *netdev = pci_get_drvdata(pdev);
1998 struct atl1e_adapter *adapter = netdev_priv(netdev);
1999 struct atl1e_hw *hw = &adapter->hw;
2000 u32 ctrl = 0;
2001 u32 mac_ctrl_data = 0;
2002 u32 wol_ctrl_data = 0;
2003 u16 mii_advertise_data = 0;
2004 u16 mii_bmsr_data = 0;
2005 u16 mii_intr_status_data = 0;
2006 u32 wufc = adapter->wol;
2007 u32 i;
2008 #ifdef CONFIG_PM
2009 int retval = 0;
2010 #endif
2011
2012 if (netif_running(netdev)) {
2013 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2014 atl1e_down(adapter);
2015 }
2016 netif_device_detach(netdev);
2017
2018 #ifdef CONFIG_PM
2019 retval = pci_save_state(pdev);
2020 if (retval)
2021 return retval;
2022 #endif
2023
2024 if (wufc) {
2025 /* get link status */
2026 atl1e_read_phy_reg(hw, MII_BMSR, &mii_bmsr_data);
2027 atl1e_read_phy_reg(hw, MII_BMSR, &mii_bmsr_data);
2028
2029 mii_advertise_data = ADVERTISE_10HALF;
2030
2031 if ((atl1e_write_phy_reg(hw, MII_CTRL1000, 0) != 0) ||
2032 (atl1e_write_phy_reg(hw,
2033 MII_ADVERTISE, mii_advertise_data) != 0) ||
2034 (atl1e_phy_commit(hw)) != 0) {
2035 netdev_dbg(adapter->netdev, "set phy register failed\n");
2036 goto wol_dis;
2037 }
2038
2039 hw->phy_configured = false; /* re-init PHY when resume */
2040
2041 /* turn on magic packet wol */
2042 if (wufc & AT_WUFC_MAG)
2043 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2044
2045 if (wufc & AT_WUFC_LNKC) {
2046 /* if orignal link status is link, just wait for retrive link */
2047 if (mii_bmsr_data & BMSR_LSTATUS) {
2048 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2049 msleep(100);
2050 atl1e_read_phy_reg(hw, MII_BMSR,
2051 &mii_bmsr_data);
2052 if (mii_bmsr_data & BMSR_LSTATUS)
2053 break;
2054 }
2055
2056 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2057 netdev_dbg(adapter->netdev,
2058 "Link may change when suspend\n");
2059 }
2060 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2061 /* only link up can wake up */
2062 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2063 netdev_dbg(adapter->netdev,
2064 "read write phy register failed\n");
2065 goto wol_dis;
2066 }
2067 }
2068 /* clear phy interrupt */
2069 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2070 /* Config MAC Ctrl register */
2071 mac_ctrl_data = MAC_CTRL_RX_EN;
2072 /* set to 10/100M halt duplex */
2073 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2074 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2075 MAC_CTRL_PRMLEN_MASK) <<
2076 MAC_CTRL_PRMLEN_SHIFT);
2077
2078 __atl1e_vlan_mode(netdev->features, &mac_ctrl_data);
2079
2080 /* magic packet maybe Broadcast&multicast&Unicast frame */
2081 if (wufc & AT_WUFC_MAG)
2082 mac_ctrl_data |= MAC_CTRL_BC_EN;
2083
2084 netdev_dbg(adapter->netdev, "suspend MAC=0x%x\n",
2085 mac_ctrl_data);
2086
2087 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2088 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2089 /* pcie patch */
2090 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2091 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2092 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2093 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2094 goto suspend_exit;
2095 }
2096 wol_dis:
2097
2098 /* WOL disabled */
2099 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2100
2101 /* pcie patch */
2102 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2103 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2104 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2105
2106 atl1e_force_ps(hw);
2107 hw->phy_configured = false; /* re-init PHY when resume */
2108
2109 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2110
2111 suspend_exit:
2112
2113 if (netif_running(netdev))
2114 atl1e_free_irq(adapter);
2115
2116 pci_disable_device(pdev);
2117
2118 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2119
2120 return 0;
2121 }
2122
2123 #ifdef CONFIG_PM
2124 static int atl1e_resume(struct pci_dev *pdev)
2125 {
2126 struct net_device *netdev = pci_get_drvdata(pdev);
2127 struct atl1e_adapter *adapter = netdev_priv(netdev);
2128 u32 err;
2129
2130 pci_set_power_state(pdev, PCI_D0);
2131 pci_restore_state(pdev);
2132
2133 err = pci_enable_device(pdev);
2134 if (err) {
2135 netdev_err(adapter->netdev,
2136 "Cannot enable PCI device from suspend\n");
2137 return err;
2138 }
2139
2140 pci_set_master(pdev);
2141
2142 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2143
2144 pci_enable_wake(pdev, PCI_D3hot, 0);
2145 pci_enable_wake(pdev, PCI_D3cold, 0);
2146
2147 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2148
2149 if (netif_running(netdev)) {
2150 err = atl1e_request_irq(adapter);
2151 if (err)
2152 return err;
2153 }
2154
2155 atl1e_reset_hw(&adapter->hw);
2156
2157 if (netif_running(netdev))
2158 atl1e_up(adapter);
2159
2160 netif_device_attach(netdev);
2161
2162 return 0;
2163 }
2164 #endif
2165
2166 static void atl1e_shutdown(struct pci_dev *pdev)
2167 {
2168 atl1e_suspend(pdev, PMSG_SUSPEND);
2169 }
2170
2171 static const struct net_device_ops atl1e_netdev_ops = {
2172 .ndo_open = atl1e_open,
2173 .ndo_stop = atl1e_close,
2174 .ndo_start_xmit = atl1e_xmit_frame,
2175 .ndo_get_stats = atl1e_get_stats,
2176 .ndo_set_rx_mode = atl1e_set_multi,
2177 .ndo_validate_addr = eth_validate_addr,
2178 .ndo_set_mac_address = atl1e_set_mac_addr,
2179 .ndo_fix_features = atl1e_fix_features,
2180 .ndo_set_features = atl1e_set_features,
2181 .ndo_change_mtu = atl1e_change_mtu,
2182 .ndo_do_ioctl = atl1e_ioctl,
2183 .ndo_tx_timeout = atl1e_tx_timeout,
2184 #ifdef CONFIG_NET_POLL_CONTROLLER
2185 .ndo_poll_controller = atl1e_netpoll,
2186 #endif
2187
2188 };
2189
2190 static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2191 {
2192 SET_NETDEV_DEV(netdev, &pdev->dev);
2193 pci_set_drvdata(pdev, netdev);
2194
2195 netdev->netdev_ops = &atl1e_netdev_ops;
2196
2197 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2198 atl1e_set_ethtool_ops(netdev);
2199
2200 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO |
2201 NETIF_F_HW_VLAN_CTAG_RX;
2202 netdev->features = netdev->hw_features | NETIF_F_LLTX |
2203 NETIF_F_HW_VLAN_CTAG_TX;
2204
2205 return 0;
2206 }
2207
2208 /**
2209 * atl1e_probe - Device Initialization Routine
2210 * @pdev: PCI device information struct
2211 * @ent: entry in atl1e_pci_tbl
2212 *
2213 * Returns 0 on success, negative on failure
2214 *
2215 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2216 * The OS initialization, configuring of the adapter private structure,
2217 * and a hardware reset occur.
2218 */
2219 static int atl1e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2220 {
2221 struct net_device *netdev;
2222 struct atl1e_adapter *adapter = NULL;
2223 static int cards_found;
2224
2225 int err = 0;
2226
2227 err = pci_enable_device(pdev);
2228 if (err) {
2229 dev_err(&pdev->dev, "cannot enable PCI device\n");
2230 return err;
2231 }
2232
2233 /*
2234 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2235 * shared register for the high 32 bits, so only a single, aligned,
2236 * 4 GB physical address range can be used at a time.
2237 *
2238 * Supporting 64-bit DMA on this hardware is more trouble than it's
2239 * worth. It is far easier to limit to 32-bit DMA than update
2240 * various kernel subsystems to support the mechanics required by a
2241 * fixed-high-32-bit system.
2242 */
2243 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2244 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2245 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2246 goto err_dma;
2247 }
2248
2249 err = pci_request_regions(pdev, atl1e_driver_name);
2250 if (err) {
2251 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2252 goto err_pci_reg;
2253 }
2254
2255 pci_set_master(pdev);
2256
2257 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2258 if (netdev == NULL) {
2259 err = -ENOMEM;
2260 goto err_alloc_etherdev;
2261 }
2262
2263 err = atl1e_init_netdev(netdev, pdev);
2264 if (err) {
2265 netdev_err(netdev, "init netdevice failed\n");
2266 goto err_init_netdev;
2267 }
2268 adapter = netdev_priv(netdev);
2269 adapter->bd_number = cards_found;
2270 adapter->netdev = netdev;
2271 adapter->pdev = pdev;
2272 adapter->hw.adapter = adapter;
2273 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2274 if (!adapter->hw.hw_addr) {
2275 err = -EIO;
2276 netdev_err(netdev, "cannot map device registers\n");
2277 goto err_ioremap;
2278 }
2279
2280 /* init mii data */
2281 adapter->mii.dev = netdev;
2282 adapter->mii.mdio_read = atl1e_mdio_read;
2283 adapter->mii.mdio_write = atl1e_mdio_write;
2284 adapter->mii.phy_id_mask = 0x1f;
2285 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2286
2287 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2288
2289 init_timer(&adapter->phy_config_timer);
2290 adapter->phy_config_timer.function = atl1e_phy_config;
2291 adapter->phy_config_timer.data = (unsigned long) adapter;
2292
2293 /* get user settings */
2294 atl1e_check_options(adapter);
2295 /*
2296 * Mark all PCI regions associated with PCI device
2297 * pdev as being reserved by owner atl1e_driver_name
2298 * Enables bus-mastering on the device and calls
2299 * pcibios_set_master to do the needed arch specific settings
2300 */
2301 atl1e_setup_pcicmd(pdev);
2302 /* setup the private structure */
2303 err = atl1e_sw_init(adapter);
2304 if (err) {
2305 netdev_err(netdev, "net device private data init failed\n");
2306 goto err_sw_init;
2307 }
2308
2309 /* Init GPHY as early as possible due to power saving issue */
2310 atl1e_phy_init(&adapter->hw);
2311 /* reset the controller to
2312 * put the device in a known good starting state */
2313 err = atl1e_reset_hw(&adapter->hw);
2314 if (err) {
2315 err = -EIO;
2316 goto err_reset;
2317 }
2318
2319 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2320 err = -EIO;
2321 netdev_err(netdev, "get mac address failed\n");
2322 goto err_eeprom;
2323 }
2324
2325 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2326 netdev_dbg(netdev, "mac address : %pM\n", adapter->hw.mac_addr);
2327
2328 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2329 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2330 netif_set_gso_max_size(netdev, MAX_TSO_SEG_SIZE);
2331 err = register_netdev(netdev);
2332 if (err) {
2333 netdev_err(netdev, "register netdevice failed\n");
2334 goto err_register;
2335 }
2336
2337 /* assume we have no link for now */
2338 netif_stop_queue(netdev);
2339 netif_carrier_off(netdev);
2340
2341 cards_found++;
2342
2343 return 0;
2344
2345 err_reset:
2346 err_register:
2347 err_sw_init:
2348 err_eeprom:
2349 iounmap(adapter->hw.hw_addr);
2350 err_init_netdev:
2351 err_ioremap:
2352 free_netdev(netdev);
2353 err_alloc_etherdev:
2354 pci_release_regions(pdev);
2355 err_pci_reg:
2356 err_dma:
2357 pci_disable_device(pdev);
2358 return err;
2359 }
2360
2361 /**
2362 * atl1e_remove - Device Removal Routine
2363 * @pdev: PCI device information struct
2364 *
2365 * atl1e_remove is called by the PCI subsystem to alert the driver
2366 * that it should release a PCI device. The could be caused by a
2367 * Hot-Plug event, or because the driver is going to be removed from
2368 * memory.
2369 */
2370 static void atl1e_remove(struct pci_dev *pdev)
2371 {
2372 struct net_device *netdev = pci_get_drvdata(pdev);
2373 struct atl1e_adapter *adapter = netdev_priv(netdev);
2374
2375 /*
2376 * flush_scheduled work may reschedule our watchdog task, so
2377 * explicitly disable watchdog tasks from being rescheduled
2378 */
2379 set_bit(__AT_DOWN, &adapter->flags);
2380
2381 atl1e_del_timer(adapter);
2382 atl1e_cancel_work(adapter);
2383
2384 unregister_netdev(netdev);
2385 atl1e_free_ring_resources(adapter);
2386 atl1e_force_ps(&adapter->hw);
2387 iounmap(adapter->hw.hw_addr);
2388 pci_release_regions(pdev);
2389 free_netdev(netdev);
2390 pci_disable_device(pdev);
2391 }
2392
2393 /**
2394 * atl1e_io_error_detected - called when PCI error is detected
2395 * @pdev: Pointer to PCI device
2396 * @state: The current pci connection state
2397 *
2398 * This function is called after a PCI bus error affecting
2399 * this device has been detected.
2400 */
2401 static pci_ers_result_t
2402 atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2403 {
2404 struct net_device *netdev = pci_get_drvdata(pdev);
2405 struct atl1e_adapter *adapter = netdev_priv(netdev);
2406
2407 netif_device_detach(netdev);
2408
2409 if (state == pci_channel_io_perm_failure)
2410 return PCI_ERS_RESULT_DISCONNECT;
2411
2412 if (netif_running(netdev))
2413 atl1e_down(adapter);
2414
2415 pci_disable_device(pdev);
2416
2417 /* Request a slot slot reset. */
2418 return PCI_ERS_RESULT_NEED_RESET;
2419 }
2420
2421 /**
2422 * atl1e_io_slot_reset - called after the pci bus has been reset.
2423 * @pdev: Pointer to PCI device
2424 *
2425 * Restart the card from scratch, as if from a cold-boot. Implementation
2426 * resembles the first-half of the e1000_resume routine.
2427 */
2428 static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2429 {
2430 struct net_device *netdev = pci_get_drvdata(pdev);
2431 struct atl1e_adapter *adapter = netdev_priv(netdev);
2432
2433 if (pci_enable_device(pdev)) {
2434 netdev_err(adapter->netdev,
2435 "Cannot re-enable PCI device after reset\n");
2436 return PCI_ERS_RESULT_DISCONNECT;
2437 }
2438 pci_set_master(pdev);
2439
2440 pci_enable_wake(pdev, PCI_D3hot, 0);
2441 pci_enable_wake(pdev, PCI_D3cold, 0);
2442
2443 atl1e_reset_hw(&adapter->hw);
2444
2445 return PCI_ERS_RESULT_RECOVERED;
2446 }
2447
2448 /**
2449 * atl1e_io_resume - called when traffic can start flowing again.
2450 * @pdev: Pointer to PCI device
2451 *
2452 * This callback is called when the error recovery driver tells us that
2453 * its OK to resume normal operation. Implementation resembles the
2454 * second-half of the atl1e_resume routine.
2455 */
2456 static void atl1e_io_resume(struct pci_dev *pdev)
2457 {
2458 struct net_device *netdev = pci_get_drvdata(pdev);
2459 struct atl1e_adapter *adapter = netdev_priv(netdev);
2460
2461 if (netif_running(netdev)) {
2462 if (atl1e_up(adapter)) {
2463 netdev_err(adapter->netdev,
2464 "can't bring device back up after reset\n");
2465 return;
2466 }
2467 }
2468
2469 netif_device_attach(netdev);
2470 }
2471
2472 static const struct pci_error_handlers atl1e_err_handler = {
2473 .error_detected = atl1e_io_error_detected,
2474 .slot_reset = atl1e_io_slot_reset,
2475 .resume = atl1e_io_resume,
2476 };
2477
2478 static struct pci_driver atl1e_driver = {
2479 .name = atl1e_driver_name,
2480 .id_table = atl1e_pci_tbl,
2481 .probe = atl1e_probe,
2482 .remove = atl1e_remove,
2483 /* Power Management Hooks */
2484 #ifdef CONFIG_PM
2485 .suspend = atl1e_suspend,
2486 .resume = atl1e_resume,
2487 #endif
2488 .shutdown = atl1e_shutdown,
2489 .err_handler = &atl1e_err_handler
2490 };
2491
2492 /**
2493 * atl1e_init_module - Driver Registration Routine
2494 *
2495 * atl1e_init_module is the first routine called when the driver is
2496 * loaded. All it does is register with the PCI subsystem.
2497 */
2498 static int __init atl1e_init_module(void)
2499 {
2500 return pci_register_driver(&atl1e_driver);
2501 }
2502
2503 /**
2504 * atl1e_exit_module - Driver Exit Cleanup Routine
2505 *
2506 * atl1e_exit_module is called just before the driver is removed
2507 * from memory.
2508 */
2509 static void __exit atl1e_exit_module(void)
2510 {
2511 pci_unregister_driver(&atl1e_driver);
2512 }
2513
2514 module_init(atl1e_init_module);
2515 module_exit(atl1e_exit_module);
Linux kernel - Deliverables
This page took 0.116464 seconds and 5 git commands to generate.